C161CS/CJ/CI -32R/-L Data Sheet v3.0

Da ta S h e e t , V 3 .0 , J a n . 2 0 0 1
C161CS-32R/-L
C161JC-32R/-L
C161JI-32R/-L
16-Bit Single-Chip Microcontroller
Microcontrollers
N e v e r
s t o p
t h i n k i n g .
Edition 2001-01
Published by Infineon Technologies AG,
St.-Martin-Strasse 53,
D-81541 München, Germany
© Infineon Technologies AG 2001.
All Rights Reserved.
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We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding
circuits, descriptions and charts stated herein.
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Information
For further information on technology, delivery terms and conditions and prices please contact your nearest
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Da ta S h e e t , V 3 .0 , J a n . 2 0 0 1
C161CS-32R/-L
C161JC-32R/-L
C161JI-32R/-L
16-Bit Single-Chip Microcontroller
Microcontrollers
N e v e r
s t o p
t h i n k i n g .
C161CS/JC/JI
Revision History:
2001-01
Previous Version:
2000-08 V2.0 (intermediate version)
1999-03
(Advance Information)
Page
Subjects (major changes since last revision)1)
All
Converted to Infineon layout
2
Derivative Synopsis Table updated
V3.0
4, 6, 10, 18 Programmable Interface Routing introduced
27, 28
GPT block diagrams updated
29
RTC description improved
35
OWD description improved
39ff
RSTCON and SDLM registers added
51
Description of input/output voltage and hysteresis improved
53
Separate table for power consumption
57
Clock generation mode table updated
60
External clock drive specification improved
62
Reset calibration time specified, definition of VAREF improved
63
Programmable sample time introduced
65ff
Timing tables updated to 25 MHz
1)
Changes refer to version 1999-03.
Controller Area Network (CAN): License of Robert Bosch GmbH
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16-Bit Single-Chip Microcontroller
C166 Family
C161CS/JC/JI
C161CS/JC/JI
• High Performance 16-bit CPU with 4-Stage Pipeline
– 80 ns Instruction Cycle Time at 25 MHz CPU Clock
– 400 ns Multiplication (16 × 16 bit), 800 ns Division (32 / 16 bit)
– Enhanced Boolean Bit Manipulation Facilities
– Additional Instructions to Support HLL and Operating Systems
– Register-Based Design with Multiple Variable Register Banks
– Single-Cycle Context Switching Support
– 16 MBytes Total Linear Address Space for Code and Data
– 1024 Bytes On-Chip Special Function Register Area
• 16-Priority-Level Interrupt System with 59 Sources, Sample-Rate down to 40 ns
• 8-Channel Interrupt-Driven Single-Cycle Data Transfer Facilities via
Peripheral Event Controller (PEC)
• Clock Generation via on-chip PLL (factors 1:1.5/2/2.5/3/4/5),
via prescaler or via direct clock input
– Additional 32 kHz Oscillator
• On-Chip Memory Modules
– 2 KBytes On-Chip Internal RAM (IRAM)
– 8 KBytes On-Chip Extension RAM (XRAM)
– 256 KBytes On-Chip Mask ROM
• On-Chip Peripheral Modules
– 12-Channel 10-bit A/D Converter with Programmable Conversion Time
down to 7.8 µs
– Two 16-Channel Capture/Compare Units (eight IO lines each)
– Two Multi-Functional General Purpose Timer Units with 5 Timers
– Two Asynchronous/Synchronous Serial Channels
– High-Speed Synchronous Serial Channel (SPI)
– On-Chip CAN Interface (Rev. 2.0B active, Full CAN / Basic CAN)
with 15 Message Objects (C161CS 2x, C161JC 1x)
– Serial Data Link Module (SDLM), compliant with J1850,
supporting Class 2 (C161JC/JI)
– IIC Bus Interface (10-bit Addressing, 400 kHz) with 2 Channels (multiplexed)
– On-Chip Real Time Clock
• Up to 16 MBytes External Address Space for Code and Data
– Programmable External Bus Characteristics for Different Address Ranges
– Multiplexed or Demultiplexed External Address/Data Buses with 8-Bit or 16-Bit
Data Bus Width
– Five Programmable Chip-Select Signals
– Hold- and Hold-Acknowledge Bus Arbitration Support
Data Sheet
1
V3.0, 2001-01
C161CS/JC/JI-32R
C161CS/JC/JI-L
• Idle, Sleep, and Power Down Modes with Flexible Power Management
• Programmable Watchdog Timer and Oscillator Watchdog
• Up to 93 General Purpose I/O Lines,
partly with Selectable Input Thresholds and Hysteresis
• Supported by a Large Range of Development Tools like C-Compilers,
Macro-Assembler Packages, Emulators, Evaluation Boards, HLL-Debuggers,
Simulators, Logic Analyzer Disassemblers, Programming Boards
• On-Chip Bootstrap Loader
• 128-Pin TQFP Package
This document describes several derivatives of the C161 group. Table 1 enumerates
these derivatives and summarizes the differences. As this document refers to all of these
derivatives, some descriptions may not apply to a specific product.
Table 1
C161CS/JC/JI Derivative Synopsis
Derivative
On-Chip
Program Memory
Serial Bus
Interface(s)
Maximum CPU
Frequency
SAK-C161CS-32RF
SAB-C161CS-32RF
256 KByte ROM
CAN1, CAN2
25 MHz
SAK-C161CS-LF
SAB-C161CS-LF
---
CAN1, CAN2
25 MHz
SAK-C161JC-32RF
SAB-C161JC-32RF
256 KByte ROM
CAN1, SDLM
25 MHz
SAK-C161JC-LF
SAB-C161JC-LF
---
CAN1, SDLM
25 MHz
SAK-C161JI-32RF
SAB-C161JI-32RF
256 KByte ROM
SDLM
25 MHz
SAK-C161JI-LF
SAB-C161JI-LF
---
SDLM
25 MHz
For simplicity all versions are referred to by the term C161CS/JC/JI throughout this
document.
Data Sheet
2
V3.0, 2001-01
C161CS/JC/JI-32R
C161CS/JC/JI-L
Ordering Information
The ordering code for Infineon microcontrollers provides an exact reference to the
required product. This ordering code identifies:
• the derivative itself, i.e. its function set, the temperature range, and the supply voltage
• the package and the type of delivery.
For the available ordering codes for the C161CS/JC/JI please refer to the “Product
Catalog Microcontrollers”, which summarizes all available microcontroller variants.
Note: The ordering codes for Mask-ROM versions are defined for each product after
verification of the respective ROM code.
Introduction
The C161CS/JC/JI derivatives are high performance derivatives of the Infineon
C166 Family of full featured single-chip CMOS microcontrollers. They combine high
CPU performance (up to 12.5 million instructions per second) with high peripheral
functionality and enhanced IO-capabilities. They also provide clock generation via PLL
and various on-chip memory modules such as program ROM, internal RAM, and
extension RAM.
VAREF VAGND VDD
VSS
Port 0
16 Bit
XTAL1
XTAL2
Port 1
16 Bit
XTAL3
XTAL4
Port 2
8 Bit
RSTIN
Port 3
15 Bit
RSTOUT
NMI
C161CS/JC/JI
Port 4
8 Bit
EA
READY
Port 6
8 Bit
ALE
Port 7
4 Bit
RD
WR/WRL
Port 5
12 Bit
Port 9
6 Bit
MCL04450
Figure 1
Data Sheet
Logic Symbol
3
V3.0, 2001-01
C161CS/JC/JI-32R
C161CS/JC/JI-L
RSTOUT
NMI
VSS
VDD
P6.0/CS0
P6.1/CS1
P6.2/CS2
P6.3/CS3
P6.4/CS4
P6.5/HOLD
P6.6/HLDA
P6.7/BREQ
P7.4/CC28IO/*
P7.5/CC29IO/*
P7.6/CC30IO/*
P7.7/CC31IO/*
VSS
VDD
P9.0/SDA0
P9.1/SCL0
P9.2/SDA1
P9.3/SCL1
P9.4/SDA2
P9.5
VSS
VDD
P1L.7/A7
P1L.6/A6
P1L.5/A5
P1L.4/A4
P1L.3/A3
P1L.2/A2
P1L.1/A1
P1L.0/A0
P0H.7/AD15
P0H.6/AD14
P0H.5/AD13
P0H.4/AD12
P0H.3/AD11
P0H.2/AD10
VSS
VDD
P1H.7/A15/CC27IO
P1H.6/A14/CC26IO
P1H.5/A13/CC25IO
P1H.4/A12/CC24IO
P1H.3/A11
P1H.2/A10
P1H.1/A9
P1H.0/A8
VSS
VDD
XTAL1
XTAL2
VSS
C161CS/JC/JI
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
P0H.1/AD9
P0H.0/AD8
VSS
VDD
P0L.7/AD7
P0L.6/AD6
P0L.5/AD5
P0L.4/AD4
P0L.3/AD3
P0L.2/AD2
P0L.1/AD1
P0L.0/AD0
EA
ALE
READY
WR/WRL
RD
VSS
VDD
P4.7/A23/*
P4.6/A22/*
P4.5/A21/*
P4.4/A20/*
P4.3/A19
P4.2/A18
P4.1/A17
P4.0/A16
VSS
VDD
P3.15/CLKOUT/FOUT
P3.13/SCLK
P3.12/BHE/WRH
P3.0/T0IN/TxD1
P3.1/T6OUT/RxD1
P3.2/CAPIN
P3.3/T3OUT
P3.4/T3EUD
P3.5/T4IN
P3.6/T3IN
P3.7/T2IN
P3.8/MRST
P3.9/MTSR
P3.10/TxD0
P3.11/RxD0
VSS
VDD
P2.8/CC8IO/EX0IN
P2.9/CC9IO/EX1IN
P2.10/CC10IO/EX2IN
P2.11/CC11IO/EX3IN
P2.12/CC12IO/EX4IN
P2.13/CC13IO/EX5IN
P2.14/CC14IO/EX6IN
P2.15/CC15IO/EX7INT7IN
VSS
VDD
P5.12/AN12/T6IN
P5.13/AN13/T5IN
P5.14/AN14/T4EUD
P5.15/AN15/T2EUD
VAREF
VAGND
P5.6/AN6
P5.7/AN7
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
P5.0/AN0
P5.1/AN1
P5.2/AN2
P5.3/AN3
P5.4/AN4
P5.5/AN5
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
RSTIN
XTAL4
XTAL3
Pin Configuration
(top view)
MCP04451
Figure 2
*) The marked pins of Port 4 and Port 7 can have interface lines assigned to them (CAN
interface in the C161CS and C161JC, SDLM interface in the C161JC and C161JI).
Table 2 on the pages below lists the possible assignments.
Data Sheet
4
V3.0, 2001-01
C161CS/JC/JI-32R
C161CS/JC/JI-L
Table 2
Pin Definitions and Functions
Symbol Pin
No.
Input
Outp.
Function
RST
OUT
1
O
Internal Reset Indication Output. This pin is set to a low level
when the part is executing either a hardware-, a software- or
a watchdog timer reset. RSTOUT remains low until the EINIT
(end of initialization) instruction is executed.
NMI
2
I
Non-Maskable Interrupt Input. A high to low transition at this
pin causes the CPU to vector to the NMI trap routine. When
the PWRDN (power down) instruction is executed, the NMI
pin must be low in order to force the C161CS/JC/JI to go into
power down mode. If NMI is high, when PWRDN is
executed, the part will continue to run in normal mode.
If not used, pin NMI should be pulled high externally.
IO
Port 6 is an 8-bit bidirectional I/O port. It is bit-wise
programmable for input or output via direction bits. For a pin
configured as input, the output driver is put into highimpedance state. Port 6 outputs can be configured as push/
pull or open drain drivers.
The Port 6 pins also serve for alternate functions:
Chip Select 0 Output
CS0
Chip Select 1 Output
CS1
Chip Select 2 Output
CS2
Chip Select 3 Output
CS3
Chip Select 4 Output
CS4
External Master Hold Request Input
HOLD
Hold Acknowledge Output (master mode)
HLDA
or Input (slave mode)
Bus Request Output
BREQ
P6
P6.0
P6.1
P6.2
P6.3
P6.4
P6.5
P6.6
5
6
7
8
9
10
11
O
O
O
O
O
I
I/O
P6.7
12
O
Data Sheet
5
V3.0, 2001-01
C161CS/JC/JI-32R
C161CS/JC/JI-L
Table 2
Pin Definitions and Functions (cont’d)
Symbol Pin
No.
Input
Outp.
Function
P7
IO
Port 7 is a 4-bit bidirectional I/O port. It is bit-wise
programmable for input or output via direction bits. For a pin
configured as input, the output driver is put into highimpedance state. Port 7 outputs can be configured as push/
pull or open drain drivers. The input threshold of Port 7 is
selectable (TTL or special). Port 7 pins provide inputs/
outputs for CAPCOM2 and serial interface lines.1)
CC28IO
CAPCOM2: CC28 Capture Inp./Compare Outp.,
CAN1_RxD CAN 1 Receive Data Input,
(C161CS/JC)
CAN2_RxD CAN 2 Receive Data Input,
(C161CS)
SDL_TxD SDLM Transmit Data Output
(C161JC/JI)
CC29IO
CAPCOM2: CC29 Capture Inp./Compare Outp.,
CAN1_TxD CAN 1 Transmit Data Output,
(C161CS/JC)
CAN2_TxD CAN 2 Transmit Data Output,
(C161CS)
SDL_RxD SDLM Receive Data Input
(C161JC/JI)
CC30IO
CAPCOM2: CC30 Capture Inp./Compare Outp.,
CAN1_RxD CAN 1 Receive Data Input,
(C161CS/JC)
CAN2_RxD CAN 2 Receive Data Input,
(C161CS)
SDL_TxD SDLM Transmit Data Output
(C161JC/JI)
CC31IO
CAPCOM2: CC31 Capture Inp./Compare Outp.,
CAN1_TxD CAN 1 Transmit Data Output,
(C161CS/JC)
CAN2_TxD CAN 2 Transmit Data Output,
(C161CS)
SDL_RxD SDLM Receive Data Input
(C161JC/JI)
P7.4
13
P7.5
14
P7.6
15
P7.7
16
P9
P9.0
P9.1
P9.2
P9.3
P9.4
P9.5
I/O
I
I
O
I/O
O
O
I
I/O
I
I
O
I/O
O
O
I
IO
19
20
21
22
23
24
I/O
I/O
I/O
I/O
I/O
–
Port 9 is a 6-bit bidirectional open drain I/O port (provide
external pullup resistors if required). It is bit-wise
programmable for input or output via direction bits. For a pin
configured as input, the output driver is put into highimpedance state.
The following Port 9 pins also serve for alternate functions:
SDA0
IIC Bus Data Line 0
SCL0
IIC Bus Clock Line 0
SDA1
IIC Bus Data Line 1
SCL1
IIC Bus Clock Line 1
SDA2
IIC Bus Data Line 2
–
Note: Port 9 pins can only tolerate positive overload currents
(see Table 9).
Data Sheet
6
V3.0, 2001-01
C161CS/JC/JI-32R
C161CS/JC/JI-L
Table 2
Pin Definitions and Functions (cont’d)
Symbol Pin
No.
Input
Outp.
Function
P5
I
Port 5 is a 12-bit input-only port with Schmitt-Trigger char.
The pins of Port 5 also serve as analog input channels for the
A/D converter, or they serve as timer inputs:
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
AN12,
T6IN
GPT2 Timer T6 Count Inp.
AN13,
T5IN
GPT2 Timer T5 Count Inp.
AN14,
T4EUD GPT1 Timer T4 Ext. Up/Down Ctrl. Inp.
AN15,
T2EUD GPT1 Timer T5 Ext. Up/Down Ctrl. Inp.
P5.0
P5.1
P5.2
P5.3
P5.4
P5.5
P5.6
P5.7
P5.12
P5.13
P5.14
P5.15
27
28
29
30
31
32
33
34
37
38
39
40
Data Sheet
I
I
I
I
I
I
I
I
I
I
I
I
7
V3.0, 2001-01
C161CS/JC/JI-32R
C161CS/JC/JI-L
Table 2
Pin Definitions and Functions (cont’d)
Symbol Pin
No.
Input
Outp.
Function
P2
IO
Port 2 is an 8-bit bidirectional I/O port. It is bit-wise
programmable for input or output via direction bits. For a pin
configured as input, the output driver is put into highimpedance state. Port 2 outputs can be configured as push/
pull or open drain drivers. The input threshold of Port 2 is
selectable (TTL or special).
The following Port 2 pins also serve for alternate functions:
CC8IO
CAPCOM1: CC8 Capture Inp./Compare Output,
EX0IN
Fast External Interrupt 0 Input
CC9IO
CAPCOM1: CC9 Capture Inp./Compare Output,
EX1IN
Fast External Interrupt 1 Input
CC10IO
CAPCOM1: CC10 Capture Inp./Compare Outp.,
EX2IN
Fast External Interrupt 2 Input
CC11IO
CAPCOM1: CC11 Capture Inp./Compare Outp.,
EX3IN
Fast External Interrupt 3 Input
CC12IO
CAPCOM1: CC12 Capture Inp./Compare Outp.,
EX4IN
Fast External Interrupt 4 Input
CC13IO
CAPCOM1: CC13 Capture Inp./Compare Outp.,
EX5IN
Fast External Interrupt 5 Input
CC14IO
CAPCOM1: CC14 Capture Inp./Compare Outp.,
EX6IN
Fast External Interrupt 6 Input
CC15IO
CAPCOM1: CC15 Capture Inp./Compare Outp.,
EX7IN
Fast External Interrupt 7 Input,
T7IN
CAPCOM2: Timer T7 Count Input
P2.8
43
P2.9
44
P2.10
45
P2.11
46
P2.12
47
P2.13
48
P2.14
49
P2.15
50
I/O
I
I/O
I
I/O
I
I/O
I
I/O
I
I/O
I
I/O
I
I/O
I
I
Note: During Sleep Mode a spike filter on the EXnIN
interrupt inputs suppresses input pulses < 10 ns.
Input pulses > 100 ns safely pass the filter.
Data Sheet
8
V3.0, 2001-01
C161CS/JC/JI-32R
C161CS/JC/JI-L
Table 2
Pin Definitions and Functions (cont’d)
Symbol Pin
No.
Input
Outp.
Function
P3
IO
Port 3 is a 15-bit bidirectional I/O port. It is bit-wise
programmable for input or output via direction bits. For a pin
configured as input, the output driver is put into highimpedance state. Port 3 outputs can be configured as push/
pull or open drain drivers. The input threshold of Port 3 is
selectable (TTL or special).
The following Port 3 pins also serve for alternate functions:
T0IN
CAPCOM1 Timer T0 Count Input,
TxD1
ASC1 Clock/Data Output (Async./Sync)
T6OUT
GPT2 Timer T6 Toggle Latch Output,
RxD1
ASC1 Data Input (Async.) or Inp./Output (Sync.)
CAPIN
GPT2 Register CAPREL Capture Input
T3OUT
GPT1 Timer T3 Toggle Latch Output
T3EUD
GPT1 Timer T3 External Up/Down Control Input
T4IN
GPT1 Timer T4 Count/Gate/Reload/Capture Inp
T3IN
GPT1 Timer T3 Count/Gate Input
T2IN
GPT1 Timer T2 Count/Gate/Reload/Capture Inp
MRST
SSC Master-Receive/Slave-Transmit Inp./Outp.
MTSR
SSC Master-Transmit/Slave-Receive Outp./Inp.
TxD0
ASC0 Clock/Data Output (Async./Sync.)
RxD0
ASC0 Data Input (Async.) or Inp./Outp. (Sync.)
External Memory High Byte Enable Signal,
BHE
External Memory High Byte Write Strobe
WRH
SCLK
SSC Master Clock Output / Slave Clock Input.
CLKOUT System Clock Output (= CPU Clock)
FOUT
Programmable Frequency Output
P3.0
53
P3.1
54
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
P3.8
P3.9
P3.10
P3.11
P3.12
55
56
57
58
59
60
61
62
63
64
65
P3.13
P3.15
66
67
Data Sheet
I
O
O
I/O
I
O
I
I
I
I
I/O
I/O
O
I/O
O
O
I/O
O
O
9
V3.0, 2001-01
C161CS/JC/JI-32R
C161CS/JC/JI-L
Table 2
Pin Definitions and Functions (cont’d)
Symbol Pin
No.
Input
Outp.
Function
P4
IO
Port 4 is an 8-bit bidirectional I/O port. It is bit-wise
programmable for input or output via direction bits. For a pin
configured as input, the output driver is put into highimpedance state. The Port 4 outputs can be configured as
push/pull or open drain drivers. The input threshold of Port 4
is selectable (TTL or special).
Port 4 can be used to output the segment address lines and
for serial interface lines:1)
A16
Least Significant Segment Address Line
A17
Segment Address Line
A18
Segment Address Line
A19
Segment Address Line
A20
Segment Address Line,
CAN2_RxD CAN 2 Receive Data Input,
(C161CS)
SDL_RxD SDLM Receive Data Input
(C161JC/JI)
A21
Segment Address Line,
CAN1_RxD CAN 1 Receive Data Input,
(C161CS/JC)
A22
Segment Address Line,
CAN1_TxD CAN 1 Transmit Data Output,
(C161CS/JC)
CAN2_TxD CAN 2 Transmit Data Output,
(C161CS)
SDL_RxD SDLM Receive Data Input
(C161JC/JI)
A23
Most Significant Segment Address Line,
CAN1_RxD CAN 1 Receive Data Input,
(C161CS/JC)
CAN2_TxD CAN 2 Transmit Data Output,
(C161CS)
CAN2_RxD CAN 2 Receive Data Input,
(C161CS)
SDL_TxD SDLM Transmit Data Output
(C161JC/JI)
O
O
O
O
O
I
I
O
I
O
O
O
I
O
I
O
I
O
P4.0
P4.1
P4.2
P4.3
P4.4
70
71
72
73
74
P4.5
75
P4.6
76
P4.7
77
RD
80
O
External Memory Read Strobe. RD is activated for every
external instruction or data read access.
WR/
WRL
81
O
External Memory Write Strobe. In WR-mode this pin is
activated for every external data write access. In WRL-mode
this pin is activated for low byte data write accesses on a
16-bit bus, and for every data write access on an 8-bit bus.
See WRCFG in register SYSCON for mode selection.
Data Sheet
10
V3.0, 2001-01
C161CS/JC/JI-32R
C161CS/JC/JI-L
Table 2
Pin Definitions and Functions (cont’d)
Symbol Pin
No.
Input
Outp.
Function
READY 82
I
Ready Input. When the Ready function is enabled, a high
level at this pin during an external memory access will force
the insertion of memory cycle time waitstates until the pin
returns to a low level.
An internal pullup device will hold this pin high when nothing
is driving it.
ALE
83
O
Address Latch Enable Output. Can be used for latching the
address into external memory or an address latch in the
multiplexed bus modes.
EA
84
I
External Access Enable pin. A low level at this pin during and
after Reset forces the C161CS/JC/JI to begin instruction
execution out of external memory. A high level forces
execution out of the internal program memory.
“ROMless” versions must have this pin tied to ‘0’.
IO
PORT0 consists of the two 8-bit bidirectional I/O ports P0L
and P0H. It is bit-wise programmable for input or output via
direction bits. For a pin configured as input, the output driver
is put into high-impedance state.
In case of an external bus configuration, PORT0 serves as
the address (A) and address/data (AD) bus in multiplexed
bus modes and as the data (D) bus in demultiplexed bus
modes.
Demultiplexed bus modes:
Data Path Width:
8-bit
16-bit
P0L.0 – P0L.7:
D0 – D7
D0 - D7
P0H.0 – P0H.7:
I/O
D8 - D15
Multiplexed bus modes:
Data Path Width:
8-bit
16-bit
P0L.0 – P0L.7:
AD0 – AD7 AD0 - AD7
P0H.0 – P0H.7:
A8 - A15
AD8 - AD15
PORT0
P0L.0-7 8592
P0H.0-7 95102
Note: At the end of an external reset (EA = ‘0’) PORT0 also
inputs the configuration values.
Data Sheet
11
V3.0, 2001-01
C161CS/JC/JI-32R
C161CS/JC/JI-L
Table 2
Pin Definitions and Functions (cont’d)
Symbol Pin
No.
Input
Outp.
Function
PORT1
P1L.0-7 103110
P1H.0-7 113120
IO
P1H.4
P1H.5
P1H.6
P1H.7
117
118
119
120
I/O
I/O
I/O
I/O
PORT1 consists of the two 8-bit bidirectional I/O ports P1L
and P1H. It is bit-wise programmable for input or output via
direction bits. For a pin configured as input, the output driver
is put into high-impedance state. PORT1 is used as the
16-bit address bus (A) in demultiplexed bus modes and also
after switching from a demultiplexed bus mode to a
multiplexed bus mode.
The following PORT1 pins also serve for alternate functions:
CC24IO
CAPCOM2: CC24 Capture Inp./Compare Outp.
CC25IO
CAPCOM2: CC25 Capture Inp./Compare Outp.
CC26IO
CAPCOM2: CC26 Capture Inp./Compare Outp.
CC27IO
CAPCOM2: CC27 Capture Inp./Compare Outp.
XTAL2
XTAL1
123
124
O
I
XTAL2:
XTAL1:
XTAL3
126
I
XTAL3:
XTAL4
127
O
Data Sheet
Output of the oscillator amplifier circuit.
Input to the oscillator amplifier and input to
the internal clock generator
To clock the device from an external source, drive XTAL1,
while leaving XTAL2 unconnected. Minimum and maximum
high/low and rise/fall times specified in the AC
Characteristics must be observed.
Input to the 32-kHz oscillator amplifier and
input to the internal clock generator
XTAL4:
Output of the oscillator amplifier circuit.
To clock the device from an external source, drive XTAL3,
while leaving XTAL4 unconnected. Minimum and maximum
high/low and rise/fall times specified in the AC
Characteristics must be observed.
12
V3.0, 2001-01
C161CS/JC/JI-32R
C161CS/JC/JI-L
Table 2
Pin Definitions and Functions (cont’d)
Symbol Pin
No.
Input
Outp.
Function
RSTIN
I/O
Reset Input with Schmitt-Trigger characteristics. A low level
at this pin while the oscillator is running resets the C161CS/
JC/JI. An internal pullup resistor permits power-on reset
using only a capacitor connected to VSS.
A spike filter suppresses input pulses < 10 ns. Input pulses
> 100 ns safely pass the filter. The minimum duration for a
safe recognition should be 100 ns + 2 CPU clock cycles.
In bidirectional reset mode (enabled by setting bit BDRSTEN
in register SYSCON) the RSTIN line is internally pulled low
for the duration of the internal reset sequence upon any reset
(HW, SW, WDT). See note below this table.
128
Note: To let the reset configuration of PORT0 settle and to
let the PLL lock a reset duration of ca. 1 ms is
recommended.
VAREF
VAGND
VDD
VSS
35
–
Reference voltage for the A/D converter.
36
–
Reference ground for the A/D converter.
4, 18, –
262),
42, 52,
68, 78,
93, 111,
121
Digital Supply Voltage:
+5 V during normal operation and idle mode.
≥ 2.5 V during power down mode if RTC is off
≥ 2.7 V during power down mode if RTC is running
3, 17, –
252),
41, 51,
69, 79,
94, 112,
122,
125
Digital Ground.
1)
The CAN and/or SDLM interface lines are assigned to ports P4 and P7 under software control. Within the CAN
module or SDLM several assignments can be selected.
2)
Supply pins 25 and 26 feed the Analog/Digital Converter and should be decoupled separately.
Data Sheet
13
V3.0, 2001-01
C161CS/JC/JI-32R
C161CS/JC/JI-L
Note: The following behavioural differences must be observed when the bidirectional
reset is active:
• Bit BDRSTEN in register SYSCON cannot be changed after EINIT and is cleared
automatically after a reset.
• The reset indication flags always indicate a long hardware reset.
• The PORT0 configuration is treated as if it were a hardware reset. In particular, the
bootstrap loader may be activated when P0L.4 is low.
• Pin RSTIN may only be connected to external reset devices with an open drain output
driver.
• A short hardware reset is extended to the duration of the internal reset sequence.
Data Sheet
14
V3.0, 2001-01
C161CS/JC/JI-32R
C161CS/JC/JI-L
Functional Description
The architecture of the C161CS/JC/JI combines advantages of both RISC and CISC
processors and of advanced peripheral subsystems in a very well-balanced way. In
addition the on-chip memory blocks allow the design of compact systems with maximum
performance.
The following block diagram gives an overview of the different on-chip components and
of the advanced, high bandwidth internal bus structure of the C161CS/JC/JI.
Note: All time specifications refer to a CPU clock of 25 MHz
(see definition in the AC Characteristics section).
C166-Core
16
Data
ROM
256 KByte
32
16
CPU
Instr. / Data
Data
16
PEC
Interrupt Controller 16-Level
Priority
ASC1
RTC
CAN/SDLM
2.0B act. / Cl.B
Peripheral Data Bus
16
EBC
ADC
ASC0
SSC
10-Bit
12
Channels
(USART)
(SPI)
16
CCOM2 CCOM1
T2
T7
T0
T3
T8
T1
T4
XBUS Control
External Bus
Control
Port 0
GPT
Port 2
400 KBd, 2 Ch.
Interrupt Bus
On-Chip XBUS (16-Bit Demux)
IIC
Port 4
WDT
16
(USART)
Port 6
XTAL
External Instr. / Data
8 KByte
8
Internal
RAM
2 KByte
Osc / PLL
XRAM
8
IRAM
Dual Port
ProgMem
T5
BRGen
Port 1
16
Port 5
T6
BRGen
Port 3
12
15
Port 7
4
8
Port 9
6
MCB04323_1CSR
Figure 3
Block Diagram
The program memory, the internal RAM (IRAM) and the set of generic peripherals are
connected to the CPU via separate buses. A fourth bus, the XBUS, connects external
resources as well as additional on-chip resoures, the X-Peripherals (see Figure 3).
The XBUS resources (XRAM, CAN, SDLM, IIC, ASC1) of the C161CS/JC/JI can be
enabled during initialization by setting the general X-Peripheral enable bit XPEN
(SYSCON.2).
If the X-Peripherals remain disabled they consume neither address space nor port pins.
Data Sheet
15
V3.0, 2001-01
C161CS/JC/JI-32R
C161CS/JC/JI-L
Memory Organization
The memory space of the C161CS/JC/JI is configured in a Von Neumann architecture
which means that code memory, data memory, registers and I/O ports are organized
within the same linear address space which includes 16 MBytes. The entire memory
space can be accessed bytewise or wordwise. Particular portions of the on-chip memory
have additionally been made directly bitaddressable.
The C161CS/JC/JI incorporates 256 KBytes of on-chip mask-programmable ROM for
code or constant data. The lower 32 KBytes of the on-chip ROM can be mapped either
to segment 0 or segment 1.
2 KBytes of on-chip Internal RAM (IRAM) are provided as a storage for user defined
variables, for the system stack, general purpose register banks and even for code. A
register bank can consist of up to 16 wordwide (R0 to R15) and/or bytewide (RL0, RH0,
…, RL7, RH7) so-called General Purpose Registers (GPRs).
1024 bytes (2 × 512 bytes) of the address space are reserved for the Special Function
Register areas (SFR space and ESFR space). SFRs are wordwide registers which are
used for controlling and monitoring functions of the different on-chip units. Unused SFR
addresses are reserved for future members of the C166 Family.
8 KBytes of on-chip Extension RAM (XRAM) are provided to store user data, user
stacks, or code. The XRAM is accessed like external memory and therefore cannot be
used for the system stack or for register banks and is not bitaddressable. The XRAM
permits 16-bit accesses with maximum speed.
In order to meet the needs of designs where more memory is required than is provided
on chip, up to 16 MBytes of external RAM and/or ROM can be connected to the
microcontroller.
Data Sheet
16
V3.0, 2001-01
C161CS/JC/JI-32R
C161CS/JC/JI-L
External Bus Controller
All of the external memory accesses are performed by a particular on-chip External Bus
Controller (EBC). It can be programmed either to Single Chip Mode when no external
memory is required, or to one of four different external memory access modes, which
are as follows:
–
–
–
–
16-/18-/20-/24-bit Addresses, 16-bit Data, Demultiplexed
16-/18-/20-/24-bit Addresses, 16-bit Data, Multiplexed
16-/18-/20-/24-bit Addresses, 8-bit Data, Multiplexed
16-/18-/20-/24-bit Addresses, 8-bit Data, Demultiplexed
In the demultiplexed bus modes, addresses are output on PORT1 and data is input/
output on PORT0 or P0L, respectively. In the multiplexed bus modes both addresses
and data use PORT0 for input/output.
Important timing characteristics of the external bus interface (Memory Cycle Time,
Memory Tri-State Time, Length of ALE and Read Write Delay) have been made
programmable to allow the user the adaption of a wide range of different types of
memories and external peripherals.
In addition, up to 4 independent address windows may be defined (via register pairs
ADDRSELx / BUSCONx) which control the access to different resources with different
bus characteristics. These address windows are arranged hierarchically where
BUSCON4 overrides BUSCON3 and BUSCON2 overrides BUSCON1. All accesses to
locations not covered by these 4 address windows are controlled by BUSCON0.
Up to 5 external CS signals (4 windows plus default) can be generated in order to save
external glue logic. The C161CS/JC/JI offers the possibility to switch the CS outputs to
an unlatched mode. In this mode the internal filter logic is switched off and the CS signals
are directly generated from the address. The unlatched CS mode is enabled by setting
CSCFG (SYSCON.6).
Access to very slow memories or memories with varying access times is supported via
a particular ‘Ready’ function.
A HOLD/HLDA protocol is available for bus arbitration and allows to share external
resources with other bus masters. The bus arbitration is enabled by setting bit HLDEN
in register PSW. After setting HLDEN once, pins P6.7 … P6.5 (BREQ, HLDA, HOLD)
are automatically controlled by the EBC. In Master Mode (default after reset) the HLDA
pin is an output. By setting bit DP6.7 to ‘1’ the Slave Mode is selected where pin HLDA
is switched to input. This allows to directly connect the slave controller to another master
controller without glue logic.
For applications which require less than 16 MBytes of external memory space, this
address space can be restricted to 1 MByte, 256 KByte, or to 64 KByte. In this case
Port 4 outputs four, two, or no address lines at all. It outputs all 8 address lines, if an
address space of 16 MBytes is used.
Data Sheet
17
V3.0, 2001-01
C161CS/JC/JI-32R
C161CS/JC/JI-L
Note: When one or both of the on-chip CAN Modules or the SDLM are used with the
interface lines assigned to Port 4, the interface lines override the segment address
lines and the segment address output on Port 4 is therefore limited to 6/4 bits i.e.
address lines A21/A19 … A16. CS lines can be used to increase the total amount
of addressable external memory.
Central Processing Unit (CPU)
The main core of the CPU consists of a 4-stage instruction pipeline, a 16-bit arithmetic
and logic unit (ALU) and dedicated SFRs. Additional hardware has been spent for a
separate multiply and divide unit, a bit-mask generator and a barrel shifter.
Based on these hardware provisions, most of the C161CS/JC/JI’s instructions can be
executed in just one machine cycle which requires 80 ns at 25 MHz CPU clock. For
example, shift and rotate instructions are always processed during one machine cycle
independent of the number of bits to be shifted. All multiple-cycle instructions have been
optimized so that they can be executed very fast as well: branches in 2 cycles, a 16 × 16
bit multiplication in 5 cycles and a 32-/16-bit division in 10 cycles. Another pipeline
optimization, the so-called ‘Jump Cache’, allows reducing the execution time of
repeatedly performed jumps in a loop from 2 cycles to 1 cycle.
CPU
Internal
RAM
SP
STKOV
STKUN
MDH
MDL
R15
Exec. Unit
Instr. Ptr.
Instr. Reg.
Mul/Div-HW
Bit-Mask Gen
General
4-Stage
Pipeline
R15
Purpose
ALU
32
ROM
16
(16-bit)
Barrel - Shifter
Registers
R0
PSW
SYSCON
Context Ptr.
BUSCON 0
BUSCON 1
BUSCON 2
BUSCON 3
BUSCON 4
ADDRSEL 1
ADDRSEL 2
ADDRSEL 3
ADDRSEL 4
Data Page Ptr.
Code Seg. Ptr.
R0
16
MCB02147
Figure 4
Data Sheet
CPU Block Diagram
18
V3.0, 2001-01
C161CS/JC/JI-32R
C161CS/JC/JI-L
The CPU has a register context consisting of up to 16 wordwide GPRs at its disposal.
These 16 GPRs are physically allocated within the on-chip RAM area. A Context Pointer
(CP) register determines the base address of the active register bank to be accessed by
the CPU at any time. The number of register banks is only restricted by the available
internal RAM space. For easy parameter passing, a register bank may overlap others.
A system stack of up to 1024 words is provided as a storage for temporary data. The
system stack is allocated in the on-chip RAM area, and it is accessed by the CPU via the
stack pointer (SP) register. Two separate SFRs, STKOV and STKUN, are implicitly
compared against the stack pointer value upon each stack access for the detection of a
stack overflow or underflow.
The high performance offered by the hardware implementation of the CPU can efficiently
be utilized by a programmer via the highly efficient C161CS/JC/JI instruction set which
includes the following instruction classes:
–
–
–
–
–
–
–
–
–
–
–
–
Arithmetic Instructions
Logical Instructions
Boolean Bit Manipulation Instructions
Compare and Loop Control Instructions
Shift and Rotate Instructions
Prioritize Instruction
Data Movement Instructions
System Stack Instructions
Jump and Call Instructions
Return Instructions
System Control Instructions
Miscellaneous Instructions
The basic instruction length is either 2 or 4 bytes. Possible operand types are bits, bytes
and words. A variety of direct, indirect or immediate addressing modes are provided to
specify the required operands.
Data Sheet
19
V3.0, 2001-01
C161CS/JC/JI-32R
C161CS/JC/JI-L
Interrupt System
With an interrupt response time within a range from just 5 to 12 CPU clocks (in case of
internal program execution), the C161CS/JC/JI is capable of reacting very fast to the
occurrence of non-deterministic events.
The architecture of the C161CS/JC/JI supports several mechanisms for fast and flexible
response to service requests that can be generated from various sources internal or
external to the microcontroller. Any of these interrupt requests can be programmed to
being serviced by the Interrupt Controller or by the Peripheral Event Controller (PEC).
In contrast to a standard interrupt service where the current program execution is
suspended and a branch to the interrupt vector table is performed, just one cycle is
‘stolen’ from the current CPU activity to perform a PEC service. A PEC service implies
a single byte or word data transfer between any two memory locations with an additional
increment of either the PEC source or the destination pointer. An individual PEC transfer
counter is implicity decremented for each PEC service except when performing in the
continuous transfer mode. When this counter reaches zero, a standard interrupt is
performed to the corresponding source related vector location. PEC services are very
well suited, for example, for supporting the transmission or reception of blocks of data.
The C161CS/JC/JI has 8 PEC channels each of which offers such fast interrupt-driven
data transfer capabilities.
A separate control register which contains an interrupt request flag, an interrupt enable
flag and an interrupt priority bitfield exists for each of the possible interrupt sources. Via
its related register, each source can be programmed to one of sixteen interrupt priority
levels. Once having been accepted by the CPU, an interrupt service can only be
interrupted by a higher prioritized service request. For the standard interrupt processing,
each of the possible interrupt sources has a dedicated vector location.
Fast external interrupt inputs are provided to service external interrupts with high
precision requirements. These fast interrupt inputs feature programmable edge
detection (rising edge, falling edge or both edges).
Software interrupts are supported by means of the ‘TRAP’ instruction in combination with
an individual trap (interrupt) number.
Table 3 shows all of the possible C161CS/JC/JI interrupt sources and the corresponding
hardware-related interrupt flags, vectors, vector locations and trap (interrupt) numbers.
Note: Interrupt nodes which are not used by associated peripherals, may be used to
generate software controlled interrupt requests by setting the respective interrupt
request bit (xIR).
Data Sheet
20
V3.0, 2001-01
C161CS/JC/JI-32R
C161CS/JC/JI-L
Table 3
C161CS/JC/JI Interrupt Nodes
Source of Interrupt or Request
PEC Service Request Flag
Enable
Flag
Interrupt
Vector
Vector
Location
Trap
Number
CAPCOM Register 0
CC0IR
CC0IE
CC0INT
00’0040H
10H
CAPCOM Register 1
CC1IR
CC1IE
CC1INT
00’0044H
11H
CAPCOM Register 2
CC2IR
CC2IE
CC2INT
00’0048H
12H
CAPCOM Register 3
CC3IR
CC3IE
CC3INT
00’004CH
13H
CAPCOM Register 4
CC4IR
CC4IE
CC4INT
00’0050H
14H
CAPCOM Register 5
CC5IR
CC5IE
CC5INT
00’0054H
15H
CAPCOM Register 6
CC6IR
CC6IE
CC6INT
00’0058H
16H
CAPCOM Register 7
CC7IR
CC7IE
CC7INT
00’005CH
17H
CAPCOM Register 8
CC8IR
CC8IE
CC8INT
00’0060H
18H
CAPCOM Register 9
CC9IR
CC9IE
CC9INT
00’0064H
19H
CAPCOM Register 10
CC10IR
CC10IE
CC10INT
00’0068H
1AH
CAPCOM Register 11
CC11IR
CC11IE
CC11INT
00’006CH
1BH
CAPCOM Register 12
CC12IR
CC12IE
CC12INT
00’0070H
1CH
CAPCOM Register 13
CC13IR
CC13IE
CC13INT
00’0074H
1DH
CAPCOM Register 14
CC14IR
CC14IE
CC14INT
00’0078H
1EH
CAPCOM Register 15
CC15IR
CC15IE
CC15INT
00’007CH
1FH
CAPCOM Register 16
CC16IR
CC16IE
CC16INT
00’00C0H
30H
CAPCOM Register 17
CC17IR
CC17IE
CC17INT
00’00C4H
31H
CAPCOM Register 18
CC18IR
CC18IE
CC18INT
00’00C8H
32H
CAPCOM Register 19
CC19IR
CC19IE
CC19INT
00’00CCH
33H
CAPCOM Register 20
CC20IR
CC20IE
CC20INT
00’00D0H
34H
CAPCOM Register 21
CC21IR
CC21IE
CC21INT
00’00D4H
35H
CAPCOM Register 22
CC22IR
CC22IE
CC22INT
00’00D8H
36H
CAPCOM Register 23
CC23IR
CC23IE
CC23INT
00’00DCH
37H
CAPCOM Register 24
CC24IR
CC24IE
CC24INT
00’00E0H
38H
CAPCOM Register 25
CC25IR
CC25IE
CC25INT
00’00E4H
39H
CAPCOM Register 26
CC26IR
CC26IE
CC26INT
00’00E8H
3AH
CAPCOM Register 27
CC27IR
CC27IE
CC27INT
00’00ECH
3BH
CAPCOM Register 28
CC28IR
CC28IE
CC28INT
00’00E0H
3CH
CAPCOM Register 29
CC29IR
CC29IE
CC29INT
00’0110H
44H
Data Sheet
21
V3.0, 2001-01
C161CS/JC/JI-32R
C161CS/JC/JI-L
Table 3
C161CS/JC/JI Interrupt Nodes (cont’d)
Source of Interrupt or Request
PEC Service Request Flag
Enable
Flag
Interrupt
Vector
Vector
Location
Trap
Number
CAPCOM Register 30
CC30IR
CC30IE
CC30INT
00’0114H
45H
CAPCOM Register 31
CC31IR
CC31IE
CC31INT
00’0118H
46H
CAPCOM Timer 0
T0IR
T0IE
T0INT
00’0080H
20H
CAPCOM Timer 1
T1IR
T1IE
T1INT
00’0084H
21H
CAPCOM Timer 7
T7IR
T7IE
T7INT
00’00F4H
3DH
CAPCOM Timer 8
T8IR
T8IE
T8INT
00’00F8H
3EH
GPT1 Timer 2
T2IR
T2IE
T2INT
00’0088H
22H
GPT1 Timer 3
T3IR
T3IE
T3INT
00’008CH
23H
GPT1 Timer 4
T4IR
T4IE
T4INT
00’0090H
24H
GPT2 Timer 5
T5IR
T5IE
T5INT
00’0094H
25H
GPT2 Timer 6
T6IR
T6IE
T6INT
00’0098H
26H
GPT2 CAPREL Reg.
CRIR
CRIE
CRINT
00’009CH
27H
A/D Conversion Compl. ADCIR
ADCIE
ADCINT
00’00A0H
28H
A/D Overrun Error
ADEIR
ADEIE
ADEINT
00’00A4H
29H
ASC0 Transmit
S0TIR
S0TIE
S0TINT
00’00A8H
2AH
ASC0 Transmit Buffer
S0TBIR
S0TBIE
S0TBINT
00’011CH
47H
ASC0 Receive
S0RIR
S0RIE
S0RINT
00’00ACH
2BH
ASC0 Error
S0EIR
S0EIE
S0EINT
00’00B0H
2CH
SSC Transmit
SCTIR
SCTIE
SCTINT
00’00B4H
2DH
SSC Receive
SCRIR
SCRIE
SCRINT
00’00B8H
2EH
SSC Error
SCEIR
SCEIE
SCEINT
00’00BCH
2FH
IIC Data Transfer Event XP0IR
XP0IE
XP0INT
00’0100H
40H
IIC Protocol Event
XP1IR
XP1IE
XP1INT
00’0104H
41H
CAN1 (C161CS/JC)
XP2IR
XP2IE
XP2INT
00’0108H
42H
PLL/OWD and RTC
XP3IR
XP3IE
XP3INT
00’010CH
43H
ASC1 Transmit
XP4IR
XP4IE
XP4INT
00’0120H
48H
ASC1 Receive
XP5IR
XP5IE
XP5INT
00’0124H
49H
ASC1 Error
XP6IR
XP6IE
XP6INT
00’0128H
4AH
CAN2 (C161CS) or
SDLM (C161JC/JI)
XP7IR
XP7IE
XP7INT
00’012CH
4BH
Data Sheet
22
V3.0, 2001-01
C161CS/JC/JI-32R
C161CS/JC/JI-L
The C161CS/JC/JI also provides an excellent mechanism to identify and to process
exceptions or error conditions that arise during run-time, so-called ‘Hardware Traps’.
Hardware traps cause immediate non-maskable system reaction which is similar to a
standard interrupt service (branching to a dedicated vector table location). The
occurence of a hardware trap is additionally signified by an individual bit in the trap flag
register (TFR). Except when another higher prioritized trap service is in progress, a
hardware trap will interrupt any actual program execution. In turn, hardware trap services
can normally not be interrupted by standard or PEC interrupts.
Table 4 shows all of the possible exceptions or error conditions that can arise during runtime:
Table 4
Hardware Trap Summary
Exception Condition
Trap
Flag
Reset Functions:
Hardware Reset
Software Reset
W-dog Timer Overflow
–
Class A Hardware Traps:
Non-Maskable Interrupt NMI
Stack Overflow
STKOF
Stack Underflow
STKUF
Class B Hardware Traps:
Undefined Opcode
Protected Instruction
Fault
Illegal Word Operand
Access
Illegal Instruction
Access
Illegal External Bus
Access
Trap
Vector
Vector
Location
Trap
Number
Trap
Priority
RESET
RESET
RESET
00’0000H
00’0000H
00’0000H
00H
00H
00H
III
III
III
NMITRAP 00’0008H
STOTRAP 00’0010H
STUTRAP 00’0018H
02H
04H
06H
II
II
II
UNDOPC BTRAP
PRTFLT BTRAP
00’0028H
00’0028H
0AH
0AH
I
I
ILLOPA
BTRAP
00’0028H
0AH
I
ILLINA
ILLBUS
BTRAP
BTRAP
00’0028H
00’0028H
0AH
0AH
I
I
Reserved
–
–
[2CH –
3CH]
[0BH –
0FH]
–
Software Traps
TRAP Instruction
–
–
Any
Any
[00’0000H – [00H –
00’01FCH] 7FH]
in steps
of 4H
Data Sheet
23
Current
CPU
Priority
V3.0, 2001-01
C161CS/JC/JI-32R
C161CS/JC/JI-L
Capture/Compare (CAPCOM) Units
The CAPCOM units support generation and control of timing sequences on up to
32 channels with a maximum resolution of 16 TCL. The CAPCOM units are typically
used to handle high speed I/O tasks such as pulse and waveform generation, pulse
width modulation (PMW), Digital to Analog (D/A) conversion, software timing, or time
recording relative to external events.
Four 16-bit timers (T0/T1, T7/T8) with reload registers provide two independent time
bases for the capture/compare register array.
The input clock for the timers is programmable to several prescaled values of the internal
system clock, or may be derived from an overflow/underflow of timer T6 in module
GPT2. This provides a wide range of variation for the timer period and resolution and
allows precise adjustments to the application specific requirements. In addition, external
count inputs for CAPCOM timers T0 and T7 allow event scheduling for the capture/
compare registers relative to external events.
Both of the two capture/compare register arrays contain 16 dual purpose capture/
compare registers, each of which may be individually allocated to either CAPCOM timer
T0 or T1 (T7 or T8, respectively), and programmed for capture or compare function.
Eight registers of each module have one port pin associated with it which serves as an
input pin for triggering the capture function, or as an output pin to indicate the occurrence
of a compare event.
When a capture/compare register has been selected for capture mode, the current
contents of the allocated timer will be latched (‘captured’) into the capture/compare
register in response to an external event at the port pin which is associated with this
register. In addition, a specific interrupt request for this capture/compare register is
generated. Either a positive, a negative, or both a positive and a negative external signal
transition at the pin can be selected as the triggering event.
The contents of all registers which have been selected for one of the five compare
modes are continuously compared with the contents of the allocated timers.
Table 5
Compare Modes (CAPCOM)
Compare Modes
Function
Mode 0
Interrupt-only compare mode;
several compare interrupts per timer period are possible
Mode 1
Pin toggles on each compare match;
several compare events per timer period are possible
Mode 2
Interrupt-only compare mode;
only one compare interrupt per timer period is generated
Mode 3
Pin set ‘1’ on match; pin reset ‘0’ on compare time overflow;
only one compare event per timer period is generated
Data Sheet
24
V3.0, 2001-01
C161CS/JC/JI-32R
C161CS/JC/JI-L
When a match occurs between the timer value and the value in a capture/compare
register, specific actions will be taken based on the selected compare mode.
Reload Reg. TxREL
fCPU
2n : 1
TxIN
Tx
Input
Control
CAPCOM Timer Tx
Mode
Control
(Capture
or
Compare)
16-Bit
Capture/
Compare
Registers
Ty
Input
Control
CAPCOM Timer Ty
Interrupt
Request
GPT2 Timer T6
Over/Underflow
CCxIO
8 Capture Inputs
8 Compare Outputs
16 Capture/Compare
Interrupt Request
CCxIO
fCPU
GPT2 Timer T6
Over/Underflow
2n : 1
x = 0, 7
y = 1, 8
n = 3 … 10
Figure 5
Data Sheet
Interrupt
Request
Reload Reg. TyREL
MCB02143c
CAPCOM Unit Block Diagram
25
V3.0, 2001-01
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C161CS/JC/JI-L
General Purpose Timer (GPT) Unit
The GPT unit represents a very flexible multifunctional timer/counter structure which
may be used for many different time related tasks such as event timing and counting,
pulse width and duty cycle measurements, pulse generation, or pulse multiplication.
The GPT unit incorporates five 16-bit timers which are organized in two separate
modules, GPT1 and GPT2. Each timer in each module may operate independently in a
number of different modes, or may be concatenated with another timer of the same
module.
Each of the three timers T2, T3, T4 of module GPT1 can be configured individually for
one of four basic modes of operation, which are Timer, Gated Timer, Counter, and
Incremental Interface Mode. In Timer Mode, the input clock for a timer is derived from
the CPU clock, divided by a programmable prescaler, while Counter Mode allows a timer
to be clocked in reference to external events.
Pulse width or duty cycle measurement is supported in Gated Timer Mode, where the
operation of a timer is controlled by the ‘gate’ level on an external input pin. For these
purposes, each timer has one associated port pin (TxIN) which serves as gate or clock
input. The maximum resolution of the timers in module GPT1 is 16 TCL.
The count direction (up/down) for each timer is programmable by software or may
additionally be altered dynamically by an external signal on a port pin (TxEUD) to
facilitate e.g. position tracking.
In Incremental Interface Mode the GPT1 timers (T2, T3, T4) can be directly connected
to the incremental position sensor signals A and B via their respective inputs TxIN and
TxEUD. Direction and count signals are internally derived from these two input signals,
so the contents of the respective timer Tx corresponds to the sensor position. The third
position sensor signal TOP0 can be connected to an interrupt input.
Timer T3 has an output toggle latch (T3OTL) which changes its state on each timer overflow/underflow. The state of this latch may be output on pin T3OUT e.g. for time out
monitoring of external hardware components, or may be used internally to clock timers
T2 and T4 for measuring long time periods with high resolution.
In addition to their basic operating modes, timers T2 and T4 may be configured as reload
or capture registers for timer T3. When used as capture or reload registers, timers T2
and T4 are stopped. The contents of timer T3 is captured into T2 or T4 in response to a
signal at their associated input pins (TxIN). Timer T3 is reloaded with the contents of T2
or T4 triggered either by an external signal or by a selectable state transition of its toggle
latch T3OTL. When both T2 and T4 are configured to alternately reload T3 on opposite
state transitions of T3OTL with the low and high times of a PWM signal, this signal can
be constantly generated without software intervention.
Data Sheet
26
V3.0, 2001-01
C161CS/JC/JI-32R
C161CS/JC/JI-L
T2EUD
fCPU
U/D
2n : 1
T2IN
Interrupt
Request
(T2IR)
GPT1 Timer T2
T2
Mode
Control
Reload
Capture
fCPU
Interrupt
Request
(T3IR)
2n : 1
Toggle FF
T3
Mode
Control
T3IN
GPT1 Timer T3
T3OTL
T3OUT
U/D
T3EUD
Capture
Reload
T4IN
fCPU
2n : 1
T4
Mode
Control
GPT1 Timer T4
Interrupt
Request
(T4IR)
U/D
T4EUD
MCT04825
n = 3 … 10
Figure 6
Block Diagram of GPT1
With its maximum resolution of 8 TCL, the GPT2 module provides precise event control
and time measurement. It includes two timers (T5, T6) and a capture/reload register
(CAPREL). Both timers can be clocked with an input clock which is derived from the CPU
clock via a programmable prescaler or with external signals. The count direction (up/
down) for each timer is programmable by software or may additionally be altered
dynamically by an external signal on a port pin (TxEUD). Concatenation of the timers is
supported via the output toggle latch (T6OTL) of timer T6, which changes its state on
each timer overflow/underflow.
The state of this latch may be used to clock timer T5, and/or it may be output on pin
T6OUT. The overflows/underflows of timer T6 can additionally be used to clock the
CAPCOM timers T0 or T1, and to cause a reload from the CAPREL register. The
CAPREL register may capture the contents of timer T5 based on an external signal
transition on the corresponding port pin (CAPIN), and timer T5 may optionally be cleared
Data Sheet
27
V3.0, 2001-01
C161CS/JC/JI-32R
C161CS/JC/JI-L
after the capture procedure. This allows the C161CS/JC/JI to measure absolute time
differences or to perform pulse multiplication without software overhead.
The capture trigger (timer T5 to CAPREL) may also be generated upon transitions of
GPT1 timer T3’s inputs T3IN and/or T3EUD. This is especially advantageous when T3
operates in Incremental Interface Mode.
fCPU
2n : 1
T5IN
T5
Mode
Control
U/D
Interrupt
Request
(T5IR)
GPT2 Timer T5
Clear
Capture
Interrupt
Request
(CRIR)
T3
MUX
CAPIN
GPT2 CAPREL
Interrupt
Request
(T6IR)
CT3
GPT2 Timer T6
T6IN
fCPU
2n :
1
U/D
T6
Mode
Control
T6OTL
T6OUT
To auxiliary
Timers
To other
Modules
mcb03999b.vsd
n=2…9
Figure 7
Data Sheet
Block Diagram of GPT2
28
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C161CS/JC/JI-L
Real Time Clock
The Real Time Clock (RTC) module of the C161CS/JC/JI consists of a chain of 3 divider
blocks, a fixed 8:1 divider, the reloadable 16-bit timer T14, and the 32-bit RTC timer
(accessible via registers RTCH and RTCL). The RTC module is directly clocked via a
separate clock driver with the on-chip main oscillator frequency divided by 32
(fRTC = fOSCm / 32) or with the on-chip auxiliary oscillator frequency (fRTC = fOSCa). It is
therefore independent from the selected clock generation mode of the C161CS/JC/JI.
All timers count up.
The RTC module can be used for different purposes:
• System clock to determine the current time and date
• Cyclic time based interrupt
• 48-bit timer for long term measurements
T14REL
Reload
T14
8:1
f RTC
Interrupt
Request
RTCH
RTCL
MCD04432
Figure 8
RTC Block Diagram
Note: The registers associated with the RTC are not affected by a reset in order to
maintain the correct system time even when intermediate resets are executed.
Data Sheet
29
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C161CS/JC/JI-32R
C161CS/JC/JI-L
A/D Converter
For analog signal measurement, a 10-bit A/D converter with 12 multiplexed input
channels and a sample and hold circuit has been integrated on-chip. It uses the method
of successive approximation. The sample time (for loading the capacitors) and the
conversion time is programmable and can so be adjusted to the external circuitry.
Overrun error detection/protection is provided for the conversion result register
(ADDAT): either an interrupt request will be generated when the result of a previous
conversion has not been read from the result register at the time the next conversion is
complete, or the next conversion is suspended in such a case until the previous result
has been read.
For applications which require less than 12 analog input channels, the remaining
channel inputs can be used as digital input port pins.
The A/D converter of the C161CS/JC/JI supports four different conversion modes. In the
standard Single Channel conversion mode, the analog level on a specified channel is
sampled once and converted to a digital result. In the Single Channel Continuous mode,
the analog level on a specified channel is repeatedly sampled and converted without
software intervention. In the Auto Scan mode, the analog levels on a prespecified
number of channels (standard or extension) are sequentially sampled and converted. In
the Auto Scan Continuous mode, the number of prespecified channels is repeatedly
sampled and converted. In addition, the conversion of a specific channel can be inserted
(injected) into a running sequence without disturbing this sequence. This is called
Channel Injection Mode.
The Peripheral Event Controller (PEC) may be used to automatically store the
conversion results into a table in memory for later evaluation, without requiring the
overhead of entering and exiting interrupt routines for each data transfer.
After each reset and also during normal operation the ADC automatically performs
calibration cycles. This automatic self-calibration constantly adjusts the converter to
changing operating conditions (e.g. temperature) and compensates process variations.
These calibration cycles are part of the conversion cycle, so they do not affect the normal
operation of the A/D converter.
In order to decouple analog inputs from digital noise and to avoid input trigger noise
those pins used for analog input can be disconnected from the digital IO or input stages
under software control. This can be selected for each pin separately via register
P5DIDIS (Port 5 Digital Input Disable).
Data Sheet
30
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C161CS/JC/JI-L
Serial Channels
Serial communication with other microcontrollers, processors, terminals or external
peripheral components is provided by three serial interfaces with different functionality,
two Asynchronous/Synchronous Serial Channels (ASC0/ASC1) and a High-Speed
Synchronous Serial Channel (SSC).
The ASC0 is upward compatible with the serial ports of the Infineon 8-bit microcontroller
families and supports full-duplex asynchronous communication at up to 781 kBaud and
half-duplex synchronous communication at up to 3.1 MBaud (@ 25 MHz CPU clock).
A dedicated baud rate generator allows to set up all standard baud rates without
oscillator tuning. For transmission, reception and error handling 4 separate interrupt
vectors are provided. In asynchronous mode, 8- or 9-bit data frames are transmitted or
received, preceded by a start bit and terminated by one or two stop bits. For
multiprocessor communication, a mechanism to distinguish address from data bytes has
been included (8-bit data plus wake up bit mode).
In synchronous mode, the ASC0 transmits or receives bytes (8 bits) synchronously to a
shift clock which is generated by the ASC0. The ASC0 always shifts the LSB first. A loop
back option is available for testing purposes.
A number of optional hardware error detection capabilities has been included to increase
the reliability of data transfers. A parity bit can automatically be generated on
transmission or be checked on reception. Framing error detection allows to recognize
data frames with missing stop bits. An overrun error will be generated, if the last
character received has not been read out of the receive buffer register at the time the
reception of a new character is complete.
The ASC1 is function compatible with the ASC0, except that its registers are not bitaddressable (XBUS peripheral) and it provides only three interrupt vectors.
The SSC supports full-duplex synchronous communication at up to 6.25 MBaud
(@ 25 MHz CPU clock). It may be configured so it interfaces with serially linked
peripheral components. A dedicated baud rate generator allows to set up all standard
baud rates without oscillator tuning. For transmission, reception and error handling three
separate interrupt vectors are provided.
The SSC transmits or receives characters of 2 … 16 bits length synchronously to a shift
clock which can be generated by the SSC (master mode) or by an external master (slave
mode). The SSC can start shifting with the LSB or with the MSB and allows the selection
of shifting and latching clock edges as well as the clock polarity.
A number of optional hardware error detection capabilities has been included to increase
the reliability of data transfers. Transmit and receive error supervise the correct handling
of the data buffer. Phase and baudrate error detect incorrect serial data.
Data Sheet
31
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C161CS/JC/JI-L
Serial Data Link Module (SDLM)
The Serial Data Link Module (SDLM) provides serial communication via a J1850 type
multiplexed serial bus via an external J1850 bus transceiver. The module conforms to
the SAE Class B J1850 specification for variable pulse width modulation (VPW). The
SDLM is integrated as an on-chip peripheral and is connected to the CPU via the XBUS.
General SDLM Features:
•
•
•
•
•
•
•
•
•
•
•
Compliant to the SAE Class B J1850 specification (VPW)
Class 2 protocol fully supported
Variable Pulse Width (VPW) operation at 10.4 kBaud
High Speed 4X operation at 41.6 kBaud
Programmable Normalization Bit
Programmable Delay for transceiver interface
Digital Noise Filter
Power Down mode with automatic wakeup support upon bus activity
Single Byte Header and Consolidated Header supported
CRC generation and checking
Receive and transmit Block Mode
Data Link Operation Features:
•
•
•
•
•
11 Byte Transmit Buffer
Double buffered 11 Byte receive buffer (optional overwrite enable)
Support for In Frame Response (IFR) types 1, 2 and 3
Transmit and Receiver Message Buffers configurable for either FIFO or Byte mode
Advanced Interrupt Handling with 8 separately enabled sources:
Error, format or bus shorted
CRC error
Lost Arbitration
Break received
In-Frame-Response request
Header received
Complete message received
Transmit successful
• Automatic IFR transmission (Types 1 and 2) for 3-Byte consolidated headers
• User configurable clock divider
• Bus status flags (IDLE, EOF, EOD, SOF, Tx and Rx in progress)
Note: When the SDLM is used with the interface lines assigned to Port 4, the interface
lines override the segment address lines and the segment address output on
Port 4 is therefore limited to 6/4 bits i.e. address lines A21/A19 … A16. CS lines
can be used to increase the total amount of addressable external memory.
Data Sheet
32
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C161CS/JC/JI-L
CAN-Modules
The integrated CAN-Modules handle the completely autonomous transmission and
reception of CAN frames in accordance with the CAN specification V2.0 part B (active),
i.e. the on-chip CAN-Modules can receive and transmit standard frames with 11-bit
identifiers as well as extended frames with 29-bit identifiers.
The modules provide Full CAN functionality on up to 15 message objects each.
Message object 15 may be configured for Basic CAN functionality. Both modes provide
separate masks for acceptance filtering which allows to accept a number of identifiers in
Full CAN mode and also allows to disregard a number of identifiers in Basic CAN mode.
All message objects can be updated independent from the other objects and are
equipped for the maximum message length of 8 bytes.
The bit timing is derived from the XCLK and is programmable up to a data rate of
1 MBaud. Each CAN-Module uses two pins of Port 4 or Port 8 to interface to an external
bus transceiver. The interface pins are assigned via software.
Module CAN2 (C161CS only) is identical with the first one, except that it uses a separate
address area and a separate interrupt node.
The two CAN modules can be internally coupled by assigning their interface pins to the
same two port pins, or they can interface to separate CAN buses.
Note: When one or both of the on-chip CAN Modules are used with the interface lines
assigned to Port 4, the interface lines override the segment address lines and the
segment address output on Port 4 is therefore limited to 6/4 bits i.e. address lines
A21/A19 … A16. CS lines can be used to increase the total amount of addressable
external memory.
IIC Module
The integrated IIC Bus Module handles the transmission and reception of frames over
the two-line IIC bus in accordance with the IIC Bus specification. The on-chip IIC Module
can receive and transmit data using 7-bit or 10-bit addressing and it can operate in slave
mode, in master mode or in multi-master mode.
Several physical interfaces (port pins) can be established under software control. Data
can be transferred at speeds up to 400 kbit/sec.
Two interrupt nodes dedicated to the IIC module allow efficient interrupt service and also
support operation via PEC transfers.
Note: The port pins associated with the IIC interfaces feature open drain drivers only, as
required by the IIC specification.
Data Sheet
33
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C161CS/JC/JI-L
Parallel Ports
The C161CS/JC/JI provides up to 93 I/O lines which are organized into eight input/output
ports and one input port. All port lines are bit-addressable, and all input/output lines are
individually (bit-wise) programmable as inputs or outputs via direction registers. The I/O
ports are true bidirectional ports which are switched to high impedance state when
configured as inputs. The output drivers of five I/O ports can be configured (pin by pin)
for push/pull operation or open-drain operation via control registers, Port 9 provides
open-drain-only drivers. During the internal reset, all port pins are configured as inputs.
The input threshold of Port 2, Port 3, Port 4, Port 6, and Port 7 is selectable (TTL or
CMOS like), where the special CMOS like input threshold reduces noise sensitivity due
to the input hysteresis. The input threshold may be selected individually for each byte of
the respective ports.
All port lines have programmable alternate input or output functions associated with
them. All port lines that are not used for these alternate functions may be used as
general purpose IO lines.
PORT0 and PORT1 may be used as address and data lines when accessing external
memory, while Port 4 outputs the additional segment address bits A23/19/17 … A16 in
systems where segmentation is enabled to access more than 64 KBytes of memory.
Port 2, Port 7, and parts of PORT1 are associated with the capture inputs or compare
outputs of the CAPCOM units.
Port 6 provides optional bus arbitration signals (BREQ, HLDA, HOLD) and chip select
signals.
Port 3 includes alternate functions of timers, serial interfaces, the optional bus control
signal BHE, and the system clock output CLKOUT (or the programmable frequency
output FOUT).
Port 5 is used for the analog input channels to the A/D converter or timer control signals.
The edge characteristics (transition time) and driver characteristics (output current) of
the C161CS/JC/JI’s port drivers can be selected via the Port Output Control registers
(POCONx).
Data Sheet
34
V3.0, 2001-01
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C161CS/JC/JI-L
Watchdog Timer
The Watchdog Timer represents one of the fail-safe mechanisms which have been
implemented to prevent the controller from malfunctioning for longer periods of time.
The Watchdog Timer is always enabled after a reset of the chip, and can only be
disabled in the time interval until the EINIT (end of initialization) instruction has been
executed. Thus, the chip’s start-up procedure is always monitored. The software has to
be designed to service the Watchdog Timer before it overflows. If, due to hardware or
software related failures, the software fails to do so, the Watchdog Timer overflows and
generates an internal hardware reset and pulls the RSTOUT pin low in order to allow
external hardware components to be reset.
The Watchdog Timer is a 16-bit timer, clocked with the system clock divided by 2/4/128/
256. The high byte of the Watchdog Timer register can be set to a prespecified reload
value (stored in WDTREL) in order to allow further variation of the monitored time
interval. Each time it is serviced by the application software, the high byte of the
Watchdog Timer is reloaded. Thus, time intervals between 20 µs and 671 ms can be
monitored (@ 25 MHz).
The default Watchdog Timer interval after reset is 5.24 ms (@ 25 MHz).
Oscillator Watchdog
The Oscillator Watchdog (OWD) monitors the clock signal generated by the on-chip
oscillator (either with a crystal or via external clock drive). For this operation the PLL
provides a clock signal which is used to supervise transitions on the oscillator clock. This
PLL clock is independent from the XTAL1 clock. When the expected oscillator clock
transitions are missing the OWD activates the PLL Unlock / OWD interrupt node and
supplies the CPU with the PLL clock signal. Under these circumstances the PLL will
oscillate with its basic frequency.
In direct drive mode the PLL base frequency is used directly (fCPU = 2 … 5 MHz).
In prescaler mode the PLL base frequency is divided by 2 (fCPU = 1 … 2.5 MHz).
Note: The CPU clock source is only switched back to the oscillator clock after a
hardware reset.
The oscillator watchdog can be disabled by setting bit OWDDIS in register SYSCON.
In this case (OWDDIS = ‘1’) the PLL remains idle and provides no clock signal, while the
CPU clock signal is derived directly from the oscillator clock or via prescaler or SDD. Also
no interrupt request will be generated in case of a missing oscillator clock.
Note: At the end of an external reset (EA = ‘0’) bit OWDDIS reflects the inverted level of
pin RD at that time. Thus the oscillator watchdog may also be disabled via
hardware by (externally) pulling the RD line low upon a reset, similar to the
standard reset configuration via PORT0. At the end of an internal reset (EA = ‘1’)
bit OWDDIS is cleared.
Data Sheet
35
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C161CS/JC/JI-L
Power Management
The C161CS/JC/JI provides several means to control the power it consumes either at a
given time or averaged over a certain timespan. Three mechanisms can be used (partly
in parallel):
• Power Saving Modes switch the C161CS/JC/JI into a special operating mode
(control via instructions).
Idle Mode stops the CPU while the peripherals can continue to operate.
Sleep Mode and Power Down Mode stop all clock signals and all operation (RTC may
optionally continue running). Sleep Mode can be terminated by external interrupt
signals.
• Clock Generation Management controls the distribution and the frequency of
internal and external clock signals (control via register SYSCON2).
Slow Down Mode lets the C161CS/JC/JI run at a CPU clock frequency of fOSC /
1 … 32 (half for prescaler operation) which drastically reduces the consumed power.
The PLL can be optionally disabled while operating in Slow Down Mode.
External circuitry can be controlled via the programmable frequency output FOUT.
• Peripheral Management permits temporary disabling of peripheral modules (control
via register SYSCON3).
Each peripheral can separately be disabled/enabled. A group control option disables
a major part of the peripheral set by setting one single bit.
The on-chip RTC supports intermittend operation of the C161CS/JC/JI by generating
cyclic wakeup signals. This offers full performance to quickly react on action requests
while the intermittend sleep phases greatly reduce the average power consumption of
the system.
Data Sheet
36
V3.0, 2001-01
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C161CS/JC/JI-L
Instruction Set Summary
Table 6 lists the instructions of the C161CS/JC/JI in a condensed way.
The various addressing modes that can be used with a specific instruction, the operation
of the instructions, parameters for conditional execution of instructions, and the opcodes
for each instruction can be found in the “C166 Family Instruction Set Manual”.
This document also provides a detailled description of each instruction.
Table 6
Mnemonic
ADD(B)
ADDC(B)
SUB(B)
SUBC(B)
MUL(U)
DIV(U)
DIVL(U)
CPL(B)
NEG(B)
AND(B)
OR(B)
XOR(B)
BCLR
BSET
BMOV(N)
BAND, BOR,
BXOR
BCMP
BFLDH/L
CMP(B)
CMPD1/2
CMPI1/2
PRIOR
SHL / SHR
ROL / ROR
ASHR
Data Sheet
Instruction Set Summary
Description
Add word (byte) operands
Add word (byte) operands with Carry
Subtract word (byte) operands
Subtract word (byte) operands with Carry
(Un)Signed multiply direct GPR by direct GPR (16-16-bit)
(Un)Signed divide register MDL by direct GPR (16-/16-bit)
(Un)Signed long divide reg. MD by direct GPR (32-/16-bit)
Complement direct word (byte) GPR
Negate direct word (byte) GPR
Bitwise AND, (word/byte operands)
Bitwise OR, (word/byte operands)
Bitwise XOR, (word/byte operands)
Clear direct bit
Set direct bit
Move (negated) direct bit to direct bit
AND/OR/XOR direct bit with direct bit
Bytes
2/4
2/4
2/4
2/4
2
2
2
2
2
2/4
2/4
2/4
2
2
4
4
Compare direct bit to direct bit
Bitwise modify masked high/low byte of bit-addressable
direct word memory with immediate data
Compare word (byte) operands
Compare word data to GPR and decrement GPR by 1/2
Compare word data to GPR and increment GPR by 1/2
Determine number of shift cycles to normalize direct
word GPR and store result in direct word GPR
Shift left/right direct word GPR
Rotate left/right direct word GPR
Arithmetic (sign bit) shift right direct word GPR
4
4
37
2/4
2/4
2/4
2
2
2
2
V3.0, 2001-01
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C161CS/JC/JI-L
Table 6
Instruction Set Summary (cont’d)
Mnemonic
MOV(B)
MOVBS
MOVBZ
JMPA, JMPI,
JMPR
JMPS
J(N)B
JBC
JNBS
CALLA, CALLI,
CALLR
CALLS
PCALL
TRAP
PUSH, POP
SCXT
RET
RETS
RETP
RETI
SRST
IDLE
PWRDN
SRVWDT
DISWDT
EINIT
ATOMIC
EXTR
EXTP(R)
EXTS(R)
NOP
Data Sheet
Description
Move word (byte) data
Move byte operand to word operand with sign extension
Move byte operand to word operand. with zero extension
Jump absolute/indirect/relative if condition is met
Bytes
2/4
2/4
2/4
4
Jump absolute to a code segment
Jump relative if direct bit is (not) set
Jump relative and clear bit if direct bit is set
Jump relative and set bit if direct bit is not set
Call absolute/indirect/relative subroutine if condition is met
4
4
4
4
4
Call absolute subroutine in any code segment
Push direct word register onto system stack and call
absolute subroutine
Call interrupt service routine via immediate trap number
Push/pop direct word register onto/from system stack
Push direct word register onto system stack and update
register with word operand
Return from intra-segment subroutine
Return from inter-segment subroutine
Return from intra-segment subroutine and pop direct
word register from system stack
Return from interrupt service subroutine
Software Reset
Enter Idle Mode
Enter Power Down Mode (supposes NMI-pin being low)
Service Watchdog Timer
Disable Watchdog Timer
Signify End-of-Initialization on RSTOUT-pin
Begin ATOMIC sequence
Begin EXTended Register sequence
Begin EXTended Page (and Register) sequence
Begin EXTended Segment (and Register) sequence
Null operation
4
4
38
2
2
4
2
2
2
2
4
4
4
4
4
4
2
2
2/4
2/4
2
V3.0, 2001-01
C161CS/JC/JI-32R
C161CS/JC/JI-L
Special Function Registers Overview
Table 7 lists all SFRs which are implemented in the C161CS/JC/JI in alphabetical order.
Bit-addressable SFRs are marked with the letter “b” in column “Name”. SFRs within the
Extended SFR-Space (ESFRs) are marked with the letter “E” in column “Physical
Address”. Registers within on-chip X-peripherals are marked with the letter “X” in column
“Physical Address”.
An SFR can be specified via its individual mnemonic name. Depending on the selected
addressing mode, an SFR can be accessed via its physical address (using the Data
Page Pointers), or via its short 8-bit address (without using the Data Page Pointers).
Note: Registers within device specific interface modules (CAN, SDLM) are only present
in the corresponding device, of course.
Table 7
Name
C161CS/JC/JI Registers, Ordered by Name
ADCIC
Physical
Address
b FF98H
ADCON
b FFA0H
8-Bit Description
Addr.
CCH A/D Converter End of Conversion
Interrupt Control Register
D0H
A/D Converter Control Register
Reset
Value
0000H
0000H
ADDAT
ADDAT2
FEA0H
50H
F0A0H E 50H
A/D Converter Result Register
A/D Converter 2 Result Register
0000H
0000H
ADDRSEL1
ADDRSEL2
FE18H
FE1AH
0CH
0DH
Address Select Register 1
Address Select Register 2
0000H
0000H
ADDRSEL3
ADDRSEL4
FE1CH
FE1EH
0EH
0FH
Address Select Register 3
Address Select Register 4
0000H
0000H
b FF9AH
CDH
A/D Converter Overrun Error Interrupt
Control Register
SDLM Buffer Control Register
0000H
0000H
BUFFSTAT
EB1CH X --BUSCON0 b FF0CH
86H
SDLM Buffer Status Register
Bus Configuration Register 0
0000H
0000H
BUSCON1 b FF14H
BUSCON2 b FF16H
8AH
8BH
Bus Configuration Register 1
Bus Configuration Register 2
0000H
0000H
BUSCON3 b FF18H
BUSCON4 b FF1AH
8CH
8DH
Bus Configuration Register 3
Bus Configuration Register 4
0000H
0000H
ADEIC
BUFFCON
EB24H
X ---
BUSSTAT
C1BTR
EB20H
EF04H
X --X ---
SDLM Bus Status Register
CAN1 Bit Timing Register
0000H
UUUUH
C1CSR
C1GMS
EF00H
EF06H
X --X ---
CAN1 Control / Status Register
CAN1 Global Mask Short
XX01H
UFUUH
Data Sheet
39
V3.0, 2001-01
C161CS/JC/JI-32R
C161CS/JC/JI-L
Table 7
Name
C161CS/JC/JI Registers, Ordered by Name (cont’d)
C1PCIR
Physical 8-Bit Description
Address
Addr.
EF02H X --CAN1 Port Control / Interrupt Register
Reset
Value
XXXXH
C1LARn
C1LGML
EFn4H X --EF0AH X ---
CAN1 Lower Arbitration Reg. (msg. n)
CAN1 Lower Global Mask Long
UUUUH
UUUUH
C1LMLM
C1MCFGn
EF0EH X --EFn6H X ---
CAN1 Lower Mask of Last Message
CAN1 Message Config. Reg. (msg. n)
UUUUH
UUH
C1MCRn
C1UARn
EFn0H
EFn2H
CAN1 Message Control Reg. (msg. n)
CAN1 Upper Arbitration Reg. (msg. n)
UUUUH
UUUUH
C1UGML
C1UMLM
EF08H X --EF0CH X ---
CAN1 Upper Global Mask Long
CAN1 Upper Mask of Last Message
UUUUH
UUUUH
C2BTR
C2CSR
EE04H
EE00H
X --X ---
CAN2 Bit Timing Register
CAN2 Control / Status Register
UUUUH
XX01H
C2GMS
C2PCIR
EE06H
EE02H
X --X ---
CAN2 Global Mask Short
CAN2 Port Control / Interrupt Register
UFUUH
XXXXH
C2LARn
C2LGML
EEn4H X --EE0AH X ---
CAN2 Lower Arbitration Reg. (msg. n)
CAN2 Lower Global Mask Long
UUUUH
UUUUH
C2LMLM
C2MCFGn
EE0EH X --EEn6H X ---
CAN2 Lower Mask of Last Message
CAN2 Message Config. Reg. (msg. n)
UUUUH
UUH
C2MCRn
C2UARn
EEn0H
EEn2H
CAN2 Message Control Reg. (msg. n)
CAN2 Upper Arbitration Reg. (msg. n)
UUUUH
UUUUH
C2UGML
C2UMLM
EE08H X --EE0CH X ---
CAN2 Upper Global Mask Long
CAN2 Upper Mask of Last Message
UUUUH
UUUUH
CAPREL
CC0
FE4AH
FE80H
25H
40H
GPT2 Capture/Reload Register
CAPCOM Register 0
0000H
0000H
CC0IC
CC1
b FF78H
FE82H
BCH
41H
CAPCOM Register 0 Interrupt Ctrl. Reg.
CAPCOM Register 1
0000H
0000H
CC10
CC10IC
FE94H
b FF8CH
4AH
C6H
CAPCOM Register 10
CAPCOM Reg. 10 Interrupt Ctrl. Reg.
0000H
0000H
CC11
CC11IC
FE96H
b FF8EH
4BH
C7H
CAPCOM Register 11
CAPCOM Reg. 11 Interrupt Ctrl. Reg.
0000H
0000H
CC12
CC12IC
FE98H
b FF90H
4CH
C8H
CAPCOM Register 12
CAPCOM Reg. 12 Interrupt Ctrl. Reg.
0000H
0000H
FE9AH
4DH
CAPCOM Register 13
0000H
CC13
Data Sheet
X --X ---
X --X ---
40
V3.0, 2001-01
C161CS/JC/JI-32R
C161CS/JC/JI-L
Table 7
Name
C161CS/JC/JI Registers, Ordered by Name (cont’d)
CC13IC
Physical
Address
b FF92H
8-Bit Description
Addr.
C9H
CAPCOM Reg. 13 Interrupt Ctrl. Reg.
Reset
Value
0000H
CC14
CC14IC
FE9CH
b FF94H
4EH
CAH
CAPCOM Register 14
CAPCOM Reg. 14 Interrupt Ctrl. Reg.
0000H
0000H
CC15
CC15IC
FE9EH
b FF96H
4FH
CBH
CAPCOM Register 15
CAPCOM Reg. 15 Interrupt Ctrl. Reg.
0000H
0000H
CC16
CC16IC
FE60H
b F160H
30H
E B0H
CAPCOM Register 16
CAPCOM Reg.16 Interrupt Ctrl. Reg.
0000H
0000H
CC17
CC17IC
FE62H
b F162H
31H
E B1H
CAPCOM Register 17
CAPCOM Reg. 17 Interrupt Ctrl. Reg.
0000H
0000H
CC18
CC18IC
FE64H
b F164H
32H
E B2H
CAPCOM Register 18
CAPCOM Reg. 18 Interrupt Ctrl. Reg.
0000H
0000H
CC19
CC19IC
FE66H
b F166H
33H
E B3H
CAPCOM Register 19
CAPCOM Reg. 19 Interrupt Ctrl. Reg.
0000H
0000H
CC1IC
CC2
b FF7AH
FE84H
BDH
42H
CAPCOM Reg. 1 Interrupt Ctrl. Reg.
CAPCOM Register 2
0000H
0000H
CC20
CC20IC
FE68H
b F168H
34H
E B4H
CAPCOM Register 20
CAPCOM Reg. 20 Interrupt Ctrl. Reg.
0000H
0000H
CC21
CC21IC
FE6AH
35H
b F16AH E B5H
FE6CH
36H
b F16CH E B6H
CAPCOM Register 21
CAPCOM Reg. 21 Interrupt Ctrl. Reg.
0000H
0000H
CAPCOM Register 22
CAPCOM Reg. 22 Interrupt Ctrl. Reg.
0000H
0000H
CAPCOM Register 23
CAPCOM Reg. 23 Interrupt Ctrl. Reg.
0000H
0000H
CC24
CC24IC
FE6EH
37H
b F16EH E B7H
FE70H
38H
b F170H E B8H
CAPCOM Register 24
CAPCOM Reg. 24 Interrupt Ctrl. Reg.
0000H
0000H
CC25
CC25IC
FE72H
b F172H
39H
E B9H
CAPCOM Register 25
CAPCOM Reg. 25 Interrupt Ctrl. Reg.
0000H
0000H
CC26
CC26IC
FE74H
b F174H
3AH
E BAH
CAPCOM Register 26
CAPCOM Reg. 26 Interrupt Ctrl. Reg.
0000H
0000H
CC27
CC27IC
FE76H
b F176H
3BH
E BBH
CAPCOM Register 27
CAPCOM Reg. 27 Interrupt Ctrl. Reg.
0000H
0000H
FE78H
3CH
CAPCOM Register 28
0000H
CC22
CC22IC
CC23
CC23IC
CC28
Data Sheet
41
V3.0, 2001-01
C161CS/JC/JI-32R
C161CS/JC/JI-L
Table 7
Name
C161CS/JC/JI Registers, Ordered by Name (cont’d)
Physical 8-Bit Description
Address
Addr.
b F178H E BCH CAPCOM Reg. 28 Interrupt Ctrl. Reg.
Reset
Value
0000H
FE7AH
3DH
b F184H E C2H
b FF7CH
BEH
FE86H
43H
CAPCOM Register 29
CAPCOM Reg. 29 Interrupt Ctrl. Reg.
0000H
0000H
CAPCOM Reg. 2 Interrupt Ctrl. Reg.
CAPCOM Register 3
0000H
0000H
CAPCOM Register 30
CAPCOM Reg. 30 Interrupt Ctrl. Reg.
0000H
0000H
CC31
CC31IC
FE7CH
3EH
b F18CH E C6H
FE7EH
3FH
b F194H E CAH
CAPCOM Register 31
CAPCOM Reg. 31 Interrupt Ctrl. Reg.
0000H
0000H
CC3IC
CC4
b FF7EH
FE88H
BFH
44H
CAPCOM Reg. 3 Interrupt Ctrl. Reg.
CAPCOM Register 4
0000H
0000H
CC4IC
CC5
b FF80H
FE8AH
C0H
45H
CAPCOM Reg. 4 Interrupt Ctrl. Reg.
CAPCOM Register 5
0000H
0000H
CC5IC
CC6
b FF82H
FE8CH
C1H
46H
CAPCOM Reg. 5 Interrupt Ctrl. Reg.
CAPCOM Register 6
0000H
0000H
CC6IC
CC7
b FF84H
FE8EH
C2H
47H
CAPCOM Reg. 6 Interrupt Ctrl. Reg.
CAPCOM Register 7
0000H
0000H
CC7IC
CC8
b FF86H
FE90H
C3H
48H
CAPCOM Reg. 7 Interrupt Ctrl. Reg.
CAPCOM Register 8
0000H
0000H
CC8IC
CC9
b FF88H
FE92H
C4H
49H
CAPCOM Reg. 8 Interrupt Ctrl. Reg.
CAPCOM Register 9
0000H
0000H
CC9IC
CCM0
b FF8AH
b FF52H
C5H
A9H
CAPCOM Reg. 9 Interrupt Ctrl. Reg.
CAPCOM Mode Control Register 0
0000H
0000H
CCM1
CCM2
b FF54H
b FF56H
AAH
ABH
CAPCOM Mode Control Register 1
CAPCOM Mode Control Register 2
0000H
0000H
CCM3
CCM4
b FF58H
b FF22H
ACH
91H
CAPCOM Mode Control Register 3
CAPCOM Mode Control Register 4
0000H
0000H
CCM5
CCM6
b FF24H
b FF26H
92H
93H
CAPCOM Mode Control Register 5
CAPCOM Mode Control Register 6
0000H
0000H
CCM7
CLKDIV
b FF28H
EB14H
94H
X ---
CAPCOM Mode Control Register 7
SDLM Clock Divider Register
0000H
0000H
FE10H
08H
CPU Context Pointer Register
FC00H
CC28IC
CC29
CC29IC
CC2IC
CC3
CC30
CC30IC
CP
Data Sheet
42
V3.0, 2001-01
C161CS/JC/JI-32R
C161CS/JC/JI-L
Table 7
Name
C161CS/JC/JI Registers, Ordered by Name (cont’d)
CRIC
Physical
Address
b FF6AH
CSP
FE08H
04H
DP0H
b F102H
E 81H
CPU Code Segment Pointer Register
(8 bits, not directly writeable)
P0H Direction Control Register
DP0L
DP1H
b F100H
b F106H
E 80H
E 83H
P0L Direction Control Register
P1H Direction Control Register
00H
00H
DP1L
b F104H
E 82H
P1L Direction Control Register
00H
DP2
DP3
b FFC2H
b FFC6H
E1H
E3H
Port 2 Direction Control Register
Port 3 Direction Control Register
0000H
0000H
DP4
DP6
b FFCAH
b FFCEH
E5H
E7H
Port 4 Direction Control Register
Port 6 Direction Control Register
00H
00H
DP7
DP9
E9H
EDH
Port 7 Direction Control Register
Port 9 Direction Control Register
00H
00H
DPP0
DPP1
b FFD2H
b FFDAH
FE00H
FE02H
00H
01H
CPU Data Page Pointer 0 Reg. (10 bits)
CPU Data Page Pointer 1 Reg. (10 bits)
0000H
0001H
DPP2
DPP3
FE04H
FE06H
02H
03H
CPU Data Page Pointer 2 Reg. (10 bits)
CPU Data Page Pointer 3 Reg. (10 bits)
0002H
0003H
ERRSTAT
EB22H
EXICON
b F1C0H
SDLM Error Status Register
External Interrupt Control Register
0000H
0000H
EXISEL
External Interrupt Source Select
Register
SDLM Flag Reset Register
0000H
0000H
FOCON
b FFAAH
D5H
GLOBCON
EB10H X --ICADR
ED06H X --ICCFG
ED00H X ---
Frequency Output Control Register
SDLM Global Control Register
0000H
0000H
ICCON
ICRTB
ED02H X --ED08H X ---
IIC Control Register
IIC Receive/Transmit Buffer
ICST
IDCHIP
ED04H X --F07CH E 3EH
IIC Status Register
Identifier
0000H
1XXXH
IDMANUF
IDMEM
F07EH
F07AH
Identifier
Identifier
1820H
X040H
FLAGRST
Data Sheet
8-Bit Description
Addr.
B5H
GPT2 CAPREL Interrupt Ctrl. Reg.
Reset
Value
0000H
0000H
X --E E0H
b F1DAH E EDH
EB28H
X ---
E 3FH
E 3DH
IIC Address Register
IIC Configuration Register
43
00H
0XXXH
XX00H
0000H
XXH
V3.0, 2001-01
C161CS/JC/JI-32R
C161CS/JC/JI-L
Table 7
Name
C161CS/JC/JI Registers, Ordered by Name (cont’d)
IDPROG
Physical 8-Bit Description
Address
Addr.
F078H E 3CH
Identifier
Reset
Value
XXXXH
IFR
INTCON
EB18H X --EB2CH X ---
SDLM In-Frame Response Register
SDLM Interrupt Control Register
0000H
0000H
IPCR
ISNC
EB04H X --F1DEH E EFH
SDLM Interface Port Connect Register
Interrupt Subnode Control Register
0007H
0000H
MDC
MDH
b FF0EH
FE0CH
87H
06H
CPU Multiply Divide Control Register
CPU Multiply Divide Reg. – High Word
0000H
0000H
MDL
ODP2
CPU Multiply Divide Reg. – Low Word
Port 2 Open Drain Control Register
0000H
0000H
ODP3
ODP4
FE0EH
07H
b F1C2H E E1H
b F1C6H E E3H
b F1CAH E E5H
Port 3 Open Drain Control Register
Port 4 Open Drain Control Register
0000H
00H
ODP6
ODP7
b F1CEH E E7H
b F1D2H E E9H
Port 6 Open Drain Control Register
Port 7 Open Drain Control Register
00H
00H
ONES
P0H
b FF1EH
b FF02H
8FH
81H
Constant Value 1’s Register (read only)
Port 0 High Reg. (Upper half of PORT0)
FFFFH
00H
P0L
P1H
b FF00H
b FF06H
80H
83H
Port 0 Low Reg. (Lower half of PORT0)
Port 1 High Reg. (Upper half of PORT1)
00H
00H
P1L
P2
b FF04H
b FFC0H
b FFC4H
b FFC8H
82H
E0H
Port 1 Low Reg. (Lower half of PORT1)
Port 2 Register
00H
0000H
E2H
E4H
Port 3 Register
Port 4 Register (7 bits)
0000H
00H
b FFA2H
b FFCCH
b FFD0H
b FFD8H
D1H
E6H
Port 5 Register (read only)
Port 6 Register (8 bits)
E8H
ECH
Port 7 Register (8 bits)
Port 9 Register (8 bits)
PECC0
PECC1
FEC0H
FEC2H
60H
61H
PEC Channel 0 Control Register
PEC Channel 1 Control Register
0000H
0000H
PECC2
PECC3
FEC4H
FEC6H
62H
63H
PEC Channel 2 Control Register
PEC Channel 3 Control Register
0000H
0000H
PECC4
PECC5
FEC8H
FECAH
64H
65H
PEC Channel 4 Control Register
PEC Channel 5 Control Register
0000H
0000H
PECC6
FECCH
66H
PEC Channel 6 Control Register
0000H
P3
P4
P5
P6
P7
P9
Data Sheet
44
XXXXH
00H
00H
00H
V3.0, 2001-01
C161CS/JC/JI-32R
C161CS/JC/JI-L
Table 7
Name
PECC7
C161CS/JC/JI Registers, Ordered by Name (cont’d)
Physical
Address
FECEH
8-Bit Description
Addr.
67H
PEC Channel 7 Control Register
Reset
Value
0000H
PICON
b F1C4H
POCON0H
F082H
E E2H
E 41H
Port Input Threshold Control Register
P0L Output Control Register
0000H
0000H
POCON0L
POCON1H
F080H
F086H
E 40H
E 43H
P0H Output Control Register
P1L Output Control Register
0000H
0000H
POCON1L
POCON2
F084H
F088H
E 42H
E 44H
P1H Output Control Register
Port 2 Output Control Register
0000H
0000H
POCON20
POCON3
F0AAH E 55H
F08AH E 45H
Dedicated Pins Output Control Register
Port 3 Output Control Register
0000H
0000H
POCON4
POCON6
F08CH
F08EH
E 46H
E 47H
Port 4 Output Control Register
Port 6 Output Control Register
0000H
0000H
POCON7
PSW
F090H
b FF10H
E 48H
88H
Port 7 Output Control Register
CPU Program Status Word
0000H
0000H
RP0H
b F108H
E 84H
System Startup Configuration Register
(Rd. only)
RSTCON
RTCH
b F1E0H m --F0D6H E 6BH
XXH
Reset Control Register
RTC High Register
00XXH
no
RTCL
RXCNT
F0D4H E 6AH
EB4CH X ---
RTC Low Register
SDLM Bus Receive Byte Counter (CPU)
no
0000H
RXCNTB
RXCPU
EB4AH X --EB4EH X ---
SDLM Bus Receive Byte Counter (bus)
SDLM CPU Receive Byte Counter Reg.
0000H
0000H
RXD00
RXD010
EB40H X --EB4AH X ---
SDLM Receive Data Register 00 (CPU)
SDLM Receive Data Register 010 (CPU)
0000H
0000H
RXD02
RXD04
EB42H
EB44H
X --X ---
SDLM Receive Data Register 02 (CPU)
SDLM Receive Data Register 04 (CPU)
0000H
0000H
RXD06
RXD08
EB46H
EB48H
X --X ---
SDLM Receive Data Register 06 (CPU)
SDLM Receive Data Register 08 (CPU)
0000H
0000H
RXD10
RXD110
EB50H X --EB5AH X ---
SDLM Receive Data Register 10 (bus)
SDLM Receive Data Register 110 (bus)
0000H
0000H
RXD12
RXD14
EB52H
EB54H
X --X ---
SDLM Receive Data Register 12 (bus)
SDLM Receive Data Register 14 (bus)
0000H
0000H
RXD16
EB56H
X ---
SDLM Receive Data Register 16 (bus)
0000H
Data Sheet
45
V3.0, 2001-01
C161CS/JC/JI-32R
C161CS/JC/JI-L
Table 7
Name
C161CS/JC/JI Registers, Ordered by Name (cont’d)
RXD18
Physical 8-Bit Description
Address
Addr.
EB58H X --SDLM Receive Data Register 18 (bus)
Reset
Value
0000H
S0BG
FEB4H
5AH
0000H
S0CON
b FFB0H
D8H
S0EIC
b FF70H
B8H
Serial Channel 0 Error Interrupt Ctrl.
Reg.
FEB2H
59H
Serial Channel 0 Receive Buffer
Register (read only)
S0RIC
b FF6EH
B7H
Serial Channel 0 Receive Interrupt
Control Register
0000H
S0TBIC
b F19CH
E CEH
0000H
FEB0H
58H
b FF6CH
B6H
Serial Channel 0 Transmit Buffer
Interrupt Control Register
Serial Channel 0 Transmit Buffer
Register
Serial Channel 0 Transmit Interrupt
Control Register
Serial Channel 1 Baud Rate Generator
Reload Register
0000H
XXXXH
S0RBUF
S0TBUF
S0TIC
Serial Channel 0 Baud Rate Generator
Reload Register
Serial Channel 0 Control Register
0000H
0000H
XXXXH
0000H
0000H
S1BG
EDA4H X ---
S1CON
S1RBUF
EDA6H X --EDA2H X ---
S1TBUF
EDA0H X ---
SOFPTR
EB60H
X ---
Serial Channel 1 Control Register
Serial Channel 1 Receive Buffer
Register (read only)
Serial Channel 1 Transmit Buffer
Register
SDLM Start-of-Frame Pointer Register
SP
SSCBR
FE12H
F0B4H
09H
E 5AH
CPU System Stack Pointer Register
SSC Baudrate Register
FC00H
0000H
SSCCON
SSCEIC
b FFB2H
b FF76H
D9H
BBH
SSC Control Register
SSC Error Interrupt Control Register
0000H
0000H
SSCRB
SSCRIC
F0B2H
b FF74H
E 59H
BAH
SSC Receive Buffer (read only)
SSC Receive Interrupt Control Register
XXXXH
0000H
SSCTB
SSCTIC
F0B0H
b FF72H
E 58H
B9H
SSC Transmit Buffer (write only)
SSC Transmit Interrupt Control Register
0000H
0000H
STKOV
STKUN
FE14H
FE16H
0AH
0BH
CPU Stack Overflow Pointer Register
CPU Stack Underflow Pointer Register
FA00H
FC00H
Data Sheet
46
0000H
0000H
0000H
V3.0, 2001-01
C161CS/JC/JI-32R
C161CS/JC/JI-L
Table 7
Name
SYSCON
C161CS/JC/JI Registers, Ordered by Name (cont’d)
Physical
Address
b FF12H
8-Bit Description
Addr.
89H
CPU System Configuration Register
Reset
Value
1)
0XX0H
SYSCON1 b F1DCH E EEH
SYSCON2 b F1D0H E E8H
CPU System Configuration Register 1
CPU System Configuration Register 2
0000H
0000H
SYSCON3 b F1D4H
T0
FE50H
CPU System Configuration Register 3
CAPCOM Timer 0 Register
0X00H
0000H
T01CON
T0IC
E EAH
28H
b FF50H
b FF9CH
FE54H
FE52H
A8H
CEH
CAPCOM Timer 0 and Timer 1 Ctrl. Reg.
CAPCOM Timer 0 Interrupt Ctrl. Reg.
0000H
0000H
2AH
29H
CAPCOM Timer 0 Reload Register
CAPCOM Timer 1 Register
0000H
0000H
F0D2H
F0D0H
E 69H
E 68H
T1IC
T1REL
b FF9EH
FE56H
CFH
2BH
CAPCOM Timer 1 Interrupt Ctrl. Reg.
CAPCOM Timer 1 Reload Register
0000H
0000H
T2
T2CON
FE40H
b FF40H
20H
A0H
GPT1 Timer 2 Register
GPT1 Timer 2 Control Register
0000H
0000H
T2IC
T3
b FF60H
FE42H
B0H
21H
GPT1 Timer 2 Interrupt Control Register
GPT1 Timer 3 Register
0000H
0000H
T3CON
T3IC
b FF42H
b FF62H
A1H
B1H
GPT1 Timer 3 Control Register
GPT1 Timer 3 Interrupt Control Register
0000H
0000H
T4
T4CON
FE44H
b FF44H
22H
A2H
GPT1 Timer 4 Register
GPT1 Timer 4 Control Register
0000H
0000H
T4IC
T5
b FF64H
FE46H
B2H
23H
GPT1 Timer 4 Interrupt Control Register
GPT2 Timer 5 Register
0000H
0000H
T5CON
T5IC
b FF46H
b FF66H
A3H
B3H
GPT2 Timer 5 Control Register
GPT2 Timer 5 Interrupt Control Register
0000H
0000H
T6
T6CON
FE48H
b FF48H
24H
A4H
GPT2 Timer 6 Register
GPT2 Timer 6 Control Register
0000H
0000H
T6IC
T7
b FF68H
F050H
B4H
E 28H
GPT2 Timer 6 Interrupt Control Register
CAPCOM Timer 7 Register
0000H
0000H
T78CON
T7IC
b FF20H
b F17AH
F054H
90H
E BDH
CAPCOM Timer 7 and 8 Ctrl. Reg.
CAPCOM Timer 7 Interrupt Ctrl. Reg.
0000H
0000H
E 2AH
CAPCOM Timer 7 Reload Register
0000H
T0REL
T1
T14
T14REL
T7REL
Data Sheet
RTC Timer 14 Register
RTC Timer 14 Reload Register
47
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V3.0, 2001-01
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C161CS/JC/JI-L
Table 7
Name
T8
T8IC
T8REL
C161CS/JC/JI Registers, Ordered by Name (cont’d)
Physical 8-Bit Description
Address
Addr.
F052H E 29H
CAPCOM Timer 8 Register
b F17CH
F056H
E BEH
E 2BH
Reset
Value
0000H
CAPCOM Timer 8 Interrupt Ctrl. Reg.
CAPCOM Timer 8 Reload Register
0000H
0000H
TFR
b FFACH
D6H
TRANSSTAT EB1EH X ---
Trap Flag Register
SDLM Transmission Status Register
0000H
0000H
TXCNT
TXCPU
EB3CH X --EB3EH X ---
SDLM Bus Transmit Byte Counter Reg.
SDLM CPU Transmit Byte Counter Reg.
0000H
0000H
TXD0
TXD10
EB30H X --EB3AH X ---
SDLM Transmit Data Register 0
SDLM Transmit Data Register 10
0000H
0000H
TXD2
TXD4
EB32H
EB34H
X --X ---
SDLM Transmit Data Register 2
SDLM Transmit Data Register 4
0000H
0000H
TXD6
TXD8
EB36H
EB38H
X --X ---
SDLM Transmit Data Register 6
SDLM Transmit Data Register 8
0000H
0000H
TxDELAY
WDT
EB16H X --FEAEH
57H
SDLM Transceiver Delay Register
Watchdog Timer Register (read only)
0014H
0000H
WDTCON
XP0IC
b FFAEH
D7H
b F186H E C3H
Watchdog Timer Control Register
IIC Data Interrupt Control Register
XP1IC
XP2IC
b F18EH
b F196H
IIC Protocol Interrupt Control Register
CAN1 Interrupt Control Register
0000H
0000H
XP3IC
XP4IC
b F19EH
b F182H
E C7H
E CBH
E CFH
E C1H
PLL/RTC Interrupt Control Register
ASC1 Transmit Interrupt Ctrl. Reg.
0000H
0000H
XP5IC
XP6IC
b F18AH
b F192H
E C5H
E C9H
ASC1 Receive Interrupt Control Register
ASC1 Error Interrupt Control Register
0000H
0000H
XP7IC
ZEROS
b F19AH E CDH
b FF1CH
8EH
CAN2/SDLM Interrupt Control Register
Constant Value 0’s Register (read only)
0000H
0000H
1)
The system configuration is selected during reset.
2)
The reset value depends on the indicated reset source.
Data Sheet
48
2)00XX
H
0000H
V3.0, 2001-01
C161CS/JC/JI-32R
C161CS/JC/JI-L
Absolute Maximum Ratings
Table 8
Absolute Maximum Rating Parameters
Parameter
Symbol
Limit Values
Unit Notes
min.
max.
TST
TJ
VDD
-65
150
°C
–
-40
150
°C
under bias
-0.5
6.5
V
–
Voltage on any pin with
respect to ground (VSS)
VIN
-0.5
VDD + 0.5 V
–
Input current on any pin
during overload condition
–
-10
10
mA
–
Absolute sum of all input
currents during overload
condition
–
–
|100|
mA
–
Power dissipation
PDISS
–
1.5
W
–
Storage temperature
Junction temperature
Voltage on VDD pins with
respect to ground (VSS)
Note: Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in
the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
During absolute maximum rating overload conditions (VIN > VDD or VIN < VSS) the
voltage on VDD pins with respect to ground (VSS) must not exceed the values
defined by the absolute maximum ratings.
Data Sheet
49
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C161CS/JC/JI-32R
C161CS/JC/JI-L
Operating Conditions
The following operating conditions must not be exceeded in order to ensure correct
operation of the C161CS/JC/JI. All parameters specified in the following sections refer
to these operating conditions, unless otherwise noticed.
Table 9
Operating Condition Parameters
Parameter
Symbol
Limit Values
min.
Digital supply voltage
VDD
VSS
IOV
Overload current
Absolute sum of overload Σ|IOV|
Unit Notes
max.
4.5
5.5
V
Active mode,
fCPUmax = 25 MHz
2.51)
5.5
V
PowerDown mode
V
Reference voltage
0
Digital ground voltage
–
±5
mA
Per pin2)3)4)
–
50
mA
3)
currents
External Load
Capacitance
CL
–
100
pF
Pin drivers in
fast edge mode5)
Ambient temperature
TA
0
70
°C
SAB-C161CS/JC/JI …
-40
85
°C
SAF-C161CS/JC/JI …
-40
125
°C
SAK-C161CS/JC/JI …
1)
Output voltages and output currents will be reduced when VDD leaves the range defined for active mode.
2)
Overload conditions occur if the standard operatings conditions are exceeded, i.e. the voltage on any pin
exceeds the specified range (i.e. VOV > VDD + 0.5 V or VOV < VSS - 0.5 V). The absolute sum of input overload
currents on all pins may not exceed 50 mA. The supply voltage must remain within the specified limits.
Proper operation is not guaranteed if overload conditions occur on functional pins line XTAL1, RD, WR, etc.
3)
Not 100% tested, guaranteed by design and characterization.
4)
Due to the different port structure of Port 9 (required by the IIC bus specification) the pins of Port 9 can only
tolerate positive overload current, i.e. VOV > VSS - 0.5 V.
5)
The timing is valid for pin drivers in high current or dynamic current mode. The reduced static output current
in dynamic current mode must be respected when designing the system.
Data Sheet
50
V3.0, 2001-01
C161CS/JC/JI-32R
C161CS/JC/JI-L
Parameter Interpretation
The parameters listed in the following partly represent the characteristics of the C161CS/
JC/JI and partly its demands on the system. To aid in interpreting the parameters right,
when evaluating them for a design, they are marked in column “Symbol”:
CC (Controller Characteristics):
The logic of the C161CS/JC/JI will provide signals with the respective timing
characteristics.
SR (System Requirement):
The external system must provide signals with the respective timing characteristics to
the C161CS/JC/JI.
DC Characteristics
(Operating Conditions apply)1)
Parameter
Symbol
Limit Values
min.
VIL
Input low voltage (TTL,
all except XTAL1, XTAL3, Port 9)
Unit Test Condition
max.
SR -0.5
0.2 VDD V
- 0.1
–
Input low voltage
XTAL1, XTAL3, Port 9
VIL2 SR -0.5
0.3 VDD V
–
Input low voltage
(Special Threshold)
VILS SR -0.5
2.0
V
–
Input high voltage (TTL, all
except RSTIN, XTAL1, XTAL3,
Port 9)
VIH
SR 0.2 VDD VDD +
+ 0.9
0.5
V
–
Input high voltage RSTIN
(when operated as input)
VIH1 SR 0.6 VDD VDD +
V
–
Input high voltage
XTAL1, XTAL3, Port 9
VIH2 SR 0.7 VDD VDD +
V
–
Input high voltage
(Special Threshold)
VIHS SR 0.8 VDD VDD +
V
–
Input Hysteresis
(Special Threshold)
HYS
Output low voltage
(PORT0, PORT1, Port 4, ALE,
RD, WR, BHE, CLKOUT,
RSTOUT, RSTIN2))
Output low voltage
(Port 9)
Data Sheet
0.5
0.5
- 0.2
0.5
400
–
mV
Series resistance
=0Ω
VOL CC –
0.45
V
IOL = 2.4 mA3)
IOL = 0.5 mA4)
VOL9 CC –
0.4
V
IOL = 3.0 mA
51
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C161CS/JC/JI-L
DC Characteristics (cont’d)
(Operating Conditions apply)1)
Parameter
Symbol
Limit Values
min.
Unit Test Condition
max.
Output low voltage
(all other outputs)
VOL1 CC –
0.45
V
Output high voltage5)
(PORT0, PORT1, Port 4, ALE,
RD, WR, BHE, CLKOUT,
RSTOUT)
VOH CC 2.4
–
V
0.9 VDD –
V
Output high voltage5)
(all other outputs)
VOH1 CC 2.4
Input leakage current (Port 5)
Input leakage current (all other)
RSTIN inactive current6)
RSTIN active current6)
READY/RD/WR inact. current9)
READY/RD/WR active current9)
ALE inactive current9)
ALE active
current9)
Port 6 inactive current
9)
Port 6 active current9)
PORT0 configuration current10)
XTAL1 input current
Pin capacitance11)
(digital inputs/outputs)
–
V
0.9 VDD –
V
IOZ1 CC –
IOZ2 CC –
±200
nA
±500
nA
IRSTH7)
IRSTL8)
IRWH 7)
IRWL8)
IALEL7)
IALEH8)
IP6H7)
IP6L8)
IP0H7)
IP0L8)
IIL CC
CIO CC
–
-10
µA
-100
–
µA
–
-40
µA
-500
–
µA
–
40
µA
500
–
µA
–
-40
µA
-500
–
µA
–
-10
µA
-100
–
µA
–
±20
µA
–
10
pF
IOL = 1.6 mA3)
IOL = 1.6 mA4)
IOH = -2.4 mA3)
IOH = -0.5 mA4)
IOH = -0.5 mA3)
IOH = -1.6 mA3)
IOH = -0.5 mA4)
IOH = -0.5 mA3)
0 V < VIN < VDD
0.45 V < VIN <
VDD
VIN = VIH1
VIN = VIL
VOUT = 2.4 V
VOUT = VOLmax
VOUT = VOLmax
VOUT = 2.4 V
VOUT = 2.4 V
VOUT = VOL1max
VIN = VIHmin
VIN = VILmax
0 V < VIN < VDD
f = 1 MHz
TA = 25 °C
1)
Keeping signal levels within the levels specified in this table, ensures operation without overload conditions.
For signal levels outside these specifications also refer to the specification of the overload current IOV.
2)
Valid in bidirectional reset mode only.
3)
This output current may be drawn from (output) pins operating in High Current mode.
4)
This output current may be drawn from (output) pins operating in Low Current mode.
5)
This specification is not valid for outputs which are switched to open drain mode. In this case the respective
output will float and the voltage results from the external circuitry.
Data Sheet
52
V3.0, 2001-01
C161CS/JC/JI-32R
C161CS/JC/JI-L
6)
These parameters describe the RSTIN pullup, which equals a resistance of ca. 50 to 250 kΩ.
7)
The maximum current may be drawn while the respective signal line remains inactive.
8)
The minimum current must be drawn in order to drive the respective signal line active.
9)
This specification is valid during Reset and during Hold-mode or Adapt-mode. During Hold-mode Port 6 pins
are only affected, if they are used (configured) for CS output and the open drain function is not enabled. The
READY-pullup is always active, except for Powerdown mode.
10)
This specification is valid during Reset and during Adapt-mode.
11)
Not 100% tested, guaranteed by design and characterization.
Power Consumption C161CS/JC/JI
(Operating Conditions apply)
Parameter
Symbol
Limit Values
min.
max.
Unit Test Condition
Power supply current (active)
with all peripherals active
IDD
–
15 +
mA
2.5 × fCPU
RSTIN = VIL
fCPU in [MHz]1)
Idle mode supply current
with all peripherals active
IIDX
–
5+
mA
1.5 × fCPU
RSTIN = VIH1
fCPU in [MHz]1)
Idle mode supply curr., Main osc, IIDOM2)
with all peripherals deactivated,
PLL off, SDD factor = 32
–
500 +
50 × fOSC
µA
RSTIN = VIH1
fOSC in [MHz]1)
Idle mode supply curr., Aux. osc, IIDOA2)
with all peripherals deactivated,
PLL off, SDD factor = 32
–
100
µA
VDD = VDDmax
fOSC = 32 kHz3)
Sleep and Power-down mode
IPDRM2)
supply current with RTC running
on main oscillator
–
200 +
25 × fOSC
µA
VDD = VDDmax
fOSC in [MHz]3)
Sleep and Power-down mode
IPDO
supply current with RTC disabled
–
50
µA
VDD = VDDmax3)
1)
The supply current is a function of the operating frequency. This dependency is illustrated in Figure 10.
These parameters are tested at VDDmax and maximum CPU clock with all outputs disconnected and all inputs
at VIL or VIH.
2)
This parameter is determined mainly by the current consumed by the oscillator (see Figure 9). This current,
however, is influenced by the external oscillator circuitry (crystal, capacitors). The values given refer to a typical
circuitry and may change in case of a not optimized external oscillator circuitry.
3)
This parameter is tested including leakage currents. All inputs (including pins configured as inputs) at 0 V to
0.1 V or at VDD - 0.1 V to VDD, all outputs (including pins configured as outputs) disconnected.
Data Sheet
53
V3.0, 2001-01
C161CS/JC/JI-32R
C161CS/JC/JI-L
I
µA
1500
1250
IIDOMmax
1000
IIDOMtyp
750
500
IPDRMmax
250
IIDOAmax
IPDOmax
0
0
4
8
12
16
MHz fOSC
MCD04453
Figure 9
Data Sheet
Idle and Power Down Supply Current as a Function of Oscillator
Frequency
54
V3.0, 2001-01
C161CS/JC/JI-32R
C161CS/JC/JI-L
I [mA]
100
IDD5max
80
IDD5typ
60
IIDX5max
40
IIDX5typ
20
10
Figure 10
Data Sheet
15
20
25
fCPU [MHz]
Supply/Idle Current as a Function of Operating Frequency
55
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C161CS/JC/JI-L
AC Characteristics
Definition of Internal Timing
The internal operation of the C161CS/JC/JI is controlled by the internal CPU clock fCPU.
Both edges of the CPU clock can trigger internal (e.g. pipeline) or external (e.g. bus
cycles) operations.
The specification of the external timing (AC Characteristics) therefore depends on the
time between two consecutive edges of the CPU clock, called “TCL” (see Figure 11).
Phase Locked Loop Operation
fOSC
TCL
fCPU
TCL
Direct Clock Drive
fOSC
TCL
fCPU
TCL
Prescaler Operation
fOSC
TCL
fCPU
TCL
Figure 11
MCT04338
Generation Mechanisms for the CPU Clock
The CPU clock signal fCPU can be generated from the oscillator clock signal fOSC via
different mechanisms. The duration of TCLs and their variation (and also the derived
external timing) depends on the used mechanism to generate fCPU. This influence must
be regarded when calculating the timings for the C161CS/JC/JI.
Note: The example for PLL operation shown in the fig. above refers to a PLL factor of 4.
The used mechanism to generate the basic CPU clock is selected by bitfield CLKCFG
in register RP0H.7-5.
Upon a long hardware reset register RP0H is loaded with the logic levels present on the
upper half of PORT0 (P0H), i.e. bitfield CLKCFG represents the logic levels on pins
Data Sheet
56
V3.0, 2001-01
C161CS/JC/JI-32R
C161CS/JC/JI-L
P0.15-13 (P0H.7-5). Register RP0H can be loaded from the upper half of register
RSTCON under software control.
Table 10 associates the combinations of these three bits with the respective clock
generation mode.
Table 10
CLKCFG
(P0H.7-5)
1 1 1
1 1 0
1 0 1
1 0 0
0 1 1
0 1 0
0 0 1
0 0 0
C161CS/JC/JI Clock Generation Modes
CPU Frequency External Clock
fCPU = fOSC × F Input Range1)
Notes
fOSC × 4
fOSC × 3
fOSC × 2
fOSC × 5
fOSC × 1
fOSC × 1.5
fOSC / 2
fOSC × 2.5
2.5 to 6.25 MHz
Default configuration
3.33 to 8.33 MHz
–
5 to 12.5 MHz
–
2 to 5 MHz
–
1 to 25 MHz
Direct drive2)
6.66 to 16.6 MHz
–
2 to 50 MHz
CPU clock via prescaler
4 to 10 MHz
–
1)
The external clock input range refers to a CPU clock range of 10 … 25 MHz.
2)
The maximum frequency depends on the duty cycle of the external clock signal.
Prescaler Operation
When prescaler operation is configured (CLKCFG = 001B) the CPU clock is derived from
the internal oscillator (input clock signal) by a 2:1 prescaler.
The frequency of fCPU is half the frequency of fOSC and the high and low time of fCPU
(i.e. the duration of an individual TCL) is defined by the period of the input clock fOSC.
The timings listed in the AC Characteristics that refer to TCLs therefore can be
calculated using the period of fOSC for any TCL.
Phase Locked Loop
When PLL operation is configured (via CLKCFG) the on-chip phase locked loop is
enabled and provides the CPU clock (see table above). The PLL multiplies the input
frequency by the factor F which is selected via the combination of pins P0.15-13 (i.e.
fCPU = fOSC × F). With every F’th transition of fOSC the PLL circuit synchronizes the CPU
clock to the input clock. This synchronization is done smoothly, i.e. the CPU clock
frequency does not change abruptly.
Due to this adaptation to the input clock the frequency of fCPU is constantly adjusted so
it is locked to fOSC. The slight variation causes a jitter of fCPU which also effects the
duration of individual TCLs.
Data Sheet
57
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C161CS/JC/JI-32R
C161CS/JC/JI-L
The timings listed in the AC Characteristics that refer to TCLs therefore must be
calculated using the minimum TCL that is possible under the respective circumstances.
The actual minimum value for TCL depends on the jitter of the PLL. As the PLL is
constantly adjusting its output frequency so it corresponds to the applied input frequency
(crystal or oscillator) the relative deviation for periods of more than one TCL is lower than
for one single TCL (see formula and Figure 12).
For a period of N × TCL the minimum value is computed using the corresponding
deviation DN:
DN [ns] = ±(13.3 + N × 6.3) / fCPU [MHz],
(N × TCL)min = N × TCLNOM - DN
and 1 ≤ N ≤ 40.
where N = number of consecutive TCLs
So for a period of 3 TCLs @ 25 MHz (i.e. N = 3): D3 = (13.3 + 3 × 6.3) / 25 = 1.288 ns,
and (3TCL)min = 3TCLNOM - 1.288 ns = 58.7 ns (@ fCPU = 25 MHz).
This is especially important for bus cycles using waitstates and e.g. for the operation of
timers, serial interfaces, etc. For all slower operations and longer periods (e.g. pulse
train generation or measurement, lower baudrates, etc.) the deviation caused by the PLL
jitter is neglectible.
Note: For all periods longer than 40 TCL the N = 40 value can be used (see Figure 12).
Max. jitter DN
ns
±30
This approximated formula is valid for
1<
–N<
– 40 and 10 MHz <
– fCPU <
– 25 MHz.
10 MHz
±26.5
±20
16 MHz
20 MHz
25 MHz
±10
±1
1
10
20
30
40
N
MCD04455
Figure 12
Data Sheet
Approximated Maximum Accumulated PLL Jitter
58
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C161CS/JC/JI-L
Direct Drive
When direct drive is configured (CLKCFG = 011B) the on-chip phase locked loop is
disabled and the CPU clock is directly driven from the internal oscillator with the input
clock signal.
The frequency of fCPU directly follows the frequency of fOSC so the high and low time of
fCPU (i.e. the duration of an individual TCL) is defined by the duty cycle of the input clock
fOSC.
The timings listed below that refer to TCLs therefore must be calculated using the
minimum TCL that is possible under the respective circumstances. This minimum value
can be calculated via the following formula:
(DC = duty cycle)
TCLmin = 1/fOSC × DCmin
For two consecutive TCLs the deviation caused by the duty cycle of fOSC is
compensated so the duration of 2TCL is always 1/fOSC. The minimum value TCLmin
therefore has to be used only once for timings that require an odd number of TCLs (1, 3,
…). Timings that require an even number of TCLs (2, 4, …) may use the formula
2TCL = 1/fOSC.
Note: The address float timings in Multiplexed bus mode (t11 and t45) use the maximum
duration of TCL (TCLmax = 1/fOSC × DCmax) instead of TCLmin.
Data Sheet
59
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C161CS/JC/JI-32R
C161CS/JC/JI-L
AC Characteristics
External Clock Drive XTAL1 (Main Oscillator)
(Operating Conditions apply)
Table 11
External Clock Drive Characteristics
Parameter
Symbol
Direct Drive
1:1
min.
Prescaler
2:1
PLL
1:N
max.
min.
max.
min.
max.
Unit
Oscillator period tOSCM SR 40
t1
SR 203)
High time2)
–
20
–
601)
5001)
ns
–
6
–
10
–
ns
Low time2)
SR 203)
–
6
–
10
–
ns
SR –
10
–
6
–
10
ns
SR –
10
–
6
–
10
ns
t2
t3
t4
Rise time2)
Fall time2)
1)
The minimum and maximum oscillator periods for PLL operation depend on the selected CPU clock generation
mode. Please see respective table above.
2)
The clock input signal must reach the defined levels VIL2 and VIH2.
3)
The minimum high and low time refers to a duty cycle of 50%. The maximum operating frequency (fCPU) in
direct drive mode depends on the duty cycle of the clock input signal.
t1
t3
t4
VIH2
0.5 VDD
VIL
t2
t OSC
MCT02534
Figure 13
External Clock Drive XTAL1
Note: If the on-chip oscillator is used together with a crystal, the oscillator frequency is
limited to a range of 4 MHz to 16 MHz.
It is strongly recommended to measure the oscillation allowance (or margin) in the
final target system (layout) to determine the optimum parameters for the oscillator
operation. Please refer to the limits specified by the crystal supplier.
When driven by an external clock signal it will accept the specified frequency
range. Operation at lower input frequencies is possible but is guaranteed by
design only (not 100% tested).
Data Sheet
60
V3.0, 2001-01
C161CS/JC/JI-32R
C161CS/JC/JI-L
AC Characteristics
External Clock Drive XTAL3 (Auxiliary Oscillator)
(Operating Conditions apply)
Table 12
Parameter
AC Characteristics
Symbol
Optimum Input Clock Variable Input Clock
= 32 kHz
1 / tOSCA = 10 to 50 kHz
min.
max.
min.
max.
31
20
100
–
0.2 × tOSCA1) –
µs
SR 61)
–
0.2 × tOSCA1) –
µs
SR –
12
–
0.4 × tOSCA µs
SR –
12
–
0.4 × tOSCA µs
Oscillator period tOSCA SR 31
t1
SR 61)
High time
Low time
Rise time
Fall time
1)
t2
t3
t4
Unit
µs
The clock input signal must reach the defined levels VIL and VIH2.
Note: The auxiliary oscillator is optimized for oscillation with a crystal at a frequency of
32 kHz. When driven by an external clock signal it will accept the specified
frequency range.
Operation at lower input frequencies is possible but is guaranteed by design only
(not 100% tested).
Data Sheet
61
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C161CS/JC/JI-L
A/D Converter Characteristics
(Operating Conditions apply)
Table 13
A/D Converter Characteristics
Parameter
Analog reference supply
Analog reference ground
Analog input voltage range
Basic clock frequency
Conversion time
Symbol
VAREF SR
VAGND SR
VAIN SR
fBC
tC
CC
Limit Values
Unit Test
Condition
min.
max.
4.0
VSS - 0.1
VAGND
VDD + 0.1 V
VSS + 0.2 V
VAREF
V
0.5
6.25
–
40 tBC + –
tS + 2tCPU
4)
3328 tBC
–
5)
1)
2)
MHz 3)
tCPU = 1 / fCPU
Calibration time after reset
tCAL
Total unadjusted error
TUE CC –
±2
LSB 1)
Internal resistance of
reference voltage source
RAREF SR –
tBC / 60
kΩ
tBC in [ns]6)7)
kΩ
tS in [ns]7)8)
pF
7)
CC –
- 0.25
Internal resistance of analog RASRC SR –
source
ADC input capacitance
CAIN CC –
tS / 450
- 0.25
33
1)
TUE is tested at VAREF = 5.0 V, VAGND = 0 V, VDD = 4.9 V. It is guaranteed by design for all other voltages
within the defined voltage range.
If the analog reference supply voltage exceeds the power supply voltage by up to 0.2 V
(i.e. VAREF = VDD = +0.2 V) the maximum TUE is increased to ±3 LSB. This range is not 100% tested.
The specified TUE is guaranteed only if the absolute sum of input overload currents on Port 5 pins (see IOV
specification) does not exceed 10 mA.
During the reset calibration sequence the maximum TUE may be ±4 LSB.
2)
VAIN may exceed VAGND or VAREF up to the absolute maximum ratings. However, the conversion result in
these cases will be X000H or X3FFH, respectively.
3)
The limit values for fBC must not be exceeded when selecting the CPU frequency and the ADCTC setting.
4)
This parameter includes the sample time tS, the time for determining the digital result and the time to load the
result register with the conversion result.
Values for the basic clock tBC depend on programming and can be taken from Table 14.
This parameter depends on the ADC control logic. It is not a real maximum value, but rather a fixum.
5)
During the reset calibration conversions can be executed (with the current accuracy). The time required for
these conversions is added to the total reset calibration time.
6)
During the conversion the ADC’s capacitance must be repeatedly charged or discharged. The internal
resistance of the reference voltage source must allow the capacitance to reach its respective voltage level
within each conversion step. The maximum internal resistance results from the programmed conversion
timing.
7)
Not 100% tested, guaranteed by design and characterization.
Data Sheet
62
V3.0, 2001-01
C161CS/JC/JI-32R
C161CS/JC/JI-L
8)
During the sample time the input capacitance CAIN can be charged/discharged by the external source. The
internal resistance of the analog source must allow the capacitance to reach its final voltage level within tS.
After the end of the sample time tS, changes of the analog input voltage have no effect on the conversion
result.
Values for the sample time tS depend on programming and can be taken from Table 14.
Sample time and conversion time of the C161CS/JC/JI’s A/D Converter are
programmable. Table 14 should be used to calculate the above timings.
The limit values for fBC must not be exceeded when selecting ADCTC.
Table 14
A/D Converter Computation Table
ADCON.15|14
(ADCTC)
A/D Converter
Basic Clock fBC
ADCON.13|12 Sample time
tS
(ADSTC)
00
fCPU / 4
fCPU / 2
fCPU / 16
fCPU / 8
00
01
10
11
01
10
11
tBC × 8
tBC × 16
tBC × 32
tBC × 64
Converter Timing Example:
Assumptions:
Basic clock
Sample time
Conversion time
Data Sheet
fCPU
fBC
tS
tC
= 25 MHz (i.e. tCPU = 40 ns), ADCTC = ‘00’, ADSTC = ‘00’.
= fCPU / 4 = 6.25 MHz, i.e. tBC = 160 ns.
= tBC × 8 = 1280 ns.
= tS + 40 tBC + 2 tCPU = (1280 + 6400 + 80) ns = 7.8 µs.
63
V3.0, 2001-01
C161CS/JC/JI-32R
C161CS/JC/JI-L
Testing Waveforms
2.4 V
1.8 V
1.8 V
Test Points
0.8 V
’
0.8 V
0.45 V
’
’
AC inputs during testing are driven at 2.4 V for a logic 1’ and 0.45 V for a logic 0’.
Timing measurements are made at VIH min for a logic 1’ and VIL max for a logic 0’.
’
MCA04414
Figure 14
Input Output Waveforms
VLoad + 0.1 V
VOH - 0.1 V
Timing
Reference
Points
VLoad - 0.1 V
VOL + 0.1 V
For timing purposes a port pin is no longer floating when a 100 mV change from load voltage occurs,
but begins to float when a 100 mV change from the loaded VOH / VOL level occurs ( I OH / I OL = 20 mA).
MCA00763
Figure 15
Data Sheet
Float Waveforms
64
V3.0, 2001-01
C161CS/JC/JI-32R
C161CS/JC/JI-L
Memory Cycle Variables
The timing tables below use three variables which are derived from the BUSCONx
registers and represent the special characteristics of the programmed memory cycle.
The following table describes, how these variables are to be computed.
Table 15
Memory Cycle Variables
Description
Symbol
Values
ALE Extension
tA
tC
tF
TCL × <ALECTL>
Memory Cycle Time Waitstates
Memory Tristate Time
2TCL × (15 - <MCTC>)
2TCL × (1 - <MTTC>)
Note: Please respect the maximum operating frequency of the respective derivative.
AC Characteristics
Multiplexed Bus
(Operating Conditions apply)
ALE cycle time = 6 TCL + 2tA + tC + tF (120 ns at 25 MHz CPU clock without waitstates)
Parameter
Symbol
Max. CPU Clock Variable CPU Clock Unit
= 25 MHz
1 / 2TCL = 1 to 25 MHz
min.
max.
min.
max.
ALE high time
t5
CC 10 + tA
–
TCL - 10
+ tA
–
ns
Address setup to ALE
t6
CC 4 + tA
–
TCL - 16
+ tA
–
ns
Address hold after ALE
t7
CC 10 + tA
–
TCL - 10
+ tA
–
ns
ALE falling edge to RD,
WR (with RW-delay)
t8
CC 10 + tA
–
TCL - 10
+ tA
–
ns
ALE falling edge to RD,
WR (no RW-delay)
t9
CC -10 + tA –
-10 + tA
–
ns
Address float after RD,
WR (with RW-delay)
t10 CC –
6
–
6
ns
Address float after RD,
WR (no RW-delay)
t11 CC –
26
–
TCL + 6
ns
RD, WR low time
(with RW-delay)
t12 CC 30 + tC
–
2TCL - 10
+ tC
–
ns
Data Sheet
65
V3.0, 2001-01
C161CS/JC/JI-32R
C161CS/JC/JI-L
Multiplexed Bus (cont’d)
(Operating Conditions apply)
ALE cycle time = 6 TCL + 2tA + tC + tF (120 ns at 25 MHz CPU clock without waitstates)
Parameter
Symbol
Max. CPU Clock Variable CPU Clock Unit
= 25 MHz
1 / 2TCL = 1 to 25 MHz
min.
max.
min.
max.
RD, WR low time
(no RW-delay)
t13 CC 50 + tC
–
3TCL - 10
+ tC
–
ns
RD to valid data in
(with RW-delay)
t14 SR –
20 + tC
–
2TCL - 20
+ tC
ns
RD to valid data in
(no RW-delay)
t15 SR –
40 + tC
–
3TCL - 20
+ tC
ns
ALE low to valid data in
t16 SR –
40 + tA
+ tC
–
3TCL - 20
+ tA + tC
ns
Address to valid data in
t17 SR –
50 + 2tA –
+ tC
4TCL - 30
+ 2tA + tC
ns
Data hold after RD
rising edge
t18 SR 0
–
0
–
ns
Data float after RD
t19 SR –
26 + tF
–
2TCL - 14
+ tF
ns
Data valid to WR
t22 CC 20 + tC
–
2TCL - 20
+ tC
–
ns
Data hold after WR
t23 CC 26 + tF
–
2TCL - 14
+ tF
–
ns
ALE rising edge after RD, t25 CC 26 + tF
WR
–
2TCL - 14
+ tF
–
ns
t27 CC 26 + tF
–
2TCL - 14
+ tF
–
ns
10 - tA
-4 - tA
10 - tA
ns
CS low to Valid Data In
t38 CC -4 - tA
t39 SR –
40
+ tC
+ 2 tA
–
3TCL - 20
+ t C + 2 tA
ns
CS hold after RD, WR1)
t40 CC 46 + tF
–
3TCL - 14
+ tF
–
ns
ALE fall. edge to RdCS,
WrCS (with RW delay)
t42 CC 16 + tA
–
TCL - 4
+ tA
–
ns
Address hold after RD,
WR
ALE falling edge to CS1)
1)
Data Sheet
66
V3.0, 2001-01
C161CS/JC/JI-32R
C161CS/JC/JI-L
Multiplexed Bus (cont’d)
(Operating Conditions apply)
ALE cycle time = 6 TCL + 2tA + tC + tF (120 ns at 25 MHz CPU clock without waitstates)
Parameter
Symbol
Max. CPU Clock Variable CPU Clock Unit
= 25 MHz
1 / 2TCL = 1 to 25 MHz
min.
max.
min.
max.
–
-4
+ tA
–
ns
Address float after RdCS, t44 CC –
WrCS (with RW delay)
0
–
0
ns
Address float after RdCS, t45 CC –
WrCS (no RW delay)
20
–
TCL
ns
ALE fall. edge to RdCS,
WrCS (no RW delay)
t43 CC -4 + tA
RdCS to Valid Data In
(with RW delay)
t46 SR –
16 + tC
–
2TCL - 24
+ tC
ns
RdCS to Valid Data In
(no RW delay)
t47 SR –
36 + tC
–
3TCL - 24
+ tC
ns
RdCS, WrCS Low Time
(with RW delay)
t48 CC 30 + tC
–
2TCL - 10
+ tC
–
ns
RdCS, WrCS Low Time
(no RW delay)
t49 CC 50 + tC
–
3TCL - 10
+ tC
–
ns
Data valid to WrCS
t50 CC 26 + tC
–
2TCL - 14
+ tC
–
ns
Data hold after RdCS
t51 SR 0
t52 SR –
–
0
–
ns
20 + tF
–
2TCL - 20
+ tF
ns
Address hold after
RdCS, WrCS
t54 CC 20 + tF
–
2TCL - 20
+ tF
–
ns
Data hold after WrCS
t56 CC 20 + tF
–
2TCL - 20
+ tF
–
ns
Data float after RdCS
1)
These parameters refer to the latched chip select signals (CSxL). The early chip select signals (CSxE) are
specified together with the address and signal BHE (see figures below).
Data Sheet
67
V3.0, 2001-01
C161CS/JC/JI-32R
C161CS/JC/JI-L
t5
t16
t25
ALE
t38
t39
t40
CSxL
t17
t27
A23-A16
(A15-A8)
BHE, CSxE
Address
t54
t19
t6
t7
t18
Read Cycle
BUS
Address
t8
Data IN
t10
t14
t12
RD
t42
`
t44
t51
t52
t46
t48
RdCSx
t23
Write Cycle
BUS
Address
t8
Data OUT
t10
t22
t56
t12
WR, WRL,
WRH
t42
t44
t50
WrCSx
t48
MCT04439
Figure 16
Data Sheet
External Memory Cycle:
Multiplexed Bus, With Read/Write Delay, Normal ALE
68
V3.0, 2001-01
C161CS/JC/JI-32R
C161CS/JC/JI-L
t5
t16
t25
ALE
t38
t39
t40
CSxL
t17
A23-A16
(A15-A8)
BHE, CSxE
t27
Address
t6
t54
t19
t7
t18
Read Cycle
BUS
Address
Data IN
t8
t10
t14
t12
RD
t42
t44
t51
t52
t46
t48
RdCSx
t23
Write Cycle
BUS
Address
Data OUT
t8
t10
t22
t56
t12
WR, WRL,
WRH
t42
t44
t50
t48
WrCSx
MCT04440
Figure 17
External Memory Cycle:
Multiplexed Bus, With Read/Write Delay, Extended ALE
Data Sheet
69
V3.0, 2001-01
C161CS/JC/JI-32R
C161CS/JC/JI-L
t5
t16
t25
ALE
t38
t39
t40
CSxL
t17
t27
A23-A16
(A15-A8)
BHE, CSxE
Address
t54
t19
t6
t7
t18
Read Cycle
BUS
Address
t9
Data IN
t11
t15
t13
RD
t43
t45
t51
t52
t47
t49
RdCSx
t23
Write Cycle
BUS
Address
t9
Data OUT
t11
t22
t56
t13
WR, WRL,
WRH
t43
t45
t50
t49
WrCSx
MCT04441
Figure 18
Data Sheet
External Memory Cycle:
Multiplexed Bus, No Read/Write Delay, Normal ALE
70
V3.0, 2001-01
C161CS/JC/JI-32R
C161CS/JC/JI-L
t5
t16
t25
ALE
t38
t39
t40
CSxL
t17
A23-A16
(A15-A8)
BHE, CSxE
t27
Address
t6
t54
t19
t7
t18
Read Cycle
BUS
Address
Data IN
t9
t11
t15
t13
RD
t43
t45
t51
t47
t49
t52
RdCSx
t23
Write Cycle
BUS
Address
Data OUT
t9
t11
t22
t56
t13
WR, WRL,
WRH
t43
t45
t50
t49
WrCSx
MCT04442
Figure 19
External Memory Cycle:
Multiplexed Bus, No Read/Write Delay, Extended ALE
Data Sheet
71
V3.0, 2001-01
C161CS/JC/JI-32R
C161CS/JC/JI-L
AC Characteristics
Demultiplexed Bus
(Operating Conditions apply)
ALE cycle time = 4 TCL + 2tA + tC + tF (80 ns at 25 MHz CPU clock without waitstates)
Parameter
Symbol
Max. CPU Clock Variable CPU Clock Unit
= 25 MHz
1 / 2TCL = 1 to 25 MHz
min.
max.
min.
max.
ALE high time
t5
CC 10 + tA
–
TCL - 10
+ tA
–
ns
Address setup to ALE
t6
CC 4 + tA
–
TCL - 16
+ tA
–
ns
ALE falling edge to RD,
WR (with RW-delay)
t8
CC 10 + tA
–
TCL - 10
+ tA
–
ns
ALE falling edge to RD,
WR (no RW-delay)
t9
CC -10 + tA –
-10
+ tA
–
ns
RD, WR low time
(with RW-delay)
t12 CC 30 + tC
–
2TCL - 10
+ tC
–
ns
RD, WR low time
(no RW-delay)
t13 CC 50 + tC
–
3TCL - 10
+ tC
–
ns
RD to valid data in
(with RW-delay)
t14 SR –
20 + tC
–
2TCL - 20
+ tC
ns
RD to valid data in
(no RW-delay)
t15 SR –
40 + tC
–
3TCL - 20
+ tC
ns
ALE low to valid data in
t16 SR –
40 +
tA + t C
–
3TCL - 20
+ tA + tC
ns
Address to valid data in
t17 SR –
50 +
–
2 tA + t C
4TCL - 30
+ 2tA + tC
ns
Data hold after RD
rising edge
t18 SR 0
–
–
ns
Data float after RD rising
edge (with RW-delay1))
t20 SR –
26 +
–
1)
2 tA + t F
2TCL - 14
+ 22tA
+ tF1)
ns
Data float after RD rising
edge (no RW-delay1))
t21 SR –
10 +
–
1)
2 tA + t F
TCL - 10
+ 22tA
+ tF1)
ns
Data Sheet
72
0
V3.0, 2001-01
C161CS/JC/JI-32R
C161CS/JC/JI-L
Demultiplexed Bus (cont’d)
(Operating Conditions apply)
ALE cycle time = 4 TCL + 2tA + tC + tF (80 ns at 25 MHz CPU clock without waitstates)
Parameter
Symbol
Max. CPU Clock Variable CPU Clock Unit
= 25 MHz
1 / 2TCL = 1 to 25 MHz
min.
max.
min.
max.
Data valid to WR
t22 CC 20 + tC
–
2TCL - 20
+ tC
–
ns
Data hold after WR
t24 CC 10 + tF
–
TCL - 10
+ tF
–
ns
ALE rising edge after RD, t26 CC -10 + tF
WR
–
-10 + tF
–
ns
Address hold after WR2)
–
0 + tF
–
ns
10 - tA
-4 - tA
10 - tA
ns
CS low to Valid Data In3)
t28 CC 0 + tF
t38 CC -4 - tA
t39 SR –
40 +
–
tC + 2tA
3TCL - 20
+ t C + 2 tA
ns
CS hold after RD, WR3)
t41 CC 6 + tF
–
TCL - 14
+ tF
–
ns
ALE falling edge to RdCS, t42 CC 16 + tA
WrCS (with RW-delay)
–
TCL - 4
+ tA
–
ns
ALE falling edge to RdCS, t43 CC -4 + tA
WrCS (no RW-delay)
–
-4
+ tA
–
ns
ALE falling edge to CS3)
RdCS to Valid Data In
(with RW-delay)
t46 SR –
16 + tC
–
2TCL - 24
+ tC
ns
RdCS to Valid Data In
(no RW-delay)
t47 SR –
36 + tC
–
3TCL - 24
+ tC
ns
RdCS, WrCS Low Time
(with RW-delay)
t48 CC 30 + tC
–
2TCL - 10
+ tC
–
ns
RdCS, WrCS Low Time
(no RW-delay)
t49 CC 50 + tC
–
3TCL - 10
+ tC
–
ns
Data valid to WrCS
t50 CC 26 + tC
–
2TCL - 14
+ tC
–
ns
Data hold after RdCS
t51 SR 0
t53 SR –
–
0
–
ns
20 + tF
–
2TCL - 20 ns
+ 2tA + tF1)
Data float after RdCS
(with RW-delay)1)
Data Sheet
73
V3.0, 2001-01
C161CS/JC/JI-32R
C161CS/JC/JI-L
Demultiplexed Bus (cont’d)
(Operating Conditions apply)
ALE cycle time = 4 TCL + 2tA + tC + tF (80 ns at 25 MHz CPU clock without waitstates)
Parameter
Symbol
Max. CPU Clock Variable CPU Clock Unit
= 25 MHz
1 / 2TCL = 1 to 25 MHz
min.
max.
min.
max.
Data float after RdCS
(no RW-delay)1)
t68 SR –
0 + tF
–
TCL - 20
ns
1)
+ 2tA + tF
Address hold after
RdCS, WrCS
t55 CC -6 + tF
–
-6 + tF
–
ns
Data hold after WrCS
t57 CC 6 + tF
–
TCL - 14 + –
ns
tF
1)
RW-delay and tA refer to the next following bus cycle (including an access to an on-chip X-Peripheral).
2)
Read data are latched with the same clock edge that triggers the address change and the rising RD edge.
Therefore address changes before the end of RD have no impact on read cycles.
3)
These parameters refer to the latched chip select signals (CSxL). The early chip select signals (CSxE) are
specified together with the address and signal BHE (see figures below).
Data Sheet
74
V3.0, 2001-01
C161CS/JC/JI-32R
C161CS/JC/JI-L
t5
t16
t26
ALE
t38
t39
t41
CSxL
t28
t17
A23-A16
A15-A0
BHE, CSxE
Address
t55
t6
t20
Read Cycle
BUS
(D15-D8)
D7-D0
t18
Data IN
t8
t14
t12
t42
t46
t48
RD
t51
t53
RdCSx
Write Cycle
BUS
(D15-D8)
D7-D0
t24
Data OUT
t8
t22
t57
t12
WR, WRL,
WRH
t42
t50
t48
WrCSx
MCT04443
Figure 20
Data Sheet
External Memory Cycle:
Demultiplexed Bus, With Read/Write Delay, Normal ALE
75
V3.0, 2001-01
C161CS/JC/JI-32R
C161CS/JC/JI-L
t5
t16
t26
ALE
t38
t39
t41
CSxL
t17
A23-A16
A15-A0
BHE, CSxE
t28
Address
t6
t55
t20
Read Cycle
BUS
(D15-D8)
D7-D0
t18
Data IN
t8
t14
t12
t42
t46
t48
RD
t51
t53
RdCSx
Write Cycle
BUS
(D15-D8)
D7-D0
t24
Data OUT
t8
t22
t57
t12
WR, WRL,
WRH
t42
t50
t48
WrCSx
MCT04444
Figure 21
Data Sheet
External Memory Cycle:
Demultiplexed Bus, With Read/Write Delay, Extended ALE
76
V3.0, 2001-01
C161CS/JC/JI-32R
C161CS/JC/JI-L
t5
t16
t26
ALE
t38
t39
t41
CSxL
t28
t17
A23-A16
A15-A0
BHE, CSxE
Address
t55
t6
t21
Read Cycle
BUS
(D15-D8)
D7-D0
t18
Data IN
t9
t15
t13
t43
t47
t49
RD
t51
t68
RdCSx
Write Cycle
t24
BUS
(D15-D8)
D7-D0
Data OUT
t22
t9
t57
t13
WR, WRL,
WRH
t43
t50
t49
WrCSx
MCT04445
Figure 22
External Memory Cycle:
Demultiplexed Bus, No Read/Write Delay, Normal ALE
Data Sheet
77
V3.0, 2001-01
C161CS/JC/JI-32R
C161CS/JC/JI-L
t5
t16
t26
ALE
t38
t39
t41
CSxL
t17
A23-A16
A15-A0
BHE, CSxE
t28
Address
t6
t55
t21
Read Cycle
BUS
(D15-D8)
D7-D0
t18
Data IN
t9
t15
t13
t43
t47
t49
RD
t51
t68
RdCSx
Write Cycle
BUS
(D15-D8)
D7-D0
t24
Data OUT
t9
t22
t57
t13
WR, WRL,
WRH
t43
t50
t49
WrCSx
MCT04446
Figure 23
Data Sheet
External Memory Cycle:
Demultiplexed Bus, No Read/Write Delay, Extended ALE
78
V3.0, 2001-01
C161CS/JC/JI-32R
C161CS/JC/JI-L
AC Characteristics
CLKOUT and READY
(Operating Conditions apply)
Parameter
Symbol
Max. CPU Clock Variable CPU Clock Unit
= 25 MHz
1 / 2TCL = 1 to 25 MHz
min.
CLKOUT cycle time
CLKOUT high time
CLKOUT low time
CLKOUT rise time
CLKOUT fall time
CLKOUT rising edge to
ALE falling edge
t29
t30
t31
t32
t33
t34
max.
min.
max.
CC 40
40
2TCL
2TCL
ns
CC 14
–
TCL - 6
–
ns
CC 10
–
TCL - 10
–
ns
CC –
4
–
4
ns
CC –
4
–
4
ns
CC 0 + tA
10 + tA
0 + tA
10 + tA
ns
Synchronous READY
setup time to CLKOUT
t35 SR 14
–
14
–
ns
Synchronous READY
hold time after CLKOUT
t36 SR 4
–
4
–
ns
Asynchronous READY
low time
t37 SR 54
–
2TCL + t58 –
ns
Asynchronous READY
setup time1)
t58 SR 14
–
14
–
ns
Asynchronous READY
hold time1)
t59 SR 4
–
4
–
ns
0
+ 2tA +
0
TCL - 20
+ 2tA + tC
+ tF2)
ns
Async. READY hold time t60 SR 0
after RD, WR high
(Demultiplexed Bus)2)
tC
+ tF2)
1)
These timings are given for test purposes only, in order to assure recognition at a specific clock edge.
2)
Demultiplexed bus is the worst case. For multiplexed bus 2TCL are to be added to the maximum values. This
adds even more time for deactivating READY.
The 2tA and tC refer to the next following bus cycle, tF refers to the current bus cycle.
The maximum limit for t60 must be fulfilled if the next following bus cycle is READY controlled.
Data Sheet
79
V3.0, 2001-01
C161CS/JC/JI-32R
C161CS/JC/JI-L
Running Cycle
READY
Waitstate
1)
MUX/Tristate 6)
t32
t33
t30
t29
CLKOUT
t31
t34
ALE
7)
Command
RD, WR
2)
t36
t35
Sync
READY
t35
3)
3)
t59
t58
Async
READY
t36
t59
t60 4)
t58
3)
3)
t37 5)
see 6)
MCT04447
Figure 24
CLKOUT and READY
Notes
1)
Cycle as programmed, including MCTC waitstates (Example shows 0 MCTC WS).
2) The leading edge of the respective command depends on RW-delay.
3) READY sampled HIGH at this sampling point generates a READY controlled waitstate,
READY sampled LOW at this sampling point terminates the currently running bus cycle.
4) READY may be deactivated in response to the trailing (rising) edge of the corresponding command (RD or
WR).
5)
If the Asynchronous READY signal does not fulfill the indicated setup and hold times with respect to CLKOUT
(e.g. because CLKOUT is not enabled), it must fulfill t37 in order to be safely synchronized. This is guaranteed,
if READY is removed in reponse to the command (see Note4)).
6)
Multiplexed bus modes have a MUX waitstate added after a bus cycle, and an additional MTTC waitstate may
be inserted here.
For a multiplexed bus with MTTC waitstate this delay is 2 CLKOUT cycles, for a demultiplexed bus without
MTTC waitstate this delay is zero.
7) The next external bus cycle may start here.
Data Sheet
80
V3.0, 2001-01
C161CS/JC/JI-32R
C161CS/JC/JI-L
AC Characteristics
External Bus Arbitration
(Operating Conditions apply)
Parameter
Symbol
Max. CPU Clock Variable CPU Clock Unit
= 25 MHz
1 / 2TCL = 1 to 25 MHz
min.
max.
min.
max.
20
–
20
–
ns
HOLD input setup time
to CLKOUT
t61 SR
CLKOUT to HLDA high
or BREQ low delay
t62 CC –
20
–
20
ns
CLKOUT to HLDA low
or BREQ high delay
t63 CC –
20
–
20
ns
CSx release
t64
t65
t66
t67
CSx drive
Other signals release
Other signals drive
Data Sheet
CC
–
20
–
20
ns
CC
-4
24
-4
24
ns
CC
–
20
–
20
ns
CC
–4
24
–4
24
ns
81
V3.0, 2001-01
C161CS/JC/JI-32R
C161CS/JC/JI-L
CLKOUT
t61
HOLD
t63
HLDA
see1)
t62
BREQ
2)
t64
3)
CSx
(On P6.x)
t66
Other
Signals
1)
Figure 25
MCT04448
External Bus Arbitration, Releasing the Bus
Notes
1) The C161CS/JC/JI will complete the currently running bus cycle before granting bus access.
2)
This is the first possibility for BREQ to get active.
3)
The CS outputs will be resistive high (pullup) after t64.
Data Sheet
82
V3.0, 2001-01
C161CS/JC/JI-32R
C161CS/JC/JI-L
CLKOUT
2)
t61
HOLD
t62
HLDA
t62
BREQ
t62
t63
1)
t65
CSx
(On P6.x)
t67
Other
Signals
MCT04449
Figure 26
External Bus Arbitration, (Regaining the Bus)
Notes
1) This is the last chance for BREQ to trigger the indicated regain-sequence.
Even if BREQ is activated earlier, the regain-sequence is initiated by HOLD going high.
Please note that HOLD may also be deactivated without the C161CS/JC/JI requesting the bus.
2) The next C161CS/JC/JI driven bus cycle may start here.
Data Sheet
83
V3.0, 2001-01
C161CS/JC/JI-32R
C161CS/JC/JI-L
Package Outline
GPP09028
P-TQFP-128-2
(Plastic Thin Metric Quad Flat Package)
Sorts of Packing
Package outlines for tubes, trays etc. are contained in our
Data Book “Package Information”.
SMD = Surface Mounted Device
Data Sheet
84
Dimensions in mm
V3.0, 2001-01
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