AN-420: Using the AD9708/AD9760/AD9701/AD9764-EB Evaluation Board PDF

a
ONE TECHNOLOGY WAY
• P.O.
AN-420
APPLICATION NOTE
BOX 9106
• NORWOOD,
MASSACHUSETTS 02062-9106
• 617/329-4700
Using the AD9708/AD9760/AD9762/AD9764-EB Evaluation Board
by Bill Odom
GENERAL DESCRIPTION
The AD9708-EB, AD9760-EB, AD9762-EB and AD9764-EB
evaluation boards are used to evaluate the AD976x family of 8-, 10-, 12- and 14-bit D/A converters (AD9708,
AD9760, AD9762, AD9764, respectively). This board allows the user to exercise the AD9708/AD9760/AD9762/
AD9764’s many features. They include resistor, transformer, op amp loading of the converter and sleep mode
operation for reduced power consumption. For greater
gain accuracy, an external reference may also be used
with the converters. Each of these functions will be outlined in this note; however, the user should refer to the
AD9708/AD9760/AD9762/AD9764 data sheet. It covers
the operation and application in far greater detail than
this evaluation board note.
family is assigned to Pin #1. The unused DAC input pins
will be floating. This allows the 8-, 10-, 12- and 14-bit
DACs to be soldered to the same evaluation board.
P1
(14 SECTIONS)
+AVDD
+DVDD
R5 AND
R6 NETS*
R1 AND
R2 NETS*
J1
R15
50Ω
R40 AND
R41 NETS
C1*, C2*,
C25*, TO C36*,
C19*
R7 AND
R8 NETS*
R3 AND
R4 NETS*
INPUT WORD
(14 PLACES)
AD9708/60/62/64
CLOCK
JP1
B POS
*THESE COMPONENTS WERE NOT INSTALLED AT THE FACTORY
Figure 1. Input Word Configuration
J3
Configuration
Although the AD9708/AD9760/AD9762/AD9764-EB evaluation board can exercise the many attributes of this D/A
family, it is shipped with the following configuration
in place:
Its digital input is designed for direct drive from various
word generators. Looking into the input connector, the
generator will see a high impedance load through small
series resistors. Its output is constructed to drive
resistive loads and a transformer. The AD9708/AD9760/
AD9762/AD9764-EB evaluation board is shipped with its
internal reference connected. If its other functions are to
be exercised (external reference, external output amplification and sleep mode) the user must build up the applicable section of the board. Figures 1 and 2 illustrate the
configuration of the board as shipped from the factory.
The entire family of converters is MSB-justified and may
be soldered into the same 28-pin socket (they are all pin
compatible), i.e., the MSB of all the members of the
IOUT A
(OUT 1)
J7
C12
22pF
R20
49.9Ω
AD9708/60/62/64
J4
IOUT B
(OUT 2)
C13
22pF
R38
49.9Ω
Figure 2. Resistor and Transformer Load
The parallel data input pins of the DAC follow standard
positive binary coding. An input of all 1s will give a +FS
output current at IOUTA. An input of all 0s will give a
zero output current at IOUTA. (IOUTB is the inversion of
IOUTA. All 1s will give zero current at IOUTB and all 0s
will give it full-scale current.)
Note: The frequency domain data shown in this application note was gathered from an AD9760.
EVALUATION BOARD OPERATION
The AD9708/AD9760/AD9762/AD9764-EB is a 5 × 5.5 inch,
four-layer board. Its layers are composed of component
and solder signal layers, ground plane and power plane.
A schematic and a parts list are on succeeding pages of
this note.
GROUND
The AD9708/AD9760/AD9762/AD9764-EB has separate
ground planes for analog and digital returns. The
ground planes are tied together by a single trace under
the AD9708/AD9760/AD9762/AD9764. Clock and the
digital input word have been routed over the digital
ground plane. Reference circuitry and output signal
have been routed over the analog ground plane. As the
users ponder the layout of their own board, they might
consider using the ground planes to develop a controlled impedance with its associated signal layers. This
is required if fast edge rates and/or long trace lengths
are present. Propagation time and line loading will become a concern under these conditions.
The AD9708/AD9760/AD9762/AD9764 is shipped with
JP2 “B” Pos, JP4 and JP1 “A” Pos installed.
For immediate operation, the user need only apply
power and a CMOS level input word to P1 and a CMOS
level clock to J1 (CMOS levels cross a threshold of
{DVDD – DGND}/2). The analog output can be observed
at J3, J4 or J7 (the transformer should be removed before making observations at J3 or J4). Refer to Figure 3
for setup. See sections on resistive and transformer
loads.
+5V
NOMINAL
DVDD
WORD
GENERATOR
+5V
NOMINAL
DGND
–5V OR
AS REQ
AVDD AVEE
+5V OR
AS REQ
AGND
AD9708/60/62/64
EVALUATION BOARD
P1
DIGITAL INPUT SIGNAL CONFIGURATIONS
To allow flexibility in the input logic levels used, the
AD9708/AD9760/AD9762/AD9764-EB allows several input coupling schemes. Refer to Figure 1.
Load impedance seen by the input word generator is
controlled by R1, R2, R5 and R6. Resistor networks R1
and R2 are tied to DGND. Resistor networks R5 and R6
are tied to DVDD. Their values can be selected to present
the desired load impedance and thevenin voltage to
meet the user’s signal generator requirements. R40 and
R41 are series resistor networks of 22 Ω. If ac-coupled
inputs are desired, R40 and R41 should be removed and
ac-coupling capacitors soldered on the backside of the
board (C19, C1, C2 and C25 through C36). Resistor networks R3, R4, R7 and R8 serve to determine the dc
clamp voltage (level shift) of the ac-coupled signal.
We recommend the clamp voltage be at the switching
threshold of the AD9708/AD9760/AD9762/AD9764 device ({DVDD – DGND}/2).
AVCC
J3, J4,
OR J7
SPECTRUM
ANALYZER
EXTERNAL
CLOCK
Figure 3. Equipment Setup
POWER CONNECTIONS
The AD9708/AD9760/AD9762/AD9764-EB is powered by
two power supplies. They are shown in the table below
with typical amplitudes for initial operation (setup is
shown in Figure 3). Power is distributed on the board
with power planes.
Care should be made to properly load the input word at
the input connector (P1, a 100 mil sq. ribbon connector)
and at the AD9708/AD9760/AD9762/AD9764. Proper load
termination at these points will insure that the digital input lines are not ringing at the AD9708/AD9760/AD9762/
AD9764 device input pins. Note: alternate pins of the
ribbon connector are grounded on the board.
Table I. Power Supplies
DVDD +5 V
AVDD +5 V
AVEE† –5 V
AVCC† +5 V
1 in = 10 mA typ*
1 in = 30 mA typ*
*Current was measured with a 50 MHz clock, +5 V supplies and 50 Ω
loads on the signal output pins.
†These supplies are not required for DAC operation. (Current drain
depends on what components are mounted.)
The AD9708/AD9760/AD9762/AD9764-EB is shipped
without R1 through R8 or the ac-coupling capacitors.
Series input resistors R40 and R41 are installed.
AVDD and DVDD may be varied independently from
+3 V to +5 V depending on the user’s application (logic
family, power limits, etc.). AVEE and AVCC are used to
power the optional, external reference and output amplifier circuits. When using high supply potentials (voltages greater that ±6.5 V, the user should ensure that the
AD9708/AD9760/AD9762/AD9764 device is not over
stressed (i.e., don’t let the AD9708/AD9760/AD9762/
AD9764 device’s reference or output pins see high voltage transients on turn-on). To avoid damage, please
consult data sheet for maximum values.
CLOCK INPUT
The AD9708/AD9760/AD9762/AD9764’s data input is
triggered on the rising edge of its input clock. This clock
signal is fed to the DAC through either J1 or P1.
The clock source may be taken from either J1 or P1, depending on the position of jumper JP1. If the jumper is
in position “A,” the clock is fed from J1 (SMA connector). If it is in position “B,” it is fed through P1 (ribbon
connector). J1 is terminated by a 49.9 Ω, 1/8 W resistor.
P1’s signal is routed through the same input loading/
level-shifting scheme as the input data word (see digital
input signal configurations). The board is shipped with
the clock signal routed from J1 (JP1 “A” Pos connected).
–2–
VCC
CONNECTOR
(+)
C8
10µ[email protected]
25V
EXISTING COMPONENTS
R18
499Ω
J3
IOUT A
(OUT 1)
JP7A
A POS
JP6A
C12
22pF
R10
499Ω
C21
0.1µF
JP8
B POS
R20
49.9Ω
AD9708/60/62/64
AD9631
J4
2
IOUT B
(OUT 2)
JP7B
A POS
JP6B
C13
22pF
R37
121Ω
7
3
R9
JP9
SHORT A POS
C22
1µF
J6
6
4
R35
499Ω
R36
499Ω
R38
49.9Ω
C23
0.1µF
C24
1µF
C5
10µ[email protected]
25V
VEE
CONNECTOR
(–)
Figure 4. Differential Amplifier Configuration
VCC
CONNECTOR
(+)
EXISTING COMPONENTS
J3
IOUT A
(OUT 1)
C8
10µ[email protected]
25V
JP6A
C12
22pF
R20
50Ω
A POS
AD9708/60/62/64
IOUT B
(OUT 2)
JP7A
R9
SHORT
C21
0.1µF
JP8
B POS
B POS
J6
AD9631
JP6B
C13
22pF
7
3
J4
C22
1µF
2
6
R37
121Ω
4
R38
50Ω
R35
499Ω
R36
499Ω
C23
0.1µF
C24
1µF
JP9
B POS
C5
10µ[email protected]
25V
VEE
CONNECTOR
(–)
Figure 5. Noninverting Amplifier Configuration
VCC
CONNECTOR
(+)
EXISTING COMPONENTS
J3
IOUT A
(OUT 1)
JP6A
C12
22pF
IOUT B
(OUT 2)
R36
499kΩ
R20
49.9Ω
A POS
AD9708/60/62/64
C8
10µ[email protected]
25V
JP7A
R9
SHORT
JP9
A POS
2
J4
B POS
3
J6
6
C23
0.1µF
VEE
CONNECTOR
(–)
Figure 6. Inverting Amplifier Configuration
–3–
R37
121Ω
4
R18
165Ω
R38
49.9Ω
C22
1µF
7
AD9631
JP6B
C13
22pF
C21
0.1µF
R35
249kΩ
C24
1µF
C5
10µ[email protected]
25V
OUTPUT CONFIGURATIONS
Resistive Load
The single-ended outputs of the AD9708/AD9760/AD9762/
AD9764 may be observed through J3 and J4. At these
points the user will observe IOUTA and its complement,
output IOUTB (respectively). The output voltage is developed by the flow of output current into 50 Ω resistors
(R20, R38) and 20 pF capacitors (C12, C13). One RC net is
shunted to ground for each output. The evaluation
board is shipped with the RC networks installed. Refer to
Figures 2 and 14 for schematics.
FCLK = 50MHz
FOUT = 5MHz
SFDR = 69dB
Figure 7 illustrates a frequency domain plot for the resistive load. It was obtained by connecting a spectrum analyzer to J3 with a 50 Ω cable. The spectrum analyzer
input impedance was set to 50 Ω. There may be some
difference between the frequency domain spurs between
IOUTA and IOUTB. The transformer must be removed
for measurements using the resistive loads.
Figure 8. Transformer Output Load
Amplifier Load
The AD9708/AD9760/AD9762/AD9764 can be operated in
differential or single-ended modes through the use of
high quality amplifiers such as the AD9631. The op amp
is especially useful at analog output frequencies below
300 kHz and where dc accuracy is important. The
AD9708/AD9760/AD9762/AD9764-EB is shipped without
the output op amp and its support components. Table II
details the components that can be mounted with the
amplifier (refer to the schematics in Figures 4, 5, 6 and
13). By mounting the components outlined in Table II,
various amplifier configurations may be obtained.
The transformer should be removed from the board before using the amplifier. Figures 9, 10 and 11 illustrate
typical frequency domain plots for differential, inverting
(AV = –2) and noninverting (AV = +2) configurations.
FCLK = 50MHz
FOUT = 5MHz
SFDR = 75dB
FCLK = 50MHz
FOUT = 5MHz
SFDR = 68dB
Figure 7. Resistive Output Load
Transformer Load
With T1 in place, the differential signals of IOUTA and
IOUTB are converted from differential to single-ended
mode. This signal can be observed at J7. It is derived by
transformer T1 (mini-circuits T1–1T). The transformer is
capable of processing signals above 350 kHz from the
AD9708/AD9760/AD9762/AD9764 device. The transformer
can process signals above 80 MHz, well beyond the
Nyquist frequency of the DAC. The board is shipped
with the transformer and its associated components in
place. Refer to Figures 2 and 14 for schematics.
Figure 9. Differential Amplifier Output
Figure 8 illustrates a frequency domain plot for the
transformer load. It was obtained by connecting a spectrum analyzer to J7 with a 50 Ω cable. The spectrum analyzer input impedance was set to 50 Ω.
–4–
Table II. Amplifier Circuit Configurations
Nomenclature
Description
Differential
Gain of 2
Inverting
Gain of 1
Noninverting
Gain of 2
J6
JP6A
JP6B
JP7A “A” Pos
JP7A “B” Pos
JP7B “A” Pos
JP7B “B” Pos
JP8 “A” Pos
JP8 “B” Pos
JP9 “A” Pos
JP9 “B” Pos
R9
R10
R12
R13
R18
R35
R36
R37
U4
SMA
Jumper
Jumper
Jumper
Jumper
Jumper
Jumper
Jumper
Jumper
Jumper
Jumper
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Op Amp
Installed
Installed
Installed
Installed
Open
Installed
Open
Open
Installed
Installed
Open
Shorted
499 Ω 1/8 W
Open
Open
499 Ω 1/8 W
499 Ω 1/8 W
499 Ω 1/8 W
121 Ω 1/8 W
AD9631
Installed
Installed
Installed
Open
Open
Installed for Out 2
Installed for Out 1
Open
Open
Installed
Open
Shorted
Open
Open
Open
165 Ω 1/8 W
249 Ω 1/8 W
499 Ω 1/8 W
121 Ω 1/8 W
AD9631
Installed
Installed
Installed
Installed for Out 1
Installed for Out 2
Open
Open
Open
Installed
Open
Installed
Open
Shorted
Open
Open
Open
499 Ω 1/8 W
499 Ω 1/8 W
121 Ω 1/8 W
AD9631
The plots shown in Figures 10, 11 and 12 were measured
with a 10X, 10 MΩ, 13 pF probe connected to J7. The
Spectrum analyzer input impedance was set to 1 MΩ.
FCLK = 50MHz
FOUT = 5MHz
SFDR = 61dB
An AD9631 op amp was used with the resistor values
shown in Table II. Other op amps can be used to fit a
specific application. A list of prospective Analog Device
op amps is shown in Table III.
FCLK = 50MHz
FOUT = 5MHz
SFDR = 63dB
Figure 11. Noninverting Gain of 2 Amplifiers
Table III. Op Amp Selection Guide
AD8011
AD9631*
AD8047
Figure 10. Inverting Gain of 2 Amplifiers
AD8041
f –3 dB = 300 MHz, +5 V or ±5 V Supplies,
Current Feedback
220 MHz Unity GBW, 16 ns Settling Time to
0.01%, ±5 V Supplies
130 MHz Unity GBW, 30 ns Settling to 0.01%,
±5 V Supplies
Rail-to-Rail, 160 MHz Unity GBW, 55 ns Settling to 0.01%, +5 V Supply, 26 mW
*Used to collect frequency domain plots
–5–
Internal Reference
The internal reference current is set up by R16. It is
roughly equal to 1.2 V/R16. It is enabled by grounding
R16 and placing Pin 16 of the DAC at DGND with JP4.
The center of JP3 is left floating (leaving the REFIO pin
undriven). JP2 B position must also be connected.
EXISTING COMPONENTS
J3
IOUT A
(OUT 1)
MSB
C12
20pF
R20
50Ω
AD9708/60/62/64
LSB'S
AVCC
CONNECTOR (+)
+0.8V
FROM R43
+DVDD
7
3
2
POWER-DOWN
(Sleep Mode)
By mounting J2 and R17, the AD9708/AD9760/AD9762/
AD9764 device may be operated in the sleep mode.
When JP2 (Pin 15) is pulled high, the DAC goes into a
sleep state in which it consumes 25 mW (typ). Internally,
the AD9708/AD9760/AD9762/AD9764’s sleep pin attaches to an active pull-down circuit. The device will be
functional until a pull-up is externally applied. Once the
DAC is sleeping, 35 ms (typ) will be required for it to
“wake up” after logic low is applied to Pin 15.
C17
0.1µF
AD8047
J5
The board is shipped with the internal reference enabled
(JP4 and JP2 “B pos” are installed).
REFIO
C8
10µ[email protected]
25V
6
4
JP5
A POS
C14
R45
1kΩ
R46
1kΩ
R44
C5
10µ[email protected]
25V
C15
0.1µF
AVEE
CONNECTOR (–)
BOARD LAYOUT CONSIDERATIONS
1. Use separate analog and digital ground planes joined
together at a single point near the AD9708/AD9760/
AD9762/AD9764.
Figure 12. Gain Control Using an External Reference
REFERENCE CIRCUITS
External Reference
The external reference may be used by installing the
components shown in Table IV. The dc reference is developed by U7 and buffered by U6. The dc level of VREF
can be adjusted with R43.
2. Power should be distributed from power planes or
very wide traces (as wide as possible).
3. Power plane decoupling should be done with Tantalum capacitors. Ceramic chip capacitors should be
used for reference and local power decoupling. These
capacitors should be placed at the applicable DAC
pins with traces no longer than 0.25 inches.
Table IV. Reference Circuit Components
JP2 “A” Pos
JP2 “B” Pos
JP3 “A” Pos
Jumper
Jumper
Jumper
JP3 “B” Pos
Jumper
JP4
JP5 “A” Pos
Jumper
Jumper
JP5 “B” Pos
Jumper
R42
R43
R44
R45, R46
C14
C16
C15, C17, C18
U7
U6
Resistor
Pot
Short
Resistor
Short
Chip Cap
Chip Cap
Reference
Op Amp
Installed for External Ref.
Installed for Internal Ref.
Connects Ext Ref. to REFIO
with U6 Amp.
Connects Ext Ref. to REFIO
with R43 and Reference U7.
Installed
Installed. Connects –V of U6
to AVEE
Open. Connects –V of U6 to
AGND
1 kΩ 1/8 W
5 kΩ 1/8 W
Similar protocols should be observed with compensation capacitor placement.
4. Digital switching signals should only be routed only
over the digital ground plane. Controlled impedance
should be considered for the transmission line effects
of fast rise and fall times. Analog signals should only
be routed only over the analog ground plane.
Note: The frequency domain data shown in this application note was gathered from an AD9760.
1 kΩ 1/8 W
1206 1 µF, 1206 Case
1206 0.1 µF, 1206 Case
REF-43
AD8047
–6–
BILL OF MATERIALS – AD9708/AD9760/AD9762/AD9764 EVALUATION BD
QTY
PER
REFERENCE
DESIGNATION
P
S
MFR
DIST
MFR P/N
DIST P/N
1
P1
CONNECTOR HDR RTA 4 0 PIN
PROTECTED, W/EJECTORS
P
AMP
(DIGI-KEY)
102159-9
AHR40G-ND
4
J1, J3, J4, J7
(J2, J5, J6 Optional)
CONNECTOR SMA VERTICAL
P.C. MOUNT .2 CTRS
P
E.F. JOHNSON
(POWELL ELECT)
142-0701-201
–
C1, C2, C19, C25-C36
(Optional)
CAPACITOR CHIP CERAMIC
.1µF, 50V, NPO, 5%
S
0805
R16
RESISTOR, 2.00K OHM
1% MF, 1/8 W
S
1206
PANASONIC
(DIGI-KEY)
P2.00KFCT-ND
R15, R20, R38
R17, R44
RESISTOR, 49.9 OHM
1% MF, 1/8 W
S
1206
PANASONIC
(DIGI-KEY)
P49.9FCT-ND
JP4, JP6A, JP6B
JUMPER HEADER 2 PIN
.025 SQ PINS, .10 CTRS
P
COMPNT CORP
(BISCO IND)
CSS-102-02
JP1, JP2, JP4
JUMPER SHUNTS 2 PIN
.025 SQ PINS .10 CTRS
P
COMPNT CORP
(BISCO IND)
CSS-101-03
U1
AD9708/AD9760/AD9762/AD9764
ANALOG DEVICES
AD9708, AD9760,
AD9762, AD9764
DESCRIPTION
PKG
BARE P.C. BOARD
1
3
1
3
1
2
SOL-28
JP1, JP2, JP3, JP5, JP7A,
JP7B, JP8, JP9
JUMPER HEADER 3 PIN
.025 SQ PINS, .10 CTRS
P
MOLEX
(DIGI-KEY)
22-10-2031
WM2723
TP2, TP5, TP18, TP19
TEST POINT BLK
P
COMPNT CORP
(BISCO IND)
TP-104-01-00
TP3, TP4, TP6, TP7
TEST POINT RED
P
COMPNT CORP
(BISCO IND)
TP-104-01-02
TP1, TP8, TP9, TP10, TP11,
TP13, TP14, TP12
TEST POINT WHT
P
COMPNT CORP
(BISCO IND)
TP-104-01-09
B1– B4, B5-B6
BINDING POST METAL
P
CONCORD
(BISCO IND)
01-2540-1-02
C3, C4, C5, C6
CAPACITOR CHIP TANT
10µF, 25V, TEH SERIES
S
PANASONIC
(DIGI-KEY)
ECS-H1ED106R
PCT5106CT-ND
C8 –C11, C15, C17, C21,
C23, C18
CAPACITOR CHIP CERAMIC
.1µF, 50V, X7R, 10%
S
PANASONIC
(DIGI-KEY)
ECU-V1H104KBW
PCC104BTR-ND
C7, C22, C24, C14, C16
CAPACITOR CHIP CERAMIC
1.0µF, 16V, +80-20%, Y5V
S
C12, C13
CAPACITOR CHIP CERAMIC
22pF, 50V, NPO, 5%
S
(C20)
CAPACITOR OPTIONAL
P
(U4, U6)
Op Amp (Optional)
P
4
2
7
4
2
9
3
2
D CASE
1206
1206
1206
MURATA
(NEWARK)
93F2254
PANASONIC
(DIGI-KEY)
ECU-V1H220JCM
PCC220CCT-ND
–
–
(R9, R10, R18, R35, R36,
R37, R42, R45, R46)
RESISTOR (Optional)
1% MF, 1/4 W
P
(R42)
RESISTOR (Optional)
1% MF, 1/4 W
P
(R43)
RESISTOR POT (Optional)
5 kΩ
P
(U7)
2.5 VOLTAGE REFERENCE (Optional) P
24
R9, R10, R12, R13, R18, R20,
R35, R36, R37, R42, R45, R46
SOCKET LOOSE
.015-.026 LEAD (.056 HOLE)
136
U4, U6, U7
R1–R8, R40, R41
SOCKET, SIP, JPEEL-A-WAY
ICS ).043 HOLE)
–
–
–
RC07-S
YAGO
(DIGI-KEY)
RC07-S
YAGO
(DIGI-KEY)
(DIGI-KEY)
3296W-502-ND
ANALOG DEVICES
REF43P
P
MILL-MAX MFG
(HDWR SPEC)
0555-0-15-01-20-2710-0
P
ADV. INTER.
(CAL-CREG COMP)
KSS10085TG
–
DIP-08
T1
1
P
TRANSFORMER RF
DIP-06
(R1–R8)
RESISTOR NETWORK (Optional)
10 PIN SIP 9 RES
P
R41, R40
RESISTOR NETWORK
10 PIN SIP 22 Ω
P
–
2
ANALOG DEVICES
DIP-08
MOD.T1-1T
X65 CASE
CTS
(DIGI-KEY)
761-3-R22-ND
SIP-10
DIP-16
–7–
MINI-CIRCUITS
–8–
Figure 13. Complete Board Schematic
NOTE: ON SOME JP'S
1–2 = A CONNECTION
2–3 = B CONNECTION
Figure 14. Silkscreen Layer—Top
Figure 15. Component Side PCB Layout (Layer 1)
–9–
Figure 16. Ground Plane PCB Layout (Layer 2)
Figure 17. Power Plane PCB Layout (Layer 3)
–10–
Figure 18. Solder Side PCB Layout (Layer 4)
Figure 19. Silkscreen Layer—Bottom
–11–
–12–
PRINTED IN U.S.A.
E3034–2–6/97