HDMI2C2-14HD ESD protection and signal booster for HDMI™ 1.4 sink interface Datasheet − production data • Protection of ultra-sensitive HDMI ASICs • Low power consumption in stand-by mode • Wake-up from stand-by through CEC bus • Improved HDMI interface ruggedness and user experience • Long and/or poor quality cable support • Companion chip for STMicroelectronics’ STixxxx HDMI decoders. Complies with the following standards • HDMI 1.4 version • IEC 61000-4-2 level 4 QFN 36L 3.5 X 6.5 • JESD22-A114D level 2 Applications Features • HDMI 1.3 and 1.4 compliant: from -40 to 85 °C • 8 kV contact ESD protection on connector side • Supports direct connection to low-voltage HDMI ASIC and/or CEC driver (down to 1.8 V) • High integration level in 1 package • TMDS high bandwidth ESD protection • DDC (I2C) link protection, bi-directional signal conditioning circuit, and dynamic pull-up • CEC bus protection, bi-directional level-shifter, backdrive protection, and independent structure from main power supply • HEAC/HPD link protection and line matching • Proposed in QFN 36 leads 500 µm pitch Benefits • Consumer and computer electronics HDMI™ sink device such as: – HD set-top boxes – DVD and Blu-Ray Disk systems – Home theater – Game console Description The HDMI2C2-14HD is a fully integrated ESD protection and signal conditioning device for control links and TMDS data video channels of HDMI receivers (Sink). The HDMI2C2-14HD is a simple solution that provides HDMI designers with an easy and fast way to reach full compliancy with the stringent HDMI 1.4 CTS on a wide temperature range. • Speed-up hardware design and certification of HDMI 1.4 application • Pin map sequence compliant with HDMI connector type A • Minimal PCB footprint in consumer area August 2014 This is information on a product in full production. TM: HDMI: the HDMI logo and High-Definition Multimedia Interface are trademarks or registered trademarks of HDMI Licensing LLC. DocID024813 Rev1 1/31 www.st.com Contents HDMI2C2-14HD Contents 1 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.1 CEC line description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.2 DDC functional block description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.3 HEAC link and HPD line protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.4 TMDS channels ESD protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.5 Application block diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5 Recommendation on PCB assembly . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.1 Stencil opening design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.2 Solder paste . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.3 Placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.4 PCB design preference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.5 Reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 2/31 DocID024813 Rev1 HDMI2C2-14HD 1 Functional description Functional description The HDMI2C2-14HD is a fully integrated ESD protection and signal conditioning device for control links and TMDS data video channels of HDMI receiver (Sink). The control stage provides a bidirectional buffer, integrating signal conditioning and dynamic pull-up on DDC bus for maximum system robustness and signal integrity. The HEAC (HDMI Ethernet and Audio return Channels) function is supported, making the component fully compliant with HDMI 1.4 version. A bidirectional CEC block is integrated, able to wake-up the application from stand-by mode (all power supply off, except the CEC power supply). The integrated TMDS links ESD protection allows a video data rate up to 10.2 Gbps, corresponding to the maximal speed specified by HDMI standard. All video format specified by HDMI standard (from 720p30 up to 1080p60 3D) are supported, giving maximum flexibility to designer. All these features are provided in a single 36 leads QFN package featuring natural PCB routing and saving space on the board. The HDMI2C2-14HD is a simple solution that provides HDMI™ designers with an easy and fast way to reach full compliancy with the stringent HDMI 1.4 CTS on a wide temperature range. STMicroelectronics proposes a dual version dedicated for the Sources interfaces: the HDMI2C1-14HD. DocID024813 Rev1 3/31 31 Functional description HDMI2C2-14HD VDD_CEC_IC nc VDD_IC nc CEC_IC Figure 1. Pin out, top view SCL_IC VDD_CEC SDA_IC DDC_EN 5V_IN nc ESD_DISCH nc DAT_D2+_IC DAT_D2+ DAT_D2 - _IC DAT_D2GND DAT_D1+_IC DAT_D1+ DAT_D1-_IC DAT_D1- DAT_D0+_IC DAT_D0+ DAT_D0- DAT_D0-_IC 4/31 DocID024813 Rev1 CEC Utility SCL SDA DAT_CK- HPD DAT_CK -_IC HEAC-/HPD_IC DAT_CK+ HEAC+ DAT_CK+_IC HDMI2C2-14HD Application information 2 Application information 2.1 CEC line description The CEC bus is described in the HDMI standard as the Consumer Electronics Control. It provides control functions between all the various audiovisual equipments chained in the user's environment. The CEC block integrated in the HDMI2C2-14HD implements a level shifter, shifting the cable CEC +3.3 V voltage (VDD_CEC) down to the ASIC power supply voltage (VDD_IC) that can be as low as 1.8 V. The Figure 2 shows the functional diagram of the integrated CEC block. Figure 2. CEC functional block diagram VDD_CEC_IC VDD_CEC VDD_CEC_IC RPU_CEC_IC HBM IEC61000-4-2 CEC_IC CEC diode decoupling capacitance Enable Ctrl circuit RPU_CEC_BUS Anti back drive decoupling capacitance CEC driver HDMI connector VDD_CEC UVLO 1 3 5 7 9 11 13 15 17 19 2 4 6 8 10 12 14 16 18 In case of no activity on the CEC bus, or if the CEC driver is off (VDD_CEC_IC = 0), the CEC pin is put in high impedance mode (open circuit) protecting the circuitry and the application against hazardous backdrive. The Figure 3 illustrates the normal operating mode of the CEC functional block when either the IC from the source on the sink drives the communication. Figure 3. CEC simplified ASIC side CEC_IC CEC_IC VDD_CEC_IC VDD_CEC_IC VIH_CEC_IC VIL_CEC_IC t t CEC Cable side CEC VDD_CEC V DD_CEC 90% VTup_CEC VHYST_CEC V Tdown_CEC 10% Block in high impedance tFALL_CEC t Block in high impedance Level shifting Source IC drives tRISE_CEC DocID024813 Rev1 t Block in high impedance Level shifting Block in high impedance Sink drives through HDMI cable 5/31 31 Application information HDMI2C2-14HD In case the application is set in stand-by mode, the +5 V main supply of the application is generally powered off in order to reduce as much as possible the global power consumption. The CEC driver can be the only device still working in low power mode, allowing a wake up of the whole application through the CEC line. When the main power supply +5 V is switched off, and if the CEC bus is still active (VDD_CEC power in on state), the HDMI2C2-14HD keeps the CEC bus working properly while all other outputs of the component are put in high impedance mode. The CEC output (cable side) integrates a protection against ESD which is compliant with IEC61000-4-2 standard, level 4 (8kV contact). 2.2 DDC functional block description The DDC bus is described in the HDMI 1.4 standard as the Display Data Channel. The topology corresponds to an I2C bus that must be compliant with the I2C bus specification version 2.1 (January 2000). The DDC bus is made of 2 lines: data line (SDA) and clock line (SCL). It is used to create a point to point communication link from the source to the sink. EEDID and HDCP protocols are flowing through this link, making this I2C communication channel a critical element in the HDMI application. The DDC block integrated in the HDMI2C2-14HD allows a bidirectional communication between the cable and the ASIC. It is fully compliant with the HDMI 1.4 standard and its CTS, but also with the I2C bus specification version 2.1. The DDC block shifts the electrical and threshold levels of SDA and SCL lines from the +5 V voltage from the cable (V5V_IN) down to the ASIC voltage level (VDD_IC), that can be as low as 1.8 V. The Figure 4 shows the functional diagram of the DDC block integrated in the HDMI2C2-14HD device. Figure 4. The DDC functional block diagram (SCL and SDA lines) VDD_IC +5V decoupling capacitance VDD_IC DDC_EN 1 3 5 5V_IN SCL_IC SDA_IC HBM reshaping circuit Drive RPU_BUS SCL SDA IEC61000-4-2 5V_IN Enable Dynamic pull-up HDMI ASIC RPU_ASIC 5V_IN 7 9 11 13 15 17 19 2 4 6 8 10 12 14 16 18 HDMI connector The DDC_EN allows to authorize or not a bidirectional communication through the functional block. It can be connected to the main +5V of the board, or to the ASIC power supply, detecting then if the application is ready for communication or not. The DDC outputs (SCL and SDA on cable side) integrate a protection against ESD which is compliant with IEC61000-4-2 standard, level 4 (8kV contact). 6/31 DocID024813 Rev1 HDMI2C2-14HD Application information The Figure 5 illustrates the electrical parameters of the DDC block specified in Table 7. Figure 5. Simplified view of the electrical parameters of the DDC functional block ASIC side SDA_IC VDD_IC Vtup_IC V Tdown_IC t SDA Cable side 5V_IN 70% Vtup_BUS V Tdown_BUS V HYST_BUS 30% t T FALL_BUS T RISE_BUS IC drives Cable drives The HDMI standard specifies that the maximum capacitance of the cable can be as high as 700 pF. Knowing that the maximum capacitance of the source input can reach up to 50 pF, this means that the I2C driver must be able to drive a load capacitance up to 750pF. On the other hand, the I2C standard specifies that the maximum rise time of the signal must be lower than 1 µs in order to keep the signal integrity. Taking into account the maximum cable capacitance of 750 pF, it is not possible to guarantee a rise time lower than 1 µs in worst case. Therefore, a dynamic pull-up, synchronized with the I2C driver, has been integrated at the output of SDA and SCL lines. This signal booster accelerates for a short period the charging time of the equivalent cable capacitance, allowing to drive any HDMI cable. This dynamic pull-up is recommended by the I2C standard. The Figure 6 illustrates the benefit of the dynamic pull-up integrated in the HDMI2C2-14HD device. DocID024813 Rev1 7/31 31 Application information HDMI2C2-14HD Figure 6. Benefit of the dynamic pull-up on the DDC bus I2C driver without dynamic pull-up I2C driver with dynamic pull-up 5V_IN Dynamic pull-up 5V_IN R PU_BUS 750pF R PU_BUS 750pF HDMI™ cable model HDMI™ cable model IC control IC control VDD_IC V DD_IC Signal on the cable Signal on the cable 5V_IN 5V_IN Rise time out of I2C specification Risk of communication failure Rise time compliant with I2C specification Signal integrity even on 750pF load capacitance In order to activate the DDC bus, both following conditions must be respected: the VDD_5V must be higher than the VDD_ON threshold (see Table 3) and all inputs and outputs of the bidirectional level shifters (SCL, SDA, SCL_IC, SDA_IC) must be set to a high level at the same time. The DDC outputs (SCL and SDA on cable side) integrate a protection against ESD which is compliant with IEC61000-4-2 standard, level 4 (8kV contact). 8/31 DocID024813 Rev1 HDMI2C2-14HD HEAC link and HPD line protection The HDMI2C2-14HD proposes a unique solution in order to manage and protect both the HEAC and the HPD links. The HPD line is describe in the HDMI standards as a Hot Plug Defect function.This line is used by the source device in order to detect if a sink device is connected through an HDMI cable. The HEAC link is described in the HDMI 1.4 standards as the HDMI ethernet and audio return channel. It corresponds physically to one differential wired pair made of the utility line and the HPD line. Two signals are transmitted through this link. The first signal corresponds to the HDMI Ethernet Channel (HEC). The signal is transmitted in differential mode (bidirectional) through the HEAC link. It is specified by the 100Base TX IEEE 802.3 standard (Fast Ethernet 100Mbps over twisted pair). Therefore, the HEC integrates an Ethernet link into the video cable, enabling IP-based applications over the HDMI cable. The second signal corresponds to the Audio Return Channel (ARC). The signal is transmitted in common mode (unidirectional, from sink to source) through the HEAC link. It is specified by the IEC 60958-1 standard. The ARC integrates an upstream audio capability, simplifying the cabling of the audiovisual equipments. It is no more necessary to use a coaxial cable from TV to audio amplifier. The HDMI2C1-14HD helps the designer to implement this high added value HEAC function in the application, protecting the link against the ESD with no disturbance of the signal, thanks to the integrated matching circuitry on HEAC+ line. It provides 2 distinct outputs HEAC+ and HEAC- in order to ease as much as possible the PCB layout. Both HPD and utility inputs (cable side) integrate a protection against ESD which is compliant with IEC61000-4-2 standard, level 4 (8kV contact). Figure 7. HEAC / HPD / utility functional block diagram VDD_IC decoupling capacitance HDMI connector HPD HDMI2C2-14HD HDMI ASIC HEAC- HPD / HEAC- HEAC- / HPD_IC IC HEAC+ DocID024813 Rev1 7 9 11 13 Utility HEAC+ 1 3 5 IEC61000-4-2 or HPD IEC61000-4-2 2.3 Application information 15 Utility / HEAC+ 17 2 4 6 8 10 12 14 16 18 19 9/31 31 Application information 2.4 HDMI2C2-14HD TMDS channels ESD protection The TMDS (Transient Minimized Differential Signaling) channels are described by the HDMI 1.4 standard. A total of 4 unidirectional differential pairs are used to transmit the video data to the sink device. There are 3 channels dedicated to the video data, and 1 channel dedicated to the clock. The frequency of the TMDS clock is 1/10 of the video data frequency. The HDMI2C2-14HD provides a simple PCB layout solution, directly compliant with HDMI connector type A. It protects the application against the ESD according the IEC61000-4-2 level 4 standard (+/-8 kV contact). The high bandwidth of this ESD protection allows to transmit HD video high speed data with no disturbance of the signal. The TDR is compliant with the HDMI specification. A capacitor can be optionally connected to the ESD_DISCH pin in order to enhance the ESD protection performances. Figure 8. TMDS lines ESD protection functional diagram 5V_IN HDMI connector VDD_IC HDMI ASIC DAT_D2+_IC DAT_D2+ DAT_D2 - _IC DAT_D2- 3 DAT_D1+_IC DAT_D1+ 5 DAT_D1- _IC DAT_D1- DAT_D0+_IC DAT_D0+ 7 9 11 DAT_D0 - _IC DAT_D0 - 13 DAT_CLK+_IC DAT_CLK+ 15 17 DAT_CLK - _IC DAT_CLK- 19 1 2 4 6 8 10 12 14 16 18 IEC61000-4-2 ESD_DSICH 2.5 Application block diagrams The Figure 9 shows a typical application block diagram proposal implementing all the possible options. The TMDS channels are simply connected to the connector and to the HDMI ASIC. The diagram shows that the CEC driver can be totally independent from the HDMI ASIC. By this way, even if the +5 V power supply and/or if the HDMI ASIC is sleeping, the CEC bus is still active in low power mode. The designer has then all the tools to optimize the power consumption of the global application in stand-by mode, and has the possibility to implement a smart wake-up through the CEC bus enhancing the final user experience. 10/31 DocID024813 Rev1 HDMI2C2-14HD Application information Figure 9. Modification of block diagram VDD_IC HDMI2C2 - 14HD TMDS lines IN 4 TMDS channels 8 lines TMDS data 2+ TMDS data 2TMDS data 1+ TMDS data 1TMDS data 0+ TMDS data 0TMDS Clock+ TMDS Clock- TMDS lines OUT ESD_DISCH DDC_EN C6 VDD_IC +5V power 5V_IN VDD_IC HDMI ASIC C2 EEPROM (EEDID) R3 C3 R2 HDMI connector VDD_IC R4 R5 DDC data SDA_IC SCL_IC HEAC+ HEAC- /HPD_IC DDC clock HEAC+ HEAC - HPD HPD / HEAC - SDA SCL SDA SCL Utility Utility / HEAC+ HPD VDD_CEC_IC VDD_CEC VDD_CEC_IC VDD_CEC C1 C5 R6 CEC driver D1 R1 CEC_IC CEC CEC bus GND Table 1. Block diagrams references Ref. Typical values R1 27 kΩ Pull-up resistance on CEC bus, specified by the HDMI standard R2, R3 47 kΩ Pull-up resistances on DDC bus, specified by the HDMI standard R4, R5 10 kΩ Pull-up resistance on DDC bus, ASIC side, value selected to be compliant with I2C levels R6 Comment 270 kΩ to 1 ΜΩ Pull-up resistance on CEC line, ASIC side D1 BAT54 Small schottky diode blocking backdrive current flowing toward the VDD_CEC supply C1, C2, C3 and C5 100 nF Decoupling capacitance on power supplies C6 1 µF ESD protection enhancement capacitance (option) Note: SCL_IC, SDA_IC, and CEC_IC have to be driven with an ASIC working with open drain outputs. Note: even if not specified by HDMI standard, it is recommended to add pull-up resistance on SDA line (cable side) to avoid floating line. DocID024813 Rev1 11/31 31 Application information HDMI2C2-14HD Figure 10. Modification of block diagram (with HDMI connector type A) VDD_CEC_IC VDD_CEC_IC R6 CEC driver EEPROM VDD_IC VDD_CEC_IC VDD_CEC C5 5V_IN C1 C2 C3 R5 R4 DDC clock DDC data SCL_IC VDD_CEC SDA_IC DDC_EN nc TMDS Data2+ ESD_DISCH nc DAT_D2+_IC DAT_D2+ DAT_D2-_IC DAT_D2- TMDS Data2 Shield 4 TMDS channels, 8 lines HDMI ASIC C6 HDMI connector type A 5V_IN TMDS Data2TMDS Data1+ DAT_D1+_IC GND DAT_D1+ TMDS Data1 Shield DAT_D1-_IC DAT_D1- DAT_D0+_IC DAT_D0+ TMDS Data1TMDS Data0+ DAT_D0-_IC DAT_D0- DAT_CK+_IC DAT_CK+ DAT_CK-_IC DAT_CK- TMDS Data0 Shield TMDS Data0TMDS Clock+ VDD_CEC TMDS Clock Shield D1 R1 TMDS ClockCEC HEAC+ HEAC - Utility / HEAC+ SCL HPD SDA R3 5V_IN R2 DDC/CEC GND / HEAC shield +5V power HPD / HEAC - The Figure 10 illustrates the fact that the HDMI2C2-14HD pin configuration eases and optimizes the PCB layout of the HDMI interface. The proposed pin-out sequence is directly compliant with HDMI connector type A. 12/31 DocID024813 Rev1 HDMI2C2-14HD Application information Table 2. Pin description Pin Name Description Pin Name 1 SDA_IC 2 nc 3 DDC input ASIC side 19 DAT_CK- TMDS output Clock CK- not connected 20 DAT_CK+ TMDS output Clock CK+ ESD_DISCH ESD protection enhancement capacitance 21 DAT_D0- TMDS output Data D0- 4 DAT_D2+_IC TMDS input Data D2+ 22 DAT_D0+ TMDS output Data D0+ 5 DAT_D2-_IC TMDS input Data D2- 23 DAT_D1- TMDS output Data D1- 6 DAT_D1+_IC TMDS input Data D1+ 24 DAT_D1+ TMDS output Data D1+ 7 DAT_D1-_IC TMDS input Data D1- 25 DAT_D2- TMDS output Data D2- 8 DAT_D0+_IC TMDS input Data D0+ 26 DAT_D2+ TMDS output Data D2+ 9 DAT_D0-_IC TMDS input Data D0- 27 nc 10 DAT_CK+_IC TMDS input Clock CK+ 28 5V_IN +5V power supply HDMI cable side 11 DAT_CK-_IC TMDS input Clock CK- 29 5V_SYS_DETECT SENSING OF +5V main power supply 12 HEAC+ HEAC+ output ASIC side 30 VDD_CEC 13 HEAC- HEAC- output ASIC side 31 VDD_CEC_IC 14 HPD HPD/HEAC- input HDMI cable side 32 nc 15 SDA DDC output HDMI cable side 33 VDD_IC 16 SCL DDC output HDMI cable side 34 nc 17 Utility Utility/HEAC+ input HDMI cable side 35 CEC_IC CEC input ASIC side 18 CEC CEC output HDMI cable side 36 SCL_IC DDC input ASIC side DocID024813 Rev1 Description not connected CEC supply HDMI cable side CEC driver power supply not connected HDMI ASIC power supply not connected 13/31 31 Application information HDMI2C2-14HD 33 VDD_CEC_IC VDD_IC 34 32 31 30 VDD_CEC SDA_IC 1 29 DDC_EN nc 2 28 5V_IN ESD_DISCH 3 27 nc DAT_D2+_IC 4 26 DAT_D2+ DAT_D2 - _IC 5 25 DAT_D2- DAT_D1+_IC 6 24 DAT_D1+ DAT_D1-_IC 7 23 DAT_D1- DAT_D0+_IC 8 22 DAT_D0+ 9 21 DAT_D0- DAT_CK+_IC 10 20 DAT_CK+ DAT_CK -_IC 11 19 DAT_CK- 13 14 15 16 17 18 HPD SDA SCL Utility CEC HEAC+ 12 GND HEAC-/HPD_IC DAT_D0-_IC 14/31 35 nc 36 nc SCL_IC CEC_IC Figure 11. Pin numbering DocID024813 Rev1 HDMI2C2-14HD 3 Electrical characteristics Electrical characteristics Table 3. Absolute maximum ratings (limiting values) Symbol Parameter Test conditions Value Unit Vpp_BUS ESD discharge on HDMI BUS side (pin 14 to 26, and pin Contact discharge 28), IEC 61000-4-2 level 4 ±8(1) kV Vpp_IC ESD discharge (all pins), HBM JESD22-A114D level 2 Contact discharge ±2 kV Tstg Storage temperature range -55 to +150 °C Top Operating temperature range -40 to +85 °C TL Maximum lead temperature 260 °C 6 V -0.3 to 6 V V5V_IN VDD_IC Supply voltages VDD_CEC VDD_CEC_IC Inputs Logical input min/max voltage range 1. With a 100 nF capacitor connected to the 5V_IN pin. Table 4. Power supply characteristics (Tamb = 25 °C) Symbol Parameter VDD_CEC CEC supply voltage, bus side 2.97 CEC supply voltage, IC side VDD_IC V5V_IN VDD_CEC_IC VDD_CEC_ON IQS_5V_IN IQS_IC IQS_CEC IQS_CEC_IC Rth PTOTAL_SB Test conditions Min. Typ. Max. 3.63 V 1.62 3.63 V Low-voltage ASIC supply voltage 1.62 3.63 V 5 V cable supply voltage range 4.7 5.0 5.3 V CEC power on reset 2.6 2.8 2.95 V VDD_5V = 5 V, VDD_IC = 1.8 V, VDD_CEC = 3.3 V Quiescent currents on VDD_5V_IN, VDD_IC, VDD_CEC, VDD_CEC_IC = 1.8 V VDD_CEC_IC Idle-state on CEC and DDC links, HPD and 5V_OUT links open 3.3 Unit 500 75 µA 200 40 Junction to ambient thermal resistance Copper heatsink as shown by Figure 24 75 °C/W Standby conditions VDD_5V = VDD_IC = 0 V VDD_CEC = 3.3 V VDD_CEC_IC = 3.3 V 0.8 mW DocID024813 Rev1 15/31 31 Electrical characteristics HDMI2C2-14HD Table 5. CEC electrical characteristics(1) Symbol VTup_CEC Parameter Test conditions Min. Typ. Max. Upward input voltage threshold on bus side 1.6 VTdown_CEC Downward input voltage threshold on bus side 0.8 Output rise-time (10% to 90%) TFALL_CEC Output fall-time (90% to 10%) IOFF_CEC VIL_CEC_IC 0.4 RUP = 14.1 kΩ(2) ±5% CCEC CABLE = 9.7 nF Leakage current in powered-off state VDD_5V = 0 V, VDD_IC = 0 V, VDD_CEC = 3.3 V Input low level on IC side CIN_CEC 1. V 250 µs 50 µs 1.8 µA 0.5 %VDD_IC VIH_CEC_IC Input high level on IC side RON_CEC On resistance across CEC and CEC_IC pins CEC pin to 0 V Input capacitance on CEC link VDD_5V = 0 V VDD_CEC = 0 V VDD_IC = 0 V VBIAS = 0 V, f = 1 MHz, VOSC = 30 mV V V VHYST_CEC Input hysteresis on bus side TRISE_CEC Unit 115 70 %VDD_IC 160 Ω 40(3) pF Tamb = 25 °C, VDD_CEC = 3.3 V, VDD_CEC_IC = 1.8 V, unless otherwise specified 2. Test conditions are compliant with worst case CEC specification: - Correspond to two 27 kΩ +5% pull-up resistances in parallel (compliant with HDMI CTS) - Max capacitance corresponding to 9 equipment chained on the CEC bus 3. Maximum capacitance allowed at connector output is 200 pF in HDMI 1.4 specification Table 6. HPD, HEAC, and utility line electrical characteristics(1) Value Symbol Parameter Test conditions Unit Min. CIN_HPD Input capacitance CIN_UTILITY fCUT_HEAC VDD_5V = 0 V, VBIAS = 0 V f = 100 kHz, VOSC = 30 mV Cut-off frequency of HEAC bus 1. Tamb = 25°C, VDD_5V = 5 V, unless otherwise specified. 16/31 DocID024813 Rev1 Typ. Max. 9 pF 500 MHz HDMI2C2-14HD Electrical characteristics Table 7. DDC bus (SDA and SCL lines) electrical characteristics(1) Value Symbol Parameter Test conditions Unit Min. Typ. VTup_BUS Upward input voltage threshold on bus side 3.5 VTdown_BUS Downward input voltage threshold on bus side 1.5 VHYST_BUS Input hysteresis on bus side 1.0 V V 1.3 V Output low level Current sunk by SDA and SCL pin is 3 mA 0.35 V TRISE_BUS Output rise-time (30% to 70%) CBUS = 750 pF(2) RUP = 2 KΩ //47 KΩ + 10%(3) 500 ns TFALL_BUS Output fall-time (30% to 70%) 50 ns VOL_BUS VTup_IC Upward input voltage threshold on IC side 55 60 65 %VDD_IC VTdown_IC Downward input voltage thresholds IC side 35 40 45 %VDD_IC 20 mV 17(4) pF VOL_IC CIN_DDC Output low level on IC side Current sunk by SDA_IC or SCL_IC pins is 500 µA Input capacitance on DDC link VDD_5V = 0 V VDD_IC = 0 V VDD_CEC = 0 V VBIAS = 0 V, f = 1 MHz VOSC = 30 mV VEN_DCC(5) DCC enabling 1. Max. 9 4.1 V Tamb = 25 °C, VDD_5V = 5 V, VDD_IC = 1.8 V, unless otherwise specified 2. Maximum load capacitance allowed on I2C entire link (cable + connector) is 750 pF in HDMI 1.4 specification. 3. Two pull-up resistors in parallel (sink 47 kΩ + source 2 kΩ). 4. Maximum capacitance allowed at connector output is 50 pF in HDMI 1.4 specification 5. In order to activate the DCC lines, the level on DCC_EN pin has to reach the VEN_DCC min value. The inputs and ouputs of the bidirectional level shifters must be set to a high level after the power-on, and the HPD line has to be activated one time. DocID024813 Rev1 17/31 31 Electrical characteristics HDMI2C2-14HD Table 8. TMDS links electrical characteristics(1) Value Symbol Parameter Test conditions Unit Min. Bandwidth at -3 dB VBR Breakdown voltage IRM Leakage current Differential mode 1. GHz 6.5 6 V VRM = 3.3 V Capacitance input/output to VI/O =0 V, f = 1 MHz, VOSC = 30 mV ground CI/O-GND Max. 4.7(2) Single ended mode fCUT_TMDS Typ. ΔCI/O-GND Capacitance variation VI/O = 0 V, f = 1 MHz, VOSC = 30 mV ZDIFF Differential impedance tr = 200ps (10%-90%) Z0DIFF=100 Ω 100 nA 1.5 pF 50 85 pF 100 115 Ω Tamb =25°C, VDD_5V = 5V, unless otherwise specified 2. The bandwidth is large enough to operate up to 340 MHz as HDMI clock frequency, corresponding to 10.2 Gbps total data rate, 3.4 Gbps on each lane Figure 12. TMDS line S21 frequency curve 0 S dd21 dB -3 -6 Scc21 -9 -12 F(Hz) -15 100k 18/31 1M 10M 100M DocID024813 Rev1 1G HDMI2C2-14HD Electrical characteristics Figure 13. TMDS line differential far end crosstalk curve 0 dB -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 F(Hz) -120 -130 10M 30M 100M 300M D2-D1_FEXT 1G 3G 10G D2-CLK_FEXT Figure 14. TMDS line: remaining voltage when positive 8 kV ESD surge applied 20 V/div 100.9 V 1 1 2 3 4 VPP: ESD peak voltage VCL :clamping voltage @ 30 ns VCL :clamping voltage @ 60 ns VCL :clamping voltage @ 100 ns 13.1 V 2 11.7 V 3 7.5 V 4 20 ns/div DocID024813 Rev1 19/31 31 Electrical characteristics HDMI2C2-14HD Figure 15. TMDS line: remaining voltage when negative 8 kV ESD surge applied 20 V/div 3.3 V -67.9 V 2 -5.1 V 3 -4.8 V 4 1 1 2 3 4 VPP: ESD peak voltage VCL :clamping voltage @ 30 ns VCL :clamping voltage @ 60 ns VCL :clamping voltage @ 100 ns 20 ns/div Figure 16. Eye diagram of TMDS line: D0, D1, D2 and CLK lanes (1.485 Gbps) 250 mV/div 112.2 ps/div 20/31 DocID024813 Rev1 HDMI2C2-14HD Electrical characteristics Figure 17. Eye diagram of TMDS line: D0, D1, D2 and CLK lanes (3.350 Gbps) 250 mV/div 49.8 ps/div Figure 18. TDR of TMDS lines: D0, D1, D2, CLK lanes TDR rise time (10%-90%): 200ps 100 W 89.8 W DocID024813 Rev1 21/31 31 Electrical characteristics HDMI2C2-14HD Figure 19. CEC typical waveforms (from source to sink communication) C2 = 1.00 V/div C3 = 500 m V/div 100 µs/div Figure 20. CEC typical waveforms (from sink to source communication) C2 = 1.00 V/div C3 = 500 m V/div 100 µs/div 22/31 DocID024813 Rev1 HDMI2C2-14HD Electrical characteristics Figure 21. DDC typical waveforms (from sink to source communication) C2 = 1.00 V/div C3 = 500 m V/div 2 µs/div Figure 22. DDC typical waveforms (source to sink communication) C2 = 1.00 V/div C3 = 500 m V/div 2 µs/div DocID024813 Rev1 23/31 31 Package information 4 HDMI2C2-14HD Package information • Epoxy meets UL94, V0 • Lead-free packages In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. Figure 23. QFN dimension definitions 24/31 DocID024813 Rev1 HDMI2C2-14HD Package information Table 9. QFN dimension values Dimensions Ref. Millimeters Inches Min. Typ. Max. Min. Typ. Max. A 0.85 0.90 0.95 0.033 0.035 0.037 A1 0.00 0.05 0.000 b 0.18 0.25 0.30 0.007 0.010 0.012 D 3.40 3.50 3.60 0.134 0.137 0.141 D2 2.25 2.30 2.35 0.088 0.090 0.092 E 6.40 6.50 6.60 0.251 0.255 0.259 E2 5.25 5.30 5.35 0.206 0.208 0.210 e 0.50 0.002 0.020 La 0.00 0.10 0.20 0.00 0.004 0.008 Lb 0.15 0.25 0.30 0.006 0.01 0.012 Lc 0.20 0.30 0.40 0.008 0.012 0.016 ddd 0.09 0.003 Figure 24. QFN footprint recommendation (dimensions in mm) 0.23 0.50 0.30 0.50 0.25 2.30 0.25 5.30 DocID024813 Rev1 0.45 25/31 31 Package information HDMI2C2-14HD Figure 25. Marking specification 2C2 - 14HD CCC Y W W e3 G WX CCC : Country of origin Y : Assy Year W W : Assy Week G : Eco Level W X : Diffusion traceability Figure 26. Tape and reel specification 2.0 Ø1.55 4.0 1.75 7.5 16.0 6.75 Ø1.5 0.9 All dimension in mm 26/31 3.75 8.0 User direction of unreeling DocID024813 Rev1 HDMI2C2-14HD Recommendation on PCB assembly 5 Recommendation on PCB assembly 5.1 Stencil opening design 1. General recommendation on stencil opening design a) Stencil opening dimensions: L (Length), W (Width), T (Thickness). Figure 27. Stencil opening dimensions L T b) W General design rule Stencil thickness (T) = 75 ~ 125 µm W Aspect Ratio = ----- ≥ 1.5 T L×W Aspect Area = ---------------------------- ≥ 0.66 2T ( L + W ) 2. Reference design a) Stencil opening thickness: 100 µm b) Stencil opening for central exposed pad: Opening to footprint ratio is 50%. c) Stencil opening for leads: Opening to footprint ratio is 90%. DocID024813 Rev1 27/31 31 Recommendation on PCB assembly HDMI2C2-14HD Figure 28. Recommended stencil window position 300 µm 13 µm 474 µm 500 µm 286 µm 7 µm 0.23 0.50 0.30 0.50 0.25 2.30 5.3 mm 300 µm 2.3 mm 1.7 mm 5.30 0.45 0.25 750 µm 3.8 mm Stencil window Footprint 5.2 28/31 Solder paste 1. Use halide-free flux, qualification ROL0 according to ANSI/J-STD-004. 2. “No clean” solder paste recommended. 3. Offers a high tack force to resist component displacement during PCB movement. 4. Use solder paste with fine particles: powder particle size 20-45 µm. DocID024813 Rev1 HDMI2C2-14HD 5.3 5.4 5.5 Recommendation on PCB assembly Placement 1. Manual positioning is not recommended. 2. It is recommended to use the lead recognition capabilities of the placement system, not the outline centering. 3. Standard tolerance of ± 0.05 mm is recommended. 4. 3.5 N placement force is recommended. Too much placement force can lead to squeezed out solder paste and cause solder joints to short. Too low placement force can lead to insufficient contact between package and solder paste that could cause open solder joints or badly centered packages. 5. To improve the package placement accuracy, a bottom side optical control should be performed with a high resolution tool. 6. For assembly, a perfect supporting of the PCB is recommended during solder paste printing, pick and place and reflow soldering by using optimized tools. PCB design preference 1. To control the solder paste amount, closed vias are recommended instead of open vias. 2. The position of tracks and open vias in the solder area should be well balanced. Symmetrical layout is recommended, in case any tilt phenomena caused by asymmetrical solder paste amount due to the solder flow away. Reflow profile Figure 29. ST ECOPACK® recommended soldering reflow profile for PCB mounting 240-245 °C Temperature (°C) 250 -2 °C/s 2 - 3 °C/s 60 sec (90 max) 200 -3 °C/s 150 -6 °C/s 100 0.9 °C/s 50 Time (s) 0 Note: 30 60 90 120 150 180 210 240 270 300 Minimize air convection currents in the reflow oven to avoid component movement. DocID024813 Rev1 29/31 31 Ordering information 6 HDMI2C2-14HD Ordering information Figure 30. Ordering information scheme HDMI2C 2 - 14 HD HDMI and I2C compliant links HDMI port type 2: sink ports Number of protected links 14 lines protected according to IEC 6100-4-2 Version HD: Full speed of HDMI supported Table 10. Ordering information 7 Order code Marking Package Weight Base qty Delivery mode HDMI2C2-14HD 2C2-14HD QFN 51.6 mg 4.000 Tape and reel Revision history Table 11. Document revision history 30/31 Date Revision 04-Aug-2014 1 Changes Initial release DocID024813 Rev1 HDMI2C2-14HD IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2014 STMicroelectronics – All rights reserved DocID024813 Rev1 31/31 31