dm00107627

AN4440
Application note
RFFE HVDAC control
Pascal Paillet
Introduction
The purpose of this application note is to familiarize mobile phone designers with RFFE
HVDAC control. Common tasks are explained and more advanced functions such as trigger
mode, extended mode or USID reprogramming are also detailed. Each frame or the
significance of the sequence is explained and illustrated with concrete examples tested with
the antenna utility tools (AUT) and the HVDAC control board either in full automatic mode or
manually (bit by bit).
HVDAC is used in mobile phones for antenna tunability. This is a programmable DC/DC
converter supplying the bias voltage for PTIC variable capacitors.
Although both SPI and RFFE interface options exist, this document concerns the latter
which is now mainstream.
April 2014
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Contents
AN4440
Contents
1
Tools installation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.1
AUT software installation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.2
HVDAC control board connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.3
HVDAC connection to the HVDAC control board . . . . . . . . . . . . . . . . . . . . 4
1.4
AUT startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.5
Register information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2
RFFE frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3
RFFE normal modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.1
Basic mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.1.1
3.2
4
5
3.2.1
Purpose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.2.2
Methodology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.1
Purpose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.2
Methodology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.3
Frame construction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
USID modification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.2
5.3
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Trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
RFFE extended mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.1
6
Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
One HVDAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.1.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.1.2
Sequence construction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Two HVDACs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.2.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.2.2
Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.2.3
Frame construction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
N HVDACs on the same RFFE bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
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Contents
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
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Tools installation
AN4440
1
Tools installation
1.1
AUT software installation
Install the latest release from ST of the AUT software on a computer. Follow the AUT
installation manual instructions.
1.2
HVDAC control board connection
Connect the HVDAC control board to the computer.
1.3
•
Release 3.00.01 embeds an RFFE HVDAC-204
•
Release 2.00.01 embeds an RFFE HVDAC-204
•
Release 1.00.01 embeds an RFFE HVDAC-304
•
Release 0.00.01 does not embed any HVDAC as its purpose is to connect an external
HVDAC to one of the numeric SPI or RFFE outputs.
HVDAC connection to the HVDAC control board
An RFFE HVDAC-253M is used in the examples provided in this document.
The HVDAC-253M EVB RFFE input is connected to the HVDAC control board RFFE output
connector. The HVDAC control board should be configured in order to send RFFE
commands to this connector instead of the onboard RFFE HVDAC. To do this, move switch
N°2 in order to have the green D8 LED OFF and the yellow D5 LED ON.
Figure 1. HVDAC control board
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1.4
Tools installation
AUT startup
1.
Click on the AUT icon on the desktop.
Figure 2. AUT startup: screenshot 1
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2.
Choose the HVDAC tab
3.
Choose the "SPI/RFFE Out" tab in the center of the window, select the HVDAC Control
Board in the COM Port dropdown menu, and press “CONNECT”.
Then when the demoboard description is successfully updated, press the "START HVDAC
CONTROL" button.
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Tools installation
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Figure 3. AUT startup: screenshot 2
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Finally, click on the HVDAC-253M tab.
Figure 4. AUT startup: screenshot 3
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1.5
Tools installation
Register information
If HVDAC-204 (on the HVDAC control board) is used (for samples only), the registers are
shifted because this is a 4-output HVDAC, then:
•
DAC A: Register 2 HVDAC-253M => Register 3 HVDAC-204
•
DAC B: Register 1 HVDAC-253M => Register 2 HVDAC-204
•
DAC C: Register 0 HVDAC-253M => Register 1 HVDAC-204
•
DAC D: N/A HVDAC-253M => Register 0 HVDAC-204
Please note that the examples given in this document concern HVDAC-253M and the
designer must adapt HVDAC-204. Please note also that HVDACs (204 versus 252x or
253M) do not have the same resolution. For more information, please refer to the respective
product datasheet.
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RFFE frame
2
AN4440
RFFE frame
The RFFE frame is a sequence composed of the start code, the unique slave identifier,
operation code (read or write), the register address, the data and the bus park. Two parity
bits check the frame integrity. The first bit counts from the unique slave identifier to the
register address. The second one checks the data.
Figure 5. RFFE frame
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RFFE normal modes
3
RFFE normal modes
3.1
Basic mode
3.1.1
Definition
This mode is the easiest way to set one DAC value. The value of the DAC changes as soon
as the frame is sent.
The register selected in the frame sent defines the modified DAC and DATA sets its value.
Example 1
Set HVDAC output B to 2.8 V
USID: 0111b; B Register: 1 = 00001b; Data value: 2.8/0.1 V = 28d = 1C = 00011100b
Frame definition
Parity bit 1 = 0 (5 bytes to 1)
Parity bit 2 = 0 (3 bytes to 1)
Figure 6. Basic mode
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RFFE normal modes
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Test with AUT (automatic mode)
HVDAC-253M does not need any configuration frame as it starts at power-up with boost ON
at 27 V and DAC A, B and C active at 0 V. Write 2.8 (for 2.8 V) in the DAC B setting textbox.
and press Send.
Read the command sent for DAC B which is in the rich text box: 0x0 0x1D 0x4 0x38
(The last bit in the schematic is the bus park => protocol bits are not indicated by the
software).
Measure HVDAC B output: should be 2.8 V.
Note:
Change the DAC B value for the next exercise
Figure 7. Test with AUT (automatic mode)
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RFFE normal modes
Test with AUT (manual mode)
On the right of the HVDAC window, enter manually each bit in the “Manual Command” text
boxes.
•
USID
•
Write
•
Register address
•
First parity bit
•
Data
•
Second parity bit
To send the manual frame, click “Send”.
Figure 8. Test with AUT (manual mode)
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Measure HVDAC B output: should be 2.8 V.
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Example 2
Set HVDAC output A to 22.8 V
USID: 0111b; A register: 2 = 00001b; Data Value: 22.8 V -> 120d = 01111000b
Frame definition
Parity bit 1 = 0 (5 bytes to 1)
Parity bit 2 = 1 (4 bytes to 1)
Figure 9. RFFE frame for 22.8 V on DAC A
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RFFE normal modes
3.2
Trigger mode
3.2.1
Purpose
When several PTICs are implemented in a mobile phone, it can be necessary to change all
or at least more than one DAC value simultaneously, for example, to re-match the antenna
when the band or use case changes. The basic mode updates the DAC value immediately
after each frame, thus DAC values are sequentially updated. The trigger mode provides a
solution for storing the DAC values without updating them and then updates simultaneously
all DAC outputs when the trigger occurs.
3.2.2
Methodology
•
1st step: trigger mode activation - trigger mask to 0 in register 28
•
2nd step: DAC values program: identical to basic mode but no change will occur on the
outputs. These values are stored in the shadow registers.
•
3rd step: trigger - set trigger bits to 1 in register 28 - Values are transferred from the
shadow registers to DAC. All selected DAC values are updated simultaneously.
Example 3
First step: activate trigger mode
Active trigger mask bits (in register 28): Reset bits D3, D4 and D5.
Figure 10. Active trigger mask bits register
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Second step: program several DACs
Program DAC A for 15.6 V and DAC B for 13.2 V
DAC A corresponds to register 2, 15.6 V -> 96d = 01100000h
Figure 11. RFFE frame for 15.6 V on DAC A
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RFFE normal modes
AN4440
DAC B corresponds to register 1, 13.2 V -> 88d = 01011000b
Figure 12. RFFE frame for 13.2 V on DAC B
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Third step: trigger bits
Set trigger bits (in register 28): only one register to update for this operation then all DACs
will be updated simultaneously.
Figure 13. Set trigger bits register
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Continue with trigger mode
To update DACs with other values, still with trigger mode, repeat : Second step: program
several DACs and : Third step: trigger bits.
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RFFE normal modes
Test with AUT (automatic mode)
Connect an oscilloscope on A and B HVDAC outputs in order to visualize their simultaneous
update when the trigger occurs.
HVDAC-253M does not need any configuration frame as it starts at power-up with boost ON
at 27 V and DAC A, B and C active at 0 V.
Remove trigger mask bits and click on "Program".
Figure 14. Test with AUT (automatic mode - detail)
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RFFE normal modes
AN4440
Set DAC values and press "Send" - no DAC value change on HVDAC outputs.
Figure 15. Updating DAC values
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RFFE normal modes
Set trigger bits and press "Program" - all DAC values change simultaneously.
Figure 16. Trigger
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Test with AUT (manual mode)
On the right of the HVDAC window, enter manually each bit in the text boxes of the “Manual
Command” section.
Remove trigger mask bits in register 28: 11100b, set Data = 0b, parity 1 = 0, parity 2 = 1.
Figure 17. Set trigger mode in manual mode
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Set DAC A value: in register 2: 10b, set data = 1100000b, parity 1 = 0, parity 2 = 1.
Figure 18. Update DAC A in manual mode
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Set DAC B value: in register 1: 01b, set data = 1011000b, parity 1 = 0, parity 2 = 0.
Figure 19. Update DAC B in manual mode
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Set trigger bits in register 28: 11100b, set data = 111b, parity 1 = 0, parity 2 = 0.
Figure 20. Trigger in manual mode
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RFFE extended mode
4
RFFE extended mode
4.1
Purpose
The extended mode allows updating simultaneously several registers (Ex: DAC A, B and C)
using a unique but longer frame than the standard one and is faster than using the trigger
mode.
4.2
Methodology
The frame is no longer the standard one as this methodology consists in defining the
quantity of consecutive registers to update, the first register address followed by each
register data.
Note:
Updated registers are consecutive. If a register which does not need an update is between
two registers that need a change, it is necessary to re-send its values.
4.3
Frame construction
The beginning of the frame has almost the same structure as other frames. Instead of the
write code, 3 x 0 bits indicates the use of the extended mode. Instead of the register
address, the byte count defines the quantity of registers that will be updated which
corresponds to the byte quantity after the start register.
Note:
Byte count starts from 0 so byte count = n means (n+1) registers updated.
Figure 21. Start of extended mode frame
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This is followed by data values for each register:
Figure 22. First half of extended mode data
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RFFE extended mode
AN4440
The frame is ended by the bus park.
Figure 23. End of extended mode data
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Example 4
Update in extended mode DAC A = 15.6 V, DAC B = 13.2 V, DAC C = 22.8 V
USID = 0111b
Extended mode = 000b
Byte Count: 3 registers to update (A, B, C - registers 2, 1, 0) => Byte Count = 2d =
00010b
Parity 1 = 1 (4 bits equal to 1)
Start register = 0
Parity 2 = 1 (0 bits equal to 1)
Figure 24. Extended mode - example
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Register 0 value: 22.8 V => 01111000b
Parity bit for register 0 = 1 (4 bits equal to 1)
Figure 25. First extended mode data
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RFFE extended mode
Register 1 value: 13.2 V => 01011000b
Parity bit for register 1 = 0 (3 bits equal to 1)
Figure 26. Second extended mode data
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Register 2 value: 15.6 V => 01100000b
Parity bit for register 2 = 1 (2 bits equal to 1)
Figure 27. Third extended mode data and end of frame
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RFFE extended mode
AN4440
Test with AUT (automatic mode)
Check the box "Enable Extended Mode" and set the DAC values.
Click on "Send" button.
Figure 28. Enable extended mode with AUT
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Test with AUT (manual mode)
The AUT is not ready for extended mode performed manually because its manual mode
sends a "bus park" after each transmission of 22 bits. The next bytes are out of the protocol,
thus, not understood and the frames are refused. No HVDAC change occurs.
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USID modification
5
USID modification
5.1
One HVDAC
5.1.1
Introduction
USID stands for Unique Slave Identifier. It is coded on 4 bits at the beginning of each RFFE
frame. Any HVDAC has a USID, by default 0111b, but can be reprogrammed. This is the
way to discriminate one slave from another and send instructions to the right device.
5.1.2
Sequence construction
USID reprogramming can be performed in 3 steps:
1.
Register 29 update
–
During this instruction, the USID, SELSID and product ID are checked and must
match the device
Figure 29. Register 29 update
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2.
Register 30 update
–
During this instruction, the manufacturer ID is checked and must match the device
Figure 30. Register 30 update
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3.
Register 31 update
–
During this instruction, the New USID is defined: here 0001b
Figure 31. Register 31 update
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USID modification
AN4440
Example 5
Change HVDAC USID to 0001b
•
First frame: register 29 update: initial USID = 0111b, register 29 = 11101b, SELSID = 1,
product ID = 00000010b, parity 1 = 1, parity 2 = 0
Figure 32. Update register 29
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•
Second frame: register 30 update: initial USID = 0111b, register 30 = 11110b,
manufacturer ID = 00000100b , parity 1 = 1, parity 2 = 0
Figure 33. Update register 30
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•
Third frame: register 31 update: initial USID = 0111b, register 31 = 11101b,
manufacturer ID (Short) = 0001b, New USID = 0001b, parity 1 = 1, parity 2 = 0
Figure 34. Update register 31
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USID modification
Test new USID
•
Send a frame with new USID: Send 96d to register 1: New USID = 0001b,
register 1 = 00001b, date = 96d = 01100000b, parity 1 = 0, parity 2 = 1
Figure 35. Send data to DAC B with new USID
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DAB value will be updated to 15.6 V
•
Send a frame with old USD: Try to send 56d to register 1: Old USID = 0111b,
register 1 = 00001b, date = 56d = 00011100b, parity 1 = 0, parity 2 = 0
Figure 36. Send data to DAC B with old USID
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DAB B value will not be updated.
Test with AUT (automatic mode)
Set SELSID: if the SELSID pin is tied to Vcc: SELSID = 1 or if SELSID is to GND:
SELSID = 0
Set new USID
Click on program
Figure 37. USID modification with AUT (automatic mode)
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HVDAC is reprogrammed with new USID.
Now each frame (programming DAC value, for example) is sent with this new USID.
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USID modification
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Test with AUT (manual mode)
•
Updated register 29
Figure 38. USID modification with AUT - register 29
*,3*)65
•
Updated register 30
Figure 39. USID modification with AUT - register 30
*,3*)65
•
Updated register 31
Figure 40. USID modification with AUT - register 31
*,3*)65
The following text is displayed in the rich text box in the bottom left of the window
Figure 41. USID modification with AUT - frames sent
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USID modification
•
Send a value to register 1
Figure 42. Test new USID
*,3*)65
•
Check that the old USID is no longer valid
Figure 43. Check that old USID is no longer valid
*,3*)65
5.2
Two HVDACs
5.2.1
Introduction
When two HVDACs are connected on the same RFFE bus, the first preoccupation is to
distinguish them. Initially both have the same USID: 0111b. The unique difference is the
SELSID pin. One HVDAC should be connected to GND and the other should be connected
to VCC. This differentiation allows reprogramming differently the USID of each one. Finally,
when the HVDACs have two different USIDs, it is possible to send commands
independently to one or the other.
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AN4440
Schematic
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AN4440
5.2.3
USID modification
Frame construction
The USID modification procedure is described for one HVDAC in Section 5.1.2: Sequence
construction.
Example 6
Change USID of HVDAC1 (SELSID to GND) and set it to 0001
•
First frame: register 29 update: initial USID = 0111b, register 29 = 11101b, SELSID = 0,
product ID = 00000010b, parity 1 = 1, parity 2 = 0. SELSID is equal to 0 which is
different from HVDAC2 and differentiates both HVDACs.
Figure 45. HVDAC1 USID - register 29
66&
86,'
:ULWH
5HJLVWHU 6(/6,'
3URGXFW,'
%XV3DUN
6&/.
6'$7$
*,3*)65
•
Second frame: register 30 update: initial USID = 0111b, register 30 = 11110b,
manufacturer ID = 00000100b, parity 1 = 1, parity 2 = 0
Figure 46. HVDAC1 USID - register 30
66&
86,'
:ULWH
5HJLVWHU %XV3DUN
0DQXIDFWXUHU,'
6&/.
6'$7$
*,3*)65
•
Third frame: register 31 update: Initial USID = 0111b, register 31 = 11101b,
manufacturer ID (short) = 0001b, New USID = 0001b, parity 1 = 0, parity 2 = 0
Figure 47. HVDAC1 USID - register 31
66&
86,'
:ULWH
5HJLVWHU 0DQXI
1HZ86,'
%XV3DUN
6&/.
6'$7$
*,3*)65
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USID modification
AN4440
Change USID of HVDAC2 (SELSID to VCC) and set it to 0010
•
First frame: register 29 update: initial USID = 0111b, register 29 = 11101b, SELSID = 1,
product ID = 00000010b, parity 1 = 1, parity 2 = 1. SELSID is equal to 1 which is
different from HVDAC2 and now HVDAC1 USID is no longer 0111 but 000,
differentiating both HVDACs.
Figure 48. HVDAC2 USID - register 29
66&
86,'
5HJLVWHU :ULWH
6(/6,'
3URGXFW,'
%XV3DUN
6&/.
6'$7$
*,3*)65
•
Second frame: register 30 update: Initial USID = 0111b, register 30 = 11110b,
manufacturer ID = 00000100b, parity 1 = 1, parity 2 = 0
Figure 49. HVDAC2 USID - register 30
66&
86,'
:ULWH
5HJLVWHU 0DQXIDFWXUHU,'
%XV3DUN
6&/.
6'$7$
*,3*)65
•
Third frame: register 31 update: Initial USID = 0111b, register 31 = 11101b,
manufacturer ID (Short) = 0001b, New USID = 0010b, parity 1 = 1, parity 2 = 1
Figure 50. HVDAC2 USID - register 31
66&
86,'
:ULWH
5HJLVWHU 0DQXI
1HZ86,'
%XV3DUN
6&/.
6'$7$
*,3*)65
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USID modification
Tests
•
Send value 40d (00101000) for 4 V to HVDAC1, register 1, USID is now 0001
Figure 51. Send data to HVDAC1
66&
86,'
5HJLVWHU$GGUHVV
:ULWH
'DWD
%XV3DUN
6&/.
6'$7$
*,3*)65
•
Send value 112d (01110000) for 20.4 V to HVDAC2, register 1 USID is now 0010
Figure 52. Send data to HVDAC2
66&
86,'
5HJLVWHU$GGUHVV
:ULWH
'DWD
%XV3DUN
6&/.
6'$7$
*,3*)65
Tests with AUT (manual mode)
•
HVDAC1 USID programming
–
Register 29 programming
Figure 53. HVDAC1 USID modification with AUT - register 29
*,3*)65
–
Register 30 programming
Figure 54. HVDAC1 USID modification with AUT - register 30
*,3*)65
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36
USID modification
–
AN4440
Register 31 programming
Figure 55. HVDAC1 USID modification with AUT - register 31
*,3*)65
•
HVDAC2 USID programming
–
Register 29 programming
Figure 56. HVDAC2 USID modification with AUT - register 29
*,3*)65
–
Register 30 programming
Figure 57. HVDAC2 USID modification with AUT - register 30
*,3*)65
–
Register 31 programming
Figure 58. HVDAC2 USID modification with AUT - register 31
*,3*)65
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USID modification
•
Send value 40d (00101000) for 4 V to HVDAC1
Figure 59. Send data to HVDAC1 with AUT
*,3*)65
•
Send value 112d (00100000) for 20.4 V to HVDAC2
Figure 60. Send data to HVDAC2 with AUT
*,3*)65
5.3
N HVDACs on the same RFFE bus
For more than 2 HVDACs (N) on the same RFFE bus, the recommendation is to connect
one HVDAC SELSID to GND and other ones to the MCU GPIOs (N-1).
This will allow reprogramming each HVDAC USID in order to transmit commands
independently to each.
For USID reprogramming, the task of the MCU is to set GPIO polarity in order to have a
unique couple "USID + SELSID" on the HVDAC in the USID reprogramming phase.
–
HVDAC with SELSID to GND reprogramming while all GPIOs are high level (it is
unique with SELSID = 0)
–
Set the next HVDAC SELSID to GND using GPIO (as the previous HVDAC USID
is no longer 0111, it is unique with USID = 0111 AND SELSID=0)
–
Repeat for all HVDACs (N-2 times)
–
Then each HVDAC has a unique USID.
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Conclusion
6
AN4440
Conclusion
The purpose of this application note has been to assist the designer in programming RFFE
HVDAC, either in basic mode, trigger mode, or the more complex extended mode. This
document may also serve as a reference for managing HVDAC programming when several
HVDACs are implemented on the same platform and connected to the same RFFE bus.
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7
Revision history
Revision history
Table 1. Document revision history
Date
Revision
29-Apr-2014
1
Changes
Initial release.
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