ADV7123-DSCC: Military Data Sheet

REVISIONS
LTR
DESCRIPTION
DATE
Prepared in accordance with ASME Y14.24
APPROVED
Vendor item drawing
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PMIC N/A
PREPARED BY
Phu H. Nguyen
Original date of drawing
YY MM DD
CHECKED BY
12-10-23
Phu H. Nguyen
APPROVED BY
Thomas M. Hess
SIZE
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REV
AMSC N/A
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CODE IDENT. NO.
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DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
http://www.landandmaritime.dla.mil/
TITLE
MICROCIRCUIT, DIGITAL-LINEAR, CMOS,
170 MHz, TRIPLE, 10-BIT HIGH SPEED VIDEO
DAC, MONOLITHIC SILICON
DWG NO.
V62/12637
16236
PAGE
1
OF
13
5962-V018-13
1. SCOPE
1.1 Scope. This drawing documents the general requirements of a high performance CMOS, 170 MHz, triple, 10-bit high speed video
DAC, microcircuit, with an operating temperature range of -55°C to +105°C.
1.2 Vendor Item Drawing Administrative Control Number. The manufacturer’s PIN is the item of identification. The vendor item
drawing establishes an administrative control number for identifying the item on the engineering documentation:
V62/12637
-
Drawing
number
01
X
B
Device type
(See 1.2.1)
Case outline
(See 1.2.2)
Lead finish
(See 1.2.3)
1.2.1 Device type(s).
Device type
Generic
01
ADV7123-EP
Circuit function
CMOS, 170 MHz, triple, 10-bit high speed video DAC
1.2.2 Case outline(s). The case outlines are as specified herein.
Outline letter
Number of pins
X
10
JEDEC PUB 95
Package style
JEDEC MO-220-WKKD
Lead Frame Chip Scale Package
1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacturer:
Finish designator
A
B
C
D
E
Z
DLA LAND AND MARITIME
COLUMBUS, OHIO
Material
Hot solder dip
Tin-lead plate
Gold plate
Palladium
Gold flash palladium
Other
SIZE
A
CODE IDENT NO.
16236
REV
DWG NO.
V62/12637
PAGE
2
1.3 Absolute maximum ratings.
1/ 2/
VAA to GND ..............................................................................................
Voltage on any digital pin ........................................................................
IOUT to GND .............................................................................................
Ambient operating temperature (TA) ........................................................
Storage temperature (TS) ........................................................................
Junction temperature (TJ) ........................................................................
Lead temperature,( Soldering, 10 sec) ....................................................
Vapor phase Soldering (1 minute) ...........................................................
+7.0 V
GND – 0.5 V to VAA + 0.5 V
0 V to VAA
2/
-55°C to +105°C
-65°C to 150°C
150°C
300°C
220°C
2. APPLICABLE DOCUMENTS
JEDEC – SOLID STATE TECHNOLOGY ASSOCIATION (JEDEC)
JEP95
–
Registered and Standard Outlines for Semiconductor Devices
(Copies of these documents are available online at http:/www.jedec.org or from JEDEC – Solid State Technology Association, 3103
North 10th Street, Suite 240–S, Arlington, VA 22201.)
3. REQUIREMENTS
3.1 Marking. Parts shall be permanently and legibly marked with the manufacturer’s part number as shown in 6.3 herein and as
follows:
A.
B.
C.
Manufacturer’s name, CAGE code, or logo
Pin 1 identifier
ESDS identification (optional)
3.2 Unit container. The unit container shall be marked with the manufacturer’s part number and with items A and C (if applicable)
above.
3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as
specified in 1.3 and table I herein.
3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein.
3.5 Diagrams.
1/
2/
3.5.1
Case outline. The case outline shall be as shown in 1.2.2 and figure 1.
3.5.2
Terminal connections. The terminal connections shall be as shown in figure 2.
3.5.3
Terminal function. The terminal function shall be as shown in figure 3.
3.5.4
Functional block diagram. The functional block diagram shall be as shown in figure 4.
3.5.5
Timing diagram. The timing diagram shall be as shown in figure 5.
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended
operating conditions” is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device
reliability.
Analog outputs short circuit to any power supply or common GND can be of an indefinite duration.
DLA LAND AND MARITIME
COLUMBUS, OHIO
SIZE
A
CODE IDENT NO.
16236
REV
DWG NO.
V62/12637
PAGE
3
TABLE I. Electrical performance characteristics. 1/
Test
Static performance
Resolution (Each DAC)
Integral nonlinearity (BSL)
Differential nonlinearity
Digital and control inputs
Input high voltage
Input low voltage
Input current
��������� pull up current
PSAVE
Input capacitance
Analog outputs
Symbol
VIH
VIL
IIN
Digital supply current 5/
Analog supply current
Standby supply current
Power supply rejection ratio
Typ
Max
-1
-1
+0.5
+0.25
10
+1
+1
2.0
Bits
LSB
V
0.8
-1
+1
20
10
CIN
VOC
ROUT
COUT
Unit
Min
RSET = 680 Ω
Output current
DAC to DAC matching
Output compliance Range
Output impedance
Output capacitance
Offset error
Gain error 4/
Voltage reference, external
Reference range
Voltage reference, internal
Reference range
Power dissipation
Limits
Test conditions
2/
Green DAC, �������
SYNC = high
������� = low
RGB DAC, SYNC
2.0
2.0
pF
26.5
18.5
1.0
0
Tested with DAC output = 0 V
FSR = 17.62 mA
VREF
1.12
VREF
1.235
0
1.35
V
1.235
fCLK = 50 MHz
fCLK = 140 MHz
fCLK = 517 MHz
RSET = 680 Ω
RSET = 680 Ω
���������
PSAVE = low, digital and control inputs at VDD
2.2
6.5
7.5
67
8
2.1
0.1
mA
%
V
kΩ
pF
%FSR
1.4
70
10
0
0
µA
V
5.0
12.0
13.5
72
5.0
0.5
mA
%/%
See footnote at end of table.
DLA LAND AND MARITIME
COLUMBUS, OHIO
SIZE
A
CODE IDENT NO.
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PAGE
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TABLE I. Electrical performance characteristics - Continued. 1/
Test
Symbol
Test conditions
6/
Limits
Min
Typ
Unit
Max
DYNAMIC SPECIFICATIONS
AC LINEARITY 3/
Spurious free Dynamic Range to Nyquist 7/
Single ended output
fCLK = 50 MHz, fOUT = 1.00 MHz
fCLK = 50 MHz, fOUT = 2.51 MHz
fCLK = 50 MHz, fOUT = 5.04 MHz
fCLK = 50 MHz, fOUT = 20.2 MHz
fCLK = 100 MHz, fOUT = 2.51 MHz
fCLK = 100 MHz, fOUT = 5.04 MHz
fCLK = 100 MHz, fOUT = 20.2 MHz
fCLK = 100 MHz, fOUT = 40.4 MHz
fCLK = 140 MHz, fOUT = 2.51 MHz
fCLK = 140 MHz, fOUT = 5.04 MHz
fCLK = 140 MHz, fOUT = 20.2 MHz
fCLK = 140 MHz, fOUT = 40.4 MHz
Double ended output
fCLK = 50 MHz, fOUT = 1.00 MHz
fCLK = 50 MHz, fOUT = 2.51 MHz
fCLK = 50 MHz, fOUT = 5.04 MHz
fCLK = 50 MHz, fOUT = 20.2 MHz
fCLK = 100 MHz, fOUT = 2.51 MHz
fCLK = 100 MHz, fOUT = 5.04 MHz
fCLK = 100 MHz, fOUT = 20.2 MHz
fCLK = 100 MHz, fOUT = 40.4 MHz
fCLK = 140 MHz, fOUT = 2.51 MHz
fCLK = 140 MHz, fOUT = 5.04 MHz
fCLK = 140 MHz, fOUT = 20.2 MHz
fCLK = 140 MHz, fOUT = 40.4 MHz
Spurious free Dynamic Range within a window
Single ended output
fCLK = 50 MHz, fOUT = 1.00 MHz; 1 MHz Span
fCLK = 50 MHz, fOUT = 5.04 MHz; 2 MHz Span
fCLK = 140 MHz, fOUT = 5.04 MHz; 4 MHz Span
Double ended output
fCLK = 50 MHz, fOUT = 1.00 MHz; 1 MHz Span
fCLK = 50 MHz, fOUT = 5.04 MHz; 2 MHz Span
fCLK = 140 MHz, fOUT = 5.04 MHz; 4 MHz Span
67
67
63
55
62
60
54
48
57
58
52
41
dBc
70
70
65
54
67
63
58
52
62
61
55
53
dBc
77
73
64
dBc
74
73
60
dBc
See footnote at end of table.
DLA LAND AND MARITIME
COLUMBUS, OHIO
SIZE
A
CODE IDENT NO.
16236
REV
DWG NO.
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PAGE
5
TABLE I. Electrical performance characteristics - Continued. 1/
Test
Symbol
Limits
Test conditions
6/
Min
Typ
Unit
Max
DYNAMIC SPECIFICATIONS – Continued.
AC LINEARITY – Continued.
3/
Total harmonic distortion
fCLK = 50 MHz, fOUT = 1.00 MHz
TA = 25°C
-55°C ≤ TA ≤ +105°C
fCLK = 50 MHz, fOUT = 2.00 MHz
fCLK = 100 MHz, fOUT = 2.00 MHz
fCLK = 140 MHz, fOUT = 2.00 MHz
DAC performance
Glitsh impulse
DAC to DAC crosstalk 8/
Data feedthrough 9/ 10/
Clock feddthrough
9/ 10/
66
65
64
64
55
dBc
10
23
22
33
pV-sec
dB
dB
dB
See footnote at end of table.
DLA LAND AND MARITIME
COLUMBUS, OHIO
SIZE
A
CODE IDENT NO.
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PAGE
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TABLE I. Electrical performance characteristics - Continued. 1/
Test
Symbol
TIMING SPECIFICATIONS
Analog outputs
Analog output delay
Analog output Rise/Fall time 12/
Analog output transition time 13/
Analog output skew 14
Clock control
Clock frequency 15/
Data and control setup
Data and control hold
Clock period
Clock pulse width high 14/
Clock pulse width low 14/
Pipeline delay 14/
���������
PSAVE up time
1/
2/
3/
4/
5/
6/
7/
8/
9/
10/
11/
12/
13/
14/
15/
14/
Limits
Test conditions
2/
3/
Min
Max
11/
t6
t7
t8
t9
fCLK
t1
t2
t3
t4
t5
tPD
Typ
Unit
7.5
1.0
15
1
0.68
2.9
5.88
2.6
2.6
1.0
fCLK_MAX = 170 MHz
fCLK_MAX = 170 MHz
t10
ns
2
170
MHz
ns
1.0
1.0
4
10
Clock
cycles
ns
Testing and other quality control techniques are used to the extent deemed necessary to assure product performance over the
specified temperature range. Product may not necessarily be tested across the full temperature range and all parameters may not
necessarily be tested. In the absence of specific parametric testing, product performance is assured by characterization and/or
design.
VAA = 3.0 V to 3.6 V, VREF = 1.235 V, RSET = 560 Ω, CL = 10 pF, -55°C ≤ TA ≤ +105°C , unless otherwise noted; TJ MAX = 110°C.
These maximum/minimum specifications are guaranteed by characterization over the 3.0 V to 3.6 V range.
Gain error = {Measured (FSC)/Ideal (FSC) – 1) X 100}, where ideal (FSC) = VREF/RSET X K X (0x3FFH) and K = 7.9896.
Digital supply is measured with a continuous clock that has data input corresponding to a ramp pattern and with an input level
at 0 V and VDD.
VAA = 3.0 V to 3.6 V, VREF = 1.235 V, RSET = 680 Ω, CL = 10 pF. All specifications are at TA = 25°C, unless otherwise noted;
TJ MAX = 110°C.
This device exhibits high performance when operating with an internal voltage reference, VREF.
DAC to DAC crosstalk measured by holding one DAC high while the other two DAC are making low to high and high to low
transactions.
Clock and data feedthrough is a function of the amount of overshoot and undershoot on the digital inputs. Glitch impulse
includes clock and data feedthrough.
TTL input values are 0 V to 3 V, with input rise/Fall times of 3 ns, measured at the 10% and 90% points. Timing reference
points are 50% for inputs and outputs.
Timing specifications are measured with input levels of 3.0 V (VIH) and 0 V (VIL).
Rise time was measured from the 10% and 90% point of zero full scale transition, fall time from 90% to 10% point of a full scale
transition.
Measured from the 50% point of full scale transition to within 2% of the final output value.
Guaranteed by characterization.
fCLK maximum specification production tested at 125 MHz.
DLA LAND AND MARITIME
COLUMBUS, OHIO
SIZE
A
CODE IDENT NO.
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Case X
D/E
PIN 1
IDENTIFIER
TOP VIEW
A2
A
SEATING
PLANE
e
b
48 PLS
A1
13
24
12
25
PIN 1
IDENTIFIER
D1/E1
1
L1
L2
36
48
37
BOTTOM VIEW
Symbol
A
A1
A2
b
D/E
Dimensions
Millimeters
Symbol
Min
Max
0.70
0.80
0.20 REF
0.05
0.18
0.30
7.00 BSC
D1/E1
e
L1
L2
Millimeters
Min
Max
3.95
4.25
0.50 BSC
0.35
0.45
0.25
NOTES:
1. All linear dimensions are in millimeters.
2. Falls within JEDEC MO-220-WKKD.
FIGURE 1. Case outline.
DLA LAND AND MARITIME
COLUMBUS, OHIO
SIZE
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CODE IDENT NO.
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Case outline X
Terminal
number
Terminal
symbol
Terminal
number
Terminal
symbol
1
2
3
G0
G1
G2
25
26
27
GND
GND
4
5
6
7
8
9
10
11
12
13
14
15
G3
G4
G5
G6
G7
G8
G9
���������
BLANK
�������
SYNC
28
29
30
31
32
33
34
35
36
37
38
39
IOB
VAA
VAA
�����
IOG
16
17
B2
B3
40
41
18
19
20
21
22
23
24
B4
B5
B6
B7
B8
B9
CLOCK
42
43
44
45
46
47
48
VAA
B0
B1
�����
IOB
IOG
�����
IOR
IOG
COMP
VREF
RSET
���������
PSAVE
R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
FIGURE 2. Terminal connections.
DLA LAND AND MARITIME
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CODE IDENT NO.
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Case outline X.
Terminal
Number
Mnemonic
1 to 10
IN1
14 to 23
D1
39 to 48
S1
���������
11
BLANK
12
�������
SYNC
13, 29, 30
24
VAA
CLOCK
25, 26
27, 31, 33
GND
�����, IOG
�����, IOR
�����
IOB
28, 32, 34
IOB, IOG, IOR
35
COMP
36
VREF
37
RSET
38
EP
���������
PSAVE
Exposed Pad
Description
Red, Green, and Blue pixel data inputs (TTL compatible). Pixel data is latched on the rising edge of clock.
R0, G0, and B0 are the least significant data bits. Unused pixel data inputs should be connected to either
the regular printed circuit board (PCB) power or ground plate.
Composite Blank Control input (TTL compatible). A logic 0 on this control input drives the analog outputs –
��������� signal is latched on the rising edge of CLOCK.
IOR, IOB, and IOG – to the blanking level. The BLANK
When ���������
BLANK is a logic 0, the R0 to R9, G0 to G9, and B0 to B9 pixel inputs are ignored.
������� input switches off a 40 IRE current
Composite Sync Control input (TTL compatible). A logic 0 on the SYNC
source. The sync current is internally connected to the IOG analog output. �������
SYNC does not override any
other control or data input; therefore, it should only be asserted during the blanking interval. �������
SYNC is latched
������� input
on the rising edge of CLOCK. If sync information is not required on the green channel, the SYNC
should be tied to logic 0.
Analog Power supply (3.3 V ±10%). All VAA pins on this device must be connected.
Clock Input (TTL compatible). The rising edge of CLOCK latched at the R0 to R9, G0 to G9, B0 to B9.
�������, and BLANK
��������� pixel and control inputs. Typically, the CLOCK input is the pixel clock rate of the video
SYNC
system. CLOCK should be driven by a dedicated TTL buffer.
Ground. The GND pins must be connected.
Differential Red, Green, and Blue current outputs (High impedance current sources). These RGB video
outputs are specified to directly drive RS-343A and RS-170 video levels into a doubly terminated 75 Ω
coaxial cable. If the complementary outputs are not required, these outputs should be tie to ground.
Red, Green and Blue current outputs (High impedance current sources) . These RGB video outputs are
specified to specified to directly drive RS-343A and RS-170 video levels into a doubly terminated 75 Ω
coaxial cable. All three currents outputs should have similar output loads whether or not they are all being
used.
Compensation pin for the Internal Reference Amplifier. A 0.1 µF ceramic capacitor must e connected
between COMP and VAA.
Voltage Reference Input for DACs or Voltage Reference Output (1.235 V). The VREF pin is normally
terminated to VAA through a 0.1 µF capacitor. However, this device can be overdriven by an external 1.23 V
reference (AD1580), if required.
A resistor (RSET) connected between this pin and GND controls the magnitude of the full scale video signal.
Note that the IRE relationships are maintained, regardless of the full scale output current. For nominal
video levels into a doubly terminated 75 Ω load, RSET = 530 Ω.
The relationship between RSET and the full scale output current on IOG (assuming ISYNC is connected to
IOG) is given by:
RSET (Ω) = 11,445 X VREF (V)/IOG (mA)
The relationship between RSET and the full scale output current on IOR, IOG and IOB is given by:
������� being asserted)
IOG (mA) = 11,445 X VREF (V)/RSET (Ω) (SYNC
IOR, IOB (mA) = 7989.6 X VREF (V)/RSET (Ω)
������� is not being used, that is, SYNC
������� is tied
The equation for IOG is the same as that for IOR and IOB when SYNC
permanently low.
Power Save Control pin. Reduce power consumption is available on this device when this pin is active.
The exposed paddle on the underside of the package must be soldered to the ground plane to increase the
reliability of the solder joints and to the maximize the thermal capability of the package.
FIGURE 3. Terminal function.
DLA LAND AND MARITIME
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V
AA
BLANK
BLANK AND
SYNC
SYNC LOGIC
R9 TO R0
10
DATA
REGISTER
10
DAC
G9 TO G0
10
DATA
REGISTER
10
DAC
B9 TO B0
10
DATA
REGISTER
10
DAC
PSAVE
IOR
IOG
IOG
IOB
IOB
VOLTAGE
REFERENCE
CIRCUIT
POWER-DOWN
MODE
CLOCK
GND
IOR
V
REF
RSET COMP
FIGURE 4. Functional block diagram.
DLA LAND AND MARITIME
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t3
t4
t5
CLOCK
t2
DIGITAL INPUTS
(R9 TO R0,G9 TO G0,B9 TO B0,
SYNC, BLANK)
t1
t6
t5
ANALOG INPUTS
(IOR,IOR,IOG,IOG,IOB,IOB)
t7
NOTES:
1. Output delay (t6) measured from the 50% point of the rising edge of clock to the 50% point of full scale transition.
2. Output Rise/Fall time (t7) measured between the 10% and 90% points of full scale transition.
3. Transition time (t8) measured from the 50% point of full scale transition to within 2% of the final output value.
FIGURE 5. Timing diagram.
DLA LAND AND MARITIME
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CODE IDENT NO.
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4. VERIFICATION
4.1 Product assurance requirements. The manufacturer is responsible for performing all inspection and test requirements as
indicated in their internal documentation. Such procedures should include proper handling of electrostatic sensitive devices,
classification, packaging, and labeling of moisture sensitive devices, as applicable.
5. PREPARATION FOR DELIVERY
5.1 Packaging. Preservation, packaging, labeling, and marking shall be in accordance with the manufacturer’s standard commercial
practices for electrostatic discharge sensitive devices.
6. NOTES
6.1 ESDS. Devices are electrostatic discharge sensitive and are classified as ESDS class 1 minimum.
6.2 Configuration control. The data contained herein is based on the salient characteristics of the device manufacturer’s data book.
The device manufacturer reserves the right to make changes without notice. This drawing will be modified as changes are provided.
6.3 Suggested source(s) of supply. Identification of the suggested source(s) of supply herein is not to be construed as a guarantee of
present or continued availability as a source of supply for the item. DLA Land and Maritime maintains an online database of all current
sources of supply at http://www.landandmaritime.dla.mil/Programs/Smcr/.
Vendor item drawing
administrative control
number 1/
Device
manufacturer
CAGE code
Vendor part number
V62/12637-01XB
24355
ADV7123SCP170EP-RL
1/ The vendor item drawing establishes an administrative control number for
identifying the item on the engineering documentation.
CAGE code
24355
DLA LAND AND MARITIME
COLUMBUS, OHIO
Source of supply
Analog Devices
1 Technology Way
P.O. Box 9106
Norwood, MA 02062-9106
SIZE
A
CODE IDENT NO.
16236
REV
DWG NO.
V62/12637
PAGE
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