AN-627: AD5235 Evaluation Kit User Manual (Rev. 0) PDF

AN-627
APPLICATION NOTE
One Technology Way • P.O. Box 9106 • Norwood, MA 02062-9106 • Tel: 781/329-4700 • Fax: 781/326-8703 • www.analog.com
AD5235 Evaluation Kit User Manual
by Alan Li
7 STEPS TO EVALUATION KIT SETUP
The AD5235 evaluation kit (AD5235EVAL25) consists of
a demonstration board and software for evaluating the
AD5235. It is a user-friendly tool that you can control
with your personal computer through the printer port.
The driving program is self-contained, so no programming languages or skills are needed. Figure 1 provides
an overview of how to set up the kit.
AD5235
H
1. INSTALL THE AD5235 SOFTWARE
2. INSTALL THE DRIVER
6. OPEN THE AD5235 SOFTWARE AND
PROGRAM THE RESISTANCE SETTINGS
3. CONNECT THE PARALLEL
PORT CABLE
4. CONFIGURE THE
EVALUATION BOARD
W1
B1
+5V
7. MEASURE THE RESULT
GND
5. APPLY THE POWER SUPPLY
Figure 1. Evaluation Kit Setup
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SETTING UP THE AD5235 EVALUATION BOARD
Note: If Windows® displays an error message, such as
“Can’t connect to service control manager,” contact the
IS department for authority to continue installation.
Step 1—Installing the AD5235 Software
To install the AD5235 software from the Revision H CD,
run setup.exe under D:\AD5235 Evaluation Software
Package. During the installation, select Ignore or Yes
to bypass error messages if they occur. You may need
to install the software a few times to get a successful
installation.
b. Change the pathname of the driver according to
the operating system.
• On a Windows 2000 or Window NT® system,
enter c:\winnt\system32\drivers\dlportio.sys.
• On a Windows XP system, enter
Step 2—Installing the Driver for PC Parallel Port
Communications
In addition to installing the AD5235 software, you need
to install a third-party driver, NTPORT from Upper
Canada Technologies (UCT), for access to the PC parallel
port. UCT offers a free trial with a nominal license fee
after 30 days.
c:\windows\system32\drivers\dlportio.sys.
c. Click the Install button, then the Start button. If
the status message indicates success, the driver is
installed and operating. Click OK.
4. Set up the driver for automatic startup. Use the
following steps that apply to your operating system.
1. Download the driver from www.uct.on.ca. From the
UCT website, download NTPORT.OCX. Save
ntport.zip in the default or specified directory. Unzip
and extract all the files to the directory.
For Windows 2000 and XP Systems
a. Go to the Device Manager.
• On a Windows 2000 system, click
Start → Settings → Control Panel → System →
Hardware → Device Manager.
2. Run setup.exe. If the setup procedure indicates
file violations during installation, select Ignore to
bypass them.
• On a Windows XP system, click
Start →Control Panel →System → Hardware →
Device Manager.
3. Ensure that the driver file, dlportio.sys, is in the
correct system directory.
a. Run loaddrv.exe under c:\program files\project1
or the specified directory. A dialog box appears.
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select show Hidden Devices to make sure that
hidden driver files are listed. If you do not see
dlportio, reboot Windows or rerun loaddrv.exe and
then reboot Windows.
b. Locate Non-Plug and Play Drivers and dlportio
in the Device Manager.
If the Non-Plug and Play Drivers entry is not visible, click the View menu in Device Manager and
c. Double-click dlportio in the Non-Plug and Play
Drivers list. The dlportio Properties page appears.
d. At the Driver tab, select Startup Type as Automatic, click Current status to Start, and click OK.
Note: If Startup is not active and you cannot change Type,
your computer may be administered by your IS department. You may need to consult them to change your PC
administrative setting.
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For Windows NT Systems
a. From the Windows NT Control Panel, select the
Devices icon. The Devices dialog box appears.
• For dual supplies, connect JP15 and JP12 to connect
the –5 V pin to VSS of U1 and U3.
Warning: Apply +2.5 V to Pin +5 V and –2.5 V to
Pin –5 V instead.
• Select the states of PR and WP from the DIP switches
on the evaluation board.
• SDO can be monitored at TPSDO.
Step 5—Applying the Power Supply
Provide a power supply to the AD5235 evaluation
board according to Step 4 for a single supply or for
dual supplies.
Step 6—Using the Evaluation Board
To open the AD5235 software program, from Windows
click Start → Programs → AD5235 Rev H.
b. Select dlportio and click the Startup button. The
Device Startup Type dialog box appears. From the
option buttons, select Automatic, and then click OK.
Figure 2 shows the graphical interface. In the Direct Control pane, on the right, you can move the scroll bars or
click the buttons to control the device. In the top pane,
you can adjust the bit pattern and then click Run to program the device. In the bottom pane, you can
approximate RWA and RWB by first entering the measured
RAB after power is applied.
Step 7—Measuring the Result
Use a multimeter to measure the result of your program
applications on the AD5235 evaluation board.
UNINSTALLING SOFTWARE
To uninstall the AD5235 software and NTPORT driver,
use Add/Remove Programs in the Control Panel.
Step 3—Connecting the Parallel Port Cable
Connect the parallel port cable from LPT1 on your PC to
the AD5235 evaluation board.
TECHNICAL SUPPORT
Due to the variations in computer platforms and configurations, Analog Devices, Inc., cannot guarantee the
software described in this application note to work on all
systems. If you encounter problems, send email to
[email protected] or call 1-408-382-3082 for
applications support. If you are interested in the AD5235
source code, send email to [email protected] for more
information.
Step 4—Configuring the Evaluation Board
Follow these requirements to configure the AD5235
evaluation board:
• For a single supply, connect JP14 and JP13 to
ground VSS of U1 and U3. Apply 5 V to Pin +5 V.
Note: Some boards do not come with jumper
caps. You should supply suitable caps or simply
short the jumpers for proper operation.
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Figure 2. AD5235 Software Graphical Interface
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section). Other op amps in PDIP can replace the AD820. For a
single-supply, 2.5 V voltage reference, AD1582 can be
used to offset the op amp bias point for ac operation.
EVALUATION BOARD SCHEMATIC
The general-purpose op amp AD820, U3A can be configured
as various building block circuits in conjunction with the
AD5235 for various circuit evaluations (see the Applications
AD5235 MAIN CIRCUIT
+5V
+5V
(LOWER TO +2.5V IF DUAL SUPPLIES)
R2
10k
R3
10k
C10
4.7F
R4
10k
C11
0.1F
DGND
J1
13
25
12
24
11
23
10
22
9
21
8
20
7
19
6
18
5
17
4
16
3
15
2
14
1
U1A
ADN2850CSP 16
15
14
13
TPSDO
SDI CLK RDY CS
1
+5V
TPCLK
S1
LOW
1
8
2
7
3
6
4
5
SW-DIP4
W1 B1 B2 W2
R1
1k
TPSDI
12
PR
11
WP
10
VDD
9
A2
SDO
2
GND
3
VSS
4
A1
TP/CS
TPRDY TP/PR TP/WP
HIGH
5
6
7
8
A1
W1
B1
R_CS 100
R_CLK 100
1
R_SDI 100
CLK
SDI
SDO
GND
VSS
A1
W1
B1
2
3
4
5
DB25
6
7
8
NOTES
USERS SHOULD IGNORE U1A, ADN2850CSP
SIGNAL GROUND WITH NET DGND
POWER GROUND WITH NET AGND
16
RDY
CS
PR
WP
VDD
A2
W2
B2
15
A2
14
13
12
W2
11
10
9
B2
U1B
AD5235TSSOP
JP14
GND
HEADER
C12
0.1F
JP15
C13
4.7F
–5V
HEADER
–5V
(LOWER TO –2.5V IF DUAL SUPPLIES)
ADDITIONAL OP AMP FOR GENERAL-PURPOSE APPLICATIONS
V+
V–
VO
JP7
JP9
JP5
HEADER
JP6
JP8
C5
0.1F
+5
JP4
HEADER
7
2
JP2
HEADER
VI_DC
1, 5, 8
U3A
AD820AR
6
VO
3
4
JP3
HEADER
C9
JP10
JP11
JP1
VI_AC
U2
AD1582
GND
+5V
3
C7
0.1F
JP12
HEADER
2
VIN
1
VOUT
2.5 VREF
JP13
HEADER
C6
–5V 0.1F
+5V
7
2
C8
0.1F
8
6
U3B
AD820AN
3
1
5
4
REPLACEABLE
OP AMP IN PDIP
Figure 3. Evaluation Board Schematic
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Table I. AD5235 24-Bit Serial Data-Word
MSB
RDAC
Instruction Byte 0
C3 C2 C1 C0 0
0
Data Byte 1
0
A0 X
EEMEM C3 C2 C1 C0 A3 A2 A1
X
X
X
X
Data Byte 0
X
LSB
D9 D8
D7
D6
D5
D4
D3
D2
D1 D0
A0 D15 D14 D13 D12 D11 D10 D9 D8
D7
D6
D5
D4
D3
D2
D1 D0
Command bits are C0 to C3. Addresses bits are A3 to A0. Data bits D0 to D9 are applicable to the RDAC wiper register, whereas D0 to D15 are applicable
to the EEMEM register. Command instruction codes are defined in Table II.
Table II. AD5235 Instruction/Operation Truth Table 1, 2, 3
Instruction Byte 0
Data Byte 1
Instruction B23 • • • • • • • • • • • • • • • • • B16 B15 • • • B8
No.
C3 C2 C1 C0 A3 A2 A1 A0 X • • • D9 D8
Data Byte 0
B7 • • • B0
D7 • • • D0 Operation
0
0
0
0
0
X X X X
X•••X X
X••• X
NOP: Do nothing. See Table V.
1
0
0
0
1
0
0
0
A0
X•••X X
X••• X
Write the contents of EEMEM(A0) to RDAC(A0). This
command leaves the device in the read program
power state. To return the device to the idle state,
perform NOP instruction 0. See Table V.
2
0
0
1
0
0
0
0
A0
X•••X X
X••• X
Save wiper setting: Write the contents of RDAC(A0)
to EEMEM(A0). See Table IV.
34
0
0
1
1
A3 A2 A1 A0
D15 • • • D8
D7• • • D0
Write the contents of serial register data bytes 0 and
1 (total 16-bit) to EEMEM(ADDR). See Table VII.
45
0
1
0
0
0
X•••X X
X••• X
Decrement 6 dB: Right-shift contents of RDAC(A0),
stops at all ”zeros.”
55
0
1
0
1
X X X X
X•••X X
X••• X
Decrement all 6 dB: Right-shift contents of all RDAC
registers, stops at all ”zeros.”
65
0
1
1
0
0
X•••X X
X••• X
Decrement contents of RDAC(A0) by ”one,” stops at
all ”zeros.”
75
0
1
1
1
X X X X
X•••X X
X••• X
Decrement contents of all RDAC registers by “one,”
stops at all “zeros.”
8
1
0
0
0
0
X•••X X
X••• X
Reset: Load all RDACs with their corresponding
EEMEM previously saved values.
9
1
0
0
1
A3 A2 A1 A0
X•••X X
X••• X
Write contents of EEMEM(ADDR) to serial register
data bytes 0 and 1. SDO activated. See Table VIII.
10
1
0
1
0
0
0
0
A0
X•••X X
X••• X
Write contents of RDAC(A0) to serial register data
bytes 0 and 1. SDO activated. See Table IX.
11
1
0
1
1
0
0
0
A0
X • • • D9D8
D7 • • • D0
Write contents of serial register data bytes 0 and 1
(total 10 bit) to RDAC(A0). See Table III.
125
1
1
0
0
0
0
0
A0
X•••X X
X••• X
Increment 6 dB: Left-shift contents of RDAC(A0),
stops at all “ones.” See Table VI.
135
1
1
0
1
X X X X
X•••X X
X••• X
Increment all 6 dB: Left-shift contents of all RDAC
registers, stops at all “ones.”
145
1
1
1
0
0
X•••X X
X••• X
Increment contents of RDAC(A0) by “one,” stops at
all “ones.” See Table IV.
155
1
1
1
1
X X X X
X•••X X
X••• X
Increment contents of all RDAC registers by “one,”
stops at all “ones.”
0
0
0
0
0
0
0
0
A0
A0
0
A0
NOTES
1
The SDO output shifts out the last 24 bits of data clocked into the serial register for daisy-chain operation. Exception: For any instruction following
instruction 9 or 10, the selected internal register data will be present in data byte 0 and 1. The instructions following 9 and 10 must also be a full 24-bit
data-word to completely clock out the contents of the serial register.
2
The RDAC register is a volatile scratchpad register that is refreshed at power-on from the corresponding nonvolatile EEMEM register.
3
Execution of the above operations takes place when the CS strobe returns to logic high.
4
Instruction 3 writes two data bytes (total 16 bit) to EEMEM. However, in the cases of addresses 0 and 1, only the last 10 bits are valid for wiper position setting.
5
The increment, decrement, and shift commands ignore the contents of the shift register data bytes 0 and 1.
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Table VI. Using Left Shift by One to Increment 6 dB Steps
PROGRAMMING EXAMPLES
The following programming examples illustrate the
typical sequence of events for various features of the
AD5235. Refer to Table II for the instructions and dataword format. The instruction numbers, addresses, and
data appearing at the SDI and SDO pins are displayed in
hexadecimal format in the tables.
SDI
SDO
C0XXXXH
XXXXXXH Moves wiper 1 to double the
present data contained in the
RDAC1 register.
C1XXXXH
C0XXXXH
Table III. Scratchpad Programming
SDI
SDO
B00100H
XXXXXXH Loads data 100H into the RDAC1
register. Wiper 1 moves to the
1/4 full-scale position.
B10200H
B00100H
Table VII. Storing Additional User Data in EEMEM
Loads data 200H into the RDAC2
register. Wiper 2 moves to the
1/2 full-scale position.
SDI
SDO
B00100H
XXXXXXH Loads data 100H into the RDAC1
register. Wiper 1 moves to the
1/4 full-scale position.
E0XXXXH
B00100H
20XXXXH
E0XXXXH
Moves wiper 2 to double the
present data contained in the
RDAC2 register.
Action
Table IV. Incrementing RDAC Followed
by Storing the Wiper Setting to EEMEM
E0XXXXH
Action
SDI
SDO
32AAAAH
XXXXXXH Stores data AAAAH into spare
EEMEM location USER1. Allowable to address in 13 locations
with maximum 16 bits of data.
335555H
32AAAAH
Action
Action
Stores data 5555H into spare
EEMEM location USER2. Allowable to address 13 locations
with maximum 16 bits of data.
Table VIII. Reading Back Data from
Various Memory Locations
Increments the RDAC1 register
by one to 101H.
Increments the RDAC1 register
by one to 102H.
Continue until the desired wiper
position is reached.
SDI
SDO
92XXXXH
XXXXXXH Prepares data read from USER1
location.
00XXXXH
92AAAAH
XXXXXXH Saves RDAC1 register data into
EEMEM1.
Optionally tie WP to GND to
protect EEMEM values.
Action
NOP instruction 0 sends 24-bit
word out of SDO where the last
16 bits contain the contents of
USER1 location. NOP command
ensures device returns to idle
power dissipation state.
Table IX. Reading Back Wiper Setting
Table V. Restoring EEMEM Values to RDAC Registers
SDI
SDO
10XXXXH XXXXXXH
Action
Restores EEMEM1 value to
RDAC1 register.
00XXXXH 10XXXXXH NOP. Recommended step to
minimize power consumption.
8XXXXXH 00XXXXH
Resets EEMEM1 and EEMEM2
values to RDAC1 and RDAC2
registers, respectively.
SDI
SDO
Action
B00200H
XXXXXXH Sets RDAC1 to midscale.
C0XXXXH
B00200H
Doubles RDAC1 from midscale
to full scale.
A0XXXXH C0XXXXH
Prepares reading wiper setting
from RDAC1 register.
XXXXXXH A003FFH
Reads back full-scale value
from RDAC1 register.
EEMEM values for RDACs can be restored by power-on, strobing the
PR pin or programming as shown above.
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APPLICATIONS
U1
AD5235
1
3
4
5
VI
6
R1 A RDAC B R2
7
8
16
RDY
CS
PR
WP
VDD
A2*
W2
B2
CLK
SDI
SDO
GND
VSS
A1*
W1
B1
2
15
14
13
12
0V
VO
R1
11
VI = 100mV
R1 = RDAC = R2 = 10k
1
10
EXTERNAL
R2
9
EXTERNAL
VO
JP15
–200mV
+5V (+2.5V)
–5V (–2.5V)
–(R2+RAB)
–R2
< VO <
(R1 + RAB) VI
R1 VI
–INPUT
7
2
1
VI_DC
0.5
1.0
POTSETTING
6
U3
AD820AR
1
0
V(VO)
1, 5, 8
VO
3
4
JP3
VI_AC C9
JP1
JP12
1
–5V (–2.5V)
Figure 4. Inverting Gain and Attenuator
U1
AD5235
1
2
3
4
5
VI
R
6
R
7
8
CLK
SDI
SDO
GND
VSS
A1*
W1
B1
A2* (SIGNAL INPUT HERE)
RDY
CS
PR
WP
VDD
A2*
W2
B2
1
16
15
–INPUT
14
13
FB
12
1
1
1V
R
11
10
EXTERNAL
VI = 1V
VO
R
JP8
9
VO
A
RDAC
–1V
B
+5V (+2.5V)
–1 < VO
7
2
JP4
VI < 1
0.5
1.0
POTSETTING
6
U3
AD820AR
JP2
0
V(VO)
1, 5, 8
VO
3
4
JP12
–5V (–2.5V)
Figure 5. Bipolar Unity Gain Amplifier
U1
AD5235
1
2
3
4
5
R
D1
R1
A
IS
6
7
8
CLK
SDI
SDO
GND
VSS
A1*
W1
B1
RDY
CS
PR
WP
VDD
A2*
W2
B2
16
FB
–INPUT
1
1
15
14
R1
13
JP7
12
11
R
10
JP6
1.2V
VO
IS = 10nA
R = 100k
RDAC = 10k
R1 = 10
1
9
RDAC
B
VO
JP15
0V
+5V (+2.5V)
–5V (–2.5V)
VI_DC
VO = –k R IS
k=1+
7
2
1
D1
RWB
RWB
+
R1
R
U3
AD820AR
3
4
JP1
JP12
–5V (–2.5V)
Figure 6. High Sensitivity I-V Coverter
REV. 0
–9–
6
0
0.5
V(VO)
1, 5, 8
POTSETTING
VO
1.0
AN-627
U1
AD5235
1
2
3
4
5
6
VIN
7
8
CLK
SDI
SDO
GND
VSS
A1*
W1
B1
16
RDY
CS
PR
WP
VDD
A2*
W2
B2
15
A
14
13
FB
12
1
1
5V
VI = 5V
RAB = 10k
11
10
9
JP2
VO
A
+5V (+2.5V)
RDAC
B
1, 5, 8
7
2
JP4
U3
AD820AR
JP4
JP2
0V
0
0.5
1.0
V(VO)
6
POTSETTING
VO
3
4
JP12
–5V (–2.5V)
Figure 7. Buffered Output Voltage
U1
AD5235
1
2
3
4
5
VI
R1
6
A RDAC B
7
8
RDY
CS
PR
WP
VDD
A2*
W2
B2
CLK
SDI
SDO
GND
VSS
A1*
W1
B1
16
15
14
13
12
–INPUT
VO
11
1
1
9
+5V (+2.5V)
R1
JP6
JP15
–5V (–2.5V)
–RWB
R1
VO =
VI = 0.1V
R1 = 5k, RAB = 10k
10
VO
G=
0V
0
0.5
1.0
V(VO)
VO
POTSETTING
3
1
–VI (D RAB)
(2n R1)
–200mV
6
U3
AD820AR
JP4
VI_DC
1, 5, 8
7
2
4
JP1
JP12
–5V (–2.5V)
Figure 8. Inverting Linear Gain and Attenuator
U1
AD5235
1
2
3
4
5
VI
6
A RDAC B
7
8
CLK
SDI
SDO
GND
VSS
A1*
W1
B1
RDY
CS
PR
WP
VDD
A2*
W2
B2
16
15
14
13
FB
12
1
–10V
–INPUT
VI = 0.1V
RAB = 10k
VO
1
11
1
10
9
VO
JP15
JP4
VI_DC
–100V
1
+5V (+2.5V)
–5V (–2.5V)
G=
JP3
–RWB
RWA
VO = VI D
2n – 1
7
2
VI_AC C9
U3
AD820AR
1
6
0
0.5
1.0
V(VO)
1, 5, 8
POTSETTING
VO
3
4
JP1
JP12
–5V (–2.5V)
Figure 9. Inverting Quasi Log Gain and Attenuator
–10–
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AN-627
FB
U1
AD5235
3
4
5
VI
A RDAC B
6
R2
RDY
CS
PR
WP
VDD
A2*
W2
B2
CLK
SDI
SDO
GND
VSS
A1*
W1
B1
2
7
8
16
15
14
13
–INPUT
VO
12
1
1
VI = 0.1V
RAB = 10k, R2 = 10k
R2
10
9
JP8
+5V (+2.5V)
VO
JP15
–10V
11
LOG
1
1
JP4
VI_DC
1, 5, 8
7
2
–100mV
1
G = –R2
RWA
–VI (2n R2)
VO =
(2n – D) RAB
JP3
VI_AC
6
U3
AD820AR
–5V (–2.5V)
0
0.5
1.0
V(VO)
VO
POTSETTING
3
C9
4
1
JP1
JP12
–5V (–2.5V)
Figure 10. Inverting Exponential Gain and Attenuator
U1
AD5235
1
3
4
5
R1
6
A RDAC B
RDY
CS
PR
WP
VDD
A2*
W2
B2
CLK
SDI
SDO
GND
VSS
A1*
W1
B1
2
7
8
16
15
14
13
12
–INPUT
VO
11
1
1
VI = 0.1V
R1 = 5k, RAB = 10k
10
9
VO
VI
300mV
+5V
JP14
JP5
G = 1 + RWB
R1
1, 5, 8
0V
6
U3
AD820AR
VI_DC
0
0.5
1.0
V(VO)
VO
POTSETTING
3
1
D RAB
VO = VI 1+ n
2 R1
7
2
R1
JP6
4
JP2
JP13
Figure 11. Noninverting Linear Gain
GND
U1
AD5235
1
2
3
4
5
6
A RDAC B
7
8
RDY
CS
PR
WP
VDD
A2*
W2
B2
CLK
SDI
SDO
GND
VSS
A1*
W1
B1
1
16
15
14
13
12
11
10
9
+5V
JP14
G = 1 + RWB
RWA
VO = VI 1+
1, 5, 8
U3
AD820AR
100mV
6
VO
3
1
D
7
2
VI_DC
2n –
VI = 0.1V
RAB = 10k
1
1
VO
VI
10V
VO
–INPUT
4
JP2
D
JP3
JP13
VI_AC C9
1
Figure 12. Noninverting Quasi Log Gain
REV. 0
–11–
0
0.5
V(VO)
POTSETTING
1.0
AN-627
GND
1
U1
AD5235
1
3
4
5
A RDAC B
6
R2
RDY
CS
PR
WP
VDD
A2*
W2
B2
CLK
SDI
SDO
GND
VSS
A1*
W1
B1
2
7
8
16
15
14
10V
13
–INPUT
VO
12
1
1
11
10
R2
9
JP8
VO
+5V
VI
JP14
G = 1 + R2
RWA
7
2
VI_DC
VO = VI 1 +
VI = 0.1V
RAB = 10k , R2 = 10k
JP2
1
2n R2
(2n – D) RAB
100mV
1, 5, 8
0
0.5
1.0
V(VO)
POTSETTING
6
U3
AD820AR
VO
3
4
JP3
VI_AC
C9
JP13
1
Figure 13. Noninverting Exponential Gain
U1
AD5235
1
2
3
4
5
+2.5V
6
7
R1
1M, 0.1%
A
RDAC
B
JP15
VO
8
CLK
SDI
SDO
GND
VSS
A1*
W1
B1
RDY
CS
PR
WP
VDD
A2*
W2
B2
+5V (+2.5V)
16
15
R1
EXTERNAL
14
13
12
11
10
–INPUT
JP8
VO
9
+5V (+2.5V)
R2
–5V (–2.5V)
2
R2
1M, 0.1%
1, 5, 8
7
–5V (–2.5V)
U3
AD820AR
–2.5V
6
VO
3
4
VW = V+ RWB
R2 + RAB
– V– JP1
RWA
R1 + RAB
JP12
–5V (–2.5V)
Figure 14. Ultrafine Adjustment
–12–
REV. 0
AN-627
U1
AD5235
1
2
3
4
5
R1
VI
6
R2
7
8
RDY
CS
PR
WP
VDD
A2*
W2
B2
CLK
SDI
SDO
GND
VSS
A1*
W1
B1
16
15
14
13
12
R1 –INPUT
11
10
9
JP15
B
2.0V
V(VO)
+5V(+2.5V)
VO
A
VO
R2
JP8
EXTERNAL
FB
JP4
C1
G = 180 – 2tan^ – 1wRC
6
U3
AD820AR
–5V(–2.5V)
JP2
1, 5, 8
7
2
RDAC
VO
V(VI)
–2.0V
0s
100s
200s
3
300s
TIME
4
VI_AC
C1
JP1
1
JP12
–5V(–2.5V)
Figure 15. Phase Shifter
U1
AD5235
1
2
3
4
5
VA
6
7
A
8
RDAC
CLK
SDI
SDO
GND
VSS
A1*
W1
B1
RDY
CS
PR
WP
VDD
A2*
W2
B2
16
15
14
13
12
+5V(+2.5V)
5.0V
11
JP8
10
9
JP15
B
JP4
2
VREF
VB
6
U3
AD820AR
–5V(–2.5V)
JP2
7
1, 5, 8
3
4
JP13
Figure 16. Level Detector
REV. 0
VA = V+ = +2.5V
VB = V– = –2.5V
VREF = 0V
+5V(+2.5V)
VO
–13–
VO
–5.0V
0
V(VO)
0.5
POTSETTING
1.0
AN-627
PCB LAYOUT
Figure 17. Evaluation Board PCB Layout
Figure 18. Top Layer
–14–
REV. 0
AN-627
Figure 19. Bottom Layer
Figure 20. Top Overlay Silkscreen
REV. 0
–15–
AN-627
PCB LAYOUT CONSIDERATIONS
To stabilize voltage supplies, bypass Pin +5 V and Pin –5 V
with a 4.7 µF or 10 µF capacitor with proper polarities. Adding 0.1 µF decoupling capacitors, very close to
the supply pins of the active component, can minimize
high frequency noise as well.
Table X. PCB Parts List
Designator
Footprint
TPSDO
TPCLK
TPSDI
TP/CS
+5 V
GND
B1
W1
A1
VI_DC
VI_AC
C9
A2
W2
B2
–5 V
VO
V–
V+
JP8
JP9
JP7
JP6
JP1
JP11
JP10
Test point 0.09
Test point 0.09
Test point 0.09
Test point 0.09
Post pin 0.125
Post pin 0.125
Post pin 0.125
Post pin 0.125
Post pin 0.125
Post pin 0.125
Post pin 0.125
RAD 0.1
Post pin 0.125
Post pin 0.125
Post pin 0.125
Post pin 0.125
Post pin 0.125
Post pin 0.125
Post pin 0.125
Jumper 0.3
Jumper 0.3
Jumper 0.3
Jumper 0.3
Jumper 0.3
Jumper 0.3
Jumper 0.3
Comment
Designator
Footprint
TPRDY
TP/WP
TP/PR
DGND
C12
C7
C11
C6
C5
R_/CS
R_CLK
R_SDI
R4
R3
R2
R1
C8
C13
C10
U2
U1B
U1A
Test point 0.09
Test point 0.09
Test point 0.09
DGNDPAD
RAD 0.1
RAD 0.1
RAD 0.1
RAD 0.1
RAD 0.1
Axial 0.3
Axial 0.3
Axial 0.3
Axial 0.3
Axial 0.3
Axial 0.3
Axial 0.3
RAD 0.2
RAD 0.2
RAD 0.2
SOT-23
TSSOP-16
LFCSP-16
5 mm × 5 mm
DIP8
SO-8
DB25SL
SIP2
SIP2
SIP2
SIP2
SIP2
SIP2
SIP2
SIP2
DIP8
U3B
U3A
J1
JP15
JP14
JP5
JP3
JP2
JP4
JP12
JP13
S1
–16–
Comment
0.1 µF
0.1 µF
0.1 µF
0.1 µF
0.1 µF
100 Ω
100 Ω
100 Ω
10 kΩ
10 kΩ
10 kΩ
1 kΩ
1 µF
4.7 µF
4.7 µF
AD1582
AD5235TSSOP
ADN2850CSP
AD820AN
AD820AR
DB25
Header
Header
Header
Header
Header
Header
Header
Header
SW-DIP4
REV. 0
AN-627
GND
13
12
25
S7
11
24
S6
10
23
S5
CS
CLK SDI
D7
D6
D5
D4
D3
D2
D1
D0
9
8
7
6
5
4
3
2
22
S4
PR
21
20
19
18
17
16
1
14
15
SDO
S3
C3
C2
NOTES
8 OUTPUT PINS ACCESSED VIA THE DATA PORT
5 INPUT PINS (1 INVERTED) ACCESSED VIA THE STATUS PORT
4 OUTPUT PINS (3 INVERTED) ACCESSED VIA THE CONTROL PORT
REMAINING 8 PINS ARE GROUNDED
C1
C0
(NTPORT1.ADDRESS = 888)
(NTPORT1.ADDRESS = 889)
(NTPORT1.ADDRESS = 890)
Figure 21. Parallel Port Connector Configuration (For VB Program Developers Only)
BIT 3 PR
(PIN 5)
BIT 2 CS
(PIN 4)
BIT 1 CLK
(PIN 3)
BIT 0 SDI
(PIN 2)
BINARY CODE 1100
DECIMAL CODE
12
1001
1011
1000
1010
1100
9
11
8
10
12
SEND OUT
NO ACTIVITY BIT_TOGO = 1
SEND OUT
BIT_TOGO = 0
LATCH DATA
Figure 22. Timing Definition (For VB Program Developers Only)
REV. 0
–17–
–18–
–19–
AN03554–0–3/04(0)
© 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners.
–20–
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