AN-729: Evaluation Kit for the AD5254 Quad 256-Position I²C-Compatible Nonvolatile Memory Digital Potentiometer (Rev. 0) PDF

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APPLICATION NOTE
One Technology Way • P.O. Box 9106 • Norwood, MA 02062-9106 • Tel: 781/329-4700 • Fax: 781/461-3113 • www.analog.com
Evaluation Kit for the AD5254 Quad 256-Position I2C-Compatible
Nonvolatile Memory Digital Potentiometer
by Alan Li
5 STEPS TO SET UP THE EVALUATION KIT
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NO PROGRAMMING SKILLS REQUIRED!
Figure 1. Evaluation Kit Setup
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4. Connect the board to the parallel port with the connector and cable that are provided.
OPERATING THE AD5254 EVALUATION KIT
1. Click the Install Software link in the digital POT CD
browser.
5. Open the AD5254 Rev. A program from the Windows®
Start program. Move the scroll bar to program the
resistance settings. The operation is self-explanatory.
2. A 2-channel SO-8 op amp (such as AD822B) and a
SC70 2.5 V reference (such as ADR03) are provided for
common building block configurations, such as DAC,
programmable gain amplifier, and programmable
filter. See the Applications section for details.
Note: This Rev. B software is a beta version. The part is
fully functional, but the Reading Function is not included
in the software.
3. Apply 5 V power supply to VDD and AGND terminals.
Connect JP2 to ground VSS.
Figure 2. AD5254 Software Graphical Interface
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AD5254 PARALLEL PORT CONNECTION
(For Visual Basic Program Developers Only)
WPB AD1 AD0 SCL SDA_WRITE
DGND
13
12
25
S7
11
24
S6
10
23
S5
D7
D6
D5
D4
D3
D2
D1
D0
9
8
7
6
5
4
3
2
22
S4
21
20
19
18
17
16
15
1
14
SDA_READ
S3
C3
SDA_READ
8 OUTPUT PINS ACCESSED VIA THE DATA PORT
5 INPUT PINS (ONE INVERTED) ACCESSED VIA THE STATUS PORT
4 OUTPUT PINS (THREE INVERTED) ACCESSED VIA THE CONTROL PORT
THE REMAINING 8 PINS ARE GROUNDED
C2
C1
C0
PORTID = VAL("&H" + "378") [378h = 888]
PORTID = VAL("&H" + "379") [379h = 889]
PORTID = VAL("&H" + "37A") [37Ah = 890]
Figure 3. Parallel Port Connector Configuration (for VB Program Developers Only)
TIMING DEFINITION
(In Visual Basic Source Code cmdRUN)
BIT 1
(PIN 3)
SCL
BIT 0
(PIN 2)
SDA
BINARY CODE
DECIMAL CODE
1100
1001
1011
1000
1010
1100
12
9
11
8
10
12
NO ACTIVITY
SEND OUT
SEND OUT
BIT_TOGO = 1 BIT_TOGO = 0
LATCH DATA
Figure 4. Timing Definition (for VB Program Developers Only)
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–3–
–4–
V–
+IN1
–IN1
OUT1
RJ45
CONNECTOR
8
7
6
5
4
3
2
1
J1
SDA_WRITE
SCL
AD0
AD1
WPB
SDA_READ
100Ω
100Ω
100Ω
100Ω
100Ω
100Ω
100Ω
VSS
4
V–
R1
10kΩ
JP1
R2
10kΩ
C2
0.1µF
U3A
U3B
8
V+
+IN2 5
–IN2 6
+IN2
–IN2
OUT2 7 OUT2
V+
C3
10µF
AD822/AD8042A
+IN1
2 –IN1
1 OUT1
3
*
C1
10µF
+IN2
–IN2
OUT2
JP3
DGND JOINTS AGND AT ONE POINT IN PCB
R9
R8
R7
R6
R5
R4
R3
VDD
VDD
1
2
3
4
5
6
7
14
13
12
11
10
9
8
JP2
C11
0.1µF
W0
VDD
B0
W3
A0
B3
AD0
A3
WPB
AD1
W1
DGND
B1
SCL
A1
W2
SDA
B2
VSS
A2
20
19
18
17
16
15
14
13
12
11
0.1µF
U4
2.5V REF
JP11
VSS
C6
ADR03
C5
0.1µF
VREF
JP14
C12
0.1µF
AD5253/AD5254
1
2
3
4
5
6
7
8
9
10
U2
QUAD DIGIT POT
1
5
TEMP TRIM
2
3 GND
4
VIN
VOUT
*JUMPER DEFAULTS ON
VDD
BNCIN1
*
C4
0.1µF
AGND
AD5251/AD5252
VDD
W3
AD0
B3
WPB
A3
W1
AD1
B1
DGND
A1
SCL
SDA
VSS
U1
DUAL DIGIT POT
A0
W0
B0
JP15
C9
10µF
VSS
V–
–IN1
VIN
+IN1
JP6
JP16
CP5
+IN1
CP6
BNCOUT1
CP2
CP4
U3A
–IN1
–IN1
C8
0.1µF
C10
0.1µF
JP7
JP8
*
JP4
JP5
JP9
CP1
CP3
–IN1
C7
10µF
V+
VDD
V+
JP10
A3
V–
W3
B2
W2
JP12
A2
B1
W1
B3
A1
CP7
JP13
OUT1
OUT1
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Figure 5. Evaluation Board Schematic
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APPENDIX
Applications
The AD5254 evaluation board comes with dual op amp,
AD822, and 2.5 V reference, ADR03. Users can con figure various building block circuits with minimum
components. Note that JP and CP stand for jumper and
connection points, respectively, in the schematics.
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Figure 6. High Voltage Programmable Gain (for example, VCOM Adjustment)
CP2
VDD
VREF
VREF (2.5V)
B
+
–
JP14
A3
JP8 + JP10
VO
OP AMP
–
+
U1
B
VO = 2.5V ×
JP4
U3A
V+
AD822
V–
B3
D
256
OUT1
JP6
JP15
Figure 7. 8-Bit DAC
CP2
VREF
VDD
VREF (2.5V)
R1
B
+
–
–
R1
A3
JP8 + JP10
VO
+
U1
B
R2
OP AMP
JP4
B3
VO =
U3A
V+
AD822
V–
R WB + R2
R1+ R2 + R AB
OUT1
JP6
R2
Figure 8. 8-Bit DAC with Floating References for Fine Adjustment
REV. 0
–5–
2.5V
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If V IN � VW ,VO � VDD , 0
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Otherwise
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VW � 2.5V �
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256
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Figure 9. Level Detector
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Figure 10. Noninverting Linear Gain
A3
U1
B3
B
VDD
W3
JP4
–IN1
–
OP AMP
VI
+
–
VO
+IN1
+
V+
AD822
V–


D
VO =  1 +
 VI

256 – D 
U3A
OUT1
JP6
Figure 11. Pseudo Log Noninverting Gain
–6–
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Figure 12. Bipolar Linear Gain
2N7000*
VDD
VI
VO
M1
VO
S
RL
G
RL
M1
VREF
VREF (+2.5V)
+
B
D
–IN1
–
JP14
OP AMP
JP10 + JP8
–
B
U1
+IN1
+
VO = 2.5V ×
JP4
V+
AD822
V–
B3
JP15
D
256
(200mA max )
U3A
OUT1
JP6
*NOT INCLUDED
Figure 13. Programmable 2.5 V Power Supply
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Figure 14. Programmable Current Source
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–7–
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256
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AN04874–0–12/05(0)
PCB LAYOUT
Figure 15. Evaluation Board
Figure 16. Top Overlay
Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips
I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
© 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners.
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