ITF87012SVT
Data Sheet
File Number
4810.2
Features
6A, 20V, 0.035 Ohm, N-Channel,
2.5V Specified Power MOSFET
• Ultra Low On-Resistance
- rDS(ON) = 0.035Ω, VGS = 4.5V
- rDS(ON) = 0.038Ω, VGS = 4.0V
- rDS(ON) = 0.045Ω, VGS = 2.5V
Packaging
TSOP-6
•
•
•
•
4
1
2
March 2000
3
2.5 V Gate Drive Capability
Small Profile Package
Gate to Source Protection Diode
Simulation Models
- Temperature Compensated PSPICE™ and SABER
Electrical Models
- Spice and SABER Thermal Impedance Models
- www.intersil.com
• Peak Current vs Pulse Width Curve
Symbol
• Transient Thermal Impedance Curve vs Board Mounting
Area
DRAIN(1)
DRAIN(6)
DRAIN(2)
DRAIN(5)
• Switching Time vs RGS Curves
Ordering Information
GATE(3)
SOURCE(4)
PART NUMBER
ITF87012SVT
PACKAGE
TSOP-6 (SC-95)
BRAND
012
NOTE: When ordering, use the entire part number. ITF87012SVT is
available only in tape and reel.
Absolute Maximum Ratings
TA = 25oC, Unless Otherwise Specified
Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDSS
Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS
Drain Current
Continuous (TA= 25oC, VGS = 4.5V) (Figure 2) (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . ID
Continuous (TA= 25oC, VGS = 4.0V) (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID
Continuous (TA= 100oC, VGS = 4.0V) (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID
Continuous (TA= 100oC, VGS = 2.5V) (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID
Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .IDM
Power Dissipation (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD
Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TL
Package Body for 10s, See Techbrief TB370 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg
NOTES:
ITF87012SVT
20
20
±12
UNITS
V
V
V
6.0
5.5
3.5
3.0
Figure 4
2
16
-55 to 150
A
A
A
A
A
W
mW/oC
oC
300
260
oC
oC
1. TJ = 25oC to 125oC.
2. 62.5oC/W measured using FR-4 board with 0.40 in2 (258.1 mm2) copper pad at 2 second.
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
1
CAUTION: These devices are sensitive to electrostatic discharge. Follow proper ESD Handling Procedures.
SABER© is a Copyright of Analogy Inc., PSPICE® is a registered trademark of MicroSim Corporation.
www.intersil.com or 321-724-7143 | Copyright © Intersil Corporation 2000
ITF87012SVT
TA = 25oC, Unless Otherwise Specified
Electrical Specifications
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
OFF STATE SPECIFICATIONS
20
-
-
V
Zero Gate Voltage Drain Current
IDSS
VDS = 20V, VGS = 0V
-
-
10
µA
Gate to Source Leakage Current
IGSS
VGS = ±12V
-
-
±10
uA
Drain to Source Breakdown Voltage
BVDSS
ID = 250µA, VGS = 0V (Figure 11)
ON STATE SPECIFICATIONS
Gate to Source Threshold Voltage
VGS(TH)
VGS = VDS, ID = 250µA (Figure 10)
0.5
-
1.5
V
Drain to Source On Resistance
rDS(ON)
ID = 6.0A, VGS = 4.5V (Figures 8, 9)
-
0.028
0.035
Ω
ID = 3.5A, VGS = 4.0V (Figure 8)
-
0.029
0.038
Ω
ID = 3.0A, VGS = 2.5V (Figure 8)
-
0.037
0.045
Ω
Pad Area = 0.40 in2 (258.1 mm2) (Note 2)
-
-
62.5
oC/W
Pad Area = 0.0163 in2 (10.54 mm2) (Figure 20)
-
-
198.2
oC/W
Pad Area = 0.0056 in2 (3.60 mm2) (Figure 20)
-
-
218.4
oC/W
VDD = 10V, ID = 3.0A
VGS = 2.5V,
RGS = 15 Ω
(Figures 14, 18, 19 )
-
79
-
ns
-
315
-
ns
-
154
-
ns
-
188
-
ns
THERMAL SPECIFICATIONS
Thermal Resistance Junction to Ambient
RθJA
SWITCHING SPECIFICATIONS (VGS = 2.5V)
Turn-On Delay Time
td(ON)
Rise Time
tr
Turn-Off Delay Time
td(OFF)
Fall Time
tf
SWITCHING SPECIFICATIONS (VGS = 4.5V)
Turn-On Delay Time
td(ON)
Rise Time
tr
Turn-Off Delay Time
td(OFF)
Fall Time
VDD = 10V, ID = 6.0A
VGS = 4.5V,
RGS = 16 Ω
(Figures 15, 18, 19 )
tf
-
42
-
ns
-
142
-
ns
-
236
-
ns
-
200
-
ns
-
7.7
-
nC
-
4.0
-
nC
-
0.30
-
nC
GATE CHARGE SPECIFICATIONS
Total Gate Charge
Qg(TOT)
Gate Charge at 2V
Qg(2)
Threshold Gate Charge
Qg(TH)
VGS = 0V to 4.5V
VGS = 0V to 2V
VGS = 0V to 0.5V
VDD = 10V,
ID = 5.5A,
Ig(REF) = 1.0mA
(Figures 13, 16, 17 )
Gate to Source Gate Charge
Qgs
-
1.1
-
nC
Gate to Drain “Miller” Charge
Qgd
-
2.7
-
nC
-
655
-
pF
-
227
-
pF
-
118
-
pF
MIN
TYP
MAX
UNITS
CAPACITANCE SPECIFICATIONS
Input Capacitance
CISS
Output Capacitance
COSS
Reverse Transfer Capacitance
CRSS
VDS = 10V, VGS = 0V,
f = 1MHz
(Figures 12 )
Source to Drain Diode Specifications
PARAMETER
SYMBOL
Source to Drain Diode Voltage
VSD
Reverse Recovery Time
Reverse Recovered Charge
2
TEST CONDITIONS
ISD = 5.5A
-
0.84
-
V
trr
ISD = 5.5A, dISD/dt = 50A/µs
-
22
-
ns
QRR
ISD = 5.5A, dISD/dt = 50A/µs
-
6.1
-
nC
ITF87012SVT
Typical Performance Curves
8
1.0
ID, DRAIN CURRENT (A)
POWER DISSIPATION MULTIPLIER
1.2
0.8
0.6
0.4
VGS = 4.5V, RθJA = 62.5oC/W
6
4
2
VGS = 2.5V, RθJA = 218.4oC/W
0.2
0
0
0
25
50
75
100
125
25
150
50
75
100
125
150
TA, AMBIENT TEMPERATURE (oC)
TA , AMBIENT TEMPERATURE (oC)
FIGURE 1. NORMALIZED POWER DISSIPATION vs AMBIENT
TEMPERATURE
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
AMBIENT TEMPERATURE
3
THERMAL IMPEDANCE
ZθJA, NORMALIZED
1
DUTY CYCLE - DESCENDING ORDER
0.5
0.2
0.1
0.05
0.02
0.01
RθJA = 62.5oC/W
0.1
PDM
t1
0.01
t2
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJA x RθJA + TA
SINGLE PULSE
0.001
10-5
10-4
10-3
10-2
10-1
100
101
102
103
t, RECTANGULAR PULSE DURATION (s)
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
IDM, PEAK CURRENT (A)
500
RθJA = 62.5oC/W
TA = 25oC
FOR TEMPERATURES
ABOVE 25oC DERATE PEAK
CURRENT AS FOLLOWS:
100
VGS = 4.5V
I = I25
150 - TA
125
VGS = 2.5V
10
1
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
10-5
10-4
10-3
10-2
10-1
100
t, PULSE WIDTH (s)
FIGURE 4. PEAK CURRENT CAPABILITY
3
101
102
103
ITF87012SVT
Typical Performance Curves
(Continued)
200
ID, DRAIN CURRENT (A)
ID, DRAIN CURRENT (A)
20
SINGLE PULSE
TJ = MAX RATED
TA = 25oC
100
100µs
10
1ms
OPERATION IN THIS
AREA MAY BE
LIMITED BY rDS(ON)
RθJA = 62.5oC/W
1
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
VDD = 15V
15
10
TJ = 150oC
5
10ms
1
TJ = 25oC
TJ = -55oC
10
0
50
1.0
1.5
2.0
2.5
VGS, GATE TO SOURCE VOLTAGE (V)
0.5
VDS, DRAIN TO SOURCE VOLTAGE (V)
FIGURE 5. FORWARD BIAS SAFE OPERATING AREA
FIGURE 6. TRANSFER CHARACTERISTICS
20
100
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
rDS(ON), DRAIN TO SOURCE
ON RESISTANCE (mΩ)
ID, DRAIN CURRENT (A)
VGS = 4.5V
VGS = 3V
15
VGS = 2.5V
10
VGS = 2V
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
5
VGS = 1.5V
TA = 25oC
0
80
ID = 6A
60
ID = 3A
40
20
1.5
0.5
1.0
VDS, DRAIN TO SOURCE VOLTAGE (V)
0
1
2.0
FIGURE 7. SATURATION CHARACTERISTICS
2
3
4
VGS, GATE TO SOURCE VOLTAGE (V)
5
FIGURE 8. DRAIN TO SOURCE ON RESISTANCE vs GATE
VOLTAGE AND DRAIN CURRENT
1.6
1.4
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
VGS = 4.5V, ID = 6A
VGS = VDS, ID = 250µA
1.4
NORMALIZED GATE
THRESHOLD VOLTAGE
NORMALIZED DRAIN TO SOURCE
ON RESISTANCE
3.0
1.2
1.0
1.2
1.0
0.8
0.6
0.8
0.4
0.6
-80
-40
0
40
80
120
TJ, JUNCTION TEMPERATURE (oC)
FIGURE 9. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
4
160
-80
-40
0
40
80
120
160
TJ, JUNCTION TEMPERATURE (oC)
FIGURE 10. NORMALIZED GATE THRESHOLD VOLTAGE vs
JUNCTION TEMPERATURE
ITF87012SVT
Typical Performance Curves
(Continued)
1500
ID = 250µA
CISS = CGS + CGD
1000
1.05
C, CAPACITANCE (pF)
NORMALIZED DRAIN TO SOURCE
BREAKDOWN VOLTAGE
1.10
1.00
0.95
COSS ≅ CDS + CGD
CRSS = CGD
100
VGS = 0V, f = 1MHz
0.90
-80
-40
0
40
80
120
50
160
0.1
1.0
TJ , JUNCTION TEMPERATURE (oC)
FIGURE 11. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
20
FIGURE 12. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
500
5
VGS = 2.5V, VDD = 10V, ID = 3.0A
VDD = 10V
4
SWITCHING TIME (ns)
VGS , GATE TO SOURCE VOLTAGE (V)
10
VDS , DRAIN TO SOURCE VOLTAGE (V)
3
2
WAVEFORMS IN
DESCENDING ORDER:
ID = 5.5A
ID = 3A
1
400
tr
300
tf
200
100
td(ON)
0
td(OFF)
0
0
2
4
6
Qg, GATE CHARGE (nC)
10
8
0
NOTE: Refer to Intersil Application Notes AN7254 and AN7260.
10
20
30
40
RGS, GATE TO SOURCE RESISTANCE (Ω)
FIGURE 14. SWITCHING TIME vs GATE RESISTANCE
FIGURE 13. GATE CHARGE WAVEFORMS FOR CONSTANT
GATE CURRENT
400
SWITCHING TIME (ns)
VGS = 4.5V, VDD = 10V, ID = 6A
td(OFF)
300
tf
200
tr
100
td(ON)
0
0
10
20
30
40
RGS, GATE TO SOURCE RESISTANCE (Ω)
FIGURE 15. SWITCHING TIME vs GATE RESISTANCE
5
50
50
ITF87012SVT
Test Circuits and Waveforms
VDS
RL
VDD
Qg(TOT)
VDS
VGS = 4.5V
VGS
+
Qg(2)
VDD
-
VGS = 2V
VGS
DUT
VGS = 0.5V
Ig(REF)
0
Qg(TH)
Qgs
Qgd
Ig(REF)
0
FIGURE 16. GATE CHARGE TEST CIRCUIT
FIGURE 17. GATE CHARGE WAVEFORMS
tON
td(ON)
RL
td(OFF)
+
VGS
tf
tr
VDS
VGS
tOFF
VDS
90%
90%
0V
10%
10%
0
DUT
RGS
90%
VGS
0
FIGURE 18. SWITCHING TIME TEST CIRCUIT
10%
50%
50%
PULSE WIDTH
FIGURE 19. SWITCHING TIME WAVEFORM
Thermal Resistance vs. Mounting Pad Area
The maximum rated junction temperature, TJM, and the thermal
resistance of the heat dissipating path determines the maximum
allowable device power dissipation, PDM, in an application.
Therefore the application’s ambient temperature, TA (oC), and
thermal resistance RθJA (oC/W) must be reviewed to ensure
that TJM is never exceeded. Equation 1 mathematically
represents the relationship and serves as the basis for
establishing the rating of the part.
( T JM – T A )
P DM = ------------------------------Z θJA
(EQ. 1)
In using surface mount devices such as the TSOP-6
package, the environment in which it is applied will have a
significant influence on the part’s current and maximum
power dissipation ratings. Precise determination of PDM is
complex and influenced by many factors:
6
1. Mounting pad area onto which the device is attached and
whether there is copper on one side or both sides of the
board.
2. The number of copper layers and the thickness of the board.
3. The use of external heat sinks.
4. The use of thermal vias.
5. Air flow and board orientation.
6. For non steady state applications, the pulse width, the duty
cycle and the transient thermal response of the part, the
board and the environment they are in.
Intersil provides thermal information to assist the designer’s
preliminary application evaluation. Figure 20 defines the RθJA
for the device as a function of the top copper (component
side) area. This is for a horizontally positioned FR-4 board
with 1oz copper after 1000 seconds of steady state power
ITF87012SVT
Displayed on the curve are RθJA values listed in the Electrical
Specifications table. The points were chosen to depict the
compromise between the copper board area, the thermal
resistance and ultimately the power dissipation, PDM.
Thermal resistances corresponding to other copper areas can
be obtained from Figure 20 or by calculation using Equation 2.
RθJA is defined as the natural log of the area times a coefficient
added to a constant. The area, in square inches is the top
copper area including the gate and source pads.
R θJA = 120.6 – 18.9 ln ( Area )
ZθJA, THERMAL
IMPEDANCE (oC/W)
160
120
260
RθJA = 120.6- 18.9*ln(AREA)
240
218.4oC/W - 0.0056in2
220
198.2oC/W - 0.0163in2
200
180
160
(EQ. 2)
The transient thermal impedance (ZθJA) is also effected by
varied top copper board area. Figure 21 shows the effect of
copper pad area on single pulse transient thermal
impedance. Each trace represents a copper pad area in
square inches corresponding to the descending list in the
graph. Spice and SABER thermal models are provided for
each of the listed pad areas.
200
Copper pad area has no perceivable effect on transient
thermal impedance for pulse widths less than 100ms. For
pulse widths less than 100ms the transient thermal
impedance is determined by the die and package. Therefore,
CTHERM1 through CTHERM5 and RTHERM1 through
RTHERM5 remain constant for each of the thermal models. A
listing of the model component values is available in Table 1.
RθJA (oC/W)
with no air flow. This graph provides the necessary
information for calculation of the steady state junction
temperature or power dissipation. Pulse applications can be
evaluated using the Intersil device Spice thermal model or
manually utilizing the normalized maximum transient thermal
impedance curve.
140
120
0.001
0.01
0.1
1.0
AREA, TOP COPPER AREA (in2)
FIGURE 20. THERMAL RESISTANCE vs MOUNTING PAD AREA
COPPER BOARD AREA - DESCENDING ORDER
0.02 in2
0.05 in2
0.10 in2
0.25 in2
0.40 in2
80
40
0
10-1
100
101
t, RECTANGULAR PULSE DURATION (s)
FIGURE 21. THERMAL IMPEDANCE vs MOUNTING PAD AREA
7
102
103
ITF87012SVT
PSPICE Electrical Model
.SUBCKT ITF87012SVT 2 1 3 ;
REV 25 Jan 2000
CA 12 8 11.00e-10
CB 15 14 9.50e-10
CIN 6 8 5.25e-10
LDRAIN
DBODY 7 5 DBODYMOD
DBREAK 5 11 DBREAKMOD
DESD1 91 9 DESD1MOD
DESD1 91 7 DESD2MOD
DPLCAP 10 5 DPLCAPMOD
DPLCAP
5
DRAIN
2
10
RLDRAIN
DBREAK
RSLC1
51
RSLC2
+
5
51
EBREAK 11 7 17 18 27.41
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 6 10 6 8 1
EVTHRES 6 21 19 8 1
EVTEMP 20 6 18 22 1
-
RDRAIN
16
6
8
ESG
EVTHRES
+ 19 8
+
GATE
1
LDRAIN 2 5 1.00e-9
LGATE 1 9 1.04e-9
LSOURCE 3 7 1.29e-10
EVTEMP
9 RGATE + 18 22
20
EBREAK
6
+
17
18
DBODY
-
21
MWEAK
MMED
MSTRO
RLGATE
DESD1
91
DESD2
MMED 16 6 8 8 MMEDMOD
MSTRO 16 6 8 8 MSTROMOD
MWEAK 16 21 8 8 MWEAKMOD
LSOURCE
CIN
SOURCE
3
7
8
RSOURCE
RLSOURCE
RBREAK 17 18 RBREAKMOD 1
RDRAIN 50 16 RDRAINMOD 2.00e-3
RGATE 9 20 118
RLDRAIN 2 5 10
RLGATE 1 9 9 10.4
RLSOURCE 3 7 1.29
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
RSOURCE 8 7 RSOURCEMOD 17.00e-3
RVTHRES 22 8 RVTHRESMOD 1
RVTEMP 18 19 RVTEMPMOD 1
S1A
S1B
S2A
S2B
11
50
-
LGATE
IT 8 17 1
ESLC
S1A
12
S2A
13
8
14
13
S1B
CA
RBREAK
15
17
18
RVTEMP
S2B
13
CB
6
8
EGS
19
-
-
IT
14
+
+
VBAT
5
8
EDS
-
+
8
22
6 12 13 8 S1AMOD
13 12 13 8 S1BMOD
6 15 14 13 S2AMOD
13 15 14 13 S2BMOD
RVTHRES
VBAT 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*175),2))}
.MODEL DBODYMOD D (IS = 3.48e-11 IKF = 0.15 XT I= 0.18 RS = 1.47e-2 TRS1 = 1.25e-3 TRS2 = 0 CJO = 3.67e-10 TT = 2.20e-8 M = 0.52)
.MODEL DBREAKMOD D (RS = 9.52e-2 TRS1 = 1.05e-3 TRS2 = 1.13e-6)
.MODEL DESD1MOD D (BV = 8.2 Tbv1= -1.87e-3 N= 12 RS = 20)
.MODEL DESD2MOD D (BV = 11.5 Tbv1= -2.01e-3 N= 8 RS = 20)
.MODEL DPLCAPMOD D (CJO = 4.91e-10 IS = 1e-30 M = 0.59)
.MODEL MMEDMOD NMOS (VTO = 1.10 KP = 2.60 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 118)
.MODEL MSTROMOD NMOS (VTO = 1.29 KP = 58 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)
.MODEL MWEAKMOD NMOS (VTO = 0.86 KP = 0.10 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 1180 RS = 0.1)
.MODEL RBREAKMOD RES (TC1 = 7.58e-4 TC2 = -1.43e-6)
.MODEL RDRAINMOD RES (TC1 = 2.21e-2 TC2 = 2.72e-5)
.MODEL RSLCMOD RES (TC1 = 1.21e-3 TC2 = 1.00e-5)
.MODEL RSOURCEMOD RES (TC1 = 1.00e-3 TC2 = 0)
.MODEL RVTHRESMOD RES (TC1 = -2.01e-3 TC2 = -1.01e-6)
.MODEL RVTEMPMOD RES (TC1 = -8.40e-4 TC2 = 0)
.MODEL S1AMOD VSWITCH (RON = 1e-5
.MODEL S1BMOD VSWITCH (RON = 1e-5
.MODEL S2AMOD VSWITCH (RON = 1e-5
.MODEL S2BMOD VSWITCH (RON = 1e-5
ROFF = 0.1
ROFF = 0.1
ROFF = 0.1
ROFF = 0.1
VON = -3.5 VOFF= -3.0)
VON = -3.0 VOFF= -3.5)
VON = -1.5 VOFF= 0)
VON = 0 VOFF= -1.5)
.ENDS
NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley.
8
ITF87012SVT
SABER Electrical Model
REV 25 Jan 2000
template itf87012svt n2,n1,n3
electrical n2,n1,n3
{
var i iscl
dp..model dbodymod = (is = 3.48e-11,ikf = 0.15,xti = 0.18,rs = 1.47e-2,trs1 = 1.25e-3,trs2 = 0,cjo = 3.67e-10,tt = 2.20e-8,m = 0.52)
dp..model dbreakmod = (rs = 9.52e-2,trs1 = 1.05e-3,trs2 = 1.13e-6)
dp..model desd1mod = (bv = 8.2,tbv1 = -1.87e-3,n1 = 12,rs = 20)
dp..model desd2mod = (bv = 11.5,tbv1 = -2.01e-3,n1 = 8,rs = 20)
dp..model dplcapmod = (cjo = 4.91e-10,is = 1e-30,m = 0.59)
m..model mmedmod = (type=_n, vto = 1.01,kp = 2.60,is = 1e-30,tox = 1)
LDRAIN
m..model mstrongmod = (type=_n, vto = 1.29, kp = 58, is = 1e-30, tox = 1)
DPLCAP 5
m..model mweakmod = (type=_n, vto = 0.86, kp = 0.10, is = 1e-30, tox = 1)
sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = -3.5, voff = -3.0) 10
RLDRAIN
sw_vcsp..model s1bmod = (ron = 1e-5, roff = 0.1, von = -3.0, voff = -3.5)
RSLC1
sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = -1.5, voff = 0)
51
sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = 0, voff = -1.5)
RSLC2
DRAIN
2
ISCL
c.ca n12 n8 = 11.00e-10
c.cb n15 n14 = 9.50e-10
c.cin n6 n8 = 5.25e-10
dp.dbody n7 n71 = model=dbodymod
dp.dbreak n72 n11 = model=dbreakmod
dp.desd1 n91 n9 = model=desd1mod
dp.desd2 n91 n7 = model=desd2mod GATE
dp.dplcap n10 n5 = model=dplcapmod 1
i.it n8 n17 = 1
l.ldrain n2 n5 = 1.00e-9
l.lgate n1 n9 = 1.04e-9
l.lsource n3 n7 = 1.29e-10
RDRAIN
6
8
ESG
DBREAK
50
EVTHRES
+ 19 8
+
LGATE
EVTEMP
RGATE + 18 22
9
20
RLGATE
DESD1
91
DESD2
21
11
DBODY
16
MWEAK
6
EBREAK
+
17
18
MMED
MSTRO
CIN
-
8
LSOURCE
7
RSOURCE
RLSOURCE
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u
m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u
S1A
12
S2A
13
8
S1B
res.rbreak n17 n18 = 1, tc1 = 7.58e-4, tc2 = -1.43e-6
res.rdrain n50 n16 = 2.00e-3, tc1 = 2.21e-2, tc2 = 2.75e-5 CA
res.rgate n9 n20 = 118
res.rldrain n2 n5 = 10
res.rlgate n1 n9 = 10.4
res.rlsource n3 n7 = 1.29
res.rslc1 n5 n51 = 1e-6, tc1 = 1.21e-3, tc2 = 1.00e-5
res.rslc2 n5 n50 = 1e3
res.rsource n8 n7 = 17.00e-3, tc1 = 1.00e-3, tc2 = 0
res.rvtemp n18 n19 = 1, tc1 = -8.40e-4, tc2 = 0
res.rvthres n22 n8 = 1, tc1 = -2.01e-3, tc2 = -1.01e-6
17
18
RVTEMP
S2B
13
CB
6
8
EGS
19
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod
v.vbat n22 n19 = dc=1
equations {
i (n51->n50) +=iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/175))** 2))
}
}
VBAT
5
8
EDS
-
-
IT
14
+
+
spe.ebreak n11 n7 n17 n18 = 27.41
spe.eds n14 n8 n5 n8 = 1
spe.egs n13 n8 n6 n8 = 1
spe.esg n6 n10 n6 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1
spe.evthres n6 n21 n19 n8 = 1
9
RBREAK
15
14
13
-
+
8
22
RVTHRES
SOURCE
3
ITF87012SVT
SPICE Thermal Model
REV 24 Jan 2000
ITF87012SVT
Copper Area = 0.02 in2
CTHERM1 th 8 1.10e-3
CTHERM2 8 7 5.00e-3
CTHERM3 7 6 7.00e-3
CTHERM4 6 5 9.00e-3
CTHERM5 5 4 1.10e-2
CTHERM6 4 3 4.00e-2
CTHERM7 3 2 3.00e-1
CTHERM8 2 tl 1.50
JUNCTION
th
CTHERM1
RTHERM1
8
CTHERM2
RTHERM2
RTHERM1 th 8 0.25
RTHERM2 8 7 0.60
RTHERM3 7 6 1.25
RTHERM4 6 5 8.00
RTHERM5 5 4 10.00
RTHERM6 4 3 43.00
RTHERM7 3 2 48.00
RTHERM8 2 tl 50.00
7
CTHERM3
RTHERM3
6
RTHERM4
SABER Thermal Model
Copper Area = 0.02 in2
template thermal_model th tl
thermal_c th, tl
{
ctherm.ctherm1 th 8 = 1.10e-3
ctherm.ctherm2 8 7 = 5.00e-3
ctherm.ctherm3 7 6 = 7.00e-3
ctherm.ctherm4 6 5 = 9.00e-3
ctherm.ctherm5 5 4 = 1.10e-2
ctherm.ctherm6 4 3 = 4.00e-2
ctherm.ctherm7 3 2 = 3.00e-1
ctherm.ctherm8 2 tl = 1.50
CTHERM4
5
CTHERM5
RTHERM5
4
RTHERM6
CTHERM6
3
CTHERM7
RTHERM7
rtherm.rtherm1 th 8 = 0.25
rtherm.rtherm2 8 7 = 0.60
rtherm.rtherm3 7 6 = 1.25
rtherm.rtherm4 6 5 = 8.00
rtherm.rtherm5 5 4 = 10.00
rtherm.rtherm6 4 3 = 43.00
rtherm.rtherm7 3 2 = 48.00
rtherm.rtherm8 2 tl = 50.00
}
2
CTHERM8
RTHERM8
tl
CASE
TABLE 1. Thermal Models
0.02 in2
0.05 in2
0.10 in2
0.25 in2
0.40 in2
CTHERM6
4.00e-2
4.00e-2
4.20e-2
4.00e-2
4.00e-2
CTHERM7
3.00e-1
3.50e-1
3.30e-1
3.00e-1
2.80e-1
CTHERM8
1.50
1.50
1.50
1.50
1.50
RTHERM6
43
35
35
27
27
RTHERM7
48
40
37
30
29
RTHERM8
50
45
42
45
37
COMPONANT
10
ITF87012SVT
MO-193AA (TSOP-6)
6 LEAD JEDEC MO-193AA TSOP PLASTIC PACKAGE
(SIMILAR TO SSOT™-6)
INCHES
E
E1
A
1
SYMBOL
MIN
MAX
MIN
MAX
A
0.035
0.043
0.90
1.10
6
A1
e
D
3
4
b
C
0.020
0.30
0.50
c
0.003
0.008
0.08
0.20
D
0.107
0.122
2.70
3.10
E
0.103
0.118
2.60
3.00
E1
0.056
0.070
1.40
1.80
0.021
2
3
0.95 BSC
0.35
0.55
4
NOTES:
1. All dimensions are within the allowable dimensions of Rev. B of
JEDEC MO-193AA outline dated 10-99.
2. Dimension "D" does not include mold flash, protrusions or gate
burrs. Mold flash, protrusions or gate burrs shall not exceed
0.006 inches (0.15mm) per side.
3. Dimension "E " does not include inter-lead flash or protrusions.
Inter-lead flash and protrusions shall not exceed 0.006 inches
(0.15mm) per side.
4. "L" is the length of terminal for soldering.
5. Controlling dimension: Millimeter.
6. Revision 1 dated 2-00.
0.004in
0.10mm
0o-8o
0.037
0.95
0.075
1.90
0.024
0.60
0.037 BSC
0.014
NOTES
0.10
0.012
L
0.039
1.00
0.004
b
e
L
MILLIMETERS
0.095
2.40
MO-193AA (TSOP-6)
8mm TAPE AND REEL
USER DIRECTION OF FEED
4.0mm
1.5mm DIAMETER HOLE
1.75mm
2.0mm
CL
3.5mm
6.0mm
4.0mm
COVER TAPE
17.0mm
13.0mm
178mm
60mm
13.0mm
GENERAL INFORMATION
1. 3000 PIECES PER REEL.
2. ORDER IN MULTIPLES OF FULL REELS ONLY.
3. MEETS EIA-481 REVISION “A” SPECIFICATIONS.
SSOT™-6 is a trademark of Fairchild Semiconductor.
11
ITF87012SVT
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site www.intersil.com
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NORTH AMERICA
Intersil Corporation
P. O. Box 883, Mail Stop 53-204
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TEL: (321) 724-7000
FAX: (321) 724-7240
12
EUROPE
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