C515

D a ta S he e t , F e b . 20 0 3
C515C
8 - B i t S i n gl e - C h i p M i c r o c o nt r o l l e r
M i c r o c o n t r o l l er s
N e v e r
s t o p
t h i n k i n g .
Edition 2003-02
Published by Infineon Technologies AG,
St.-Martin-Strasse 53,
81669 München, Germany
© Infineon Technologies AG 2003.
All Rights Reserved.
Attention please!
The information herein is given to describe certain components and shall not be considered as a guarantee of
characteristics.
Terms of delivery and rights to technical change reserved.
We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding
circuits, descriptions and charts stated herein.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest
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(www.infineon.com).
Warnings
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D a ta S he e t , F e b . 20 0 3
C515C
8 - B i t S i n gl e - C h i p M i c r o c o nt r o l l e r
M i c r o c o n t r o l l er s
N e v e r
s t o p
t h i n k i n g .
C515C Data Sheet
Revision History:
2003-02
Previous Version:
2000-08
Page
Subjects (major changes since last revision)
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8-Bit Single-Chip Microcontroller
C515C
Features
• Full upward compatibility with SAB 80C515A
• On-chip program memory (with optional memory protection)
– C515C-8R 64 Kbytes on-chip ROM
– C515C-8E 64 Kbytes on-chip OTP
– alternatively up to 64 Kbytes external program memory
• 256 bytes on-chip RAM
• 2 Kbytes of on-chip XRAM
• Up to 64 Kbytes external data memory
• Superset of the 8051 architecture with 8 datapointers
• Up to 10 MHz external operating frequency (1 µs instruction cycle time at 6 MHz
external clock)
• On-chip emulation support logic (Enhanced Hooks Technology)
• Current optimized oscillator circuit and EMI optimized design
On-Chip Emulation Support Module
(further features are on next page)
Figure 1
Data Sheet
Full-CAN
Controller
SSC (SPI)
Interface
Oscillator
Watchdog
Power
Save Modes
Idle/
Power down
Slow down
XRAM
2k x 8
10 Bit ADC
(8 inputs)
RAM
256 x 8
T0
CPU
8 Datapointer
Timer 2
Capture/Compare Unit
Port 7
Port 6
Port 5
Port 4
I/O
Analog/
Digital
Input
I/O
I/O
T1
Program Memory
C515C-8R : 64k x 8 ROM
C515C-8E : 64k x 8 OTP
Port 0
I/O
Port 1
I/O
Port 2
I/O
Port 3
I/O
8 Bit
USART
MCA03646
C515C Functional Units
1
2003-02
C515C
• Eight ports: 48 + 1 digital I/O lines, 8 analog inputs
– Quasi-bidirectional port structure (8051 compatible)
– Port 5 selectable for bidirectional port structure (CMOS voltage levels)
• Full-CAN controller on-chip
– 256 register/data bytes are located in external data memory area
– max. 1 MBaud at 8 - 10 MHz operating frequency
• Three 16-bit timer/counters
– Timer 2 can be used for compare/capture functions
• 10-bit A/D converter with multiplexed inputs and built-in self calibration
• Full duplex serial interface with programmable baudrate generator (USART)
• SSC synchronous serial interface (SPI compatible)
– Master and slave capable
– Programmable clock polarity/clock-edge to data phase relation
– LSB/MSB first selectable
– 2.5 MHz transfer rate at 10 MHz operating frequency
• Seventeen interrupt vectors, at four priority levels selectable
• Extended watchdog facilities
– 15-bit programmable watchdog timer
– Oscillator watchdog
• Power saving modes
– Slow-down mode
– Idle mode (can be combined with slow-down mode)
– Software power-down mode with wake-up capability through INT0 or RXDC pin
– Hardware power-down mode
• CPU running condition output pin
• ALE can be switched off
• Multiple separate VDD/VSS pin pairs
• P-MQFP-80-1 package
• Temperature Ranges:
SAB-C515C versions: TA = 0 to 70 °C
SAF-C515C versions: TA = -40 to 85 °C
SAH-C515C versions: TA = -40 to 110 °C
Note: Versions for extended temperature range -40 °C to 110 °C (SAH-C515C) are
available on request.
The C515C is an enhanced, upgraded version of the SAB 80C515A 8-bit microcontroller
which additionally provides a full CAN interface, a SPI compatible synchronous serial
interface, extended power save provisions, additional on-chip RAM, 64K of on-chip
program memory, two new external interrupts and RFI related improvements. With a
maximum external clock rate of 10 MHz it achieves a 600 ns instruction cycle time (1 µs
at 6 MHz).
Data Sheet
2
2003-02
C515C
The C515C-8R contains a non-volatile 64 Kbytes read-only program memory. The
C515C-L is identical to the C515C-8R, except that it lacks the on-chip program memory.
The C515C-8E is the OTP version in the C515C microcontroller with an on-chip
64 Kbytes one-time programmable (OTP) program memory. The C515C is mounted in
a P-MQFP-80-1 package.
If compared to the C515C-8R and C515C-L, the C515C-8E OTP version additionally
provides two features:
• The wake-up from software power down mode can, additionally to the external pin
P3.2/INT0 wake-up capability, also be triggered alternatively by a second pin
P4.7/RXDC.
• For power consumption reasons the on-chip CAN controller can be switched off.
Table 1
Device
Differences in Internal Program Memory of the C505 MCUs
Internal Program Memory
ROM
OTP
C515C-LM
–
–
C515C-8RM
64 Kbytes
–
C515C-8EM
–
64 Kbytes
Note: The term C515C refers to all versions described within this document unless
otherwise noted.
Ordering Information
The ordering code for Infineon Technologies’ microcontrollers provides an exact
reference to the required product. This ordering code identifies:
• The derivative itself, i.e. its function set
• The specified temperature rage
• The package and the type of delivery
For the available ordering codes for the C515C please refer to the “Product information
Microcontrollers”, which summarizes all available microcontroller variants.
Note: The ordering codes for the Mask-ROM versions are defined for each product after
verification of the respective ROM code.
Data Sheet
3
2003-02
C515C
VAGND
VAREF
Port 0
8 Bit Digital I/O
Port 1
8 Bit Digital I/O
XTAL1
XTAL2
Port 2
8 Bit Digital I/O
ALE
PSEN
EA
RESET
PE/SWD
HWPD
CPUR
Port 3
8 Bit Digital I/O
Port 4
8 Bit Digital I/O
C515C
Port 5
8 Bit Digital I/O
Port 6
8 Bit Analog/
Digital Inputs
VSSE1
VDDE1
VSSE2
VDDE2
Port 7
1 Bit Digital I/O
VSS1
VDD1
VSSCLK
VDDCLK
VSSEXT
VDDEXT
MCL02714
Figure 2
Data Sheet
Logic Symbol
4
2003-02
P5.7
P0.7/AD7
P0.6/AD6
P0.5/AD5
P0.4/AD4
P0.3/AD3
P0.2/AD2
P0.1/AD1
P0.0/AD0
VSSEXT
VDDEXT
EA
ALE
PSEN
CPUR
P2.7/A15
P2.6/A14
P2.5/A13
P2.4/A12
P2.3/A11
C515C
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
P5.6
P5.5
P5.4
P5.3
P5.2
P5.1
P5.0
VDDE2
HWPD
VSSE2
N.C.
P4.0/ADST
P4.1/SCLK
P4.2/SRI
PE/SWD
P4.3/STO
P4.4/SLS
P4.5/INT8
P4.6/TXDC
P4.7/RXDC
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
C515C
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
P2.2/A10
P2.1/A9
P2.0/A8
XTAL1
XTAL2
VSSE1
VSS1
VDD1
VDDE1
P1.0/INT3/CC0
P1.1/INT4/CC1
P1.2/INT5/CC2
P1.3/INT6/CC3
P1.4/INT2
P1.5/T2EX
P1.6/CLKOUT
P1.7/T2
P7.0/INT7
P3.7/RD
P3.6/WR
RESET
N.C.
VAREF
VAGND
P6.7/AIN7
P6.6/AIN6
P6.5/AIN5
P6.4/AIN4
P6.3/AIN3
P6.2/AIN2
P6.1/AIN1
P6.0/AIN0
VSSCLK
VDDCLK
P3.0/RXD
P3.1/TXD
P3.2/INT0
P3.3/INT1
P3.4/T0
P3.5/T1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
Figure 3
Data Sheet
MCP02715
C515C Pin Configuration P-MQFP-80-1 (top view)
5
2003-02
C515C
Table 2
Symbol
Pin Definitions and Functions
Pin Number
I/O1) Function
P-MQFP-80-1
RESET
1
I
RESET
A low level on this pin for the duration of two
machine cycles while the oscillator is running resets
the C515C. A small internal pullup resistor permits
power-on reset using only a capacitor connected to
VSS .
VAREF
VAGND
3
–
Reference voltage for the A/D converter
4
–
Reference ground for the A/D converter
P6.0-P6.7
12-5
I
Port 6
is an 8-bit unidirectional input port to the
A/D converter. Port pins can be used for digital
input, if voltage levels simultaneously meet the
specifications high/low input voltages and for the
eight multiplexed analog inputs.
I/O
Port 7
is an 1-bit quasi-bidirectional I/O port with internal
pull-up resistor. When a 1 is written to P7.0 it is
pulled high by an internal pull-up resistor, and in that
state can be used as input. As input, P7.0 being
externally pulled low will source current (IIL, in the
DC characteristics) because of the internal pull-up
resistor. If P7.0 is used as interrupt input, its output
latch must be programmed to a one (1). The
secondary function is assigned to the port 7 pin as
follows:
P7.0 INT7, Interrupt 7 input
P7.0 / INT7 23
Data Sheet
6
2003-02
C515C
Table 2
Symbol
Pin Definitions and Functions (cont’d)
Pin Number
I/O1) Function
P-MQFP-80-1
P3.0-P3.7
15-22
15
16
17
18
19
20
21
22
Data Sheet
I/O
Port 3
is an 8-bit quasi-bidirectional I/O port with internal
pullup resistors. Port 3 pins that have 1's written to
them are pulled high by the internal pullup resistors,
and in that state can be used as inputs. As inputs,
port 3 pins being externally pulled low will source
current (IIL, in the DC characteristics) because of
the internal pullup resistors. Port 3 also contains the
interrupt, timer, serial port and external memory
strobe pins that are used by various options. The
output latch corresponding to a secondary function
must be programmed to a one (1) for that function to
operate. The secondary functions are assigned to
the pins of port 3, as follows:
P3.0 RXD
Receiver data input (asynch.) or
data input/output (synch.) of
serial interface
P3.1 TXD
Transmitter data output (asynch.)
or clock output (synch.) of serial
interface
P3.2 INT0
External interrupt 0 input / timer 0
gate control input
P3.3 INT1
External interrupt 1 input / timer 1
gate control input
P3.4 T0
Timer 0 counter input
P3.5 T1
Timer 1 counter input
P3.6 WR
WR control output; latches the
data byte from port 0 into the
external data memory
P3.7 RD
RD control output; enables the
external data memory
7
2003-02
C515C
Table 2
Symbol
Pin Definitions and Functions (cont’d)
Pin Number
I/O1) Function
P-MQFP-80-1
P1.0 - P1.7 31-24
I/O
Port 1
is an 8-bit quasi-bidirectional I/O port with internal
pullup resistors. Port 1 pins that have 1's written to
them are pulled high by the internal pullup resistors,
and in that state can be used as inputs. As inputs,
port 1 pins being externally pulled low will source
current (IIL, in the DC characteristics) because of
the internal pullup resistors. The port is used for the
low-order address byte during program verification.
Port 1 also contains the interrupt, timer, clock,
capture and compare pins that are used by various
options. The output latch corresponding to a
secondary function must be programmed to a one
(1) for that function to operate (except when used for
the compare functions). The secondary functions
are assigned to the port 1 pins as follows:
P1.0 INT3 CC0 Interrupt 3 input / compare 0
output / capture 0 input
P1.1 INT4 CC1 Interrupt 4 input / compare 1
output / capture 1 input
P1.2 INT5 CC2 Interrupt 5 input / compare 2
output / capture 2 input
P1.3 INT6 CC3 Interrupt 6 input / compare 3
output / capture 3 input
P1.4 INT2
Interrupt 2 input
P1.5 T2EX
Timer 2 external reload / trigger
input
P1.6 CLKOUT System clock output
P1.7 T2
Counter 2 input
I
XTAL2
Input to the inverting oscillator amplifier and input to
the internal clock generator circuits.
To drive the device from an external clock source,
XTAL2 should be driven, while XTAL1 is left
unconnected. Minimum and maximum high and low
times as well as rise/fall times specified in the AC
characteristics must be observed.
31
30
29
28
27
26
25
24
XTAL2
Data Sheet
36
8
2003-02
C515C
Table 2
Symbol
Pin Definitions and Functions (cont’d)
Pin Number
I/O1) Function
P-MQFP-80-1
XTAL1
37
O
XTAL1
Output of the inverting oscillator amplifier.
P2.0-P2.7
38-45
I/O
Port 2
is an 8-bit quasi-bidirectional I/O port with internal
pullup resistors. Port 2 pins that have 1's written to
them are pulled high by the internal pullup resistors,
and in that state can be used as inputs. As inputs,
port 2 pins being externally pulled low will source
current (IIL, in the DC characteristics) because of
the internal pullup resistors.
Port 2 emits the high-order address byte during
fetches from external program memory and during
accesses to external data memory that use 16-bit
addresses (MOVX @DPTR). In this application it
uses strong internal pullup resistors when issuing
1's. During accesses to external data memory that
use 8-bit addresses (MOVX @Ri), port 2 issues the
contents of the P2 special function register.
CPUR
46
O
CPU Running Condition
This output pin is at low level when the CPU is
running and program fetches or data accesses in
the external data memory area are executed. In idle
mode, hardware and software power down mode,
and with an active RESET signal CPUR is set to
high level.
CPUR can be typically used for switching external
memory devices into power saving modes.
PSEN
47
O
The Program Store Enable
output is a control signal that enables the external
program memory to the bus during external fetch
operations. It is activated every six oscillator
periods, except during external data memory
accesses. The signal remains high during internal
program execution.
Data Sheet
9
2003-02
C515C
Table 2
Symbol
Pin Definitions and Functions (cont’d)
Pin Number
I/O1) Function
P-MQFP-80-1
ALE
48
O
The Address Latch Enable
output is used for latching the address into external
memory during normal operation. It is activated
every six oscillator periods, except during an
external data memory access. ALE can be switched
off when the program is executed internally.
EA
49
I
External Access Enable
When held high, the C515C executes instructions
always from the internal ROM. When held low, the
C515C fetches all instructions from external
program memory.
Note: For the ROM protection version EA pin is
latched during reset.
P0.0-P0.7
52-59
I/O
Port 0
is an 8-bit open-drain bidirectional I/O port.
Port 0 pins that have 1's written to them float, and in
that state can be used as high-impedance inputs.
Port 0 is also the multiplexed low-order address and
data bus during accesses to external program and
data memory. In this application it uses strong
internal pullup resistors when issuing 1's.
Port 0 also outputs the code bytes during program
verification in the C515C. External pullup resistors
are required during program verification.
P5.0-P5.7
67-60
I/O
Port 5
is an 8-bit quasi-bidirectional I/O port with internal
pullup resistors. Port 5 pins that have 1's written to
them are pulled high by the internal pullup resistors,
and in that state can be used as inputs. As inputs,
port 5 pins being externally pulled low will source
current (IIL, in the DC characteristics) because of
the internal pullup resistors.
Port 5 can also be switched into a bidirectional
mode, in which CMOS levels are provided. In this
bidirectional mode, each port 5 pin can be
programmed individually as input or output.
Data Sheet
10
2003-02
C515C
Table 2
Symbol
Pin Definitions and Functions (cont’d)
Pin Number
I/O1) Function
P-MQFP-80-1
HWPD
69
I
Hardware Power Down
A low level on this pin for the duration of one
machine cycle while the oscillator is running resets
the C515C.
A low level for a longer period will force the part to
power down mode with the pins floating.
P4.0-P4.7
72-74, 76-80
I/O
Port 4
is an 8-bit quasi-bidirectional I/O port with internal
pull-up resistors. Port 4 pins that have 1’s written to
them are pulled high by the internal pull-up resistors,
and in that state can be used as inputs. As inputs,
port 4 pins being externally pulled low will source
current (IIL, in the DC characteristics) because of
the internal pull-up resistors.
P4 also contains the external A/D converter control
pin, the SSC pins, the CAN controller input/output
lines, and the external interrupt 8 input. The output
latch corresponding to a secondary function must
be programmed to a one (1) for that function to
operate. The alternate functions are assigned to
port 4 as follows:
P4.0 ADST External A/D converter start pin
P4.1 SCLK SSC Master Clock Output /
SSC Slave Clock Input
P4.2 SRI
SSC Receive Input
P4.3 STO
SSC Transmit Output
P4.4 SLS
Slave Select Input
External interrupt 8 input
P4.5 INT8
P4.6 TXDC Transmitter output of the CAN
controller
P4.7 RXDC Receiver input of the CAN controller
72
73
74
76
77
78
79
80
Data Sheet
11
2003-02
C515C
Table 2
Symbol
Pin Definitions and Functions (cont’d)
Pin Number
I/O1) Function
P-MQFP-80-1
PE/SWD
75
I
Power saving mode enable / Start watchdog
timer
A low level on this pin allows the software to enter
the power down, idle and slow down mode. In case
the low level is also seen during reset, the watchdog
timer function is off on default.
Use of the software controlled power saving modes
is blocked, when this pin is held on high level. A high
level during reset performs an automatic start of the
watchdog timer immediately after reset. When left
unconnected this pin is pulled high by a weak
internal pull-up resistor.
VSSCLK
13
–
Ground (0 V) for on-chip oscillator
This pin is used for ground connection of the on-chip
oscillator circuit.
VDDCLK
14
–
Supply voltage for on-chip oscillator
This pin is used for power supply of the on-chip
oscillator circuit.
VDDE1
VDDE2
32
68
–
Supply voltage for I/O ports
These pins are used for power supply of the I/O
ports during normal, idle, and power down mode.
VSSE1
VSSE2
35
70
–
Ground (0 V) for I/O ports
These pins are used for ground connections of the
I/O ports during normal, idle, and power down
mode.
VDD1
33
–
Supply voltage for internal logic
This pins is used for the power supply of the internal
logic circuits during normal, idle, and power down
mode.
VSS1
34
–
Ground (0 V) for internal logic
This pin is used for the ground connection of the
internal logic circuits during normal, idle, and power
down mode.
Data Sheet
12
2003-02
C515C
Table 2
Symbol
Pin Definitions and Functions (cont’d)
Pin Number
I/O1) Function
P-MQFP-80-1
VDDEXT
50
–
Supply voltage for external access pins
This pin is used for power supply of the I/O ports and
control signals which are used during external
accesses (for Port 0, Port 2, ALE, PSEN, P3.6/WR,
and P3.7/RD).
VSSEXT
51
–
Ground (0 V) for external access pins
This pin is used for the ground connection of the I/O
ports and control signals which are used during
external accesses (for Port 0, Port 2, ALE, PSEN,
P3.6/WR, and P3.7/RD).
N.C.
2, 71
–
Not connected
These pins should not be connected.
1)
I = Input; O = Output
Data Sheet
13
2003-02
C515C
Oscillator Watchdog
XRAM
2k x 8
XTAL1
XTAL2
RAM
256 x 8
ROM/OTP
64k x 8
Multiple
V DD /V SS
Lines
OSC & Timing
ALE
CPU
PSEN
8 Datapointers
EA
CPUR
Emulation
Support
Logic
Programmable
Watchdog Timer
PE/SWD
HWPD
Timer 0
Port 0
Port 0
8 Bit Digital I/O
Port 1
Port 1
8 Bit Digital I/O
Capture
Compare Unit
Port 2
Port 2
8 Bit Digital I/O
USART
Port 3
Port 3
8 Bit Digital I/O
Port 4
Port 4
8 Bit Digital I/O
Port 5
Port 5
8 Bit Digital I/O
Port 6
Port 6
8 Bit Analog/
Digital Inputs
Port 7
Port 7
1 Bit Digital I/O
RESET
Timer 1
Timer 2
Baud Rate Generator
256 Byte
Reg./Data
SSC (SPI) Interface
Full-CAN
Controller
Interrupt Unit
V AREF
V AGND
A/D Converter
10 Bit
S&H
MUX
C515C
MCB03647
Figure 4
Data Sheet
Block Diagram of the C515C
14
2003-02
C515C
CPU
The C515C is efficient both as a controller and as an arithmetic processor. It has
extensive facilities for binary and BCD arithmetic and excels in its bit-handling
capabilities. Efficient use of program memory results from an instruction set consisting
of 44% one-byte, 41% two-byte, and 15% three-byte instructions. With a 6 MHz crystal,
58% of the instructions are executed in 1 µs (10 MHz: 600 ns).
PSW
Special Function Register
(D0H)
Reset Value: 00H
Bit No. MSB
D0H
LSB
D7H
D6H
D5H
D4H
D3H
D2H
D1H
D0H
CY
AC
F0
RS1
RS0
OV
F1
P
PSW
Bit
Function
CY
Carry Flag
Used by arithmetic instruction.
AC
Auxiliary Carry Flag
Used by instructions which execute BCD operations.
F0
General Purpose Flag
RS1
RS0
Register Bank select control bits
These bits are used to select one of the four register banks.
RS1
RS0
Function
0
0
Bank 0 selected, data address 00H-07H
0
1
Bank 1 selected, data address 08H-0FH
1
0
Bank 2 selected, data address 10H-17H
1
1
Bank 3 selected, data address 18H-1FH
OV
Overflow Flag
Used by arithmetic instruction.
F1
General Purpose Flag
P
Parity Flag
Set/cleared by hardware after each instruction to indicate an
odd/even number of “one” bits in the accumulator, i.e. even parity.
Data Sheet
15
2003-02
C515C
Memory Organization
The C515C CPU manipulates data and operands in the following five address spaces:
•
•
•
•
•
•
up to 64 Kbytes of internal/external program memory
up to 64 Kbytes of external data memory
256 bytes of internal data memory
256 bytes CAN controller registers / data memory
2 Kbytes of internal XRAM data memory
a 128 byte special function register area
Figure 5 illustrates the memory address spaces of the C515C.
Alternatively
FFFF H
FFFF H
Internal
XRAM
(2 KByte)
External
Data
Memory
F800 H
Internal
(EA = 1)
Int. CAN
Controller
(256 Byte)
F6FF H
External
(EA = 0)
F7FF H
F700 H
Indirect
Address
Direct
Address
FF H
Internal
RAM
80 H
External
Special
Function
Register
FF H
80 H
7F H
Internal
RAM
0000 H
0000 H
"Code Space"
"Data Space"
00 H
"Internal Data Space"
MCD02717
Figure 5
Data Sheet
C515C Memory Map
16
2003-02
C515C
Control of XRAM/CAN Controller Access
The XRAM in the C515C is a memory area that is logically located at the upper end of
the external memory space, but is integrated on the chip. Because the XRAM and the
CAN controller is used in the same way as external data memory the same instruction
types (MOVX) must be used for accessing the XRAM. Two bits in SFR SYSCON,
XMAP0 and XMAP1, control the accesses to the XRAM and the CAN controller.
SYSCON
Special Function Register
Bit No. MSB
7
B1H
–
6
(B1H)
5
PMOD EALE
4
3
RMAP
–
C515C-8R Reset Value: X010XX01B
C515C-8E Reset Value: X010X001B
2
1
LSB
0
CSWO XMAP1 XMAP0
SYSCON
The function of the shaded bits is not described in this section.
Bit
Function
XMAP1
XRAM/CAN controller visible access control
Control bit for RD/WR signals during XRAM/CAN Controller
accesses. If addresses are outside the XRAM/CAN controller
address range or if XRAM is disabled, this bit has no effect.
XMAP1 = 0: The signals RD and WR are not activated during
accesses to the XRAM/CAN Controller
XMAP1 = 1: Ports 0, 2 and the signals RD and WR are activated
during accesses to XRAM/CAN Controller. In this
mode, address and data information during
XRAM/CAN Controller accesses are visible externally.
XMAP0
Global XRAM/CAN controller access enable/disable control
XMAP0 = 0: The access to XRAM and CAN controller is enabled.
XMAP0 = 1: The access to XRAM and CAN controller is disabled
(default after reset). All MOVX accesses are
performed via the external bus. Further, this bit is
hardware protected.
Bit XMAP0 is hardware protected. If it is reset once (XRAM/CAN controller access
enabled) it cannot be set by software. Only a reset operation will set the XMAP0 bit
again.
Data Sheet
17
2003-02
C515C
The XRAM/CAN controller can be accessed by read/write instructions (MOVX A,DPTR,
MOVX @DPTR,A), which use the 16-bit DPTR for indirect addressing. For accessing the
XRAM or CAN controller, the effective address stored in DPTR must be in the range of
F700H to FFFFH.
The XRAM can be also accessed by read/write instructions (MOVX A,@Ri, MOVX
@Ri,A), which use only an 8-bit address (indirect addressing with registers R0 or R1).
Therefore, a special page register XPAGE which provides the upper address information
(A8-A15) during 8-bit XRAM accesses. The behaviour of Port 0 and P2 during a MOVX
access depends on the control bits XMAP0 and XMAP1 in register SYSCON and on the
state of pin EA. Table 3 lists the various operating conditions.
Data Sheet
18
2003-02
C515C
Table 3
Behaviour of P0/P2 and RD/WR During MOVX Accesses
XMAP1, XMAP0
EA = 0
MOVX
@DPTR
MOVX
@ Ri
EA = 1
MOVX
@DPTR
MOVX
@ Ri
00
10
X1
DPTR
<
XRAM/CAN
address range
a) P0/P2→Bus
b) RD/WR active
c) ext.memory
is used
a) P0/P2→Bus
b) RD/WR active
c) ext.memory
is used
a) P0/P2→Bus
b) RD/WR active
c) ext.memory
is used
DPTR
≥
XRAMCAN
address range
a) P0/P2→Bus
(RD/WR-Data)
b) RD/WR inactive
c) XRAM is used
a) P0/P2→Bus
(RD/WR-Data)
b) RD/WR active
c) XRAM is used
a) P0/P2→Bus
XPAGE
<
XRAMCAN
addr. page
range
a) P0→Bus
P2→I/O
b) RD/WR active
c) ext.memory
is used
a) P0→Bus
P2→I/O
b) RD/WR active
c) ext.memory
is used
a) P0→Bus
P2→I/O
b) RD/WR active
c) ext.memory
is used
XPAGE
≥
XRAMCAN
addr. page
range
a) P0→Bus
(RD/WR-Data)
P2→I/O
b) RD/WR inactive
c) XRAM is used
a) P0→Bus
(RD/WR-Data only)
P2→I/O
b) RD/WR active
c) XRAM is used
a) P0→Bus
P2→I/O
DPTR
<
XRAM/CAN
address range
a) P0/P2→Bus
b) RD/WR active
c) ext.memory
is used
a) P0/P2→Bus
b) RD/WR active
c) ext.memory
is used
a) P0/P2→Bus
b) RD/WR active
c) ext.memory
is used
DPTR
≥
XRAMCAN
address range
a) P0/P2→Ι/0
a) P0/P2→Bus
b) RD/WR inactive
c) XRAM is used
a) P0/P2→Bus
(RD/WR-Data)
b) RD/WR active
c) XRAM is used
XPAGE
<
XRAMCAN
addr. page
range
a) P0→Bus
P2→I/O
b) RD/WR active
c) ext.memory
is used
a) P0→Bus
P2→I/O
b) RD/WR active
c) ext.memory is
used
a) P0→Bus
P2→I/O
b) RD/WR active
c) ext.memory
is used
XPAGE
≥
XRAMCAN
addr. page
range
a) P2→I/O
P0/P2→I/O
a) P0→Bus
(RD/WR-Data)
P2→I/O
b) RD/WR active
c) XRAM is used
a) P0→Bus
P2→I/O
b) RD/WR inactive
c) XRAM is used
b) RD/WR active
c) ext.memory
is used
b) RD/WR active
c) ext.memory
is used
b) RD/WR active
c) ext.memory
is used
b) RD/WR active
c) ext.memory
is used
modes compatible to 8051/C501 family
Data Sheet
19
2003-02
C515C
Reset and System Clock
The reset input is an active low input at pin RESET. Since the reset is synchronized
internally, the RESET pin must be held low for at least two machine cycles (12 oscillator
periods) while the oscillator is running. A pullup resistor is internally connected to VDD to
allow a power-up reset with an external capacitor only. An automatic reset can be
obtained when VDD is applied by connecting the RESET pin to VSS via a capacitor.
Figure 6 shows the possible reset circuitries.
a)
b)
&
+
RESET
RESET
C515C
C515C
c)
+
RESET
C515C
Figure 6
MCS02721
Reset Circuitries
Figure 7 shows the recommended oscillator circiutries for crystal and external clock
operation.
Data Sheet
20
2003-02
C515C
Crystal/Resonator Oscillator Mode
Driving from External Source
C
N.C.
XTAL1
XTAL1
2 - 10 MHz
External Oscillator
Signal
C
XTAL2
Crystal Mode
: C = 20 pF ± 10 pF (incl. stray capacitance)
Resonator Mode : C = depends on selected ceramic resonator
Figure 7
XTAL2
MCT02765
Recommended Oscillator Circuitries
Multiple Datapointers
As a functional enhancement to the standard 8051 architecture, the C515C contains
eight 16-bit datapointers instead of only one datapointer. The instruction set uses just
one of these datapointers at a time. The selection of the actual datapointer is done in the
special function register DPSEL. Figure 8 illustrates the datapointer addressing
mechanism.
- - - - -
.2 .1 .0
DPSEL(92 H)
DPSEL
DPTR7
Selected
Data-
.2
.1
.0
pointer
0
0
0
DPTR 0
0
0
1
DPTR 1
0
1
0
DPTR 2
0
1
1
DPTR 3
1
0
0
DPTR 4
1
0
1
DPTR 5
1
1
0
DPTR 6
1
1
1
DPTR 7
Figure 8
Data Sheet
DPTR0
DPH(83 H )
DPL(82 H)
External Data Memory
MCD00779
External Data Memory Addressing using Multiple Datapointers
21
2003-02
C515C
Enhanced Hooks Emulation Concept
The Enhanced Hooks Emulation Concept of the C500 microcontroller family is a new,
innovative way to control the execution of C500 MCUs and to gain extensive information
on the internal operation of the controllers. Emulation of on-chip ROM based programs
is possible, too.
Each production chip has built-in logic for the support of the Enhanced Hooks Emulation
Concept. Therefore, no costly bond-out chips are necessary for emulation. This also
ensure that emulation and production chips are identical.
The Enhanced Hooks Technology, which requires embedded logic in the C500 allows
the C500 together with an EH-IC to function similar to a bond-out chip. This simplifies the
design and reduces costs of an ICE-system. ICE-systems using an EH-IC and a
compatible C500 are able to emulate all operating modes of the different versions of the
C500 microcontrollers. This includes emulation of ROM, ROM with code rollover and
ROMless modes of operation. It is also able to operate in single step mode and to read
the SFRs after a break.
ICE-System Interface
to Emulation Hardware
RESET
EA
ALE
PSEN
SYSCON
PCON
TCON
C500
MCU
RSYSCON
RPCON
RTCON
EH-IC
Enhanced Hooks
Interface Circuit
Port 0
Port 2
Optional
I/O Ports
Port 3
Port 1
RPort 2 RPort 0
Target System Interface
Figure 9
TEA TALE TPSEN
MCS03280
Basic C500 MCU Enhanced Hooks Concept Configuration
Port 0, port 2 and some of the control lines of the C500 based MCU are used by
Enhanced Hooks Emulation Concept to control the operation of the device during
emulation and to transfer informations about the program execution and data transfer
between the external emulation hardware (ICE-system) and the C500 MCU.
Data Sheet
22
2003-02
C515C
Special Function Registers
The registers, except the program counter and the four general purpose register banks,
reside in the special function register area. The special function register area consists of
two portions: the standard special function register area and the mapped special function
register area. Two special function registers of the C515C (PCON1 and DIR5) are
located in the mapped special function register area. For accessing the mapped special
function register area, bit RMAP in special function register SYSCON must be set. All
other special function registers are located in the standard special function register area
which is accessed when RMAP is cleared (“0”). As long as bit RMAP is set, mapped
special function register area can be accessed. This bit is not cleared by hardware
automatically. Thus, when non-mapped/mapped registers are to be accessed, the bit
RMAP must be cleared/set by software, respectively each.
SYSCON
Special Function Register
Bit No. MSB
7
B1H
–
6
(B1H)
5
PMOD EALE
4
3
RMAP
–
C515C-8R Reset Value: X010XX01B
C515C-8E Reset Value: X010X001B
2
1
LSB
0
CSWO XMAP1 XMAP0
SYSCON
The function of the shaded bits is not described in this section.
Bit
Function
RMAP
Special function register map bit
RMAP = 0: The access to the non-mapped (standard) special
function register area is enabled (reset value).
RMAP = 1: The access to the mapped special function register
area is enabled.
The 59 special function registers (SFRs) in the standard and mapped SFR area include
pointers and registers that provide an interface between the CPU and the other on-chip
peripherals. The SFRs of the C515C are listed in Table 4 and Table 5. In Table 4 they
are organized in groups which refer to the functional blocks of the C515C. The CANSFRs are also included in Table 4. Table 5 illustrates the contents of the SFRs in
numeric order of their addresses. Table 6 list the CAN-SFRs in numeric order of their
addresses.
Data Sheet
23
2003-02
C515C
Table 4
Special Function Registers - Functional Block
Block
Symbol
Name
Addr
Contents after
Reset
CPU
ACC
B
DPH
DPL
DPSEL
PSW
SP
SYSCON1)
Accumulator
B-Register
Data Pointer, High Byte
Data Pointer, Low Byte
Data Pointer Select Register
Program Status Word Register
Stack Pointer
System Control Register
C515C-8R
C515C-8E
E0H2)
F0H2)
83H
82H
92H
D0H2)
81H
B1H
B1H
00H
00H
00H
00H
XXXXX000B3)
00H
07H
X010XX01B3)
X010X001B3)
A/DConverter
ADCON01)
ADCON1
ADDATH
ADDATL
A/D Converter Control Register 0
A/D Converter Control Register 1
A/D Converter Data Register High Byte
A/D Converter Data Register Low Byte
D8H2)
DCH
D9H
DAH
00H
0XXXX000B3)
00H
00XXXXXXB3)
Interrupt
System
IEN01)
IEN11)
IEN2
IP01)
IP1
TCON1)
T2CON1)
SCON1)
IRCON
Interrupt Enable Register 0
Interrupt Enable Register 1
Interrupt Enable Register 2
Interrupt Priority Register 0
Interrupt Priority Register 1
Timer Control Register
Timer 2 Control Register
Serial Channel Control Register
Interrupt Request Control Register
A8H2)
B8H2)
9AH
A9H
B9H
88H2)
C8H2)
98H2)
C0H2)
00H
00H
XX00X00XB3)
00H
0X000000B3)
00H
00H
00H
00H
XRAM
XPAGE
91H
00H
SYSCON1)
Page Address Register for Extended
on-chip XRAM and CAN Controller
System Control Register
C515C-8R
C515C-8E
B1H
B1H
X010XX01B3)
X010X001B3)
P0
P1
P2
P3
P4
P5
DIR5
P6
P7
SYSCON1)
Port 0
Port 1
Port 2
Port 3
Port 4
Port 5
Port 5 Direction Register
Port 6, Analog/Digital Input
Port 7
System Control Register
80H2)
90H2)
A0H2)
B0H2)
E8H2)
F8H2)
F8H2)4)
DBH
FAH
B1H
FFH
FFH
FFH
FFH
FFH
FFH
FFH
–
XXXXXXX1B3)
X010XX01B3)
X010X001B3)
WDTREL
IEN01)
IEN11)
IP01)
Watchdog Timer Reload Register
Interrupt Enable Register 0
Interrupt Enable Register 1
Interrupt Priority Register 0
86H
A8H2)
B8H2)
A9H
00H
00H
00H
00H
Ports
Watchdog
Data Sheet
24
C515C-8R
C515C-8E
2003-02
C515C
Table 4
Special Function Registers - Functional Block (cont’d)
Block
Symbol
Name
Addr
Contents after
Reset
Serial
Channel
ADCON01)
PCON1)
SBUF
SCON
SRELL
SRELH
A/D Converter Control Register 0
Power Control Register
Serial Channel Buffer Register
Serial Channel Control Register
Serial Channel Reload Register, low byte
Serial Channel Reload Register, high byte
D8H2)
87H
99H
98H2)
AAH
BAH
00H
00H
XXH3)
00H
D9H
XXXXXX11B3)
CAN
Controller
CR
SR
IR
BTR0
BTR1
GMS0
GMS1
UGML0
UGML1
LGML0
LGML1
UMLM0
Control Register
Status Register
Interrupt Register
Bit Timing Register Low
Bit Timing Register High
Global Mask Short Register Low
Global Mask Short Register High
Upper Global Mask Long Register Low
Upper Global Mask Long Register High
Lower Global Mask Long Register Low
Lower Global Mask Long Register High
Upper Mask of Last Message Register
Low
Upper Mask of Last Message Register
High
Lower Mask of Last Message Register
Low
Lower Mask of Last Message Register
High
Message Object Registers:
Message Control Register Low
Message Control Register High
Upper Arbitration Register Low
Upper Arbitration Register High
Lower Arbitration Register Low
Lower Arbitration Register High
Message Configuration Register
Message Data Byte 0
Message Data Byte 1
Message Data Byte 2
Message Data Byte 3
Message Data Byte 4
Message Data Byte 5
Message Data Byte 6
Message Data Byte 7
F700H
F701H
F702H
F704H
F705H
F706H
F707H
F708H
F709H
F70AH
F70BH
F70CH
101H
XXH6)
XXH6)
UUH6)
0UUUUUUUB6)
UUH6)
UUU11111B6)
UUH6)
UUH6)
UUH6)
UUUUU000B6)
UUH6)
F70DH
UUH6)
F70EH
UUH6)
F70FH
UUUUU000B6)
F7n0H5)
F7n1H5)
F7n2H5)
F7n3H5)
F7n4H5)
F7n5H5)
F7n6H5)
F7n7H5)
F7n8H5)
F7n9H5)
F7nAH5)
F7nBH5)
F7nCH5)
F7nDH5)
F7nEH5)
UUH6)
UUH6)
UUH6)
UUH6)
UUH6)
UUUUU000B6)
UUUUUU00B6)
XXH6)
XXH6)
XXH6)
XXH6)
XXH6)
XXH6)
XXH6)
XXH6)
UMLM1
LMLM0
LMLM1
MCR0
MCR1
UAR0
UAR1
LAR0
LAR1
MCFG
DB0n
DB1n
DB2n
DB3n
DB4n
DB5n
DB6n
DB7n
Data Sheet
25
2003-02
C515C
Table 4
Special Function Registers - Functional Block (cont’d)
Block
Symbol
Name
Addr
Contents after
Reset
SSC
Interface
SSCCON
STB
SRB
SCF
SCIEN
SSCMOD
SSC Control Register
SSC Transmit Buffer
SSC Receive Register
SSC Flag Register
SSC Interrupt Enable Register
SSC Mode Test Register
93H2)
94H
95H
ABH2)
ACH
96H
07H
XXH3)
XXH3)
XXXXXX00B3)
XXXXXX00B3)
00H
Timer 0/
Timer 1
TCON
TH0
TH1
TL0
TL1
TMOD
Timer 0/1 Control Register
Timer 0, High Byte
Timer 1, High Byte
Timer 0, Low Byte
Timer 1, Low Byte
Timer Mode Register
88H2)
8CH
8DH
8AH
8BH
89H
00H
00H
00H
00H
00H
00H
Comp./Capture Enable Reg.
Comp./Capture Reg. 1, High Byte
Comp./Capture Reg. 2, High Byte
Comp./Capture Reg. 3, High Byte
Comp./Capture Reg. 1, Low Byte
Comp./Capture Reg. 2, Low Byte
Comp./Capture Reg. 3, Low Byte
Com./Rel./Capt. Reg. High Byte
Com./Rel./Capt. Reg. Low Byte
Timer 2, High Byte
Timer 2, Low Byte
Timer 2 Control Register
C1H
C3H
C5H
C7H
C2H
C4H
C6H
CBH
CAH
CDH
CCH
C8H2)
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
Compare/
CCEN
Capture Unit/ CCH1
Timer 2
CCH2
CCH3
CCL1
CCL2
CCL3
CRCH
CRCL
TH2
TL2
T2CON
Power Save
Modes
PCON1)
PCON1
Power Control Register
Power Control Register 1
87H
C515C-8R 88H7)
C515C-8E 88H7)
00H
0XXXXXXXB3)
0XX0XXXXB3)
1)
This special function register is listed repeatedly since some bits of it also belong to other functional blocks.
2)
Bit-addressable special function registers
3)
“X” means that the value is undefined and the location is reserved.
4)
This SFR is a mapped SFR. For accessing this SFR, bit PDIR in SFR IP1 must be set.
5)
The notation “n” in the message object address definition defines the number of the related message object.
6)
“X” means that the value is undefined and the location is reserved. “U” means that the value is unchanged by
a reset operation. “U” values are undefined (as “X”) after a power-on reset operation.
7)
SFR is located in the mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be set.
Data Sheet
26
2003-02
C515C
Table 5
Contents of the SFRs, SFRs in Numeric Order
of their Addresses
Addr. Register
Content Bit 7
after
Reset1)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
80H2)
P0
FFH
.7
.6
.5
.4
.3
.2
.1
.0
81H
SP
07H
.7
.6
.5
.4
.3
.2
.1
.0
82H
DPL
00H
.7
.6
.5
.4
.3
.2
.1
.0
83H
DPH
00H
.7
.6
.5
.4
.3
.2
.1
.0
86H
WDTREL
00H
WDT
PSEL
.6
.5
.4
.3
.2
.1
.0
87H
PCON
00H
SMOD
PDS
IDLS
SD
GF1
GF0
PDE
IDLE
88H2)
TCON
00H
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
88H3)
PCON14)
0XXXXXXXB
EWPD
–
–
–
–
–
–
–
88H3)
PCON15)
0XX0XXXXB
EWPD
–
–
WS
–
–
–
–
89H
TMOD
00H
GATE
C/T
M1
M0
GATE
C/T
M1
M0
8AH
TL0
00H
.7
.6
.5
.4
.3
.2
.1
.0
8BH
TL1
00H
.7
.6
.5
.4
.3
.2
.1
.0
8CH
TH0
00H
.7
.6
.5
.4
.3
.2
.1
.0
8DH
TH1
00H
.7
.6
.5
.4
.3
.2
.1
.0
90H2)
P1
FFH
T2
CLKOUT
T2EX
INT2
INT6
INT5
INT4
INT3
91H
XPAGE
00H
.7
.6
.5
.4
.3
.2
.1
.0
92H
DPSEL
XXXXX000B
–
–
–
–
–
.2
.1
.0
93H
SSCCON
07H
SCEN
TEN
MSTR CPOL
CPHA
BRS2
BRS1
BRS0
94H
STB
XXH
.7
.6
.5
.4
.3
.2
.1
.0
95H
SRB
XXH
.7
.6
.5
.4
.3
.2
.1
.0
96H
SSCMOD
00H
LOOPB TRIO
0
0
0
0
0
LSBSM
98H2)
SCON
00H
SM0
SM1
SM2
REN
TB8
RB8
TI
RI
99H
SBUF
XXH
.7
.6
.5
.4
.3
.2
.1
.0
9AH
IEN2
X00XX00XB
–
–
EX8
EX7
–
ESSC
ECAN
–
A0H2)
P2
FFH
.7
.6
.5
.4
.3
.2
.1
.0
A8H2)
IEN0
00H
EAL
WDT
ET2
ES
ET1
EX1
ET0
EX0
A9H
IP0
00H
OWDS
WDTS .5
.4
.3
.2
.1
.0
Data Sheet
27
2003-02
C515C
Table 5
Contents of the SFRs, SFRs in Numeric Order
of their Addresses (cont’d)
Addr. Register
Content Bit 7
after
Reset1)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
AAH
SRELL
D9H
.7
.6
.5
.4
.3
.2
.1
.0
ABH
SCF
XXXXXX00B
–
–
–
–
–
–
WCOL
TC
ACH
SCIEN
XXXXXX00B
–
–
–
–
–
–
WCEN
TCEN
B0H2)
P3
FFH
RD
WR
T1
T0
INT1
INT0
TxD
RxD
XMAP1 XMAP0
4)
B1H
SYSCON
X010XX01B
–
PMOD EALE
RMAP –
–
B1H
SYSCON5) X010X001B
–
PMOD EALE
RMAP –
CSWO XMAP1 XMAP0
B8H2)
IEN1
00H
EXEN2
SWDT EX6
EX5
EX4
EX3
EX2
EADC
B9H
IP1
0X000000B
PDIR
–
.5
.4
.3
.2
.1
.0
BAH
SRELH
XXXXXX11B
–
–
–
–
–
–
.1
.0
C0H2) IRCON
00H
EXF2
TF2
IEX6
IEX5
IEX4
IEX3
IEX2
IADC
C1H
CCEN
00H
COCA
H3
COCA
L3
COCA COCA COCA COCA
H2
L2
H1
L1
COCA
H0
COCA
L0
C2H
CCL1
00H
.7
.6
.5
.4
.3
.2
.1
.0
C3H
CCH1
00H
.7
.6
.5
.4
.3
.2
.1
.0
C4H
CCL2
00H
.7
.6
.5
.4
.3
.2
.1
.0
C5H
CCH2
00H
.7
.6
.5
.4
.3
.2
.1
.0
C6H
CCL3
00H
.7
.6
.5
.4
.3
.2
.1
.0
C7H
CCH3
00H
.7
.6
.5
.4
.3
.2
.1
.0
C8H2) T2CON
00H
T2PS
I3FR
I2FR
T2R1
T2R0
T2CM
T2I1
T2I0
CAH
CRCL
00H
.7
.6
.5
.4
.3
.2
.1
.0
CBH
CRCH
00H
.7
.6
.5
.4
.3
.2
.1
.0
CCH
TL2
00H
.7
.6
.5
.4
.3
.2
.1
.0
CDH
TH2
00H
.7
.6
.5
.4
.3
.2
.1
.0
Data Sheet
28
2003-02
C515C
Table 5
Contents of the SFRs, SFRs in Numeric Order
of their Addresses (cont’d)
Addr. Register
Content Bit 7
after
Reset1)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
D0H2) PSW
00H
CY
AC
F0
RS1
RS0
OV
F1
P
D8H2) ADCON0
00H
BD
CLK
ADEX
BSY
ADM
MX2
MX1
MX0
D9H
ADDATH
00H
.9
.8
.7
.6
.5
.4
.3
.2
DAH
ADDATL
00XXXXXXB
.1
.0
–
–
–
–
–
–
DBH
P6
–
.7
.6
.5
.4
.3
.2
.1
.0
DCH
ADCON1
0XXXX000B
ADCL
–
–
–
0
MX2
MX1
MX0
E0H2)
ACC
00H
.7
.6
.5
.4
.3
.2
.1
.0
E8H2)
P4
FFH
RXDC
TXDC
INT8
SLS
STO
SRI
SCLK
ADST
F0H2)
F8H2)
F8H2)
B
00H
.7
.6
.5
.4
.3
.2
.1
.0
P5
FFH
.7
.6
.5
.4
.3
.2
.1
.0
DIR56)
FFH
.7
.6
.5
.4
.3
.2
.1
.0
FAH
P7
XXXXXXX1B
–
–
–
–
–
–
–
INT7
FCH
VR07)8)
C5H
1
1
0
0
0
1
0
1
FDH
VR17)8)
95H
1
0
0
1
0
1
0
1
FEH
VR27)8)
0
0
0
0
0
0
1
0
02H
9)
1)
“X” means that the value is undefined and the location is reserved.
2)
Bit-addressable special function registers
3)
SFR is located in the mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be set.
4)
This SFR is available in the C515C-8R and C515C-L.
5)
This SFR is available in the C515C-8E.
6)
This SFR is a mapped SFR. For accessing this SFR, bit PDIR in SFR IP1 must be set.
7)
This SFR is a mapped SFR. For accessing this SFR, bit RMAP in SFR SYSCON must be set.
8)
These SFRs are read-only registers (C515C-8E only).
9)
The content of this SFR varies with the actual step of the C515C-8E (e.g. 01H for the first step).
Data Sheet
29
2003-02
C515C
Table 6
Contents of the CAN Registers in Numeric Order
of their Addresses
Addr.
Regis1)
n = 1 to FH
ter
Content Bit 7
after
Reset2)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
EIE
SIE
IE
INIT
RXOK
TXOK
LEC2
LEC1
LEC0
F700H
CR
01H
TEST
CCE
F701H
SR
XXH
BOFF
EWRN –
F702H
IR
XXH
F704H
BTR0
UUH
F705H
BTR1
0UUU.
UUUUB
F706H
GMS0
UUH
F707H
GMS1
UUU1.
1111B
F708H
ID28-21
F709H
UGML0 UUH
UGML1 UUH
F70AH
LGML0
UUH
ID12-5
F70BH
LGML1
UUUU.
U000B
F70CH
F70DH
UMLM0 UUH
UMLM1 UUH
F70EH
LMLM0
UUH
F70FH
LMLM1
UUUU.
U000B
F7n0H
MCR0
UUH
MSGVAL
TXIE
RXIE
INTPND
F7n1H
MCR1
UUH
RMTPND
TXRQ
MSGLST
CPUUPD
NEWDAT
F7n2H
UAR0
UUH
F7n3H
UAR1
UUH
F7n4H
LAR0
UUH
F7n5H
LAR1
UUUU.
U000B
F7n6H
MCFG
UUUU.
UU00B
F7n7H
DB0n
XXH
.7
.6
.5
F7n8H
DB1n
XXH
.7
.6
F7n9H
DB2n
XXH
.7
F7nAH
DB3n
XXH
F7nBH
DB4n
XXH
Data Sheet
INTID
SJW
BRP
0
TSEG2
TSEG1
ID28-21
ID20-18
1
1
1
1
1
0
0
0
0
0
ID20-13
ID4-0
ID28-21
ID20-18
ID17-13
ID12-5
ID4-0
0
ID28-21
ID20-18
ID17-13
ID12-5
ID4-0
0
0
0
DIR
XTD
0
0
.4
.3
.2
.1
.0
.5
.4
.3
.2
.1
.0
.6
.5
.4
.3
.2
.1
.0
.7
.6
.5
.4
.3
.2
.1
.0
.7
.6
.5
.4
.3
.2
.1
.0
DLC
30
2003-02
C515C
Table 6
Contents of the CAN Registers in Numeric Order
of their Addresses (cont’d)
Addr.
Regis1)
n = 1 to FH
ter
Content Bit 7
after
Reset2)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
F7nCH
DB5n
XXH
.7
.6
.5
.4
.3
.2
.1
.0
F7nDH
DB6n
XXH
.7
.6
.5
.4
.3
.2
.1
.0
F7nEH
DB7n
XXH
.7
.6
.5
.4
.3
.2
.1
.0
1)
The notation “n” in the address definition defines the number of the related message object.
2)
“X” means that the value is undefined and the location is reserved. “U” means that the value is
unchanged by a reset operation. “U” values are undefined (as “X”) after a power-on reset operation.
Data Sheet
31
2003-02
C515C
Digital I/O Ports
The C515C allows for digital I/O on 49 lines grouped into 6 bidirectional 8-bit ports and
one 1-bit port. Each port bit consists of a latch, an output driver and an input buffer. Read
and write accesses to the I/O ports P0 through P7 are performed via their corresponding
special function registers P0 to P7. The port structure of port 5 of the C515C is especially
designed to operate either as a quasi-bidirectional port structure, compatible to the
standard 8051-Family, or as a genuine bidirectional port structure. This port operating
mode can be selected by software (setting or clearing the bit PMOD in the SFR
SYSCON).
The output drivers of port 0 and 2 and the input buffers of port 0 are also used for
accessing external memory. In this application, port 0 outputs the low byte of the external
memory address, time-multiplexed with the byte being written or read. Port 2 outputs the
high byte of the external memory address when the address is 16 bits wide. Otherwise,
the port 2 pins continue emitting the P2 SFR contents.
Analog Input Ports
Ports 6 is available as input port only and provides two functions. When used as digital
inputs, the corresponding SFR P6 contains the digital value applied to the port 6 lines.
When used for analog inputs the desired analog channel is selected by a three-bit field
in SFR ADCON0 or SFR ADCON1. Of course, it makes no sense to output a value to
these input-only ports by writing to the SFR P6. This will have no effect.
If a digital value is to be read, the voltage levels are to be held within the input voltage
specifications (VIL/VIH). Since P6 is not bit-addressable, all input lines of P6 are read at
the same time by byte instructions.
Nevertheless, it is possible to use port 6 simultaneously for analog and digital input.
However, care must be taken that all bits of P6 that have an undetermined value caused
by their analog function are masked.
Data Sheet
32
2003-02
C515C
Port Structure Selection of Port 5
After a reset operation of the C515C, the quasi-bidirectional 8051-compatible port
structure is selected. For selection of the bidirectional (CMOS) port 5 structure the bit
PMOD of SFR SYSCON must be set. Because each port 5 pin can be programmed as
an input or an output, additionally, after the selection of the bidirectional mode the
direction register DIR5 of port 5 must be written. This direction register is mapped to the
port 5 register. This means, the port register address is equal to its direction register
address. Figure 10 illustrates the port and direction register configuration.
Write to Port
Int. Bus, Bit 7
D
Enable
Q
Internal
Bus
Port Register
PDIR
Write to IP 1
R
Q
Delay:
2.5 Machine Cycles
Enable
Direction Register
Read Port
Instruction sequence for the programming of the direction registers:
ORL IP1, #80H ; Set bit PDIR
MOV DIRx, #OYYH ; Write port x direction register with value YYH
Figure 10
Data Sheet
MCS02649
Port Register, Direction Register
33
2003-02
C515C
Timer / Counter 0 and 1
Timer / Counter 0 and 1 can be used in four operating modes as listed in Table 7:
Table 7
Mode
Timer/Counter 0 and 1 Operating Modes
Description
TMOD
Timer/Counter Input Clock
M1
M0
internal
external (max)
0
8-bit timer/counter with a
divide-by-32 prescaler
0
0
fOSC/6 × 32
fOSC/12 × 32
1
16-bit timer/counter
0
1
fOSC/6
fOSC/12
2
8-bit timer/counter with 8-bit 1
autoreload
0
3
Timer/counter 0 used as
one 8-bit timer/counter and
one 8-bit timer / Timer 1
stops
1
1
In the “timer” function (C/T = ‘0’) the register is incremented every machine cycle.
Therefore the count rate is fOSC/6.
In the “counter” function the register is incremented in response to a 1-to-0 transition at
its corresponding external input pin (P3.4/T0, P3.5/T1). Since it takes two machine
cycles to detect a falling edge the max. count rate is fOSC/12. External inputs INT0 and
INT1 (P3.2, P3.3) can be programmed to function as a gate to facilitate pulse width
measurements. Figure 11 illustrates the input clock logic.
OSC
÷6
f OSC /6
C/T = 0
Timer 0/1
Input Clock
C/T = 1
P3.4/T0
P3.5/T1
Gate
(TMOD)
Control
TR0
TR1
=1
&
<_ 1
P3.2/INT0
P3.3/INT1
Figure 11
Data Sheet
MCS03117
Timer/Counter 0 and 1 Input Clock Logic
34
2003-02
C515C
Timer / Counter 2 with Compare/Capture/Reload
The timer 2 of the C515C provides additional compare/capture/reload features, which
allow the selection of the following operating modes:
• Compare: up to 4 PWM signals with 16-bit/600 ns resolution
• Capture: up to 4 high speed capture inputs with 600 ns resolution
• Reload: modulation of timer 2 cycle time
The block diagram in Figure 12 shows the general configuration of timer 2 with the
additional compare/capture/reload registers. The I/O pins which can used for timer 2
control are located as multifunctional port functions at port 1.
P1.5/
T2EX
Sync.
P1.7/
T2
Sync.
EXF2
T2I0
T2I1
<_ 1
Interrupt
Request
EXEN2
&
Reload
÷6
OSC
Reload
f OSC
÷12
Timer 2
TL2 TH2
T2PS
TF2
Compare
16 Bit
Comparator
16 Bit
Comparator
16 Bit
Comparator
P1.0/
INT3/
CC0
16 Bit
Comparator
Capture
CCL3/CCH3
CCL2/CCH2
CCL1/CCH1
CRCL/CRCH
Input/
Output
Control
P1.1/
INT4/
CC1
P1.2/
INT5/
CC2
P1.2/
INT6/
CC3
MCB02730
Figure 12
Data Sheet
Timer 2 Block Diagram
35
2003-02
C515C
Timer 2 Operating Modes
The timer 2, which is a 16-bit-wide register, can operate as timer, event counter, or gated
timer. A roll-over of the count value in TL2/TH2 from all 1’s to all 0’s sets the timer
overflow flag TF2 in SFR IRCON, which can generate an interrupt. The bits in register
T2CON are used to control the timer 2 operation.
Timer Mode: In timer function, the count rate is derived from the oscillator frequency. A
prescaler offers the possibility of selecting a count rate of 1/6 or 1/12 of the oscillator
frequency.
Gated Timer Mode: In gated timer function, the external input pin T2 (P1.7) functions as
a gate to the input of timer 2. If T2 is high, the internal clock input is gated to the timer.
T2 = 0 stops the counting procedure. This facilitates pulse width measurements. The
external gate signal is sampled once every machine cycle.
Event Counter Mode: In the event counter function. the timer 2 is incremented in
response to a 1-to-0 transition at its corresponding external input pin T2 (P1.7). In this
function, the external input is sampled every machine cycle. Since it takes two machine
cycles (12 oscillator periods) to recognize a 1-to-0 transition, the maximum count rate is
1/12 of the oscillator frequency. There are no restrictions on the duty cycle of the external
input signal, but to ensure that a given level is sampled at least once before it changes,
it must be held for at least one full machine cycle.
Reload of Timer 2: Two reload modes are selectable:
In mode 0, when timer 2 rolls over from all 1’s to all 0’s, it not only sets TF2 but also
causes the timer 2 registers to be loaded with the 16-bit value in the CRC register, which
is preset by software.
In mode 1, a 16-bit reload from the CRC register is caused by a negative transition at the
corresponding input pin P1.5/T2EX. This transition will also set flag EXF2 if bit EXEN2
in SFR IEN1 has been set.
Data Sheet
36
2003-02
C515C
Timer 2 Compare Modes
The compare function of a timer/register combination operates as follows: the 16-bit
value stored in a compare or compare/capture register is compared with the contents of
the timer register; if the count value in the timer register matches the stored value, an
appropriate output signal is generated at a corresponding port pin and an interrupt can
be generated.
Compare Mode 0
In compare mode 0, upon matching the timer and compare register contents, the output
signal changes from low to high. lt goes back to a low level on timer overflow. As long as
compare mode 0 is enabled, the appropriate output pin is controlled by the timer circuit
only and writing to the port will have no effect. Figure 13 shows a functional diagram of
a port circuit when used in compare mode 0. The port latch is directly controlled by the
timer overflow and compare match signals. The input line from the internal bus and the
write-to-latch line of the port latch are disconnected when compare mode 0 is enabled.
Port Circuit
Read Latch
VDD
Compare Register
Circuit
Compare Reg.
16 Bit
Comparator
16 Bit
Compare
Match
S
D
Q
Port
Latch
CLK
Q
R
Internal
Bus
Write to
Latch
Port
Pin
Timer Register
Timer Circuit
Timer
Overflow
Read Pin
MCS02661
Figure 13
Data Sheet
Port Latch in Compare Mode 0
37
2003-02
C515C
Compare Mode 1
If compare mode 1 is enabled and the software writes to the appropriate output latch at
the port, the new value will not appear at the output pin until the next compare match
occurs. Thus, it can be choosen whether the output signal has to make a new transition
(1-to-0 or 0-to-1, depending on the actual pin-level) or should keep its old value at the
time when the timer value matches the stored compare value.
In compare mode 1 (see Figure 14) the port circuit consists of two separate latches. One
latch (which acts as a “shadow latch”) can be written under software control, but its value
will only be transferred to the port latch (and thus to the port pin) when a compare match
occurs.
Port Circuit
Read Latch
VDD
Compare Register
Circuit
Compare Reg.
Internal
Bus
16 Bit
Comparator
16 Bit
Compare
Match
D
Q
Shadow
Latch
CLK
Write to
Latch
D
Q
Port
Latch
CLK
Q
Port
Pin
Timer Register
Timer Circuit
Read Pin
MCS02662
Figure 14
Data Sheet
Compare Function in Compare Mode 1
38
2003-02
C515C
Serial Interface (USART)
The serial port is full duplex and can operate in four modes (one synchronous mode,
three asynchronous modes) as illustrated in Table 8.
Table 8
Mode
USART Operating Modes
SCON
Description
SM0
SM1
0
0
0
Shift register mode, fixed baud rate
Serial data enters and exits through R×D; T×D outputs
the shift clock; 8-bit are transmitted/received (LSB first)
1
0
1
8-bit UART, variable baud rate
10 bits are transmitted (through T×D) or received (at
R×D)
2
1
0
9-bit UART, fixed baud rate
11 bits are transmitted (through T×D) or received (at
R×D)
3
1
1
9-bit UART, variable baud rate
Like mode 2
For clarification some terms regarding the difference between “baud rate clock” and
“baud rate” should be mentioned. In the asynchronous modes the serial interfaces
require a clock rate which is 16 times the baud rate for internal synchronization.
Therefore, the baud rate generators/timers have to provide a “baud rate clock” (output
signal in Figure 15 to the serial interface which - there divided by 16 - results in the
actual “baud rate”. Further, the abbreviation fOSC refers to the oscillator frequency
(crystal or external clock operation).
The variable baud rates for modes 1 and 3 of the serial interface can be derived either
from timer 1 or from a dedicated baud rate generator (see Figure 15).
Data Sheet
39
2003-02
C515C
Timer 1
Overflow
f OSC
ADCON0.7
(BD)
Baud
Rate
Generator
Mode 1
Mode 3
0
1
SCON.7
SCON.6
(SM0/
SM1)
PCON.7
(SMOD)
÷2
0
1
(SRELH
SRELL)
Baud
Rate
Clock
Mode 2
Only one mode
can be selected
Mode 0
÷6
Note: The switch configuration shows the reset state.
Figure 15
MCS02733
Block Diagram of Baud Rate Generation for the Serial Interface
Table 9 below lists the values/formulas for the baud rate calculation of the serial
interface with its dependencies of the control bits BD and SMOD.
Table 9
Serial Interface - Baud Rate Dependencies
Serial Interface
Operating Modes
Active Control
Bits
Baud Rate Calculation
BD
SMOD
Mode 0 (Shift
Register)
–
–
fOSC / 6
Mode 1 (8-bit UART)
Mode 3 (9-bit UART)
0
X
Controlled by timer 1 overflow:
(2SMOD × timer 1 overflow rate) / 32
1
X
Controlled by baud rate generator
(2SMOD × fOSC) /
(32 × baud rate generator overflow rate)
–
0
1
fOSC / 32
fOSC / 16
Mode 2 (9-bit UART)
Data Sheet
40
2003-02
C515C
SSC Interface
The C515C microcontroller provides a Synchronous Serial Channel unit, the SSC. This
interface is compatible to the popular SPI serial bus interface. Figure 16 shows the block
diagram of the SSC. The central element of the SSC is an 8-bit shift register. The input
and the output of this shift register are each connected via a control logic to the pin P4.2
/ SRI (SSC Receiver In) and P4.3 / STO (SSC Transmitter Out). This shift register can
be written to (SFR STB) and can be read through the Receive Buffer Register SRB.
P4.1/SCLK
f OSC
P4.2/SRI
Clock Divider
STB
Pin
Control
Logic
P4.3/STO
Shift Register
Clock Selection
SRB
Receive Buffer Register
P4.4/SLS
Interrupt
SCIEN
Int. Enable Reg.
Control Logic
SSCCON
Control Register
SCF
Status Register
Internal Bus
Figure 16
MCB02735
SSC Block Diagram
The SSC has implemented a clock control circuit, which can generate the clock via a
baud rate generator in the master mode, or receive the transfer clock in the slave mode.
The clock signal is fully programmable for clock polarity and phase. The pin used for the
clock signal is P4.1 / SCLK. When operating in slave mode, a slave select input is
provided which enables the SSC interface and also will control the transmitter output.
The pin used for this is P4.4 / SLS.
The SSC control block is responsible for controlling the different modes and operation of
the SSC, checking the status, and generating the respective status and interrupt signals.
Data Sheet
41
2003-02
C515C
CAN Controller
The on-chip CAN controller is the functional heart which provides all resources that are
required to run the standard CAN protocol (11-bit identifiers) as well as the extended
CAN protocol (29-bit identifiers). It provides a sophisticated object layer to relieve the
CPU of as much overhead as possible when controlling many different message objects
(up to 15). This includes bus arbitration, resending of garbled messages, error handling,
interrupt generation, etc. In order to implement the physical layer, external components
have to be connected to the C515C.
The internal bus interface connects the on-chip CAN controller to the internal bus of the
microcontroller. The registers and data locations of the CAN interface are mapped to a
specific 256 bytes wide address range of the external data memory area (F700H to
F7FFH) and can be accessed using MOVX instructions. Figure 17 shows a block
diagram of the on-chip CAN controller.
Data Sheet
42
2003-02
C515C
TXDC
RXDC
BTL-Configuration
CRC
Gen./Check
Bit
Timing
Logic
Timing
Generator
TX/RX Shift Register
Messages
Messages
Handlers
Clocks
(to all)
Control
Intelligent
Memory
Interrupt
Register
Status +
Control
Bit
Stream
Processor
Error
Management
Logic
Status
Register
to internal Bus
Figure 17
MCB02736
CAN Controller Block Diagram
The TX/RX Shift Register holds the destuffed bit stream from the bus line to allow the
parallel access to the whole data or remote frame for the acceptance match test and the
parallel transfer of the frame to and from the Intelligent Memory.
The Bit Stream Processor (BSP) is a sequencer controlling the sequential data stream
between the TX/RX Shift Register, the CRC Register, and the bus line. The BSP also
controls the EML and the parallel data stream between the TX/RX Shift Register and the
Intelligent Memory such that the processes of reception, arbitration, transmission, and
error signalling are performed according to the CAN protocol. Note that the automatic
retransmission of messages which have been corrupted by noise or other external error
conditions on the bus line is handled by the BSP.
Data Sheet
43
2003-02
C515C
The Cyclic Redundancy Check Register (CRC) generates the Cyclic Redundancy
Check code to be transmitted after the data bytes and checks the CRC code of incoming
messages. This is done by dividing the data stream by the code generator polynomial.
The Error Management Logic (EML) is responsible for the fault confinement of the
CAN device. Its counters, the Receive Error Counter and the Transmit Error Counter, are
incremented and decremented by commands from the Bit Stream Processor. According
to the values of the error counters, the CAN controller is set into the states error active,
error passive and busoff.
The Bit Timing Logic (BTL) monitors the busline input RXDC and handles the busline
related bit timing according to the CAN protocol. The BTL synchronizes on a recessive
to dominant busline transition at Start of Frame (hard synchronization) and on any further
recessive to dominant busline transition, if the CAN controller itself does not transmit a
dominant bit (resynchronization). The BTL also provides programmable time segments
to compensate for the propagation delay time and for phase shifts and to define the
position of the Sample Point in the bit time. The programming of the BTL depends on the
baudrate and on external physical delay times.
The Intelligent Memory (CAM/RAM array) provides storage for up to 15 message
objects of maximum 8 data bytes length. Each of these objects has a unique identifier
and its own set of control and status bits. After the initial configuration, the Intelligent
Memory can handle the reception and transmission of data without further CPU actions.
Switch-off Capability of the CAN Controller (C515C-8E only)
For power consumption reasons, the on-chip CAN controller in the C515C-8E can be
switched off by setting bit CSWO (bit 2) in SFR SYSCON. When the CAN controller is
switched off its clock signal is turned off and the operation of the CAN controller is
stopped. This switch-off state of the CAN controller is equal to its state in software power
down mode. After clearing bit CSWO again the CAN controller has to be reconfigured.
Data Sheet
44
2003-02
C515C
10-Bit A/D Converter
The C515C includes a high performance / high speed 10-bit A/D-Converter (ADC) with
8 analog input channels. It operates with a successive approximation technique and
uses self calibration mechanisms for reduction and compensation of offset and linearity
errors. The A/D converter provides the following features:
•
•
•
•
•
•
•
8 multiplexed input channels (port 6), which can also be used as digital inputs
10-bit resolution
Single or continuous conversion mode
Internal or external start-of-conversion trigger capability
Interrupt request generation after each conversion
Using successive approximation conversion technique via a capacitor array
Built-in hidden calibration of offset and linearity errors
The main functional blocks of the A/D converter are shown in Figure 19.
The A/D converter uses basically two clock signals for operation: the input clock fIN
(= 1/tIN) and the conversion clock fADC (= 1/tADC). These clock signals are derived from
the C515C system clock fOSC which is applied at the XTAL pins. The input clock fIN is
equal to fOSC. The conversion clock is limited to a maximum frequency of 2 MHz and
therefore must be adapted to fOSC by programming the conversion clock prescaler. The
table in Figure 18 shows the prescaler ratios and the resulting A/D conversion times
which must be selected for typical system clock rates.
Data Sheet
45
2003-02
C515C
ADCL
f OSC
÷4
Conversion Clock f ADC
MUX
÷8
A/D
Converter
Clock Prescaler
Conditions:
Figure 18
Data Sheet
Input Clock f IN
f ADC max <_ 2 MHz
f IN = f OSC =
1
CLP
MCU System
Clock Rate
(fOSC)
ADCL
Conversion
Clock
fADC [MHz]
2 MHz
0
.5
4 MHz
0
1
6 MHz
0
1.5
8 MHz
0
2
10 MHz
1
1.25
MCS02748
A/D Converter Clock Selection
46
2003-02
C515C
Internal
Bus
IEN1 (B8 H)
EXEN2 SWDT
EX6
EX5
EX4
EX3
EX2
EADC
TF2
IEX6
IEX5
IEX4
IEX3
IEX2
IADC
P6.6
P6.5
P6.4
P6.3
P6.2
P6.1
P6.0
-
-
-
MX2
MX1
MX0
ADEX
BSY
ADM
MX2
MX1
MX0
IRCON (C0 H)
EXF2
P6 (DB H )
P6.7
ADCON1 (DC H )
ADCL
-
ADCON0 (D8 H)
BD
CLK
Single/
Continuous
Mode
Port 6
MUX
S&H
A/D
Converter
Conversion
Clock
Prescaler
f OSC
Conversion
Clock f ADC
Input
Clock f IN
VAREF
VAGND
P4.0/ADST
Write to
ADDATL
Start of
Conversion
Internal
Bus
Shaded bit locations are not used in ADC-functions.
Figure 19
Data Sheet
ADDATH ADDATL
(D9H ) (DA H)
.2
.3
.4
.5
.6
.7
LSB
.8
.1
MSB
MCB02747
A/D Converter Block Diagram
47
2003-02
C515C
Interrupt System
The C515C provides 17 interrupt sources with four priority levels. Seven interrupts can
be generated by the on-chip peripherals (timer 0, timer 1, timer 2, serial interface,
A/D converter, SSC interface, CAN controller), and ten interrupts may be triggered
externally (P1.5/T2EX, P3.2/INT0, P3.3/INT1, P1.4/INT2, P1.0/INT3, P1.1/INT4,
P1.2/INT5, P1.3/INT6, P7.0/INT7, P4.5/INT8). The wake-up from power-down mode
interrupt has a special functionality which allows to exit from the software power-down
mode by a short low pulse at pin P3.2/INT0.
In the C515C the 17 interrupt sources are combined to six groups of two or three interrupt
sources. Each interrupt group can be programmed to one of the four interrupt priority
levels. Figure 20 to Figure 22 give a general overview of the interrupt sources and
illustrate the interrupt request and control flags.
Data Sheet
48
2003-02
C515C
Highest
Priority Level
P3.2/
INT0
IE0
TCON.1
IT0
TCON.0
A/D Converter
IADC
IRCON.0
Timer 0
Overflow
TF0
TCON.5
EX0
IEN0.0
0003 H
EADC
IEN1.0
0043 H
Lowest
Priority Level
ET0
IEN0.1
000B H
ECAN
IEN2.1
008B H
EX2
IEN1.1
004B H
IP1.0
IP0.0
IP1.1
IP0.1
SIE
CR.2
Polling Sequence
CAN Controller Interrupt Sources
Status
<_1
IE
CR.1
Error
EIE
CR.3
Message
Transmit
Message
Receive
see Note
TXIE
MCR0.3/2
<_ 1
INTPND
MCR0.0/1
RXIE
MCR0.5/4
P1.4/
INT2
I2FR
T2CON.5
Bit addressable
IEX2
IRCON.1
EAL
IEN0.7
MCS02752
Request Flag is
cleared by hardware
Note: Each of the 15 CAN controller message objects provides the bits/flags in the shaded area.
Figure 20
Data Sheet
Interrupt Request Sources (Part 1)
49
2003-02
C515C
Highest
Priority Level
IE1
TCON.3
IT1
TCON.2
SSC
Inerface
WCOL
SCF.1
TC
SCF.0
P1.0/
INT3/
CC0
WCEN
SCIEN.1
Timer 1
Overflow
ESSC
IEN2.2
IEX3
IRCON.2
TF1
TCON.7
P1.1/
INT4/
CC1
IEX4
IRCON.3
Bit addressable
0013 H
Lowest
Priority Level
<_ 1
TCEN
SCIEN.0
I3FR
T2CON.6
EX1
IEN0.2
EX3
IEN1.2
ET1
IEN0.3
EX4
IEN1.3
0093 H
0053 H
Data Sheet
IP0.2
IP1.3
IP0.3
001B H
005B H
EAL
IEN0.7
Request Flag is
cleared by hardware
Figure 21
IP1.2
Polling Sequence
P3.3/
INT1
MCS02753
Interrupt Request Sources (Part 2)
50
2003-02
C515C
USART
Highest
Priority Level
<_ 1
TI
SCON.1
0023 H
ES
IEN0.4
Lowest
Priority Level
P7.0/
INT7
00A3 H
EX7
IEN2.4
P1.2/
INT5/
CC2
IEX5
IRCON.4
Timer 2
Overflow
TF2
IRCON.6
P1.5/
T2EX
EXEN2
IEN1.7
P4.5/
INT8
0063 H
EX5
IEN1.4
IEX6
IRCON.5
IP0.5
00AB H
006B H
EX6
IEN1.5
EAL
IEN0.7
Bit addressable
Request Flag is
cleared by hardware
Data Sheet
IP1.5
002B H
ET2
IEN0.5
EX8
IEN2.5
Figure 22
IP0.4
<_ 1
EXF2
IRCON.7
P1.3/
INT6/
CC3
IP1.4
Polling Sequence
RI
SCON.0
MCS02754
Interrupt Request Sources (Part 3)
51
2003-02
C515C
Table 10
Interrupt Source and Vectors
Interrupt Source
Interrupt Vector
Address
Interrupt Request Flags
External Interrupt 0
0003H
IE0
Timer 0 Overflow
000BH
TF0
External Interrupt 1
0013H
IE1
Timer 1 Overflow
001BH
TF1
Serial Channel
0023H
RI / TI
Timer 2 Overflow / Ext. Reload 002BH
TF2 / EXF2
A/D Converter
0043H
IADC
External Interrupt 2
004BH
IEX2
External Interrupt 3
0053H
IEX3
External Interrupt 4
005BH
IEX4
External Interrupt 5
0063H
IEX5
External Interrupt 6
006BH
IEX6
Wake-up from power-down
mode
007BH
–
CAN controller
008BH
–
External Interrupt 7
00A3H
–
External Interrupt 8
00ABH
–
SSC interface
0093H
TC / WCOL
Data Sheet
52
2003-02
C515C
Fail Save Mechanisms
The C515C offers two on-chip peripherals which monitor the program flow and ensure
an automatic “fail-safe” reaction for cases where the controller’s hardware fails or the
software hangs up:
• A programmable watchdog timer (WDT) with variable time-out period from
512 microseconds up to approx. 1.1 seconds at 6 MHz.
• An oscillator watchdog (OWD) which monitors the on-chip oscillator and forces the
microcontroller into reset state in case the on-chip oscillator fails; it also provides the
clock for a fast internal reset after power-on.
Programmable Watchdog Timer
The watchdog timer in the C515C is a 15-bit timer, which is incremented by a count rate
of fOSC/12 up to fOSC/192. For programming of the watchdog timer overflow rate, the
upper 7 bit of the watchdog timer can be written. Figure 23 shows the block diagram of
the watchdog timer unit.
0
f OSC /6
÷2
7
÷16
WDTL
14
8
WDT Reset Request
WDTH
IP0 (A9 H)
-
WDTS
-
-
-
-
-
-
External HW Reset
WDTPSEL
External HW Power-Down
PE/SWD
Control Logic
7 6
-
WDT
-
-
-
-
-
-
IEN0 (A8 H)
-
SWDT
-
-
-
-
-
-
IEN1 (B8 H)
0
WDTREL (86 H)
MCB02755
Figure 23
Block Diagram of the Programmable Watchdog Timer
The watchdog timer can be started by software (bit SWDT) or by hardware through pin
PE/SWD, but it cannot be stopped during active mode of the C515C. If the software fails
to refresh the running watchdog timer an internal reset will be initiated on watchdog timer
overflow. For refreshing of the watchdog timer the content of the SFR WDTREL is
transferred to the upper 7-bit of the watchdog timer. The refresh sequence consists of
Data Sheet
53
2003-02
C515C
two consecutive instructions which set the bits WDT and SWDT each. The reset cause
(external reset or reset caused by the watchdog) can be examined by software (flag
WDTS). It must be noted, however, that the watchdog timer is halted during the idle
mode and power down mode of the processor.
Oscillator Watchdog
The oscillator watchdog unit serves for four functions:
• Monitoring of the on-chip oscillator’s function
The watchdog supervises the on-chip oscillator's frequency; if it is lower than the
frequency of the auxiliary RC oscillator in the watchdog unit, the internal clock is
supplied by the RC oscillator and the device is brought into reset; if the failure
condition disappears (i.e. the on-chip oscillator has a higher frequency than the RC
oscillator), the part executes a final reset phase of typ. 1 ms in order to allow the
oscillator to stabilize; then the oscillator watchdog reset is released and the part starts
program execution again.
• Fast internal reset after power-on
The oscillator watchdog unit provides a clock supply for the reset before the on-chip
oscillator has started. The oscillator watchdog unit also works identically to the
monitoring function.
• Restart from the hardware power down mode
If the hardware power down mode is terminated the oscillator watchdog has to control
the correct start-up of the on-chip oscillator and to restart the program. The oscillator
watchdog function is only part of the complete hardware power down sequence;
however, the watchdog works identically to the monitoring function.
• Control of external wake-up from software power-down mode
When the software power-down mode is left by a low level at the P3.2/INT0 pin, the
oscillator watchdog unit assures that the microcontroller resumes operation
(execution of the power-down wake-up interrupt) with the nominal clock rate. In the
power-down mode the RC oscillator and the on-chip oscillator are stopped. Both
oscillators are started again when power-down mode is released. When the on-chip
oscillator has a higher frequency than the RC oscillator, the microcontroller starts
operation after a final delay of typ. 1 ms in order to allow the on-chip oscillator to
stabilize.
Data Sheet
54
2003-02
C515C
EWPD
(PCON1.7)
P3.2/
INT0
Power-Down
Mode Activated
Control
Logic
Power-Down Mode
Wake-Up Interrupt
Control
Logic
Internal
Reset
Start/
Stop
RC
Oscillator
f RC
3 MHz
÷2
÷5
f1
Frequency
Comparator
Start/
Stop
XTAL1
XTAL2
f2<f1
Delay
<_ 1
f2
On-Chip
Oscillator
IP0 (A9 H)
OWDS
Internal
Clock
MCB02757
Figure 24
Data Sheet
Block Diagram of the Oscillator Watchdog
55
2003-02
C515C
Power Saving Modes
The C515C provides two basic power saving modes, the idle mode and the power down
mode. Additionally, a slow down mode is available. This power saving mode reduces the
internal clock rate in normal operating mode and it can be also used for further power
reduction in idle mode.
• Idle mode
The CPU is gated off from the oscillator. All peripherals are still provided with the clock
and are able to work. Idle mode is entered by software and can be left by an interrupt
or reset.
• Power down mode
The operation of the C515C is completely stopped and the oscillator is turned off. This
mode is used to save the contents of the internal RAM with a very low standby current.
Software power down mode: Software power down mode is entered by software
and can be left by reset or by a short low pulse at pin P3.2/INT0 (or P4.7/RXDC,
C515C-8E only).
Hardware power down mode: Hardware power down mode is entered when the pin
HWPD is put to low level.
• Slow-down mode
The controller keeps up the full operating functionality, but its normal clock frequency
is internally divided by 32. This slows down all parts of the controller, the CPU and all
peripherals, to 1/32th of their normal operating frequency. Slowing down the frequency
significantly reduces power consumption. The slow down mode can be combined with
the idle mode.
Table 11 gives a general overview of the entry and exit conditions of the power saving
modes.
In the power down mode of operation, VDD can be reduced to minimize power
consumption. It must be ensured, however, that VDD is not reduced before the power
down mode is invoked, and that VDD is restored to its normal operating level, before the
power down mode is terminated.
If e.g. the idle mode is left through an interrupt, the microcontroller state (CPU, ports,
peripherals) remains preserved. If a power saving mode is left by a hardware reset, the
microcontroller state is disturbed and replaced by the reset state of the C515C.
If WS (bit 4) is SFR PCON1 is set (C515C-8E only), pin P4.7/RXDC is alternatively
selected as wake-up pin for the software power down mode. If WS (bit 4) is SFR PCON1
is cleared (C515C-8E only), pin P3.2/INT0 is selected as wake-up pin for the software
power down mode.
For the C515C-8R, P3.2/INT0 is always selected as wake-up pin.
Data Sheet
56
2003-02
C515C
Table 11
Power Saving Modes Overview
Mode
Entering
(2-Instruction
Example)
Leaving by
Idle mode
ORL PCON, #01H Occurrence of an
ORL PCON, #20H interrupt from a
peripheral unit
Hardware Reset
Remarks
CPU clock is stopped;
CPU maintains their data;
peripheral units are active (if
enabled) and provided with
clock
Software
Power-Down
Mode
ORL PCON, #02H Hardware Reset
ORL PCON, #40H Short low pulse at
pin P3.2/INT0
(or P4.7/RXDC,
C515C-8E only)
Oscillator is stopped;
contents of on-chip RAM
and SFR’s are maintained;
Hardware
Power-Down
Mode
HWPD = low
C515C is put into its reset
state and the oscillator is
stopped;
ports become floating
outputs
Slow Down
Mode
ORL PCON, #10H ANL PCON, #0EFH Oscillator frequency is
or
reduced to 1/32 of its
Hardware Reset
nominal frequency
Data Sheet
HWPD = high
57
2003-02
C515C
OTP Memory Operation (C515C-8E only)
The C515C-8E contains a 64 Kbytes one-time programmable (OTP) program memory.
With the C515C-8E fast programming cycles are achieved (1 byte in 100 µs). Also
several levels of OTP memory protection can be selected.
For programming of the device, the C515C-8E must be put into the programming mode.
This typically is done not in-system but in a special programming hardware. In the
programming mode the C515C-8E operates as a slave device similar as an EPROM
standalone memory device and must be controlled with address/data information,
control lines, and an external 11.5 V programming voltage. Figure 25 shows the pins of
the C515C-8E which are required for controlling of the OTP programming mode.
VDD
A0-7
A8-A15
VSS
Port 2
Port 0
PALE
PMSEL0
PMSEL1
C515C-8E
P0-7
EA/VPP
PROG
PRD
RESET
PSEN
PSEL
XTAL1
XTAL2
MCP03651
Figure 25
Data Sheet
Programming Mode Configuration of the C515C-8E
58
2003-02
C515C
N.C.
D7
D6
D5
D4
D3
D2
D1
D0
VSS
VDD
EA/VPP
PROG
PSEN
N.C.
A7/A15
A6/A14
A5/A13
A4/A12
A3/A11
C515C-8E Pin Configuration in Programming Mode
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
VDD
N.C.
VSS
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
C515C-8E
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
A2/A10
A1/A9
A0/A8
XTAL1
XTAL2
VSS
VSS
VDD
VDD
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
RESET
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
VSS
VDD
PMSEL0
PMSEL1
PSEL
PRD
PALE
N.C.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
Figure 26
Data Sheet
MCP03652
P-MQFP-80-1 Pin Configuration of the C515C-8E in Programming
Mode (top view)
59
2003-02
C515C
The following Table 12 contains the functional description of all C515C-8E pins which
are required for OTP memory programming.
Table 12
Pin Definitions and Functions in Programming Mode
Symbol
Pin Number I/O1) Function
RESET
1
PMSEL0 15
PMSEL1 16
I
Reset
This input must be at static “0” (active) level during the
whole programming mode.
I
I
Programming mode selection pins
These pins are used to select the different access
modes in programming mode. PMSEL1,0 must satisfy
a setup time to the rising edge of PALE. When the logic
level of PMSEL1,0 is changed, PALE must be at low
level.
PMSEL1
PMSEL0
Access Mode
0
0
Reserved
0
1
Read version bytes
1
0
Program/read lock bits
1
1
Program/read OTP memory
byte
PSEL
17
I
Basic programming mode select
This input is used for the basic programming mode
selection and must be switched according Figure 27.
PRD
18
I
Programming mode read strobe
This input is used for read access control for OTP
memory read, version byte read, and lock bit read
operations.
PALE
19
I
Programming address latch enable
PALE is used to latch the high address lines. The high
address lines must satisfy a setup and hold time to/from
the falling edge of PALE. PALE must be at low level
whenever the logic level of PMSEL1,0 is changed.
XTAL2
36
I
XTAL2
Input to the oscillator amplifier.
XTAL1
37
O
XTAL1
Output of the inverting oscillator amplifier.
Data Sheet
60
2003-02
C515C
Table 12
Pin Definitions and Functions in Programming Mode (cont’d)
Symbol
Pin Number I/O1) Function
A0/A8 A7/A15
38 - 45
I
Address lines
P2.0-7 are used as multiplexed address input lines
A0-A7 and A8-A15. A8-A15 must be latched with PALE.
PSEN
47
I
Program store enable
This input must be at static “0” level during the whole
programming mode.
PROG
48
I
Programming mode write strobe
This input is used in programming mode as a write
strobe for OTP memory program and lock bit write
operations. During basic programming mode selection
a low level must be applied to PROG.
EA/VPP
49
I
External Access / Programming voltage
This pin must be at 11.5 V (VPP) voltage level during
programming of an OTP memory byte or lock bit. During
an OTP memory read operation this pin must be at high
level (VIH). This pin is also used for basic programming
mode selection. At basic programming mode selection
a low level must be applied to EA/VPP.
D0 - 7
52 - 58
I/O
Data lines 0-7
During programming mode, data bytes are read or
written from or to the C515C-8E via the bidirectional
D0-7 which are located at port 0.
VSS
13, 34, 35,
51, 70
–
Circuit ground potential
must be applied to these pins in programming mode.
VDD
14, 32, 33,
50, 69
–
Power supply terminal
must be applied to these pins in programming mode.
N.C.
2-12, 20-31,
46, 60-67,
69, 71-80
–
Not Connected
These pins should not be connected in programming
mode.
1)
I = Input; O = Output
Data Sheet
61
2003-02
C515C
C515C-8E Basic Programming Mode Selection
The basic programming mode selection scheme is shown in Figure 27.
5V
VDD
Clock
(XTAL1/XTAL2)
Stable
RESET
"0"
PSEN
"0"
0.1
PMSEL1, 0
PROG
"0"
"1"
PRD
PSEL
"0"
PALE
VPP
EA/VPP
VIH
0V
Ready for access
mode selection
During this period signals
are not actively driven
Figure 27
Data Sheet
MCT03653
C515C-8E Basic Programming Mode Selection
62
2003-02
C515C
Table 13
Access Modes Selection
Access Mode
EA/ PROG PRD
VPP
PMSEL
1
0
Address
(Port 2)
Data
(Port 0)
Program OTP memory
byte
VPP
H
H
H
A0-7
A8-15
D0-7
Read OTP memory byte
H
H
L
–
Read OTP lock bits
VIH H
VPP
VIH H
D1, D0
see
Table 14
Read OTP version byte
VIH
L
H
Byte addr.
of version
byte
D0-7
Program OTP lock bits
H
C515C-8E Lock Bits Programming / Read
The C515C-8E has two programmable lock bits which, when programmed according
Table 14, provide four levels of protection for the on-chip OTP code memory. The state
of the lock bits can also be read.
Data Sheet
63
2003-02
C515C
Table 14
Lock Bit Protection Types
Lock Bits at
D1, D0
Protection Protection Type
Level
D1
D0
1
1
Level 0
The OTP lock feature is disabled. During normal
operation of the C515C-8E, the state of the EA pin is
not latched on reset.
1
0
Level 1
During normal operation of the C515C-8E, MOVC
instructions executed from external program memory
are disabled from fetching code bytes from internal
memory. EA is sampled and latched on reset. An OTP
memory read operation is only possible according to
ROM verification mode 2, as it is defined for a
protected ROM version of the C515C-8R. Further
programming of the OTP memory is disabled
(reprogramming security).
0
1
Level 2
Same as level 1, but also OTP memory read operation
using ROM verification mode 2 is disabled.
0
0
Level 3
Same as level 2; but additionally external code
execution by setting EA = low during normal operation
of the C515C-8E is no more possible.
External code execution, which is initiated by an
internal program (e.g. by an internal jump instruction
above the ROM boundary), is still possible.
Data Sheet
64
2003-02
C515C
Absolute Maximum Ratings
Parameter
Symbol
Limit Values
Unit Notes
min.
max.
-65
150
°C
–
-0.5
6.5
V
–
Voltage on any pin with respect VIN
to ground (VSS)
-0.5
VDD + 0.5
V
–
Input current on any pin during –
overload condition
-10
10
mA
–
Absolute sum of all input
currents during overload
condition
–
–
|100 mA|
mA
–
Power dissipation
PDISS
–
1
W
–
Storage temperature
Voltage on VDD pins with
respect to ground (VSS)
TST
VDD
Note: Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage of the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for longer periods may
affect device reliability. During absolute maximum rating overload
conditions (VIN > VDD or VIN < VSS) the voltage on VDD pins with respect to
ground (VSS) must not exceed the values defined by the absolute maximum
ratings.
Data Sheet
65
2003-02
C515C
Operating Conditions
Parameter
Supply voltage
Ground voltage
Symbol
VDD
Limit Values
min.
max.
4.25
5.5
V
Active mode,
fOSCmax = 10 MHz
2
5.5
V
Power Down
mode
V
Reference voltage
°C
–
VSS
0
Ambient temperature:
TA
TA
SAF-C505
TA
SAH-C505
Analog reference voltage VAREF
VAGND
Analog ground voltage
Analog input voltage
VAIN
fOSC
XTAL clock
SAB-C515C
Data Sheet
Unit Notes
0
70
-40
85
-40
110
4
VSS - 0.1
VAGND
VDD + 0.1 V
VSS + 0.2 V
VAREF
V
2
10
66
–
–
–
MHz –
2003-02
C515C
DC Characteristics (Operating Conditions apply)
Parameter
Input low voltages all except
EA, RESET, HWPD
EA pin
RESET and HWPD pins
Port 5 in CMOS mode
Input high voltages
all except XTAL2, RESET,
and HWPD)
XTAL2 pin
RESET and HWPD pins
Port 5 in CMOS mode
Symbol
min.
VIL
VIL1
VIL2
VILC
VIH
VIH1
VIH2
VIHC
Output low voltages
Ports 1, 2, 3, 4, 5, 7 (incl. CMOS) VOL
Port 0, ALE, PSEN, CPUR
VOL1
P4.1, P4.3 in push-pull mode
VOL3
Output high voltages
Ports 1, 2, 3, 4, 5, 7
Limit Values
max.
Unit Test
Condition
V
–
V
–
0.2 VDD - 0.1
0.2 VDD - 0.3
0.2 VDD + 0.1
0.3 VDD
-0.5
-0.5
-0.5
-0.5
0.2 VDD + 0.9
0.7 VDD
0.6 VDD
0.7 VDD
VDD + 0.5
VDD + 0.5
VDD + 0.5
VDD + 0.5
–
–
–
0.45
0.45
0.45
V
IOL = 1.6 mA1)
IOL = 3.2 mA1)
IOL = 3.75 mA1)
V
VOH
Port 0 in external bus mode,
ALE, PSEN, CPUR
Port 5 in CMOS mode
P4.1, P4.3 in push-pull mode
VOH2
VOHC
VOH3
Logic 0 input current
Ports 1, 2, 3, 4, 5, 7
IIL
-10
-70
µA
VIN = 0.45 V
Logical 0-to-1 transition current
Ports 1, 2, 3, 4, 5, 7
ITL
-65
-650
µA
VIN = 2 V
Input leakage current
Port 0, EA, P6, HWPD, AIN0-7
ILI
–
±1
µA
0.45 < VIN < VDD
Input low current
To RESET for reset
XTAL2
PE/SWD
ILI2
ILI3
ILI4
–
–
–
-100
-15
-20
Pin capacitance
CIO
–
10
pF
fc = 1 MHz,
TA = 25 °C
Overload current
IOV
–
±5
mA
3)4)
Programming voltage
VPP
10.9
12.1
V
11.5 V ± 5%
Data Sheet
–
–
–
–
–
–
IOH = -80 µA
IOH = -10 µA
IOH = -800 µA
IOH = -80 µA2)
IOH = -800 µA
IOH = -833 µA
2.4
0.9 VDD
2.4
0.9 VDD
0.9 VDD
0.9 VDD
µA
67
VIN = 0.45 V
VIN = 0.45 V
VIN = 0.45 V
2003-02
C515C
1)
Capacitive loading on ports 0 and 2 may cause spurious noise pulses to be superimposed on the VOL of ALE
and port 3. The noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these
pins make 1-to-0 transitions during bus operation. In the worst case (capacitive loading > 100 pF), the noise
pulse on ALE line may exceed 0.8 V. In such cases it may be desirable to qualify ALE with a Schmitt-trigger,
or use an address latch with a Schmitt-trigger strobe input.
2)
Capacitive loading on ports 0 and 2 may cause the VOH on ALE and PSEN to momentarily fall below the
0.9 VDD specification when the address lines are stabilizing.
3)
Overload conditions under operating conditions occur if the voltage on the respective pin exceeds the specified
operating range (i.e. VOV > VDD + 0.5 V or VOV < VSS - 0.5 V). The absolute sum of input overload currents on
all port pins may not exceed 50 mA. The supply voltage (VDD and VSS) must remain within the specified limits.
4)
Not 100% tested, guaranteed by design characterization.
Data Sheet
68
2003-02
C515C
Power Supply Current
Parameter
Sym- Limit Values Unit Test Condition
bol
typ.1) max.2)
C515C-8R/ 6 MHz IDD
C515C-LM 10 MHz
11.97
18.81
13.74
21.10
mA
6 MHz IDD
10 MHz
11.3
17.66
12.94
20.10
mA
C515C-8R/ 6 MHz IDD
C515C-LM 10 MHz
6.9
10.46
7.87
11.87
mA
6 MHz IDD
10 MHz
3.95
4.71
4.70
5.50
mA
Active mode
C515C-8R/ 6 MHz IDD
with slow-down C515C-LM 10 MHz
enabled
C515C-8E 6 MHz IDD
10 MHz
4.06
4.62
5.03
5.75
mA
4.01
4.65
4.77
5.53
mA
C515C-8R/ 6 MHz IDD
C515C-LM 10 MHz
3.54
3.86
4.46
4.90
mA
6 MHz IDD
10 MHz
3.62
4.14
4.21
4.77
mA
26
42.9
µA
Active mode
C515C-8E
Idle mode
C515C-8E
Idle mode with
slow-down
enabled
C515C-8E
Power-down
mode
C515C-8R/
C515C-LM
IPD
C515C-8E
IPD
11.14
IDDP –
At EA/VPP in
programming
mode
C515C-8E
30
µA
30
mA
3)
4)
5)
6)
VDD = 2 … 5.5 V
7)
–
1)
The typical IDD values are periodically measured at TA = +25 °C and VDD = 5 V but not 100% tested.
2)
The maximum IDD values are measured under worst case conditions (TA = 0 °C or -40 °C and VDD = 5.5 V)
3)
IDD (active mode) is measured with:
XTAL2 driven with tCLCH, tCHCL = 5 ns, VIL = VSS + 0.5 V, VIH = VDD - 0.5 V; XTAL1 = N.C.;
EA = PE/SWD = Port 0 = Port 6 = VDD; HWPD = VDD; RESET = VSS; all other pins are disconnected.
4)
IDD (idle mode) is measured with all output pins disconnected and with all peripherals disabled;
XTAL2 driven with tCLCH, tCHCL = 5 ns, VIL = VSS + 0.5 V, VIH = VDD - 0.5 V; XTAL1 = N.C.;
RESET = VDD; EA = VSS; Port0 = VDD; all other pins are disconnected;
5)
IDD (active mode with slow-down mode) is measured with all output pins disconnected and with all peripherals
disabled;
XTAL2 driven with tCLCH, tCHCL = 5 ns, VIL = VSS + 0.5 V, VIH = VDD - 0.5 V; XTAL1 = N.C.;
RESET = VDD; all other pins are disconnected; the microcontroller is put into slow-down mode by software.
Data Sheet
69
2003-02
C515C
6)
IDD (idle mode with slow-down mode) is measured with all output pins disconnected and with all peripherals
disabled;
XTAL2 driven with tCLCH, tCHCL = 5 ns, VIL = VSS + 0.5 V, VIH = VDD - 0.5 V; XTAL1 = N.C.;
RESET = VDD; EA = VSS; Port0 = VDD; all other pins are disconnected; the microcontroller is put into idle mode
with slow-down enabled by software.
7)
IPD (power-down mode) is measured under following conditions:
EA = RESET = Port 0 = Port 6 = VDD; XTAL1 = N.C.; XTAL2 = VSS; PE/SWD = VSS; HWPD = VDD;
VAGND = VSS; VAREF = VDD; all other pins are disconnected.
IPD (hardware power-down mode) is independent of any particular pin connection.
Data Sheet
70
2003-02
C515C
Power Supply Current Calculation Formulas
Parameter
Active mode
C515C-8R/
C515C-LM
C515C-8E
Idle mode
C515C-8R/
C515C-LM
C515C-8E
Active mode with
slow-down enabled
C515C-8R/
C515C-LM
C515C-8E
Idle mode with slow-down
enabled
C515C-8R/
C515C-LM
C515C-8E
Symbol
Formula
IDD typ
IDD max
IDD typ
IDD max
IDD typ
IDD max
IDD typ
IDD max
IDD typ
IDD max
IDD typ
IDD max
IDD typ
IDD max
IDD typ
IDD max
1.71 × fOSC + 1.71
1.84 × fOSC + 2.7
1.59 × fOSC + 1.76
1.79 × fOSC + 2.2
0.89 × fOSC + 1.56
1.00 × fOSC + 1.87
0.19 × fOSC + 2.81
0.20 × fOSC + 3.5
0.14 × fOSC + 3.22
0.18 × fOSC + 3.95
0.16 × fOSC + 3.05
0.19 × fOSC + 3.63
0.08 × fOSC + 3.06
0.11 × fOSC + 3.8
0.13 × fOSC + 2.84
0.14 × fOSC + 3.37
Note: fOSC is the oscillator frequency in MHz. IDD values are given in mA.
Data Sheet
71
2003-02
C515C
[mA]
C515C-8E
C515C-LM
25
20
eM
od
e
15
Ac
ti v
e
M
od
e
Ac
tiv
IDD max
IDD typ
10
le
Id
M
e
od
eM
Idl
o
own M
Slow-d
e
od
de
5
Idle+Slow-down
fOSC
2
Figure 28
Data Sheet
4
6
8
10
[MHz]
IDD Diagrams of C515C-8R/C515C-LM
72
2003-02
C515C
C515C-8E
[mA]
25
Ac
tiv
e
M
od
e
20
15
IDD max
IDD typ
10
Slow
Mode+
e
v
ti
c
A
-down
Idle M
ode
5
Idle Mode+Slow-down
fOSC
2
Figure 29
Data Sheet
4
6
8
10
[MHz]
IDD Diagrams of C515C-8E
73
2003-02
C515C
A/D Converter Characteristics (Operating Conditions apply)
Parameter
Symbol
Limit Values
Unit Test Condition
min.
max.
VAGND
1)
ns
Prescaler ÷ 8
Prescaler ÷ 42)
Conversion cycle time
tADCC
–
VAREF
16 × tIN
8 × tIN
96 × tIN
48 × tIN
V
Sample time
VAIN
tS
ns
Prescaler ÷ 8
Prescaler ÷ 43)
Total unadjusted error
TUE
–
±2
LSB
4)
Internal resistance of
RAREF
reference voltage source
–
tADC / 250 kΩ
Internal resistance of
analog source
RASRC
–
ADC input capacitance
CAIN
Analog input voltage
1)
–
tADC in [ns]5)6)
- 0.25
tS / 500
kΩ
tS in [ns]2)6)
pF
6)
- 0.25
–
50
VAIN may exceed VAGND or VAREF up to the absolute maximum ratings. However, the conversion result in
these cases will be X000H or X3FFH, respectively.
2)
During the sample time the input capacitance CAIN can be charged/discharged by the external source. The
internal resistance of the analog source must allow the capacitance to reach their final voltage level within tS.
After the end of the sample time tS, changes of the analog input voltage have no effect on the conversion result.
3)
This parameter includes the sample time tS, the time for determining the digital result and the time for the
calibration. Values for the conversion clock tADC depend on programming and can be taken from the table on
the previous page.
4)
TUE is tested at VAREF = 5.0 V, VAGND = 0 V, VDD = 4.9 V. It is guaranteed by design characterization for all
other voltages within the defined voltage range.
If an overload condition occurs on maximum 2 not selected analog input pins and the absolute sum of input
overload currents on all analog input pins does not exceed 10 mA, an additional conversion error of 1/2 LSB
is permissible.
5)
During the conversion the ADC’s capacitance must be repeatedly charged or discharged. The internal
resistance of the reference source must allow the capacitance to reach their final voltage level within the
indicated time. The maximum internal resistance results from the programmed conversion timing.
6)
Not 100% tested, but guaranteed by design characterization.
Data Sheet
74
2003-02
C515C
Clock Calculation Table
tADC
8 × tIN
4 × tIN
Clock Prescaler Ratio
ADCL
÷8
1
÷4
0
Further timing conditions:
tADC min = 500 ns
tIN = 1 / fOSC = tCLP
Data Sheet
75
tS
16 × tIN
8 × tIN
tADCC
96 × tIN
48 × tIN
2003-02
C515C
AC Characteristics (Operating Conditions apply)
(CL for port 0, ALE and PSEN outputs = 100 pF; CL for all other outputs = 80 pF)
Program Memory Characteristics
Parameter
Symbol
Limit Values
Unit
Variable Clock
1/CLP = 2 MHz
to 10 MHz
10-MHz Clock
Duty Cycle
0.4 to 0.6
min.
max.
min.
max.
60
–
CLP - 40
–
ns
15
–
TCLHmin - 25 –
ns
15
–
TCLHmin - 25 –
ns
–
113
–
ns
tLLPL
tPLPH
20
–
TCLLmin - 20 –
ns
115
–
–
CLP +
TCLHmin - 30
ns
PSEN to valid
instruction in
tPLIV
–
75
–
CLP +
ns
TCLHmin - 65
Input instruction hold
after PSEN
tPXIX
0
–
0
–
Input instruction float
after PSEN
tPXIZ1)
–
30
–
TCLLmin - 10 ns
Address valid after
PSEN
tPXAV1)
35
–
TCLLmin - 5
–
Address to valid
instruction in
tAVIV
–
180
–
2 CLP +
ns
TCLHmin - 60
Address float to PSEN
tAZPL
0
0
–
tLHLL
Address setup to ALE tAVLL
Address hold after ALE tLLAX
ALE to valid instruction tLLIV
ALE pulse width
2 CLP - 87
in
ALE to PSEN
PSEN pulse width
1)
ns
ns
ns
Interfacing the C515C to devices with float times up to 35 ns is permissible. This limited bus contention will not
cause any damage to port 0 drivers.
Data Sheet
76
2003-02
C515C
External Data Memory Characteristics
Parameter
Symbol
Limit Values
10-MHz Clock
Duty Cycle
0.4 to 0.6
Unit
Variable Clock
1/CLP= 2 MHz to 10 MHz
min.
max.
min.
max.
tRLRH
tWLWH
tLLAX2
230
–
3 CLP - 70
–
ns
230
–
3 CLP - 70
–
ns
48
–
CLP - 15
–
ns
tRLDV
–
150
–
2 CLP +
TCLHmin - 90
ns
tRHDX
tRHDZ
Data float after RD
ALE to valid data in tLLDV
Address to valid data tAVDV
0
–
0
–
ns
–
80
–
CLP - 20
ns
–
267
–
4 CLP - 133
ns
–
285
–
ns
4 CLP +
TCLHmin - 155
RD pulse width
WR pulse width
Address hold after
ALE
RD to valid data in
Data hold after RD
in
ALE to WR or RD
tLLWL
90
190
CLP +
TCLLmin - 50
CLP +
TCLLmin + 50
ns
Address valid to WR
tAVWL
tWHLH
103
–
2 CLP - 97
–
ns
15
65
TCLHmin - 25
TCLHmin + 25
ns
Data valid to WR
transition
tQVWX
5
–
TCLLmin - 35
–
ns
Data setup before
WR
tQVWH
218
–
3 CLP +
–
TCLLmin - 122
ns
Data hold after WR
tWHQX
tRLAZ
13
–
TCLHmin - 27
–
ns
–
0
–
0
ns
WR or RD high to
ALE high
Address float after
RD
Data Sheet
77
2003-02
C515C
SSC Interface Characteristics
Parameter
Symbol
Clock Cycle Time:
Master Mode
Slave Mode
tSCLK
tSCLK
tSCH
tSCL
tD
tHO
tS
tHI
tDTC
Clock high time
Clock low time
Data output delay
Data output hold
Data input setup
Data input hold
TC bit set delay
Limit Values
Unit
min.
max.
0.4
1.0
–
–
µs
µs
360
–
ns
360
–
ns
–
100
ns
0
–
ns
100
–
ns
100
–
ns
–
8 CLP
ns
External Clock Drive at XTAL2
Parameter
Symbol CPU Clock = 10 MHz
Duty cycle 0.4 to 0.6
Variable CPU Clock
1/CLP = 2 to 10 MHz
Unit
min.
max.
min.
max.
Oscillator period CLP
100
100
100
500
ns
High time
TCLH
40
–
40
CLP - TCLL
ns
Low time
TCLL
40
–
40
CLP - TCLH
ns
Rise time
tR
tF
–
12
–
12
ns
–
12
–
12
ns
Oscillator duty
cycle
DC
0.4
0.6
40 / CLP
1 - 40 / CLP
–
Clock cycle
TCL
40
60
CLP × DCmin CLP × DCmax ns
Fall time
Note: The 10 MHz values in the tables are given as an example for a typical duty cycle
variation of the oscillator clock from 0.4 to 0.6.
Data Sheet
78
2003-02
C515C
t LHLL
ALE
t AVLL
t PLPH
t LLPL
t LLIV
t PLIV
PSEN
t AZPL
t PXAV
t LLAX
t PXIZ
t PXIX
Port 0
A0 - A7
Instr.IN
A0 - A7
t AVIV
Port 2
A8 - A15
A8 - A15
MCT00096
Figure 30
Data Sheet
Program Memory Read Cycle
79
2003-02
C515C
t WHLH
ALE
PSEN
t LLDV
t LLWL
t RLRH
RD
t RLDV
t AVLL
t RHDZ
t LLAX2
t RLAZ
Port 0
t RHDX
A0 - A7 from
Ri or DPL
Data IN
A0 - A7
from PCL
Instr.
IN
t AVWL
t AVDV
Port 2
P2.0 - P2.7 or A8 - A15 from DPH
A8 - A15 from PCH
MCT00097
Figure 31
Data Sheet
Data Memory Read Cycle
80
2003-02
C515C
t WHLH
ALE
PSEN
t LLWL
t WLWH
WR
t QVWX
t AVLL
t WHQX
t LLAX2
A0 - A7 from
Ri or DPL
Port 0
t QVWH
A0 - A7
from PCL
Data OUT
Instr.IN
t AVWL
Port 2
P2.0 - P2.7 or A8 - A15 from DPH
A8 - A15 from PCH
MCT00098
Figure 32
Data Memory Write Cycle
tR
TCLH
tF
V IH2
V IL
XTAL2
TCLL
CLP
Figure 33
Data Sheet
MCT02704
External Clock Drive at XTAL2
81
2003-02
C515C
t SCLK
t SCL
t SCH
~
~
SCLK
t HD
~
~
tD
MSB
LSB
~
~
STO
t HI
~
~
tS
MSB
LSB
~
~
SRI
t DTC
~
~
TC
MCT02417
Figure 34
SSC Timing
Notes:
1. Shown is the data/clock relationship for CPOL = CPHA = 1. The timing diagram is
valid for the other cases accordingly.
2. In the case of slave mode and CPHA = 0, the output delay for the MSB applies to the
falling edge of SLS (if transmitter is enabled).
3. In the case of master mode and CPHA = 0, the MSB becomes valid after the data
has been written into the shift register, i.e. at least one half SCLK clock cycle before
the first clock transition.
Data Sheet
82
2003-02
C515C
OTP Memory Programming Mode Characteristics
VDD = 5 V ± 10%; VPP = 11.5 V ± 5%; TA = 25 °C ± 10 °C
Parameter
Symbol
Limit Values
Unit
min.
max.
tPAW
tPMS
tPAS
35
–
ns
10
–
ns
10
–
ns
Address hold after ALE, PROG, or PRD
falling edge
tPAH
10
–
ns
Address, data setup to PROG or PRD
tPCS
tPCH
tPMS
tPMH
tPWW
tPRW
tPAD
tPRD
tPDH
tPDF
tPWH1
100
–
ns
0
–
ns
10
–
ns
10
–
ns
100
–
µs
100
–
ns
–
75
ns
–
20
ns
0
–
ns
–
20
ns
1
–
µs
PRD high between two consecutive PRD
low pulses
tPWH2
100
–
ns
XTAL clock period
tCLKP
2
10
MHz
ALE pulse width
PMSEL setup to ALE rising edge
Address setup to ALE, PROG, or PRD
falling edge
Address, data hold after PROG or PRD
PMSEL setup to PROG or PRD
PMSEL hold after PROG or PRD
PROG pulse width
PRD pulse width
Address to valid data out
PRD to valid data out
Data hold after PRD
Data float after PRD
PROG high between two consecutive
PROG low pulses
Data Sheet
83
2003-02
C515C
t PAW
PALE
t PMS
H, H
PMSEL1,0
t PAS
Port 2
t PAH
A8-15
A0-7
D0-7
Port 0
PROG
t PWH
t PCS
t PWW
Notes: PRD must be high during a programming write cycle.
Figure 35
Data Sheet
t PCH
MCT03690
Programming Code Byte - Write Cycle Timing
84
2003-02
C515C
t PAW
PALE
t PMS
H, H
PMSEL1,0
t PAS
Port 2
t PAH
A8-15
A0-7
t PAD
t PDH
D0-7
Port 0
t PRD
t PDF
PRD
t PWH
t PCS
t PRW
Notes: PROG must be high during a programming read cycle.
Figure 36
Data Sheet
t PCH
MCT03689
Verify Code Byte - Read Cycle Timing
85
2003-02
C515C
PMSEL1,0
H, L
Port 0
D0, D1
H, L
D0, D1
t PCH
t PCS
t PMS
t PMH
PROG
t PDH
t PMS t PRD
t PWW
t PDF
t PRW
t PMH
PRD
Note: PALE should be low during a lock bit read / write cycle.
Figure 37
Data Sheet
MCT03393
Lock Bit Access Timing
86
2003-02
C515C
L, H
PMSEL1,0
e. g. FD H
Port 2
t PCH
D0-7
Port 0
t PCS
t PDH
t PDF
t PRD
t PMS
t PRW
PRD
t PMH
Note: PROG must be high during a programming read cycle.
MCT03394
Figure 38
Data Sheet
Version Byte - Read Timing
87
2003-02
C515C
ROM/OTP Verification Characteristics for C515C-8R / C515C-8E
ROM Verification Mode 1 (C515C-8R)
Parameter
Symbol
Address to valid data
P1.0 - P1.7
P2.0 - P2.7
tAVQV
Limit Values
min.
max.
–
5 CLP
Address
Unit
ns
New Address
t AVQV
Port 0
Data Out
New Data Out
Data:
P0.0 - P0.7 = D0 - D7
Addresses: P1.0 - P1.7 = A0 - A7
P2.0 - P2.7 = A8 - A15
Inputs: PSEN = VSS
ALE, EA = VIH
RESET = VIL2
MCT02764
Figure 39
Data Sheet
ROM Verification Mode 1
88
2003-02
C515C
ROM/OTP Verification Mode 2
Parameter
Symbol
Limit Values
Unit
min.
typ.
max.
–
CLP
–
ns
–
6 CLP
–
ns
–
–
2 CLP
ns
4 CLP
–
–
ns
P3.5 setup to ALE low
tAWD
tACY
tDVA
tDSA
tAS
–
tCL
–
ns
Oscillator frequency
1 / CLP
4
–
6
MHz
ALE pulse width
ALE period
Data valid after ALE
Data stable after ALE
t ACY
t AWD
ALE
t DSA
t DVA
Port 0
Data Valid
t AS
P3.5
MCT02613
Figure 40
Data Sheet
ROM/OTP Verification Mode 2
89
2003-02
C515C
VDD - 0.5 V
0.2 VDD + 0.9
Test Points
0.2 VDD - 0.1
0.45 V
MCT00039
AC Inputs during testing are driven at VDD - 0.5 V for a logic ‘1’ and 0.45 V for a logic ‘0’.
Timing measurements are made at VIHmin for a logic ‘1’ and VILmax for a logic ‘0’.
Figure 41
AC Testing: Input, Output Waveforms
VOH -0.1 V
VLoad +0.1 V
Timing Reference
Points
VLoad
VLoad -0.1 V
VOL +0.1 V
MCT00038
For timing purposes a port pin is no longer floating when a 100 mV change from load voltage
occurs and begins to float when a 100 mV change from the loaded VOH/VOL level occurs.
IOL/IOH ≥ ± 20 mA
Figure 42
AC Testing: Float Waveforms
Crystal/Resonator Oscillator Mode
Driving from External Source
C
N.C.
XTAL1
XTAL1
2 - 10 MHz
External Oscillator
Signal
C
XTAL2
Crystal Mode
: C = 20 pF ± 10 pF (incl. stray capacitance)
Resonator Mode : C = depends on selected ceramic resonator
XTAL2
MCT02765
Figure 43
Recommended Oscillator Circuits for Crystal Oscillator
Data Sheet
90
2003-02
C515C
Package Outlines
0.65
0.3 ±0.08
H
7˚max
0.15 +0.08
-0.02
0.25 min
2 +0.1
-0.05
2.45 max
P-MQFP-80-1
(Plastic Metric Quad Flat Package)
0.88
C
0.1
12.35
0.12
17.2
0.2 A-B D 80x
0.2 A-B D H 4x
14
1)
M
A-B D C 80x
D
B
14 1)
17.2
A
80
1
Index Marking
0.6x45˚
1) Does not include plastic or metal protrusions of 0.25 max per side
GPM05249
You can find all of our packages, sorts of packing and others in our
Infineon Internet Page “Products”: http://www.infineon.com/products.
Dimensions in mm
SMD = Surface Mounted Device
Data Sheet
91
2003-02
w w w . i n f i n e o n . c o m
Published by Infineon Technologies AG
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