AN-1209: Logarithmic Audio Volume Control with Glitch Reduction Using the AD5292 Digital Potentiometer (Rev. B) PDF

AN-1209
APPLICATION NOTE
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Logarithmic Audio Volume Control with Glitch Reduction
Using the AD5292 Digital Potentiometer
CIRCUIT FUNCTION AND BENEFITS
CIRCUIT DESCRIPTION
This circuit provides a logarithmic audio volume control with
glitch reduction using the AD5292 digital potentiometer in
conjunction with the dual AD8676 and single AD8541 op amps,
ADCMP371 comparators, and 7408 AND gates.
Table 1. Devices Connected/Referenced
This circuit provides low total harmonic distortion (THD), a
maximum signal attenuation of 46 dB, and a shutdown function
that attenuates up to 130 dB, as shown in Figure 3. The AD5292
can be placed in shutdown mode by executing a software
shutdown command. This feature places the RDAC in a special
state in which terminal A is open-circuited and wiper W is
connected to terminal B.
AD8676
AD8541
This circuit offers a logarithmic gain control function over an
output voltage range of ±14 V (10 V rms) and is capable of
delivering up to ±20 mA output current. The AD5292 is
programmable over an SPI-compatible serial interface.
In addition, the AD5292 has an internal 20-times programmable
memory that allows a customized volume setting at power-up.
V+
+15V
U1A
ADCMP371
Description
Digital potentiometer, 10 bits, 1% resistor
tolerance
Ultraprecision, dual, rail-to-rail output op amp
General-purpose CMOS, single, rail-to-rail
amplifier
Comparator with push-pull output stage
This circuit employs the AD5292 digital potentiometer in
conjunction with the dual AD8676 and single AD8541 op amps,
ADCMP371 comparators, and 7408 AND gates, providing a
low distortion logarithmic audio volume control with glitch
reduction. The logarithmic taper is achieved by adding resistor
R8 between the wiper connection and ground. This method is
described in detail in the article “Tack a Log Taper onto a
Digital Potentiometer” by Hank Zumbahlen, EDN, 1/20/00.
The circuit provides an input/output buffer, minimizing the
load effects with other external circuits; the AD8676 dual
op amp ensures low noise and precision rail-to-rail output
voltage. Figure 2 shows the logarithmic output voltage,
VOUT, normalized by VIN.
This circuit provides low noise, low THD, high signal
attenuation, low tempco, and high voltage capatibility.
It is well suited for many audio applications.
VCC
+3.3V
0V ±14V
1/2
AD8676
100kΩ
R1
100kΩ
±0.1%
V–
–15V
R4
90.9kΩ ±0.1%
+1.657V
0.0133V
R2
806Ω
±0.1%
+3.3V
U3
VCC
ADCMP371
GND
+1.645V
±1.4V
+3.3V
R5
9.09kΩ ±0.1%
+3.3V
R6
27.4kΩ
±0.1%
U2
V+
+1.81V
AD8541
V–
A
AD5292
SERIAL
INTERFACE
+3.3V
U5A
1/2
7408
U4
VCC
ADCMP371
GND
R3
100kΩ
±0.1%
U4B
2/2
7408
U1B
W
RAB
20kΩ
2/2
VOUT
AD8676
SYNC
R8
20kΩ
B
+1.643V
R7
33.2kΩ
±0.1%
VDD
+15V
U6
SYNC
VSS
–15V
Figure 1. Logarithmic Audio Volume Control with Glitch Reduction (Simplified Schematic: Decoupling and All Connections Not Shown)
Rev. B | Page 1 of 4
08499-001
C1
VIN 100nF
Product
AD5292
AN-1209
Application Note
1.0
0
–20
–40
0.6
FFT (dB)
NORMALIZED VOUT (V)
0.8
0.4
–60
–80
–100
0.2
0
500
1000
–140
0
2
4
6
8
CODE (Decimal)
10
12
14
16
18
20
22
24
08499-004
0
08499-002
–120
FREQUENCY (kHz)
Figure 2. Normalized VOUT vs. Code
Figure 4. FFT for 1 kHz, 1 VRMS Input Signal, 0 dB Gain
0
0.1
–73
GAIN FULL SCALE
–15
0
GAIN HALF SCALE
–60
–0.4
PHASE
–75
–0.5
–90
–0.6
–105
–0.7
–135
0.001
0.1
–76
–77
–0.8
GAIN SHUTDOWN
–0.9
0.01
–75
1
10
–78
10
FREQUENCY (kHz)
100
1k
10k
FREQUENCY (Hz)
Figure 3. Gain and Phase vs. Frequency for 1 VRMS Input Signal
Figure 5. THD + Noise vs. Frequency, 1 VRMS Input Signal, 0 dB Gain
The audio volume control guarantees a maximum attenuation
of 46 dB and up to 130 dB in shutdown mode. Figure 3 shows
the attenuation for typical codes, including shutdown mode and
signal phase delay, which is independent of the code.
This circuit is a zero crossing detector that minimizes the glitch
by allowing the attenuation to change only when the signal is
crossing 0 V. Resistors R4 and R5 attenuate the input signal by
90.91% and establish the common-mode voltage of 1.645 V into
the window comparator. The maximum uncertainty of the zero
crossing is approximately 133 mV reflected to the input. The
output of the window comparator is AND’ed with the external
SYNC command to drive the SYNC input of the AD5292. After
the negative-going edge of SYNC to the AD5292, the next clock
pulse updates the internal DAC register.
The circuit provides low total harmonic distortion, THD,
typically −93 dB, as shown in Figure 4 for a 1 kHz, 1 VRMS input
signal. Typical THD + Noise performance is shown in Figure 4,
Figure 5, and Figure 6.
Without the glitch reduction circuit, the glitch due to a large
attenuation step is shown in Figure 7, and the glitch due to the
code transition of the internal switches is shown in Figure 8.
The glitch reduction circuit employs the AD8541, ADCMP371,
and 7408 AND gates. Comparators U2 and U3 act as window
comparators, with a 13.3 mV threshold between the two. This is
large enough to overcome the typical comparator offset voltage.
Resistors R1 to R7 should be 0.1% tolerance to ensure an
optimal zero cross detection, which provides a smaller energy
glitch and prevents large attenuation step. The threshold
window is approximately 133 mV referenced to the input signal
voltage, VIN. A typical attenuation step with glitch reduction
circuit active is shown in Figure 9.
Rev. B | Page 2 of 4
08499-005
VDD/VSS = ±15V
THD + N (dB)
–0.2
GAIN ZERO SCALE
08499-003
GAIN (dB)
–45
–120
–74
–0.1
PHASE (Degrees)
–30
Application Note
AN-1209
The AD5292 has 20-times programmable memory, which enables
the user to preset the attenuation to a specific value at power-up.
1.0
Optimum layout, grounding, and decoupling techniques must
be utilized in order to achieve the desired performance
(see Tutorial MT-031 and Tutorial MT-101). As a minimum, a
4-layer PCB should be used with one ground plane layer, one
power plane layer, and two signal layers.
VOUT (V)
0.5
COMMON VARIATIONS
The AD5291 (8 bits with 20-times programmable power-up
memory) and AD5293 (10 bits, no power-up memory) are both
±1% tolerance digital potentiometers that are suitable for this
application.
0
–1.0
–0.004
–0.002
0
0.002
0.004
08499-008
–0.5
TIME (Seconds)
0
Figure 8. Small Change in Attenuation Showing Glitch Without Glitch
Reduction Circuit
–10
THD + N (dB)
1.2
–30
0.7
VOUT (V)
–50
–90
0.001
0.01
0.1
1
08499-006
–70
10
0.2
–0.3
Figure 6. THD + Noise vs. 1 kHz Input Signal Amplitude, 0 dB Gain
–0.8
0.010
0.015
0.020
0.025
TIME (Seconds)
15
Figure 9. Glitch Reduction Circuit Activated
LEARN MORE
10
Zumbahlen, Hank. “Tack a Log Taper onto a Digital
Potentiometer,” EDN, January 20, 2000.
VOUT (V)
5
MT-031 Tutorial, Grounding Data Converters and Solving the
Mystery of "AGND" and "DGND". Analog Devices.
0
MT-087 Tutorial, Voltage References. Analog Devices.
–5
MT-091 Tutorial, Digital Potentiometers. Analog Devices.
MT-101 Tutorial, Decoupling Techniques. Analog Devices.
–15
–0.003
–0.002
–0.001
0
0.001
0.002
0.003
0.004
08499-007
–10
Data Sheets
AD5292 Data Sheet
AD5291 Data Sheet
TIME (Seconds)
Figure 7. Large Step Change in Attenuation Shows Glitch Without Glitch
Reduction Circuit
AD5293 Data Sheet
AD8676 Data Sheet
AD8541 Data Sheet
ADCMP371 Data Sheet
Rev. B | Page 3 of 4
08499-009
VIN (RMS)
AN-1209
Application Note
REVISION HISTORY
4/13—Rev. A to Rev. B
Changed Title of Document from CN-0120 to
AN-1209............................................................................... Universal
3/10—Rev. 0 to Rev. A
Changes to Circuit Function and Benefits Section ...................... 1
10/09—Revision 0: Initial Version
©2009–2013 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
AN08499-0-4/13(B)
Rev. B | Page 4 of 4
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