AN-1289: Using the AD5755 and Similar Dynamic Power Control DACs in Applications Without Dynamic Power Control (Rev. 0) PDF

AN-1289
APPLICATION NOTE
One Technology Way • P.O. Box 9106 • Norwood, MA 02062-9106, U.S.A. • Tel: 781.329.4700 • Fax: 781.461.3113 • www.analog.com
Using the AD5755 and Similar Dynamic Power Control DACs
in Applications Without Dynamic Power Control
by David Rice
INTRODUCTION
There are low power applications that may not require dynamic
power control. In these cases, the dc-to-dc converter can be
excluded from the design. This reduces the number of external
components and is useful for applications with spaceconstraints that require the AD5755 quad-channel feature.
This application note describes using the AD5755 and other
similar industrial DACs in applications that do not require the
dynamic power control (DPC) feature.
This group of products consists of five industrial DACs, which
have multiple options to suit various applications. Table 1 lists
and highlights the features of each DAC.
This application note describes two alternatives to using the dcto-dc converter. The first method uses an external PMOS to
limit on-chip power dissipation. The second method involves
powering the DAC directly with all power dissipated directly
on chip. Each method describes the setup and calculates total
power dissipation both on and off chip.
DPC operates by sensing the load on the current output pin and
supplying only the power that is required. To achieve this, the
AD5755, for example, controls a dc-to-dc converter to step up a
5 V supply to between 7.4 V and 29.5 V.
DPC is particularly useful in systems with wide load ranges
including a short-circuit condition (0 Ω load to ground) where
all power generated by the supply is dissipated on chip. In nonDPC systems, this results in higher IC temperatures that
increase overall system temperatures.
Table 1. AD5755 and Similar Dynamic Power Control DACs
ADC
AD5755
AD5755-1
AVCC
5.0V
SW
AD5735
VBOOST
AD5757
DC-TO-DC
CONVERTER
POWER
CONTROL
7.4V TO 29.5V VSEN1
REG
AD5737
VSEN2
R2
R3
DAC
R1
12049-001
IOUT
Figure 1. AD5755 with Dynamic Power Control
Rev. 0 | Page 1 of 8
Features
16-Bit, Quad Channel, Current and Voltage Output
DAC
16-Bit, Quad Channel, Current and Voltage Output
DAC with HART Connectivity
12-Bit, Quad Channel, Current and Voltage Output
DAC
16-Bit, Quad Channel, Current Output DAC with
HART Connectivity
12-Bit, Quad Channel, Current Output DAC with
HART Connectivity
AN-1289
Application Note
TABLE OF CONTENTS
Introduction ...................................................................................... 1
Method 1—Using External PMOS..............................................3
Revision History ............................................................................... 2
Method 2—Connecting VBOOST to AVDD ....................................6
REVISION HISTORY
3/14—Revision 0: Initial Version
Rev. 0 | Page 2 of 8
Application Note
AN-1289
METHOD 1—USING EXTERNAL PMOS
As an alternative to the dc-to-dc converter, an external PMOS
transistor can be used to limit the on-chip power dissipation,
though this does not reduce the power dissipation of the total
system. On the AD5755, AD5735, and AD5755-1, the PMOS
circuit is set up as shown in Figure 2.
VBOOST must be powered for both voltage and current output
ranges. VBOOST can be tied to AVDD as long as sufficient headroom is maintained between VBOOST and the output per the
formula shown in Table 2.
The power dissipated by PMOS is calculated as follows (using
worst-case figures):
VBOOST = 33 V
Zener Voltage = 5 V
RLOAD = 0 Ω
IOUT = 24 mA
One Channel
On-chip power
Leave the SWx and COMPDCDC_A pins open circuit. Tie AVCC to
DVDD. This maintains the voltage on the AVCC pin above the
most negative supply, AVSS or 0 V (this applies only to the
AD5755-1, AD5737, and AD5757). If the voltage on the AVCC
pin is equal to or below the most negative voltage, it can result
in latch-up. See Table 2 for recommended supplies for the AVCC
and VBOOST rails. All other pins are set up in the same manner as
when the dynamic power control function is used. Details are
outlined in the Pin Configuration section and Layout
Guidelines section of the product data sheet.
VBOOST is powered externally and the Zener diode holds the gate
of the external PMOS at VBOOST – Zener voltage. This means
that the majority of the power dissipation of the channel takes
place in the external PMOS transistor.
5 V × 0.024 A = 0.12 W
Off-chip power
28 V × 0.024 A = 0.672 W
Four Channels
On-chip power
0.12 W × 4 = 0.48 W
Off-chip power
0.672 W × 4 = 2.688 W
The calculations in this section do not factor in the quiescent
currents of the AD5755; Table 3 includes these currents
to calculate the maximum power and allowed ambient
temperature for the AD5755. From the calculations, VBOOST is
5 V in the equation. The remainder of the power is dissipated
off chip on the PMOS.
Rev. 0 | Page 3 of 8
AN-1289
Application Note
dissipated). The PMOS chosen must be able to tolerate a VDS
voltage of –VBOOST and handle the power dissipation required.
The PMOS typically has minimal effect on current output
performance.
When selecting R1, it is important that the power is kept low.
In this example, R1 = 1 MΩ and 33 V is the voltage supplied.
There is a 5 V drop across the Zener diode. This means that
there is 28 µA flowing through the 1 MΩ resistor (0.784 mW
VBOOST_A
(EXTERNAL SUPPLY)
SWA (OPEN CIRCUIT)
R3
R2
DAC A
IOUT_A
CURRENT OUTPUT
R1
RLOAD
R1
RSET_A
CHART A
DAC CHANNEL A
SWGNDA
COMPDCDC_A (OPEN CIRCUIT)
Figure 2. Configuration of a Channel using an External Zener Diode on the AD5755-1
Rev. 0 | Page 4 of 8
12049-002
AVCC
Application Note
AN-1289
The PMOS chosen must be able to tolerate a VDS voltage of
–VBOOST and handle the power dissipation required. The PMOS
typically has minimal effect on current output performance.
Figure 3 shows the AD5757/AD5737 which have pins (IGATEx)
dedicated to controlling an external PMOS. Therefore, a Zener
diode is not required. The IGATEx pins are only used when the
dynamic power control feature is not being used. It holds the
gate of the external PMOS at VBOOST – 5 V causing the majority
of the power dissipation to take place on the external PMOS.
VBOOST_A
(EXTERNAL SUPPLY)
SWA (OPEN CIRCUIT)
R3
R2
DAC A
IOUT_A
(VBOOST_A –5V)
IGATEA
CURRENT OUTPUT
R1
RLOAD
RSET_A
CHART A
DAC CHANNEL A
SWGNDA
COMPDCDC_A (OPEN CIRCUIT)
Figure 3. Configuration of a Channel using IGATE (AD5757 or AD5737)
Rev. 0 | Page 5 of 8
12049-003
AVCC
The setup and calculations are the same as in the PMOS/Zener
diode configuration.
AN-1289
Application Note
METHOD 2—CONNECTING VBOOST TO AVDD
With Method 2, although no extra components are required,
all power is dissipated on chip. Users must be aware of the
maximum allowed power dissipation and ambient temperatures
if this method is used. Exceeding the absolute maximum ratings
specified in the data sheet can damage components.
VBOOST must be powered for both voltage and current output
ranges. VBOOST can be tied to AVDD as long as sufficient headroom is maintained between VBOOST and the output per the
formula in Table 2.
Leave the SWx and COMPDCDC_A pins open circuit. Tie AVCC to
DVDD. This maintains the voltage on the AVCC pin above the
most negative supply, AVSS or 0 V (this applies only to the
AD5755-1, AD5737, and AD5757). If the voltage on the AVCC
pin is equal to or below the most negative voltage, it can result
in latch-up. See Table 2 for recommended supplies for the AVCC
and VBOOST rails. All other pins are set up in the same manner as
when the dynamic power control function is used. Details are
outlined in the Pin Configuration section and Layout
Guidelines section of the AD5755 data sheet.
The AD5755 is packaged in a 64-lead, 9 mm × 9 mm LFCSP.
The thermal impedance, θJA, is 28°C/W. It is important that
the device is not operated under conditions that exceed the
junction temperature limit (125°C).
Worst-case conditions occur when the AD5755 is at maximum
VBOOST (33 V) and driving the maximum current (24 mA) to
ground (RLOAD = 0Ω). The quiescent current of the AD5755
must also be taken into account.
The calculations in Table 3 estimate maximum power dissipation under these worst-case conditions, and determine
maximum ambient temperature based on this information.
These figures assume that proper layout and grounding
techniques are followed to minimize power dissipation as
outlined in the Layout Guidelines section of the AD5755 data
sheet. It also refers to the operating currents as specified in the
AD5755 data sheet.
Note that if dynamic power control is not used, then it is of
even greater importance to understand the effects of power
dissipation.
AVCC
SWA (OPEN CIRCUIT)
VBOOST_A
(EXTERNAL SUPPLY)
R2
R3
DAC A
IOUT
RLOAD
R1
RSET_A
SWGNDA
COMPDCDC_A (OPEN CIRCUIT)
Figure 4. AD5755 without Dynamic Power Control on One Channel
Rev. 0 | Page 6 of 8
12049-004
DAC CHANNEL A
Application Note
AN-1289
Table 2. Changes in Power Supplies
Parameter
AVCC
VBOOST
Recommended Minimum/Maximum Voltage
DVDD to 5.5 V
7.4 V (minimum) to 33 V (maximum)
Current output
(IOUT × RLOAD) + Headroom
Typically 2.4 V headroom, maximum 2.7 V headroom
Voltage output
Typically 15 V, maximum VOUT + headroom
Maximum 2.2 V headroom
Table 3. Thermal and Supply Conditions (Assuming AVSS = −15 V, AVCC = 5 V, and AVDD/VBOOST = 33 V)
Parameter
Maximum Allowable Power Dissipation when Operating at
an Ambient Temperature of 85°C
Calculation
Maximum Allowable Ambient Temperature—One Channel
AVDD
TJMAX − TA
θJA
=
125 − 85
= 1.42 W
28
33 V × 0.0075 A = 0.2475 W
AVSS
−15 V × 0.0017 A = 0.0255 W
AVCC
5 V × 0.001 A = 0.005 W
VBOOST1 (1 channel)
33 V × 0.025 A = 0.825 W
Total (1 channel)
1.103 W
Temperature increase
1.103 × 28 = 30.9°C
Maximum ambient temperature
125°C – 30.9°C = 94.1°C
Maximum Allowable Ambient Temperature—Four Channels
AVDD
33 V × 0.0075 A = 0.2475 W
AVSS
−15 V × 0.0017 A = 0.0255 W
AVCC
5 V × 0.001 A = 0.005 W
VBOOST1 (4 channels)
(33 V × 0.025 A) × 4 = 3.3 W
Total (4 channels)
3.578 W
Temperature increase
3.578W × 28 = 100.18°C
Maximum ambient temperature
125°C – 100.18°C = 24.816°C
Includes 1 mA VBOOST quiescent current.
1
Rev. 0 | Page 7 of 8
AN-1289
Application Note
NOTES
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registered trademarks are the property of their respective owners.
AN12049-0-3/14(0)
Rev. 0 | Page 8 of 8
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