INFINEON FZE1658G

FZE 1658G
8 x Digital Sensor Interface
Features
●
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Input protection against 2000 V burst/500 V surge
pulse according to IEC 801 4/5
Input characteristic according to IEC 65 A, type 2
(24 V DC)
Digital filter
Serial in/out for easy cascading
Low power dissipation
SMD package
P-DSO-24-1
Type
Ordering Code
Package
FZE 1658G
Q67000-A8361
P-DSO-24-1
The FZE 1658G is an integrated interface for digital sensors - i.e. proximity switches - in
industrial automation equipment. The IC has eight integrated highly protected and
failsafe inputs with status LED and a serial synchronous output for direct MC-interfacing.
Semiconductor Group
1
01.97
FZE 1658G
Pin Configuration
(top view)
Semiconductor Group
2
FZE 1658G
Pin Definitions and Functions
Pin
Symbol Function
15, 13, 11, 9,
5, 3, 1, 23
I0 - I7
Inputs for 24-V signals, in conjunction with RV and REXT
current sink characteristic.
16, 14, 12,
10, 6, 4, 2, 24
L0 - L7
Outputs for the status LEDs; LED lights when H-signal is
present at input.
21
CT
Pin for connecting the frequency-determining capacitor for
the filter clock; also reset input if CT is connected to DGND.
7
GND
Ground for all 24-V signals, substrate.
22
DGND
Ground for all 5-V signals, no internal connection to GND.
Any interruption of GND or DGND with the supply voltage
present may result in destruction of the device.
8
VS
Supply voltage; undervoltage activates internal reset.
20
SO-N
Serial output, open drain.
17
SE-N
Extention input for serial cascading with pull-up current
source.
18
LO-N
Latch input, edge H-L results in transfer of data from the
digital filters to the output register.
19
T
Clock for serial output, positive edge triggered.
Semiconductor Group
3
FZE 1658G
Functional Description and Application
The Integrated circuit FZE 1658G is used to detect the signal states of eight independent
input lines according to IEC 65A Type 2 (e.g. two-wire proximity switches) with a
common ground (GND). For operation in accordance with IEC 65A, it is necessary for
the device to be wired with resistors rated RV = 820 Ω and REXT = 4.4 kΩ with ± 2 %
tolerance and 200 ppm TK. The input device has the following characteristics:
–
–
–
–
–
Minimization of power dissipation due to constant current characteristic
Inputs protected against reverse polarity and transient overvoltages
Status LED output for each input
Digital averaging of the input signals to suppress interference pulses
Serial output of the detected signals (cascadable)
Maximum voltage ratings at inputs D0 ... D7 within test circuit 2.
Voltage Range
Notes
DC voltage
– 3 V … + 32 V
– 32 V … + 32 V
full function
non-destructive, no latch-up
Overvoltage 500 ms
– 3 V … + 35 V
– 35 V … + 35 V
full function
non-destructive, no latch-up
Overvoltage 1.3 ms
to VDE 0160
– 3 V … + 55 V
± 55
full function
non-destructive, no latch-up
Surge pulse 50 µs
to IEC 801-5, Zi = 2 Ω
± 0.5 kV
1)
Burst pulse 50 ns
to IEC 801-4, Zi = 50 Ω
± 2 kV
2)
1)
Non-destructive in temperature range 15 °C ≤ TA ≤ 35 °C.
2)
In temperature range 15 °C ≤ TA ≤ 35 °C:
Data retained if the supply voltage remains within the operating range; without supply voltage
non-destructive.
The rated voltage may be applied to all inputs simultaneously.
The values given in the table may be regarded as guaranteed, but are only checked as
part of a qualification (no 100 % series testing).
Within the application circuit given the same voltage ratings as above apply for the
supply line.
Semiconductor Group
4
FZE 1658G
Circuit Description
In IEC 65A, the following values are specified for 24-VDC input stages of type 2:
Level
Input Voltage
Input Current
1
0
min. 11 V
max. 11 V
or max. 5 V
min. 6 mA
max. 2 mA
The current in the input circuit is determined by the switching element in state “0” and by
characteristics of the input stage in state “1”.
The octal input device FZE 1658G is intended for a configuration comprising two
specified external resistors per channel, as shown in the block diagram. As a result the
power dissipation within the P-DSO-24-1 package is at a minimum.
The voltage dependent current through the external resistor REXT is compensated by a
negative differential resistance of the current sink across pins E and L, therefore input D
behaves like a constant current sink.
The comparator assigns level 1 or 0 to the voltage present at input E. To improve
interference protection, the comparator is provided with hysteresis and a delay element.
A status LED is connected in series with the input circuit (REXT and current sink). The
LED drive short-circuits the status LED if the comparator detects “0”. A constant current
sink in parallel with the LED reduces the operating current of the LED, and a voltage
limiter ensures that the input circuit remains operational if the LED is interrupted. The
specified switching thresholds may change if the LED is interrupted.
For each channel a digital filter is provided which samples the comparator signal at a rate
provided by the clock oscillator. The digital filter is designed as a 5-section shift register.
If any four out of 5 sampling values are identical, the output S changes to the
corresponding state.
On a falling edge at input LO-N, the parallel data S0 - S7 are clocked into the output shift
register. The data can be shifted out serially to the output SO-N by the clock signal T,
with a “1” at the input being represented by a L-signal at the output SO-N. The serial
interface of the shift register fits the synchronous interface of the 8051 microcontroller
(see diagram Serial Data Output Function). By connecting output SO-N to input SEN of the next device, several FZE 1658G can be cascaded (see Application Circuit).
SO-N is designed as an open-drain output. SE-N has an internal pull-up current source.
Inputs SE-N, T and SO-N have Schmitt trigger characteristics. The device has separate
ground pins for the input circuitry (GND) and for the logic (DGND). If the supply voltage
falls below VUSR or CT is connected to DGND, the output shift register will be cleared and
the output SO-N disabled. If the supply voltage is too low, the LED drives will also be
disabled, i.e. the LED lights as soon as current flows in the input circuit.
Semiconductor Group
5
FZE 1658G
Block Diagram
Semiconductor Group
6
FZE 1658G
Absolute Maximum Ratings
Tj = – 40 to 150 °C
Parameter
Symbol
Limit Values
min.
max.
Unit Notes
Transient input current
inputs I0 - I7
II
– 0.6
– 1.2
– 2.5
0.6
1.2
2.5
A
A
A
t50 % ≤ 50 µs
t50 % ≤ 1.2 µs
t50 % ≤ 50 ns
Ground current
IGND
–5
– 10
5
10
A
A
t50 % ≤ 50 µs
t50 % ≤ 50 ns
Junction temperature
Tj
– 40
150
°C
Storage temperature
TS
– 50
125
°C
Thermal resistance
System/air
Rthja
95
K/W
soldered-in
Transient thermal resistance;
Same current through all
inputs I0 - I7
Zth
Zth
0.15
0.4
K/W
K/W
50 µs pulse
120 µs pulse
Supply voltage
VS
– 0.3
65
V
Ground offset DGND to GND
VDGND
–4
4
V
VDGND < VS
Current at the LED outputs
IL
– 15
– 500
– 250
– 125
15
500
250
125
mA
mA
mA
mA
t50 % ≤ 50 µs
t50 % ≤ 1.2 µs
t50 % ≤ 50 µs
Voltage at
T, LO-N, SO-N, SE-N
VLOG
–4
– 0.3
9
9
V
V
referred to DGND
Capacitance at CT
CCT
2
µF
when VS falls
below VCT
ESD voltage 100 pF / 1.5 kΩ
VESD
1000
V
MIL Std. 883
Meth. 3015
1000
All voltages are, unless otherwise specified, referred to GND. This also applies to the
operating range and the characteristics.
Semiconductor Group
7
FZE 1658G
Operating Range
Parameter
Symbol
Limit Values
min.
max.
Unit Notes
Supply voltage
VS
10
48
V
Supply voltage rise
SRVS
– 0.1
1
V/µs
Supply voltage
VS-VDGND
9
GND potential difference
VDGND
– 1.5
1.5
V
Input terminal current
IIT
– 10
10
mA
Input voltage SE-N, T, LO-N
VIH
VIL
2.8
– 0.5
6
1.7
V
V
Input current SE-N, T, LO-N
II
–1
1
mA
Junction temperature
Tj
– 25
150
°C
Ambient temperature
TA
– 25
105
°C
Clock frequency
fT
1
MHz
Clock pulse width H or L
tTH, tTL
300
ns
SE-N set up time to T ↑
tVSE
300
ns
LO-N set up time to T ↑
tVLO
1.2
µs
SE-N, LO-N, T rise and fall time tr, tf
within thresholds
V
3
µs
Note power
dissipation1)
2)
Clamp current
Dependent on Rth
3)
1)
Input voltages may rise before the supply voltage.
Full function at VS > VVSRO (see Characteristics).
2)
Limits GND potential difference at minimum supply voltage.
3)
Also applies to several cascaded FZE 1658G (note dependence with clock frequency).
For definition of timing items, see timing diagram.
Semiconductor Group
8
FZE 1658G
Characteristics
VS = 15 V to 30 V; VDGND = 0, Tj = – 25 °C < Tj < 125 °C
Parameter
Symbol
Limit Values
min.
typ.
max.
Unit Test Condition Test
Circuit
Inputs I0 - I7 or D0 - D7 Respectively
Switching
threshold H
VDH
Switching
threshold L
VDL
8
V
VL ≤ 2.2 V
2
Hysteresis
VDHY
1
V
VL ≤ 2.2 V
2
Switching
threshold L
IDLL
2.5
mA
ILED = 0
2
Input current
IDH
6.21)
8
mA
VL ≤ 3.5 V,
2
VD = 11 … 30 V
Input current
IDL
5
7
mA
VL = VLL,
VD = 5 V
2
Input current
IIC +
1
mA
VI = 30 V 2)
1
75
V
II = 10 mA,
Tj = 25 °C 2)
1
mA
VI = – 30 V 2)
1
V
II = – 10 mA,
Tj = 25 °C 2)
1
10.85 V
Input clamp voltage VIT +
35
IIC –
–1
Input current
2
1)
Input clamp voltage VIT –
– 75
– 35
1)
Headroom to IEC 65 A for tolerance of ext. resistor.
2)
Also valid at VS = 0.
Semiconductor Group
9
FZE 1658G
Characteristics (cont’d)
VS = 15 V to 30 V; VDGND = 0, Tj = – 25 °C < Tj < 125 °C
Parameter
Symbol
Limit Values
min.
typ.
max.
Unit Test Condition Test
Circuit
LED Drive L0 - L7
Open-load voltage
VLO
3.5
5
V
VD = 24 V,
ILED = 0
2
“Low”- voltage
VLL
0
0.75
V
VD = 5 V,
ILED = 0
2
Output current
ILED
3
5
mA
VD = 11 … 30 V, 2
VL = 1.5 … 3 V
Output current
ILED
1.5
6
mA
VD = 11 … 30 V, 2
VL = 1.2 … 3.5 V
Power down
output current
IL
– 0.12
mA
VS < VVSRU
1
Propagation delay
rising and falling
edge
tDL
7.5
75
µs
VD = 12 V ←
→ 7V
2
CT source/sink
current
ICT
150
250
µA
Frequency
fCT
1
1.5
kHz
Upper switching
threshold
VCTP
3.3
4.3
V
2
Lower switching
threshold
VCTN
1.4
2.2
V
2
Reset threshold
VCTR
0.8
1.4
V
1
Reset input current
ICTR
– 300
– 150 µA
VCT = 0.8 V
1
Signal delay
tDFI
2
4
CT = 39 nF
2
Oscillator
Semiconductor Group
10
ms
1
CT = 39 nF
2
FZE 1658G
Characteristics (cont’d)
VS = 15 V to 30 V; VDGND = 0, Tj = – 25 °C < Tj < 125 °C
Parameter
Symbol
Limit Values
min.
typ.
max.
Unit Test Condition Test
Circuit
5-V Logic
Input current
T, LO-N
II
– 10
10
µA
Vi = 0 … 5 V
1
Input current SE-N
IISE
– 600
– 400 µA
Vi = 0 … 3 V
1
Input current
T, LO-N, SE-N
II0
0
20
µA
Vi = 0 … 5 V
VS = 0 V
1
Input capacitance
CI
10
pF
L-output current
SO-N
ISOL
5.5
8
mA
VQ = 3 … 5 V
1
L-output level SO-N VSOL
0
0.5
V
ISO = 2 mA
1
H-leakage current
SO-N
ISOH
0
50
µA
VSO = 5 V
1
Output
capacitance SO-N
CSOH
20
pF
VSO = 1.5 V
1
Rise/fall time of
output current
SO-N
trSO, tfSO
50
ns
VSO = 2.5 V
1
Delay time
T to SO-N
(see timing
diagram)
tSOT
150
ns
VSO = 2.5 V
1
Delay time
LO-N to SO-N
(see timing
diagram)
tSOLO
300
ns
VSO = 2.5 V
1
mV
no 100% testing
Hysteresis SE-N,
LO-N
Semiconductor Group
60
11
1
FZE 1658G
Characteristics (cont’d)
VS = 15 V to 30 V; VDGND = 0, Tj = – 25 °C < Tj < 125 °C
Parameter
Symbol
Limit Values
min.
Hysteresis
Clock input
typ.
max.
200
Unit Test Condition Test
Circuit
mV
no 100% testing
Voltage Supply
Current drain static
IS
2
5
mA
VS = 10 … 30 V 2
VLO-N = 5 V
VT = 5 V
ISE-N = 0
Current drain
during serial
readout
IS
2
6
mA
VS = 10 … 40 V 2
VLO-N = 0 V
fT = 1 MHz
Current drain
during high supply
voltage
ISMAX
7
mA
VS < 45 V
2
Logic ground
current
IDGND
0
mA
VDGND =
1
Under voltage
lockout
VVSRO
– 2.5
– 1.5 … 1.5 V,
LO-N = H
10
V
VVSRU
8
V
VVSRH
0.2
V
Semiconductor Group
12
upper switching
treshold
lower switching
threshold
hysteresis
2
2
2
FZE 1658G
Test Circuit 1
Test Circuit 2
Semiconductor Group
13
FZE 1658G
Application Circuit
Supply Voltage Decoupling Circuit
Cascading Multiple FZE 1658G
Semiconductor Group
14
FZE 1658G
Serial Data Output Function
Semiconductor Group
15
FZE 1658G
Timing Diagram
Semiconductor Group
16
FZE 1658G
Input Characteristic with Worst-Case
Values per IEC 65A Input D Rest Circuit D
Semiconductor Group
17
FZE 1658G
Package Outlines
GPS05144
Plastic-Package, P-DSO-24-1 (SMD)
(Plastic Dual Small Outline Package)
Sorts of Packing
Package outlines for tubes, trays etc. are contained in our
Data Book “Package Information”.
SMD = Surface Mounted Device
Semiconductor Group
18
Dimensions in mm