5 kV, 7-Channel, SPIsolator Multiple Slave, Digital Isolator for SPI ADuM4154 Data Sheet FUNCTIONAL BLOCK DIAGRAM Supports up to 17 MHz SPI clock speed 4 high speed, low propagation delay, SPI signal isolation channels Supports up to 4 slave devices 20-lead SOIC_IC package with 8.3 mm creepage High temperature operation: 125°C High common-mode transient immunity: >25 kV/µs Safety and regulatory approvals UL recognition per UL 1577 5000 V rms for 1 minute SOIC long package CSA Component Acceptance Notice 5A VDE certificate of conformity DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 VIORM = 849 V peak VDD1 1 GND1 2 ADuM4154 20 VDD2 ENCODE DECODE 19 GND2 SCLK MCLK 3 ENCODE DECODE 18 MO 4 DECODE ENCODE 17 SI DECODE 16 SO MSS 6 15 SS0 SSA0 7 14 SS1 13 SS2 MI 5 SSA1 8 ENCODE MUX CONTROL BLOCK NIC 9 GND1 10 CONTROL BLOCK 12 SS3 11 GND2 12366-001 FEATURES Figure 1. APPLICATIONS Industrial programmable logic controllers (PLCs) Sensor isolation GENERAL DESCRIPTION The ADuM41541 is an SPIsolator™ digital isolator optimized for a serial peripheral interface (SPI) that includes support for up to four slave devices. Based on the Analog Devices, Inc., iCoupler® chip scale transformer technology, the low propagation delay and jitter in the CLK, MO/SI, MI/SO, and SS SPI bus signals support SPI clock rates of up to 17 MHz. The ADuM4154 isolator also provides a slave select multiplexing system that allows up to four slave devices to be serviced from one isolator. When a target slave is selected, the slave select signal propagates to the desired output with low propagation delay, allowing tight timing control. The isolated SSx is addressed through a 250 kbps low speed, 2-channel address bus, allowing the target slave device to be changed in as little as 2.5 µs. 1 Table 1. Related Products Product ADuM3150 ADuM3151/ADuM3152/ ADuM3153 ADuM3154 ADuM4150 ADuM4151/ADuM4152/ ADuM4153 Description 3.75 kV, high speed, clock delayed SPIsolator 3.75 kV, multichannel SPIsolator 3.75 kV, multiple slave SPIsolator 5 kV, high speed, clock delayed SPIsolator 5 kV, multichannel SPIsolator Protected by U.S. Patents 5,952,849; 6,262,600; 6,873,065; and 7075329. Other patents are pending. Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2014–2015 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com ADuM4154 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Absolute Maximum Ratings ......................................................... 13 Applications ....................................................................................... 1 ESD Caution................................................................................ 13 Functional Block Diagram .............................................................. 1 Pin Configuration and Function Descriptions........................... 14 General Description ......................................................................... 1 Typical Performance Characteristics ........................................... 16 Revision History ............................................................................... 2 Applications Information .............................................................. 17 Specifications..................................................................................... 3 Introduction ................................................................................ 17 Electrical Characteristics—5 V Operation................................ 3 Printed Circuit Board (PCB) Layout ....................................... 19 Electrical Characteristics—3.3 V Operation ............................ 5 Propagation Delay Related Parameters ................................... 19 Electrical Characteristics—Mixed 5 V/3.3 V Operation ........ 7 DC Correctness and Magnetic Field Immunity ..................... 19 Electrical Characteristics—Mixed 3.3 V/5 V Operation ........ 9 Power Consumption .................................................................. 20 Package Characteristics ............................................................. 10 Insulation Lifetime ..................................................................... 20 Regulatory Information ............................................................. 11 Outline Dimensions ....................................................................... 22 Insulation and Safety Related Specifications .......................... 11 Ordering Guide .......................................................................... 22 DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 Insulation Characteristics ............................................................................ 12 Recommended Operating Conditions .................................... 12 REVISION HISTORY 3/15—Rev. 0 to Rev. A Changes to Features Section and Table 1 ...................................... 1 Changes to Supply Current Parameter, Table 3 ............................ 4 Changes to Supply Current Parameter, Table 5 ............................ 6 Changes to Supply Current Parameter, Table 7 ............................ 8 Changes to Supply Current Parameter, Table 9 .......................... 10 Changes to Table 11 ........................................................................ 11 Changes to Table 13 ........................................................................ 12 Changes to High Speed Channels Section .................................. 17 10/14—Revision 0: Initial Version Rev. A | Page 2 of 22 Data Sheet ADuM4154 SPECIFICATIONS ELECTRICAL CHARACTERISTICS—5 V OPERATION All typical specifications are at TA = 25°C and VDD1 = VDD2 = 5 V. Minimum and maximum specifications apply over the entire recommended operation range: 4.5 V ≤ VDD1 ≤ 5.5 V, 4.5 V ≤ VDD2 ≤ 5.5 V, and −40°C ≤ TA ≤ +125°C, unless otherwise noted. Switching specifications are tested with CL = 15 pF and CMOS signal levels, unless otherwise noted. Table 2. Switching Specifications Parameter MCLK, MO, SO SPI Clock Rate Data Rate Fast (MO, SO) Propagation Delay Pulse Width Pulse Width Distortion Codirectional Channel Matching1 Jitter, High Speed MSS Data Rate Fast Propagation Delay Pulse Width Pulse Width Distortion Setup Time2 Jitter, High Speed SSA0, SSA1 Data Rate Slow Propagation Delay Pulse Width Jitter, Low Speed SSAx3 Minimum Input Skew4 Symbol SPIMCLK DRFAST tPHL, tPLH PW PWD tPSKCD JHS DRFAST tPHL, tPLH PW PWD MSSSETUP JHS DRSLOW tPHL, tPLH PW JLS tSSAx SKEW3 Min A Grade Typ Max Min 1 2 25 100 B Grade Typ Max 12 12.5 2 2 2 2 1 1 21 2 26 100 21 1.5 3 10 1 1 250 2.6 0.1 4 2.5 40 34 26 12.5 3 0.1 4 17 34 14 250 2.6 2.5 40 Unit MHz Mbps ns ns ns ns ns Test Conditions/Comments Within PWD limit 50% input to 50% output Within PWD limit |tPLH − tPHL| Mbps ns ns ns ns ns Within PWD limit 50% input to 50% output Within PWD limit |tPLH − tPHL| kbps µs µs µs ns Within PWD limit 50% input to 50% output Within PWD limit Codirectional channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier. The MSS signal is glitch filtered in both speed grades, whereas the other fast signals are not glitch filtered in the B grade. To guarantee that MSS reaches the output ahead of another fast signal, set up MSS prior to the competing signal by different times depending on speed grade. 3 SSAx = SSA0 or SSA1. 4 An internal asynchronous clock, not available to users, samples the low speed signals. If edge sequence in codirectional channels is critical to the end application, the leading pulse must be at least 1 tSSAx SKEW ahead of a later pulse to guarantee the correct order or simultaneous arrival at the output. 1 2 Rev. A | Page 3 of 22 ADuM4154 Data Sheet Table 3. For All Models1, 2, 3 Parameter SUPPLY CURRENT A Grade and B Grade B Grade DC SPECIFICATIONS MCLK, MSS, MO, SO, SSA0, SSA1 Input Threshold Logic High Logic Low Input Hysteresis Input Current per Channel SCLK, MI, SI, SS0, SS1, SS2, SS3 Output Voltages Logic High Logic Low VDD1, VDD2 Undervoltage Lockout Supply Current per High Speed Channels Dynamic Input Dynamic Output Supply Current for All Low Speed Channels Quiescent Input Quiescent Output AC SPECIFICATIONS Output Rise/Fall Time Common-Mode Transient Immunity4 Symbol Min Typ Max Unit Test Conditions/Comments IDD1 4.8 8.5 mA IDD2 6.5 13 mA IDD1 10 18 mA IDD2 13.5 19 mA CL = 0 pF, DRFAST = 1 MHz, DRSLOW = 0 MHz CL = 0 pF, DRFAST = 1 MHz, DRSLOW = 0 MHz CL = 0 pF, DRFAST = 17 MHz, DRSLOW = 0 MHz CL = 0 pF, DRFAST = 17 MHz, DRSLOW = 0 MHz VIH VIL VIHYST II 0.7 × VDDx VOH VDDx − 0.1 VDDx − 0.4 +1 V V mV µA 0.1 0.4 2.6 V V V V V 0.3 × VDDx −1 VOL 500 +0.01 5.0 4.8 0.0 0.2 UVLO IDDI(D) IDDO(D) 0.080 0.046 mA/Mbps mA/Mbps IDD1(Q) IDD2(Q) 4.2 6.1 mA mA 2.5 35 ns kV/µs tR/tF |CM| 25 0 V ≤ VINPUT ≤ VDDx IOUTPUT = −20 µA, VINPUT = VIH IOUTPUT = −4 mA, VINPUT = VIH IOUTPUT = 20 µA, VINPUT = VIL IOUTPUT = 4 mA, VINPUT = VIL 10% to 90% VINPUT = VDDx, VCM = 1000 V, transient magnitude = 800 V VDDx = VDD1 or VDD2. VINPUT is the input voltage of any of the MCLK, MSS, MO, SO, SSA0, or SSA1 pins. 3 IOUTPUT is the output current of any of the SCLK, MI, SI, SS0, SS1, SS2, or SS3 pins. 4 |CM| is the maximum common-mode voltage slew rate that can be sustained while maintaining output voltages within the VOH and VOL limits. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. 1 2 Rev. A | Page 4 of 22 Data Sheet ADuM4154 ELECTRICAL CHARACTERISTICS—3.3 V OPERATION All typical specifications are at TA = 25°C and VDD1 = VDD2 = 3.3 V. Minimum and maximum specifications apply over the entire recommended operation range: 3.0 V ≤ VDD1 ≤ 3.6 V, 3.0 V ≤ VDD2 ≤ 3.6 V, and −40°C ≤ TA ≤ +125°C, unless otherwise noted. Switching specifications are tested with CL = 15 pF and CMOS signal levels, unless otherwise noted. Table 4. Switching Specifications Parameter MCLK, MO, SO SPI Clock Rate Data Rate Fast (MO, SO) Propagation Delay Pulse Width Pulse Width Distortion Codirectional Channel Matching1 Jitter, High Speed MSS Data Rate Fast Propagation Delay Pulse Width Pulse Width Distortion Setup Time2 Jitter, High Speed SSA0, SSA1 Data Rate Slow Propagation Delay Pulse Width Jitter, Low Speed SSAx3 Minimum Input Skew4 Symbol SPIMCLK DRFAST tPHL, tPLH PW PWD tPSKCD JHS DRFAST tPHL, tPLH PW PWD MSSSETUP JHS DRSLOW tPHL, tPLH PW JLS tSSAx SKEW3 Min A Grade Typ Max Min B Grade Typ Max 1 2 30 100 12.5 34 21 12.5 3 3 2 2 1 1 2 34 100 34 34 12.5 3 1.5 3 10 1 0.1 4 1 250 2.6 0.1 4 2.5 40 250 2.6 2.5 40 Unit MHz Mbps ns ns ns ns ns Test Conditions/Comments Within PWD limit 50% input to 50% output Within PWD limit |tPLH − tPHL| Mbps ns ns ns ns ns Within PWD limit 50% input to 50% output Within PWD limit |tPLH − tPHL| kbps µs µs µs ns Within PWD limit 50% input to 50% output Within PWD limit Codirectional channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier. 2 The MSS signal is glitch filtered in both speed grades, whereas the other fast signals are not glitch filtered in the B grade. To guarantee that MSS reaches the output ahead of another fast signal, set up MSS prior to the competing signal by different times depending on speed grade. 3 SSAx = SSA0 or SSA1. 4 An internal asynchronous clock, not available to users, samples the low speed signals. If edge sequence in codirectional channels is critical to the end application, the leading pulse must be at least 1 tSSAx SKEW ahead of a later pulse to guarantee the correct order or simultaneous arrival at the output. 1 Rev. A | Page 5 of 22 ADuM4154 Data Sheet Table 5. For All Models1, 2, 3 Parameter SUPPLY CURRENT A Grade and B Grade B Grade DC SPECIFICATIONS MCLK, MSS, MO, SO, SSA0, SSA1 Input Threshold Logic High Logic Low Input Hysteresis Input Current per Channel SCLK, MI, SI, SS0, SS1, SS2, SS3 Output Voltages Logic High Logic Low VDD1, VDD2 Undervoltage Lockout Supply Current per High Speed Channel Dynamic Input Dynamic Output Supply Current for All Low Speed Channels Quiescent Input Quiescent Output AC SPECIFICATIONS Output Rise/Fall Time Common-Mode Transient Immunity4 Symbol Min Typ Max Unit Test Conditions/Comments IDD1 3.4 6.5 mA IDD2 5 9 mA IDD1 11.7 15 mA IDD2 10 14 mA CL = 0 pF, DRFAST = 1 MHz, DRSLOW = 0 MHz CL = 0 pF, DRFAST = 1 MHz, DRSLOW = 0 MHz CL = 0 pF, DRFAST = 17 MHz, DRSLOW = 0 MHz CL = 0 pF, DRFAST = 17 MHz, DRSLOW = 0 MHz VIH VIL VIHYST II 0.7 × VDDx VOH VDDx − 0.1 VDDx − 0.4 0.3 × VDDx −1 500 +0.01 +1 V V mV µA UVLO 5.0 4.8 0.0 0.2 2.6 IDDI(D) IDDO(D) 0.078 0.026 mA/Mbps mA/Mbps IDD1(Q) IDD2(Q) 2.9 4.7 mA mA 2.5 35 ns kV/µs VOL tR/tF |CM| 25 0.1 0.4 V V V V V 0 V ≤ VINPUT ≤ VDDx IOUTPUT = −20 µA, VINPUT = VIH IOUTPUT = −4 mA, VINPUT = VIH IOUTPUT = 20 µA, VINPUT = VIL IOUTPUT = 4 mA, VINPUT = VIL 10% to 90% VINPUT = VDDx, VCM = 1000 V, transient magnitude = 800 V VDDx = VDD1 or VDD2. VINPUT is the input voltage of any of the MCLK, MSS, MO, SO, SSA0, or SSA1 pins. 3 IOUTPUT is the output current of any of the SCLK, MI, SI, SS0 SS1, SS2, or SS3 pins. 4 |CM| is the maximum common-mode voltage slew rate that can be sustained while maintaining output voltages within the VOH and VOL limits. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. 1 2 Rev. A | Page 6 of 22 Data Sheet ADuM4154 ELECTRICAL CHARACTERISTICS—MIXED 5 V/3.3 V OPERATION All typical specifications are at TA = 25°C and VDD1 = 5 V, VDD2 = 3.3 V. Minimum and maximum specifications apply over the entire recommended operation range: 4.5 V ≤ VDD1 ≤ 5.5 V, 3.0 V ≤ VDD2 ≤ 3.6 V, and −40°C ≤ TA ≤ +125°C, unless otherwise noted. Switching specifications are tested with CL = 15 pF and CMOS signal levels, unless otherwise noted. Table 6. Switching Specifications Parameter MCLK, MO, SO SPI Clock Rate Data Rate Fast (MO, SO) Propagation Delay Pulse Width Pulse Width Distortion Codirectional Channel Matching1 Jitter, High Speed MSS Data Rate Fast Propagation Delay Pulse Width Pulse Width Distortion Setup Time2 Jitter, High Speed SSA0, SSA1 Data Rate Slow Propagation Delay Pulse Width Jitter, Low Speed SSAx3 Minimum Input Skew4 Symbol SPIMCLK DRFAST tPHL, tPLH PW PWD tPSKCD JHS DRFAST tPHL, tPLH PW PWD MSSSETUP JHS DRSLOW tPHL, tPLH PW JLS tSSAx SKEW3 Min A Grade Typ Max Min B Grade Typ Max 1 2 27 25 15.6 34 17 12.5 2 2 2 2 1 1 2 30 25 34 30 12.5 2 1.5 2 10 1 0.1 4 1 250 2.6 0.1 4 2.5 40 250 2.6 2.5 40 Unit MHz Mbps ns ns ns ns ns Test Conditions/Comments Within PWD limit 50% input to 50% output Within PWD limit |tPLH − tPHL| Mbps ns ns ns ns ns Within PWD limit 50% input to 50% output Within PWD limit |tPLH − tPHL| kbps µs µs µs ns Within PWD limit 50% input to 50% output Within PWD limit |tPLH − tPHL| Codirectional channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier. 2 The MSS signal is glitch filtered in both speed grades, whereas the other fast signals are not glitch filtered in the B grade. To guarantee that MSS reaches the output ahead of another fast signal, set up MSS prior to the competing signal by different times depending on speed grade. 3 SSAx = SSA0 or SSA1. 4 An internal asynchronous clock, not available to users, samples the low speed signals. If edge sequence in codirectional channels is critical to the end application, the leading pulse must be at least 1 tSSAx SKEW ahead of a later pulse to guarantee the correct order or simultaneous arrival at the output. 1 Rev. A | Page 7 of 22 ADuM4154 Data Sheet Table 7. For All Models1, 2, 3 Parameter SUPPLY CURRENT A Grade and B Grade B Grade DC SPECIFICATIONS MCLK, MSS, MO, SO, SSA0, SSA1 Input Threshold Logic High Logic Low Input Hysteresis Input Current per Channel SCLK, MI, SI, SS0, SS1, SS2, SS3 Output Voltages Logic High Logic Low VDD1, VDD2 Undervoltage Lockout Supply Current for All Low Speed Channels Quiescent Input Quiescent Output AC SPECIFICATIONS Output Rise/Fall Time Common-Mode Transient Immunity4 Symbol Min Typ Max Unit Test Conditions/Comments IDD1 4.8 8.5 mA IDD2 5 9 mA IDD1 10 18 mA IDD2 10 14 mA CL = 0 pF, DRFAST = 1 MHz, DRSLOW = 0 MHz CL = 0 pF, DRFAST = 1 MHz, DRSLOW = 0 MHz CL = 0 pF, DRFAST = 17 MHz, DRSLOW = 0 MHz CL = 0 pF, DRFAST = 17 MHz, DRSLOW = 0 MHz VIH VIL VIHYST II 0.7 × VDDx VOH VDDx − 0.1 VDDx − 0.4 0.3 × VDDx −1 500 +0.01 +1 V V mV µA UVLO 5.0 4.8 0.0 0.2 2.6 IDD1(Q) IDD2(Q) 4.2 4.7 mA mA 2.5 35 ns kV/µs VOL tR/tF |CM| 25 0.1 0.4 V V V V V 0 V ≤ VINPUT ≤ VDDX IOUTPUT = −20 µA, VINPUT = VIH IOUTPUT = −4 mA, VINPUT = VIH IOUTPUT = 20 µA, VINPUT = VIL IOUTPUT = 4 mA, VINPUT = VIL 10% to 90% VINPUT = VDDx, VCM = 1000 V, transient magnitude = 800 V VDDx = VDD1 or VDD2. VINPUT is the input voltage of any of the MCLK, MSS, MO, SO, SSA0, or SSA1 pins. 3 IOUTPUT is the output current of any of the SCLK, MI, SI, SS0, SS1, SS2, or SS3 pins. 4 |CM| is the maximum common-mode voltage slew rate that can be sustained while maintaining output voltages within the VOH and VOL limits. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. 1 2 Rev. A | Page 8 of 22 Data Sheet ADuM4154 ELECTRICAL CHARACTERISTICS—MIXED 3.3 V/5 V OPERATION All typical specifications are at TA = 25°C and VDD1 = 3.3 V, VDD2 = 5 V. Minimum and maximum specifications apply over the entire recommended operation range: 3.0 V ≤ VDD1 ≤ 3.6 V, 4.5 V ≤ VDD2 ≤ 5.5 V, and −40°C ≤ TA ≤ +125°C, unless otherwise noted. Switching specifications are tested with CL = 15 pF and CMOS signal levels, unless otherwise noted. Table 8. Switching Specifications Parameter MCLK, MO, SO SPI Clock Rate Data Rate Fast (MO, SO) Propagation Delay Pulse Width Pulse Width Distortion Codirectional Channel Matching1 Jitter, High Speed MSS Jitter Data Rate Fast Propagation Delay Pulse Width Pulse Width Distortion Setup Time2 Jitter, High Speed SSA0, SSA1 Data Rate Slow Propagation Delay Pulse Width Jitter, Low Speed SSAx3 Minimum Input Skew4 Symbol SPIMCLK DRFAST tPHL, tPLH PW PWD tPSKCD JHS Min A Grade Typ Max Min 1 2 28 100 15.6 34 17 12.5 2 2 2 2 1 1 1 DRFAST tPHL, tPLH PW PWD MSSSETUP JHS DRSLOW tPHL, tPLH PW JLS tSSAx SKEW3 B Grade Typ Max 1 2 28 100 21 12.5 2 1.5 2 10 1 0.1 4 1 250 2.6 0.1 4 2.5 40 34 28 250 2.6 2.5 40 Unit MHz Mbps ns ns ns ns ns ns Mbps ns ns ns ns ns kbps µs µs µs ns Test Conditions/Comments Within PWD limit 50% input to 50% output Within PWD limit |tPLH − tPHL| Within PWD limit 50% input to 50% output Within PWD limit |tPLH − tPHL| Within PWD limit 50% input to 50% output Within PWD limit |tPLH − tPHL| Codirectional channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier. The MSS signal is glitch filtered in both speed grades, whereas the other fast signals are not glitch filtered in the B grade. To guarantee that MSS reaches the output ahead of another fast signal, set up MSS prior to the competing signal by different times depending on speed grade. 3 SSAx = SSA0 or SSA1. 4 An internal asynchronous clock, not available to users, samples the low speed signals. If edge sequence in codirectional channels is critical to the end application, the leading pulse must be at least 1 tSSAx SKEW ahead of a later pulse to guarantee the correct order or simultaneous arrival at the output. 1 2 Rev. A | Page 9 of 22 ADuM4154 Data Sheet Table 9. For All Models1, 2, 3 Parameter SUPPLY CURRENT A Grade and B Grade Symbol B Grade DC SPECIFICATIONS MCLK, MSS, MO, SO, SSA0, SSA1 Input Threshold Logic High Logic Low Input Hysteresis Input Current per Channel SCLK, MI, SI, SS0, SS1, SS2, SS3 Output Voltages Logic High Logic Low Min Typ Max Unit Test Conditions/Comments IDD 3.4 6.5 mA IDD2 6.5 13 mA IDD 11.7 15 mA IDD2 13.5 19 mA CL = 0 pF, DRFAST = 1 MHz, DRSLOW = 0 MHz CL = 0 pF, DRFAST = 1 MHz, DRSLOW = 0 MHz CL = 0 pF, DRFAST = 17 MHz, DRSLOW = 0 MHz CL = 0 pF, DRFAST = 17 MHz, DRSLOW = 0 MHz VIH VIL VIHYST II 0.7 × VDDx VOH VDDx − 0.1 VDDx − 0.4 0.3 × VDDx 500 +0.01 −1 UVLO 5.0 4.8 0.0 0.2 2.6 IDD1Q) IDD2(Q) 2.9 6.1 mA mA 2.5 35 ns kV/µs VOL VDD1, VDD2 Undervoltage Lockout Supply Current for All Low Speed Channels Quiescent Input Quiescent Output AC SPECIFICATIONS Output Rise/Fall Time Common-Mode Transient Immunity4 +1 V V mV µA tR/tF |CM| 25 0.1 0.4 V V V V V 0 V ≤ VINPUT ≤ VDDx IOUTPUT = −20 µA, VINPUT = VIH IOUTPUT = −4 mA, VINPUT = VIH IOUTPUT = 20 µA, VINPUT = VIL IOUTPUT = 4 mA, VINPUT = VIL 10% to 90% VINPUT = VDDx, VCM = 1000 V, transient magnitude = 800 V VDDx = VDD1 or VDD2. VINPUT is the input voltage of any of the MCLK, MSS, MO, SO, SSA0, or SSA1 pins. 3 IOUTPUT is the output current of any of the SCLK, MI, SI, SS0, SS1, SS2, or SS3 pins. 4 |CM| is the maximum common-mode voltage slew rate that can be sustained whereas maintaining output voltages within the VOH and VOL limits. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. 1 2 PACKAGE CHARACTERISTICS Table 10. Parameter Resistance (Input to Output)1 Capacitance (Input to Output)1 Input Capacitance2 IC Junction to Ambient Thermal Resistance 1 2 Symbol RI-O CI-O CI θJA Min Typ 1012 1.0 4.0 46 Max Unit Ω pF pF °C/W Test Conditions/Comments f = 1 MHz Thermocouple located at center of package underside The device is considered a 2-terminal device: Pin 1 through Pin 10 are shorted together, and Pin 11 through Pin 20 are shorted together. Input capacitance is from any input data pin to ground. Rev. A | Page 10 of 22 Data Sheet ADuM4154 REGULATORY INFORMATION The ADuM4154 is approved and pending approval by the organizations listed in Table 11. See Table 16 and the Insulation Lifetime section for recommended maximum working voltages for specific cross isolation waveforms and insulation levels. Table 11. UL Recognized Under UL 1577 Component Recognition Program1 5000 V rms Single Protection File E214100 CSA Approved under CSA Component Acceptance Notice #5A Basic insulation per CSA 60950-1-07+A1+A2 and IEC 60950-12nd Ed+A1+A2., 800 V rms (1131 V peak) maximum working voltage3 CSA 60950-1-07+A1+A2 and IEC 60950-1 2nd Ed.+A1+A2, 400 V rms (565 V peak) maximum working voltage Reinforced insulation (2MOPP) per IEC 60601-1 Ed.3.1, 250 V rms (353 V peak) maximum working File 205078 VDE Certified according to DIN V VDE V 0884-10 (VDE V 0884-10):2006-122 Reinforced insulation, 849 V peak File 2471900-4880-0001 In accordance with UL 1577, each ADuM4154 is proof tested by applying an insulation test voltage ≥ 6000 V rms for 1 second (current leakage detection limit = 5 µA). In accordance with DIN V VDE V 0884-10, each ADuM4154 is proof tested by applying an insulation test voltage ≥ 1590 V peak for 1 second (partial discharge detection limit = 5 pC). The asterisk (*) marked on the component designates DIN V VDE V 0884-10 approval. 3 Use at working voltages above 400 VAC RMS shortens lifetime of the isolator significantly. See Table 16 for recommended maximum working voltages under ac and dc conditions. 1 2 INSULATION AND SAFETY RELATED SPECIFICATIONS Table 12. Parameter Rated Dielectric Insulation Voltage Minimum External Air Gap (Clearance) Symbol L(I01) Value 5000 8.3 Unit V rms mm min Minimum External Tracking (Creepage) L(I02) 8.3 mm min Minimum Internal Gap (Internal Clearance) Tracking Resistance (Comparative Tracking Index) Material Group CTI 0.017 >400 II mm min V Rev. A | Page 11 of 22 Test Conditions/Comments 1 minute duration Measured from input terminals to output terminals, shortest distance through air Measured from input terminals to output terminals, shortest distance path along body Distance through insulation DIN IEC 112/VDE 0303 Part 1 Material group (DIN VDE 0110, 1/89, Table 1) ADuM4154 Data Sheet DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 INSULATION CHARACTERISTICS This isolator is suitable for reinforced electrical isolation only within the safety limit data. Maintenance of the safety data is ensured by protective circuits. The asterisk (*) marked on packages denotes DIN V VDE V 0884-10 approval. Table 13. Description Installation Classification per DIN VDE 0110 For Rated Mains Voltage ≤ 150 V rms For Rated Mains Voltage ≤ 300 V rms For Rated Mains Voltage ≤ 400 V rms Climatic Classification Pollution Degree per DIN VDE 0110, Table 1 Maximum Working Insulation Voltage Input-to-Output Test Voltage, Method b1 Input-to-Output Test Voltage, Method a After Environmental Tests Subgroup 1 After Input and/or Safety Test Subgroup 2 and Subgroup 3 Highest Allowable Overvoltage Surge Isolation Voltage VIORM × 1.875 = Vpd(m), 100% production test, tini = tm = 1 sec, partial discharge < 5 pC VIORM × 1.5 = Vpd(m), tini = 60 sec, tm = 10 sec, partial discharge < 5 pC VIORM × 1.2 = Vpd(m), tini = 60 sec, tm = 10 sec, partial discharge < 5 pC VIOSM(TEST) = 10 kV, 1.2 µs rise time, 50 µs, 50% fall time Maximum value allowed in the event of a failure (see Figure 2) Safety Limiting Values Case Temperature Safety Total Dissipated Power Insulation Resistance at TS SAFE LIMITING POWER (W) Test Conditions/Comments VIO = 500 V Symbol Characteristic Unit VIORM Vpd(m) I to IV I to III I to II 40/105/21 2 849 1592 V peak V peak Vpd(m) 1274 V peak Vpd(m) 1019 V peak VIOTM VIOSM 6000 6250 V peak V peak TS PS RS 135 2.4 >109 °C W Ω 3.0 RECOMMENDED OPERATING CONDITIONS 2.5 Table 14. Parameter Operating Temperature Range Supply Voltage Range1 Input Signal Rise and Fall Times 2.0 1.5 1 1.0 50 100 AMBIENT TEMPERATURE (°C) 150 12366-002 0 Value −40°C to +125°C 3.0 V to 5.5 V 1.0 ms See the DC Correctness and Magnetic Field Immunity section for information on the immunity to the external magnetic fields. 0.5 0 Symbol TA VDD1, VDD2 Figure 2. Thermal Derating Curve, Dependence of Safety Limiting Values with Case Temperature per DIN V VDE V 0884-10 Rev. A | Page 12 of 22 Data Sheet ADuM4154 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 16. Maximum Continuous Working Voltage1 Table 15. Parameter 60 Hz AC Voltage Max 400 V rms DC Voltage 1173 V peak Parameter Storage Temperature (TST) Range Ambient Operating Temperature (TA) Range Supply Voltages (VDD1, VDD2) Input Voltages (MCLK, MSS, MO, SO, SSA0, SSA1) Output Voltages (SCLK, MI, SI, SS0 SS1, SS2, SS3) Average Output Current per Pin1 Common-Mode Transients2 1 2 Rating −65°C to +150°C −40°C to +125°C −0.5 V to +7.0 V −0.5 V to VDDx + 0.5 V See the Insulation Lifetime section for details. Other pollution degree and material group requirements yield a different limit. 3 Some system level standards allow components to use the printed wiring board (PWB) creepage values. The supported dc voltage may be higher for those standards. 1 −0.5 V to VDDx + 0.5 V 2 −10 mA to +10 mA −100 kV/µs to +100 kV/µs See Figure 2 for maximum safety rated current values across temperature. Refers to common-mode transients across the insulation barrier. Commonmode transients exceeding the absolute maximum ratings may cause latch-up or permanent damage. Constraint 20-year lifetime at 0.1% failure rate, zero average voltage Limited by the creepage of the package, Pollution Degree 2, Material Group II2, 3 ESD CAUTION Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Rev. A | Page 13 of 22 ADuM4154 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS VDD1 1 20 GND1 2 19 GND2 MCLK 3 18 SCLK MO 4 ADuM4154 17 SI MI 5 16 SO MSS 6 TOP VIEW (Not to Scale) SSA0 15 SS0 7 14 SS1 SSA1 8 13 SS2 NIC 9 12 GND1 10 11 SS3 GND2 NOTES 1. NIC = NOT INTERNALLY CONNECTED. THIS PIN IS NOT INTERNALLY CONNECTED AND SERVES NO FUNCTION IN THE ADuM4154. 12366-003 VDD2 Figure 3. Pin Configuration Table 17. Pin Function Descriptions Pin No. 1 2, 10 3 4 5 6 Mnemonic VDD1 GND1 MCLK MO MI MSS Direction Power Return Input Input Output Input 7 8 9 11, 19 12 13 14 15 16 17 18 20 SSA0 SSA1 NIC GND2 SS3 SS2 SS1 SS0 SO SI SCLK VDD2 Input Input Return Output Output Output Output Input Output Output Power Description Input Power Supply for Isolator Side 1. A bypass capacitor from VDD1 to GND1 to local ground is required. Ground 1. Ground reference for Isolator Side 1. SPI Clock from the Master Controller. SPI Data from the Master to the Slave MO/SI Line. SPI Data from the Slave to the Master MI/SO Line. Slave Select from the Master. This signal uses an active low logic. The slave select pin can require as much as a 10 ns setup time from the next clock or data edge depending on the speed grade. Multiplexer Selection Input, Low Order Bit. Multiplexer Selection Input, High Order Bit. Not Internally Connected. This pin is not internally connected and serves no function in the ADuM4154. Ground 2. Ground reference for Isolator Side 2. Routed Slave Select Signal 3. High-Z when SS3 is not selected. Routed Slave Select Signal 2. High-Z when SS2 is not selected. Routed Slave Select Signal 1. High-Z when SS1 is not selected. Routed Slave Select Signal 0. High-Z when SS0 is not selected. SPI Data from the Slave to the Master MI/SO Line. SPI Data from the Master to the Slave MO/SI Line. SPI Clock from the Master Controller. Input Power Supply for Isolator Side 2. A bypass capacitor from VDD2 to GND2 to local ground is required. Rev. A | Page 14 of 22 Data Sheet ADuM4154 Table 18. Multiplexer Select Truth Table1 Master Mux Inputs MSS 1 0 1 0 1 0 1 0 1 SSA0 0 0 1 1 0 0 1 1 Slave Mux Outputs SSA1 0 0 0 0 1 1 1 1 SS0 1 0 Z Z Z Z Z Z SS1 Z Z 1 0 Z Z Z Z SS2 Z Z Z Z 1 0 Z Z SS3 Z Z Z Z Z Z 1 0 Z = high impedance. Table 19. Power Off Default State Truth Table (Positive Logic)1, 2 Power State VDD1 Unpowered3 Powered Powered Powered 1 2 3 Master Side Output MI Z Z 1 0 Inputs MCLK X X 1 0 MO X X 1 0 Power State VDD2 Powered Unpowered3 Powered Powered Z = high impedance. X = irrelevant. Outputs on an unpowered side are high impedance within one diode drop of ground. Rev. A | Page 15 of 22 Slave Side Input SO X X 1 0 Outputs SCLK Z Z 1 0 SI Z Z 1 0 ADuM4154 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 4.0 7 3.5 DYNAMIC SUPPLY CURRENT PER OUTPUT CHANNEL (mA) 5 5.0V 3.3V 4 3 2 1 5.0V 2.5 2.0 3.3V 1.5 1.0 0.5 20 40 DATA RATE (Mbps) 80 60 0 Figure 4. Typical Dynamic Supply Current per Input Channel vs. Data Rate for 5.0 V and 3.3 V Operation 0 80 60 40 DATA RATE (Mbps) Figure 7. Typical Dynamic Supply Current per Output Channel vs. Data Rate for 5.0 V and 3.3 V Operation 30 25 IDD2 SUPPLY CURRENT (mA) 25 20 5.0V 3.3V 15 10 5 0 20 40 DATA RATE (Mbps) 80 60 20 5.0V 15 3.3V 10 5 0 12366-006 0 0 20 60 80 25 16 3.3V 14 PROPAGATION DELAY (ns) 3.3V 12 10 40 DATA RATE (Mbps) Figure 8. Typical IDD2 Supply Current vs. Data Rate for 5.0 V and 3.3 V Operation Figure 5. Typical IDD1 Supply Current vs. Data Rate for 5.0 V and 3.3 V Operation PROPAGATION DELAY (ns) 20 12366-005 0 12366-004 0 IDD1 SUPPLY CURRENT (mA) 3.0 12366-007 DYNAMIC SUPPLY CURRENT PER INPUT CHANNEL (mA) 6 5.0V 8 6 4 20 5.0V 15 10 5 10 60 AMBIENT TEMPERATURE (°C) 110 0 –40 12366-008 0 –40 10 60 AMBIENT TEMPERATURE (°C) Figure 6. Typical Propagation Delay vs. Ambient Temperature for High Speed Channels Without Glitch Filter (See the High Speed Channels Section) 110 12366-009 2 Figure 9. Typical Propagation Delay vs. Ambient Temperature for High Speed Channels with Glitch Filter (See the High Speed Channels Section) Rev. A | Page 16 of 22 Data Sheet ADuM4154 APPLICATIONS INFORMATION INTRODUCTION The ADuM4154 was created to optimize isolation of the SPI for speed and to provide additional low speed channels for control and status monitoring functions. The isolator is based on differential signaling iCoupler technology for enhanced speed and noise immunity. High Speed Channels The ADuM4154 has four high speed channels. The first three channels, CLK, MI/SO, and MO/SI (the slash indicates the connection of the particular input and output channel across the isolator), are optimized for either low propagation delay in the B grade, or high noise immunity in the A grade. The difference between the grades is the addition of a glitch filter to these three channels in the A grade version, which increases the propagation delay. The B grade version, with a maximum propagation delay of 14 ns, supports a maximum clock rate of 17 MHz in standard 4-wire SPI. However, because the glitch filter is not present in the B grade version, ensure that spurious glitches of less than 10 ns are not present. SS (slave select bar) is typically an active low signal. SS can have many different functions in SPI and SPI like busses. Many of these functions are edge triggered; therefore, the SS path contains a glitch filter in both the A grade and the B grade. The glitch filter prevents short pulses from propagating to the output or causing other errors in operation. The MSS signal requires a 10 ns setup time in the B grade devices prior to the first active clock edge to allow the added propagation time of the glitch filter. Slave Select Multiplexer The ADuM4154 can control up to four independent slave devices. Figure 10 shows how this can be done using generalpurpose isolators. An isolation channel is required for each slave select; therefore, seven high speed channels are required to transfer bidirectional data to four slaves. Glitches of less than 10 ns in the B grade devices can cause the second edge of the glitch to be missed. This pulse condition is then seen as a spurious data transition on the output that is corrected by a refresh or the next valid data edge. It is recommended to use the A grade devices in noisy environments. The relationship between the SPI signal paths and the pin mnemonics of the ADuM4154 and data directions is detailed in Table 20. Table 20. Pin Mnemonics Correspondence to SPI Signal Path Names Master Side 1 MCLK MO MI MSS Data Direction → → ← → Slave Side 2 SCLK SI SO SSx ISOLATOR CLK CLK MOSI MOSI MISO MISO SS0 SS0 SS1 CLK SS2 MOSI SS3 MISO SLAVE 0 SLAVE 1 SS1 CLK SLAVE 2 MOSI MISO SS2 CLK SLAVE 3 MOSI MISO The datapaths are SPI mode agnostic. The CLK and MO/SI SPI datapaths are optimized for propagation delay and channel to channel matching. The MI/SO SPI datapath is optimized for propagation delay. The device does not synchronize to the clock channel; therefore, there are no constraints on the clock polarity or the timing with respect to the data line. To allow compatibility with nonstandard SPI interfaces, the MI pin is always active, and does not tristate when the slave select is not asserted. This precludes tying several MI lines together without adding a trisate buffer or multiplexor. Rev. A | Page 17 of 22 SS3 Figure 10. Multiple Slave Control with Standard Isolators 12366-010 SPI Signal Path CLK MO/SI MI/SO SS MASTER ADuM4154 Data Sheet Figure 12 illustrates the behavior of the SSA0 and SSA1 channels. This diagram assumes that MSS is low and that SS0, SS1, SS2, and SS3 are pulled up. Figure 11 shows how the ADuM4154 can control up to four slaves by routing the MSS input to one of four outputs on the slave side of the isolator, which eliminates three isolation channels compared to the standard solution. CLK MOSI MISO MSS ADDRESS0 ADDRESS1 SAMPLE CLOCK ADuM4154 MASTER SCLK MCLK MO SI MI SO MSS SLAVE 0 SSA0 MOSI SSA1 MISO A B A C SS SSA0 SSA1 CLK MUX SS0 SS1 SS2 SS3 CLK SLAVE 1 SS0 C MOSI SS1 MISO A SS2 SS SS3 MOSI OUTPUT CLOCK MISO Figure 12. Mux Select Timing SS CLK The following details the mux select timing shown in Figure 12: SLAVE 3 MOSI 12366-011 MISO SS B SLAVE 2 12366-012 CLK Figure 11. Multiple Slave Control The multiplexer select lines are low speed channels implemented as part of the dc correctness scheme in the ADuM4154. The dc value of all high and low speed inputs on a given side of the device are sampled simultaneously, packetized, and shifted across an isolation coil. The high speed channels are compared for dc accuracy, and the low speed mux select lines, SSA0 and SSA1, are transferred to the mux control block. The dc correctness data for the high speed channels is handled internally with no visibility off chip. This data is regulated by a free running internal clock. Because data is sampled at discrete times based on this clock, the propagation delay for mux select lines is between 0.1 μs and 2.6 μs, depending on where the input data edge changes with respect to the internal sample clock. After an address propagation delay time of up to 2.6 μs, the multiplexer routes the MSS signals to the desired output. The outputs that are not selected are set to high-Z, and the application pulls them to the desired idle state. Rev. A | Page 18 of 22 Point A: The mux select lines must be switched simultaneously to within the tSSAx SKEW time. Failure to do this may allow sampling the inputs between the edges and selecting an incorrect mux output. Point A on SS1 is a metastable state on the output mux resulting from wide spacing between SSA0 and SSA1. Point B: For mux select lines to be processed predictably, a state of SSA0 and SSA1 must be stable for longer than 4 μs before switching the mux to another output. This guarantees that at least two samples are taken of the inputs before the mux output is changed. Point C: This point in Figure 12 shows a clean transfer between SS3 being active and SS0 being active. The mux was designed to eliminate any short duration metastable states between any two selected outputs. Data Sheet ADuM4154 PRINTED CIRCUIT BOARD (PCB) LAYOUT DC CORRECTNESS AND MAGNETIC FIELD IMMUNITY The ADuM4154 digital isolator requires no external interface circuitry for the logic interfaces. Power supply bypassing is strongly recommended at both the VDD1 and VDD2 supply pins (see Figure 13). The capacitor value must be between 0.01 μF and 0.1 μF. The total lead length between both ends of the capacitor and the input power supply pin must not exceed 20 mm. Positive and negative logic transitions at the isolator input cause narrow (~1 ns) pulses to be sent via the transformer to the decoder. The decoder is bistable and is, therefore, either set or reset by the pulses indicating input logic transitions. In the absence of logic transitions at the input for more than ~1.2 μs, a periodic set of refresh pulses indicative of the correct input state are sent via the low speed channel to ensure dc correctness at the output. BYPASS < 10mm VDD2 GND2 ADuM4154 MO TOP VIEW (Not to Scale) MI If the low speed decoder receives no pulses for more than about 5 μs, the input side is assumed to be unpowered or nonfunctional, in which case, the isolator output is forced to a high-Z state by the watchdog timer circuit. SCLK SI SO MSS SS0 SSA0 SS1 SSA1 SS2 NIC SS3 GND2 GND1 12366-013 MCLK Figure 13. Recommended PCB Layout In applications involving high common-mode transients, it is important to minimize board coupling across the isolation barrier. Furthermore, design the PCB layout so that any coupling that does occur affects all pins equally on a given component side. Failure to ensure this may cause voltage differentials between pins that exceed the absolute maximum ratings of the device, thereby leading to latch-up or permanent damage. The limitation on the magnetic field immunity of the device is set by the condition in which induced voltage in the transformer receiving coil is sufficiently large to either falsely set or reset the decoder. The following analysis defines such conditions. The ADuM4154 is examined in a 3 V operating condition because it represents the most susceptible mode of operation for this product. The pulses at the transformer output have an amplitude greater than 1.5 V. The decoder has a sensing threshold of about 1.0 V; thereby establishing a 0.5 V margin in which induced voltages can be tolerated. The voltage induced across the receiving coil is given by PROPAGATION DELAY RELATED PARAMETERS V = (−dβ/dt)Σπrn2; n = 1, 2, …, N INPUT 50% OUTPUT tPHL 12366-014 tPLH 50% Figure 14. Propagation Delay Parameters Pulse width distortion is the maximum difference between these two propagation delay values and an indication of how accurately the timing of the input signal is preserved. Channel to channel matching refers to the maximum amount the propagation delay differs between channels within a single ADuM4154 component. where: β is the magnetic flux density. rn is the radius of the nth turn in the receiving coil. N is the number of turns in the receiving coil. Given the geometry of the receiving coil in the ADuM4154 and an imposed requirement that the induced voltage be, at most, 50% of the 0.5 V margin at the decoder, a maximum allowable magnetic field is calculated, as shown in Figure 15. 100 MAXIMUM ALLOWABLE MAGNETIC FLUX DENSITY (kgauss) Propagation delay is a parameter that describes the time it takes a logic signal to propagate through a component. The input to output propagation delay time for a high to low transition may differ from the propagation delay time of a low to high transition. 10 1 0.1 0.01 0.001 1k 10k 100k 1M 10M MAGNETIC FIELD FREQUENCY (Hz) 100M Figure 15. Maximum Allowable External Magnetic Flux Density Rev. A | Page 19 of 22 12366-015 VDD1 GND1 ADuM4154 Data Sheet For example, at a magnetic field frequency of 1 MHz, the maximum allowable magnetic field of 0.5 kgauss induces a voltage of 0.25 V at the receiving coil. This voltage is about 50% of the sensing threshold and does not cause a faulty output transition. If such an event occurs, with the worst-case polarity, during a transmitted pulse, the interference reduces the received pulse from >1.0 V to 0.75 V. This voltage is still well above the 0.5 V sensing threshold of the decoder. These quiescent currents add to the high speed current as is shown in the following equations for the total current for each side of the isolator. Dynamic currents are taken from Table 3 and Table 5 for the respective voltages. The preceding magnetic flux density values correspond to specific current magnitudes at given distances away from the ADuM4154 transformers. Figure 16 expresses these allowable current magnitudes as a function of frequency for selected distances. The ADuM4154 is insensitive to external fields. Only extremely large, high frequency currents very close to the component are potentially a concern. For the 1 MHz example noted, placing a 1.2 kA current 5 mm away from the ADuM4154 affects component operation. For Side 2, the supply current is given by DISTANCE = 1m 100 IDD1 = IDDI(D) × (fMCLK + fMO + fMSS) + fMI × (IDDO(D) + ((0.5 × 10−3) × CL(MI) × VDD1)) + IDD1(Q) IDD2 = IDDI(D) × fSO + fSCLK × (IDDO(D) +((0.5 × 10−3) × CL(SCLK) × VDD2)) + fSI × (IDDO(D) +((0.5 × 10−3) × CL(SI) × VDD2)) + fSSx × (IDDO(D) +((0.5 × 10−3) × CL(SSx) × VDD2)) + IDD2(Q) where: IDDI(D), IDDO(D) are the input and output dynamic supply currents per channel (mA/Mbps). fx is the logic signal data rate for the specified channel (Mbps). IDD1(Q), IDD2(Q) are the specified Side 1 and Side 2 quiescent supply currents (mA). CL(x) is the load capacitance of the specified output (pF). VDDx is the supply voltage of the side being evaluated (V). Figure 4 and Figure 7 show the typical supply current per channel as a function of data rate for an input and unloaded output. Figure 5 and Figure 8 show the total IDD1 and IDD2 supply currents as a function of data rate for ADuM4154 channel configurations with all high speed channels running at the same speed and the low speed channels at idle. 10 DISTANCE = 100mm 1 DISTANCE = 5mm 0.1 INSULATION LIFETIME 0.01 1k 10k 100k 1M 10M MAGNETIC FIELD FREQUENCY (Hz) 100M 12366-016 MAXIMUM ALLOWABLE CURRENT (kA) 1000 For Side 1, the supply current is given by Figure 16. Maximum Allowable Current for Various Current to ADuM4154 Spacings At combinations of a strong magnetic field and high frequency, any loops formed by the PCB traces may induce sufficiently large error voltages to trigger the thresholds of succeeding circuitry. Take care to avoid PCB structures that form loops. POWER CONSUMPTION The supply current at a given channel of the ADuM4154 isolator is a function of the supply voltage, the data rate of the channel, the output load of the channel, and whether it is a high or low speed channel. All insulation structures eventually break down when subjected to voltage stress over a sufficiently long period. The rate of insulation degradation is dependent on the characteristics of the voltage waveform applied across the insulation, as well as the materials and material interfaces. Two types of insulation degradation are of primary interest: breakdown along surfaces exposed to the air and insulation wear out. Surface breakdown is the phenomenon of surface tracking and the primary determinant of surface creepage requirements in system level standards. Insulation wear out is the phenomenon where charge injection or displacement currents inside the insulation material cause long-term insulation degradation. The low speed channels draw a constant quiescent current caused by the internal ping-pong datapath. The operating frequency is low enough that the capacitive losses caused by the recommended capacitive load are negligible compared to the quiescent current. The explicit calculation for the data rate is eliminated for simplicity, and the quiescent current for each side of the isolator due to the low speed channels can be found in Table 3, Table 5, Table 7, and Table 9 for the particular operating voltages. Rev. A | Page 20 of 22 Data Sheet ADuM4154 Calculation and Use of Parameters Example Surface tracking is addressed in electrical safety standards by setting a minimum surface creepage based on the working voltage, the environmental conditions, and the properties of the insulation material. Safety agencies perform characterization testing on the surface insulation of components that allow the components to be categorized in different material groups. Lower material group ratings are more resistant to surface tracking and, therefore, can provide adequate lifetime with smaller creepage. The minimum creepage for a given working voltage and material group is in each system level standard and is based on the total rms voltage across the isolation, pollution degree, and material group. The material group and creepage for the ADuM4154 isolator are detailed in Table 12. The following is an example that frequently arises in power conversion applications. Assume that the line voltage on one side of the isolation is 240 VAC RMS, and a 400 VDC bus voltage is present on the other side of the isolation barrier. The isolator material is polyimide. To establish the critical voltages in determining the creepage clearance and lifetime of a device, see Figure 17 and the following equations. The lifetime of insulation caused by wear out is determined by its thickness, the material properties, and the voltage stress applied. It is important to verify that the product lifetime is adequate at the application working voltage. The working voltage supported by an isolator for wear out may not be the same as the working voltage supported for tracking. It is the working voltage applicable to tracking that is specified in most standards. Testing and modeling have shown that the primary driver of long-term degradation is displacement current in the polyimide insulation causing incremental damage. The stress on the insulation can be broken down into two broad categories, such as dc stress, which causes very little wear out because there is no displacement current, and an ac component time varying voltage stress, which causes wear out. The ratings in certification documents are usually based on 60 Hz sinusoidal stress, because this reflects isolation from line voltage. However, many practical applications have combinations of 60 Hz ac and dc across the barrier, as shown in Equation 1. Because only the ac portion of the stress causes wear out, the equation can be rearranged to solve for the ac rms voltage, as shown in Equation 2. For insulation wear out with the polyimide materials used in this product, the ac rms voltage determines the product lifetime. VRMS VAC RMS2 VDC 2 (1) VAC RMS VRMS 2 VDC 2 (2) or where: VRMS is the total rms working voltage. VAC RMS is the time varying portion of the working voltage. VDC is the dc offset of the working voltage. VAC RMS VPEAK VRMS VDC TIME 12366-017 Insulation Wear Out ISOLATION VOLTAGE Surface Tracking Figure 17. Critical Voltage Example The working voltage across the barrier from Equation 1 is VRMS VAC RMS2 VDC 2 VRMS 2402 4002 VRMS = 466 V The 466 V rms working voltage is used together with the material group and pollution degree when looking up the creepage required by a system standard. To determine if the lifetime is adequate, obtain the time varying portion of the working voltage. The ac rms voltage can be obtained from Equation 2. VAC RMS VRMS 2 VDC 2 VAC RMS 4662 4002 VAC RMS = 240 V In this case, the VAC RMS is simply the line voltage of 240 VRMS. This calculation is more relevant when the waveform is not sinusoidal. The value is compared to the limits for the working voltage listed in Table 16 for the expected lifetime, less than a 60 Hz sine wave, and it is well within the limit for a 50-year service life. Note that the dc working voltage limit in Table 16 is set by the creepage of the package as specified in IEC 60664-1. This value may differ for specific system level standards. Rev. A | Page 21 of 22 ADuM4154 Data Sheet OUTLINE DIMENSIONS 15.40 15.30 15.20 1.93 REF 20 11 7.60 7.50 7.40 1 10.51 10.31 10.11 10 PIN 1 MARK 2.64 2.54 2.44 2.44 2.24 45° SEATING PLANE 1.27 BSC 8° 0° 1.01 0.76 0.51 0.46 0.36 0.32 0.23 11-15-2011-A 0.30 0.20 0.10 COPLANARITY 0.1 0.71 0.50 0.31 0.25 BSC GAGE PLANE COMPLIANT TO JEDEC STANDARDS MS-013 Figure 18. 20-Lead Standard Small Outline Package, with Increased Creepage [SOIC_IC] Wide Body (RI-20-1) Dimension shown in millimeters ORDERING GUIDE Model1, 2 ADuM4154ARIZ ADuM4154ARIZ-RL No. of Inputs, VDD1 Side 5 5 No. of Inputs, VDD2 Side 1 1 Maximum Data Rate (MHz) 1 1 Maximum Propagation Delay, 5 V (ns) 25 25 Isolation Rating (V rms) 5000 5000 Temperature Range −40°C to +125°C −40°C to +125°C ADuM4154BRIZ 5 1 17 14 5000 −40°C to +125°C ADuM4154BRIZ-RL 5 1 17 14 5000 −40°C to +125°C EVAL-ADuM3154Z 1 2 Package Description 20-Lead SOIC_IC 20-Lead SOIC_IC, 13” Tape and Reel 20-Lead SOIC_IC Package Option RI-20-1 RI-20-1 20-Lead SOIC_IC, 13” Tape and Reel Evaluation Board RI-20-1 RI-20-1 Z = RoHS Compliant Part. The EVAL-ADuM3154Z uses a functionally equivalent device for evaluation. The pad layout on the EVAL-ADuM3154Z evaluation board does not support the 20-lead SOIC_IC package. ©2014–2015 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D12366-0-3/15(A) Rev. A | Page 22 of 22