3.0 kV RMS, Single-Channel Digital Isolator ADuM110N Data Sheet FEATURES GENERAL DESCRIPTION High common-mode transient immunity: 100 kV/μs High robustness to radiated and conducted noise Low propagation delay 13 ns maximum for 5 V operation 15 ns maximum for 1.8 V operation 150 Mbps maximum data rate Safety and regulatory approvals (pending) UL recognition 3000 V rms for 1 minute per UL 1577 CSA component acceptance notice 5A VDE certificate of conformity DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 VIORM = 565 V peak CQC Certification per GB4943.1-2011 Backward compatibility Pin compatible with the ADuM1100 Low dynamic power consumption 1.8 V to 5 V level translation High temperature operation: 125°C Fail-safe high or low options 8-lead, RoHS-compliant, SOIC package The ADuM110N is a single-channel digital isolator based on Analog Devices, Inc., iCoupler® technology. Combining high speed, complementary metal-oxide semiconductor (CMOS) and monolithic air core transformer technology, this isolation component provides outstanding performance characteristics, superior to alternatives such as optocoupler devices and other integrated couplers. The maximum propagation delay is 13 ns with a pulse width distortion of less than 3 ns at 5 V operation. The ADuM110N supports data rates as high as 150 Mbps with a withstand voltage rating of 3.0 kV rms (see the Ordering Guide). The device operates with the supply voltage on either side ranging from 1.8 V to 5 V, providing compatibility with lower voltage systems as well as enabling voltage translation functionality across the isolation barrier. Unlike other optocoupler alternatives, dc correctness is ensured in the absence of input logic transitions. Two different fail-safe options are available, in which the outputs transition to a predetermined state when the input power supply is not applied or the inputs are disabled. The ADuM110N is pin compatible with the ADuM1100. APPLICATIONS General-purpose single-channel isolation Industrial field bus isolation FUNCTIONAL BLOCK DIAGRAM VI 2 (DATA IN) D E C O D E E N C O D E VDD1 3 GND1 4 ADuM110N 8 VDD2 7 GND2 6 VO (DATA OUT) 5 GND2 13736-001 VDD1 1 Figure 1. 1 Protected by U.S. Patents 5,952,849; 6,873,065; 6,903,578; and 7,075,329. Other patents are pending. Rev. 0 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2015 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com ADuM110N Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Recommended Operating Conditions .......................................9 Applications ....................................................................................... 1 Absolute Maximum Ratings ......................................................... 10 General Description ......................................................................... 1 ESD Caution................................................................................ 10 Functional Block Diagram .............................................................. 1 Pin Configuration and Function Descriptions........................... 11 Revision History ............................................................................... 2 Typical Performance Characteristics ........................................... 12 Specifications..................................................................................... 3 Applications Information .............................................................. 13 Electrical Characteristics—5 V Operation................................ 3 Overview ..................................................................................... 13 Electrical Characteristics—3.3 V Operation ............................ 4 PCB Layout ................................................................................. 13 Electrical Characteristics—2.5 V Operation ............................ 5 Propagation Delay Related Parameters ................................... 14 Electrical Characteristics—1.8 V Operation ............................ 6 Jitter Measurement ..................................................................... 14 Insulation and Safety Related Specifications ............................ 7 Insulation Lifetime ..................................................................... 14 Package Characteristics ............................................................... 7 Outline Dimensions ....................................................................... 16 Regulatory Information ............................................................... 8 Ordering Guide .......................................................................... 16 DIN V VDE V 0884-10 (VDE V 0884-10) Insulation Characteristics .............................................................................. 8 REVISION HISTORY 10/15—Revision 0: Initial Version Rev. 0 | Page 2 of 16 Data Sheet ADuM110N SPECIFICATIONS ELECTRICAL CHARACTERISTICS—5 V OPERATION All typical specifications are at TA = 25°C, VDD1 = VDD2 = 5 V. Minimum/maximum specifications apply over the entire recommended operation range of 4.5 V ≤ VDD1 ≤ 5.5 V, 4.5 V ≤ VDD2 ≤ 5.5 V, and −40°C ≤ TA ≤ +125°C, unless otherwise noted. Switching specifications are tested with CL = 15 pF and CMOS signal levels, unless otherwise noted. Supply currents are specified with 50% duty cycle signals. Table 1. Parameter SWITCHING SPECIFICATIONS Pulse Width Data Rate Propagation Delay Pulse Width Distortion Change vs. Temperature Propagation Delay Skew Symbol Min PW 6.6 tPHL, tPLH PWD Typ 150 4.8 7.2 0.5 1.5 tPSK Max 13 3 6.0 Jitter 380 55 Unit Test Conditions/Comments ns Within pulse width distortion (PWD) limit Within PWD limit 50% input to 50% output |tPLH − tPHL| Mbps ns ns ps/°C ns ps p-p ps rms Between any two units at the same temperature, voltage, and load See the Jitter Measurement section See the Jitter Measurement section DC SPECIFICATIONS Input Threshold Logic High Logic Low Output Voltage Logic High VIH VIL 0.7 × VDD1 VOH VDD2 − 0.1 VDD2 VDD2 − 0.4 Logic Low VOL VDD2 − 0.2 0.0 0.2 +0.01 0.1 0.4 +10 V V V μA Output current (IO) = −20 μA, input voltage (VI) = VIH IO = −4 mA, VI = VIH IO = 20 μA, VI = VIL IO = 4 mA, VI = VIL 0 V ≤ VI ≤ VDD1 IDD1 (Q) IDD2 (Q) IDD1 (Q) IDD2 (Q) 0.9 1.0 3.6 1.0 1.4 1.3 6.0 1.4 mA mA mA mA VI = 0 (N0), 1 (N1)1 VI = 0 (N0), 1 (N1)1 VI = 1 (N0), 0 (N1)1 VI = 1 (N0), 0 (N1)1 IDDI (D) IDDO (D) UVLO VDDxUV+ VDDxUV− VDDxUVH 0.01 0.02 mA/Mbps mA/Mbps Inputs switching, 50% duty cycle Inputs switching, 50% duty cycle 1.6 1.5 0.1 V V V Input Current per Channel Quiescent Supply Current Dynamic Supply Current Dynamic Output Dynamic Input Undervoltage Lockout Positive VDDx Threshold Negative VDDx Threshold VDDx Hysteresis AC SPECIFICATIONS Output Rise/Fall Time Common-Mode Transient Immunity2 1 2 II 0.3 × VDD1 −10 V V V tR/tF |CMH| 75 2.5 100 ns kV/μs |CML| 75 100 kV/μs 10% to 90% VI = VDD1, VCM = 1000 V, transient magnitude = 800 V VI = 0 V, VCM = 1000 V, transient magnitude = 800 V N0 indicates the ADuM110N0 models and N1 indicates the ADuM110N1 models. See the Ordering Guide section. |CMH| is the maximum common-mode voltage slew rate that can be sustained while maintaining the voltage output (VO) > 0.8 VDD2. |CML| is the maximum commonmode voltage slew rate that can be sustained while maintaining VO > 0.8 V. The common-mode voltage slew rates apply to both the rising and falling common-mode voltage edges. Rev. 0 | Page 3 of 16 ADuM110N Data Sheet Table 2. Total Supply Current vs. Data Throughput—5 V Operation Parameter SUPPLY CURRENT Supply Current Side 1 Supply Current Side 2 Symbol Min IDD1 IDD2 1 Mbps Typ Max 2.2 1.1 Min 3.7 1.6 25 Mbps Typ Max 2.5 1.6 3.9 2.3 Min 100 Mbps Typ Max 3.6 3.1 4.9 4.6 Unit mA mA ELECTRICAL CHARACTERISTICS—3.3 V OPERATION All typical specifications are at TA = 25°C, VDD1 = VDD2 = 3.3 V. Minimum/maximum specifications apply over the entire recommended operation range: 3.0 V ≤ VDD1 ≤ 3.6 V, 3.0 V ≤ VDD2 ≤ 3.6 V, and −40°C ≤ TA ≤ +125°C, unless otherwise noted. Switching specifications are tested with CL = 15 pF and CMOS signal levels, unless otherwise noted. Supply currents are specified with 50% duty cycle signals. Table 3. Parameter SWITCHING SPECIFICATIONS Pulse Width Data Rate Propagation Delay Pulse Width Distortion Change vs. Temperature Propagation Delay Skew Symbol Min PW 6.6 150 4.8 tPHL, tPLH PWD Typ 6.8 0.7 1.5 tPSK Test Conditions/Comments 14 3 ns Mbps ns ns ps/°C ns Within PWD limit Within PWD limit 50% input to 50% output |tPLH − tPHL| 290 45 DC SPECIFICATIONS Input Threshold Logic High Logic Low Output Voltage Logic High VIH VIL 0.7 × VDD1 VOH VDD2 − 0.1 VDD2 − 0.4 Logic Low VOL Dynamic Supply Current Dynamic Input Dynamic Output Undervoltage Lockout Positive VDDx Threshold Negative VDDx Threshold VDDx Hysteresis Unit 7.0 Jitter Input Current per Channel Quiescent Supply Current Max ps p-p ps rms Between any two units at the same temperature, voltage, and load See the Jitter Measurement section See the Jitter Measurement section 0.3 × VDD1 V V VDD2 VDD2 − 0.2 0.0 0.2 +0.01 0.1 0.4 +10 V V V V μA IO = −20 μA, VI = VIH IO = −2 mA, VI = VIH IO = 20 μA, VI = VIL IO = 2 mA, VI = VIL 0 V ≤ VI ≤ VDD1 IDD1 (Q) IDD2 (Q) IDD1 (Q) IDD2 (Q) 0.8 0.9 3.6 0.9 1.3 1.4 5.8 1.4 mA mA mA mA VI = 0 (N0), 1 (N1)1 VI = 0 (N0), 1 (N1)1 VI = 1 (N0), 0 (N1)1 VI = 1 (N0), 0 (N1)1 IDDI (D) IDDO (D) UVLO VDDxUV+ VDDxUV− VDDxUVH 0.01 0.01 mA/Mbps mA/Mbps Inputs switching, 50% duty cycle Inputs switching, 50% duty cycle 1.6 1.5 0.1 V V V II −10 Rev. 0 | Page 4 of 16 Data Sheet ADuM110N Parameter AC SPECIFICATIONS Output Rise/Fall Time Common-Mode Transient Immunity2 1 2 Symbol Min Typ tR/tF |CMH| 75 |CML| 75 Max Unit Test Conditions/Comments 2.5 100 ns kV/μs 100 kV/μs 10% to 90% VI = VDD1, VCM = 1000 V, transient magnitude = 800 V VI = 0 V, VCM = 1000 V, transient magnitude = 800 V N0 indicates the ADuM110N0 models and N1 indicates the ADuM110N1 models. See the Ordering Guide section. |CMH| is the maximum common-mode voltage slew rate that can be sustained while maintaining the voltage output (VO) > 0.8 VDD2. |CML| is the maximum commonmode voltage slew rate that can be sustained while maintaining VO > 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. Table 4. Total Supply Current vs. Data Throughput—3.3 V Operation Parameter SUPPLY CURRENT Supply Current Side 1 Supply Current Side 2 Symbol Min 1 Mbps Typ Max IDD1 IDD2 2.2 0.9 Min 3.5 1.5 25 Mbps Typ Max 2.4 1.4 3.6 2.0 Min 100 Mbps Typ Max 3.2 2.8 4.6 4.3 Unit mA mA ELECTRICAL CHARACTERISTICS—2.5 V OPERATION All typical specifications are at TA = 25°C, VDD1 = VDD2 = 2.5 V. Minimum/maximum specifications apply over the entire recommended operation range: 2.25 V ≤ VDD1 ≤ 2.75 V, 2.25 V ≤ VDD2 ≤ 2.75 V, −40°C ≤ TA ≤ +125°C, unless otherwise noted. Switching specifications are tested with CL = 15 pF and CMOS signal levels, unless otherwise noted. Supply currents are specified with 50% duty cycle signals. Table 5. Parameter SWITCHING SPECIFICATIONS Pulse Width Data Rate Propagation Delay Pulse Width Distortion Change vs. Temperature Propagation Delay Skew Symbol Min PW 6.6 150 5.0 tPHL, tPLH PWD Typ 7.0 0.7 1.5 tPSK Test Conditions/Comments 14 3 ns Mbps ns ns ps/°C ns Within PWD limit Within PWD limit 50% input to 50% output |tPLH − tPHL| 320 65 DC SPECIFICATIONS Input Threshold Logic High Logic Low Output Voltage Logic High VIH VIL 0.7 × VDD1 VOH VDD2 − 0.1 VDD2 − 0.4 Logic Low VOL Dynamic Supply Current Dynamic Input Dynamic Output Unit 7.0 Jitter Input Current per Channel Quiescent Supply Current Max ps p-p ps rms Between any two units at the same temperature, voltage, load See the Jitter Measurement section See the Jitter Measurement section 0.3 × VDD1 V V VDD2 VDD2 − 0.2 0.0 0.2 +0.01 0.1 0.4 +10 V V V V μA IO = −20 μA, VI = VIH IO = −2 mA, VI = VIH IO = 20 μA, VI = VIL IO = 2 mA, VI = VIL 0 V ≤ VI ≤ VDD1 IDD1 (Q) IDD2 (Q) IDD1 (Q) IDD2 (Q) 0.8 0.9 3.5 1.0 1.1 1.2 5.6 1.2 mA mA mA mA VI = 0 (N0), 1 (N1)1 VI = 0 (N0), 1 (N1)1 VI = 1 (N0), 0 (N1)1 VI = 1 (N0), 0 (N1)1 IDDI (D) IDDO (D) 0.01 0.01 mA/Mbps mA/Mbps Inputs switching, 50% duty cycle Inputs switching, 50% duty cycle II −10 Rev. 0 | Page 5 of 16 ADuM110N Data Sheet Parameter Undervoltage Lockout Positive VDDx Threshold Negative VDDx Threshold VDDx Hysteresis AC SPECIFICATIONS Output Rise/Fall Time Common-Mode Transient Immunity2 1 2 Symbol Min Typ VDDxUV+ VDDxUV− VDDxUVH Max Unit 1.6 1.5 0.1 V V V tR/tF |CMH| 75 2.5 100 ns kV/μs |CML| 75 100 kV/μs Test Conditions/Comments 10% to 90% VI = VDD1, VCM = 1000 V, transient magnitude = 800 V VI = 0 V, VCM = 1000 V, transient magnitude = 800 V N0 indicates the ADuM110N0 models and N1 indicates the ADuM110N1 models. See the Ordering Guide section. |CMH| is the maximum common-mode voltage slew rate that can be sustained while maintaining the voltage output (VO) > 0.8 VDD2. |CML| is the maximum commonmode voltage slew rate that can be sustained while maintaining VO > 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. Table 6. Total Supply Current vs. Data Throughput—2.5 V Operation Parameter SUPPLY CURRENT Supply Current Side 1 Supply Current Side 2 Symbol 1 Mbps Typ Max Min IDD1 IDD2 2.2 0.9 Min 3.4 1.4 25 Mbps Typ Max 2.4 1.3 3.6 1.8 Min 100 Mbps Typ Max 3.2 2.3 4.3 3.5 Unit mA mA ELECTRICAL CHARACTERISTICS—1.8 V OPERATION All typical specifications are at TA = 25°C, VDD1 = VDD2 = 1.8 V. Minimum/maximum specifications apply over the entire recommended operation range: 1.7 V ≤ VDD1 ≤ 1.9 V, 1.7 V ≤ VDD2 ≤ 1.9 V, and −40°C ≤ TA ≤ +125°C, unless otherwise noted. Switching specifications are tested with CL = 15 pF and CMOS signal levels, unless otherwise noted. Supply currents are specified with 50% duty cycle signals. Table 7. Parameter SWITCHING SPECIFICATIONS Pulse Width Data Rate Propagation Delay Pulse Width Distortion Change vs. Temperature Propagation Delay Skew Symbol Min PW 6.6 150 5.8 tPHL, tPLH PWD Typ 8.7 0.7 1.5 tPSK Unit Test Conditions/Comments 15 3 ns Mbps ns ns ps/°C ns Within PWD limit Within PWD limit 50% input to 50% output |tPLH − tPHL| 7.0 Jitter 630 190 DC SPECIFICATIONS Input Threshold Logic High Logic Low Output Voltage Logic High VIH VIL 0.7 × VDD1 VOH VDD2 − 0.1 VDD2 − 0.4 Logic Low VOL Input Current per Channel Quiescent Supply Current Max II IDD1 (Q) IDD2 (Q) IDD1 (Q) IDD2 (Q) −10 ps p-p ps rms Between any two units at the same temperature, voltage, and load See the Jitter Measurement section See the Jitter Measurement section 0.3 × VDD1 V V VDD2 VDD2 − 0.2 0.0 0.2 +0.01 0.1 0.4 +10 V V V V μA IO = −20 μA, VI = VIH IO = −2 mA, VI = VIH IO = 20 μA, VI = VIL IO = 2 mA, VI = VIL 0 V ≤ VI ≤ VDD1 0.7 0.9 3.4 0.9 1.1 1.2 5.4 1.2 mA mA mA mA VI = 0 (N0), 1 (N1)1 VI = 0 (N0), 1 (N1)1 VI = 1 (N0), 0 (N1)1 VI = 1 (N0), 0 (N1)1 Rev. 0 | Page 6 of 16 Data Sheet ADuM110N Parameter Dynamic Supply Current Dynamic Input Dynamic Output Undervoltage Lockout Positive VDDx Threshold Negative VDDx Threshold VDDx Hysteresis AC SPECIFICATIONS Output Rise/Fall Time Common-Mode Transient Immunity2 1 2 Symbol Min Typ IDDI (D) IDDO (D) UVLO VDDxUV+ VDDxUV− VDDxUVH Max Unit Test Conditions/Comments 0.01 0.01 mA/Mbps mA/Mbps Inputs switching, 50% duty cycle Inputs switching, 50% duty cycle 1.6 1.5 0.1 V V V tR/tF |CMH| 75 2.5 100 ns kV/μs |CML| 75 100 kV/μs 10% to 90% VI = VDD1, VCM = 1000 V, transient magnitude = 800 V V1 = 0 V, VCM = 1000 V, transient magnitude = 800 V N0 indicates the ADuM110N0 models and N1 indicates the ADuM110N1 models. See the Ordering Guide section. |CMH| is the maximum common-mode voltage slew rate that can be sustained while maintaining the voltage output (VO) > 0.8 VDD2. |CML| is the maximum commonmode voltage slew rate that can be sustained while maintaining VO > 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. Table 8. Total Supply Current vs. Data Throughput—1.8 V Operation Parameter SUPPLY CURRENT Supply Current Side 1 Supply Current Side 2 Symbol 1 Mbps Typ Max Min IDD1 IDD2 2.1 0.9 Min 3.1 1.2 25 Mbps Typ Max 2.3 1.2 3.4 1.6 Min 100 Mbps Typ Max 3.0 2.2 4.2 3.2 Unit mA mA INSULATION AND SAFETY RELATED SPECIFICATIONS For additional information, see www.analog.com/icouplersafety. Table 9. Parameter Rated Dielectric Insulation Voltage Minimum External Air Gap (Clearance) Symbol L (I01) Value 3000 4.0 Unit V rms mm min Minimum External Tracking (Creepage) L (I02) 4.0 mm min Minimum Clearance in the Plane of the Printed Circuit Board (PCB Clearance) L (PCB) 4.5 mm min CTI 25.5 >400 II μm min V Minimum Internal Gap (Internal Clearance) Tracking Resistance (Comparative Tracking Index) Material Group Test Conditions/Comments 1-minute duration Measured from input terminals to output terminals, shortest distance through air Measured from input terminals to output terminals, shortest distance path along body Measured from input terminals to output terminals, shortest distance through air, line of sight, in the PCB mounting plane Insulation distance through insulation DIN IEC 112/VDE 0303 Part 1 Material Group (DIN VDE 0110, 1/89, Table 1) PACKAGE CHARACTERISTICS Table 10. Parameter Resistance (Input to Output)1 Capacitance (Input to Output)1 Input Capacitance2 IC Junction to Ambient Thermal Resistance 1 2 Symbol RI-O CI-O CI θJA Min Typ 1013 2 4.0 80 Max Unit Ω pF pF °C/W Test Conditions/Comments f = 1 MHz Thermocouple located at center of package underside The ADuM110N is considered a 2-terminal device: Pin 1 through Pin 4 are shorted together, and Pin 5 through Pin 8 are shorted together. Input capacitance is from any input data pin to ground. Rev. 0 | Page 7 of 16 ADuM110N Data Sheet REGULATORY INFORMATION See Table 15 and the Insulation Lifetime section for details regarding recommended maximum working voltages for specific crossisolation waveforms and insulation levels. Table 11. UL (Pending) Recognized Under 1577 Component Recognition Program1 Single Protection, 3000 V rms Isolation Voltage Double Protection, 3000 V rms Isolation Voltage CSA (Pending) Approved under CSA Component Acceptance Notice 5A CSA 60950-1-07+A1+A2 and IEC 60950-1, Second Edition, +A1+A2 Basic insulation at 400 V rms (565 V peak) Reinforced insulation at 200 V rms (283 V peak) IEC 60601-1 Edition 3.1 VDE (Pending) Certified according to DIN V VDE V 0884-10 (VDE V 0884-10):2006-122 Basic insulation 565 V peak, VIOSM = 10 kV peak CQC (Pending) Certified by CQC11-471543-2012 Reinforced insulation, 565 V peak, VIOSM = 6000 V peak Basic insulation at 770 V rms (1089 V peak), reinforced insulation at 385 V rms (545 V peak), tropical climate, altitude ≤5000 meters File 2471900-4880-0001 File (pending) Basic insulation (1 MOPP), 250 V rms (354 V peak) CSA 61010-1-12 and IEC 61010-1 Third Edition File E214100 1 2 Basic insulation at 300 V rms (main), 400 V rms (565 V peak) Reinforced insulation at 300 V rms (main), 200 V (secondary) (283 V peak) File 205078 GB4943.1-2011 In accordance with UL 1577, each ADuM110N is proof tested by applying an insulation test voltage ≥ 3600 V rms for 1 sec. In accordance with DIN V VDE V 0884-10, each ADuM110N is proof tested by applying an insulation test voltage ≥ 1059 V peak for 1 sec (partial discharge detection limit = 5 pC). The * marking branded on the component designates DIN V VDE V 0884-10 approval. DIN V VDE V 0884-10 (VDE V 0884-10) INSULATION CHARACTERISTICS This isolator is suitable for reinforced electrical isolation only within the safety limit data. Protective circuits ensure the maintenance of the safety data. The * marking on packages denotes DIN V VDE V 0884-10 approval. Table 12. Description Installation Classification per DIN VDE 0110 For Rated Mains Voltage ≤ 150 V rms For Rated Mains Voltage ≤ 300 V rms For Rated Mains Voltage ≤ 400 V rms Climatic Classification Pollution Degree per DIN VDE 0110, Table 1 Maximum Working Insulation Voltage Input to Output Test Voltage, Method B1 Input to Output Test Voltage, Method A After Environmental Tests Subgroup 1 After Input and/or Safety Test Subgroup 2 and Subgroup 3 Highest Allowable Overvoltage Surge Isolation Voltage Basic Reinforced Test Conditions/Comments VIORM × 1.875 = Vpd (m), 100% production test, tini = tm = 1 sec, partial discharge < 5 pC VIORM × 1.5 = Vpd (m), tini = 60 sec, tm = 10 sec, partial discharge < 5 pC VIORM × 1.2 = Vpd (m), tini = 60 sec, tm = 10 sec, partial discharge < 5 pC V peak = 10.0 kV, 1.2 μs rise time, 50 μs, 50% fall time V peak = 10.0 kV, 1.2 μs rise time, 50 μs, 50% fall time Rev. 0 | Page 8 of 16 Symbol Characteristic Unit VIORM Vpd (m) I to IV I to III I to III 40/105/21 2 565 1059 V peak V peak Vpd (m) 848 V peak 678 V peak VIOTM 4200 V peak VIOSM 10,000 V peak VIOSM 6000 V peak Data Sheet ADuM110N Description Safety Limiting Values Test Conditions/Comments Maximum value allowed in the event of a failure (see Figure 2) Maximum Junction Temperature Total Power Dissipation at 25°C Insulation Resistance at TS VIO = 500 V 1.8 Symbol Characteristic Unit TS PS RS 150 1.56 >109 °C W Ω RECOMMENDED OPERATING CONDITIONS 1.6 SAFE LIMITING POWER (W) Table 13. 1.4 Parameter Operating Temperature Supply Voltages Input Signal Rise and Fall Times 1.2 1.0 0.8 0.6 0.4 0 0 50 100 150 AMBIENT TEMPERATURE (°C) 200 13736-002 0.2 Figure 2. Thermal Derating Curve, Dependence of Safety Limiting Values with Ambient Temperature per DIN V VDE V 0884-10 Rev. 0 | Page 9 of 16 Symbol TA VDD1, VDD2 Rating −40°C to +125°C 1.7 V to 5.5 V 1.0 ms ADuM110N Data Sheet ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Table 14. Parameter Storage Temperature (TST) Range Ambient Operating Temperature (TA) Range Supply Voltages (VDD1, VDD2) Input Voltages (VI) Output Voltages (VO) Average Output Current per Pin3 Side 2 Output Current (IO2) Common-Mode Transients4 Rating −65°C to +150°C −40°C to +125°C −0.5 V to +7.0 V −0.5 V to VDDI1 + 0.5 V −0.5 V to VDDO2 + 0.5 V ESD CAUTION −10 mA to +10 mA −150 kV/μs to +150 kV/μs 1 VDDI is the input side supply voltage. VDDO is the output side supply voltage. 3 See Figure 2 for the maximum rated current values for various temperatures. 4 Refers to the common-mode transients across the insulation barrier. Common-mode transients exceeding the absolute maximum ratings may cause latch-up or permanent damage. 2 Table 15. Maximum Continuous Working Voltage1 Parameter AC Voltage Bipolar Waveform Basic Insulation Reinforced Insulation Unipolar Waveform Basic Insulation Reinforced Insulation DC Voltage Basic Insulation Reinforced Insulation 1 Rating Constraint 789 V peak 403 V peak Lifetime limited by package creepage maximum approved working voltage per IEC 60950-1 Lifetime limited by package creepage maximum approved working voltage per IEC 60950-1 909 V peak 469 V peak Lifetime limited by package creepage maximum approved working voltage per IEC 60950-1 Lifetime limited by package creepage maximum approved working voltage per IEC 60950-1 558 V peak 285 V peak Lifetime limited by package creepage maximum approved working voltage per IEC 60950-1 Lifetime limited by package creepage maximum approved working voltage per IEC 60950-1 Refers to the continuous voltage magnitude imposed across the isolation barrier. See the Insulation Lifetime section for more details. Truth Table Table 16. Truth Table (Positive Logic) VI Input1 L H X3 X3 VDDI State Powered Powered Unpowered Powered VDD2 State Powered Powered Powered Unpowered Default Low (N0),2 VO Output1 L H L Indeterminate 1 Default High (N1),2 VO Output1 L H H Indeterminate Test Conditions/ Comments Normal operation Normal operation Fail-safe output H means high, L means low, and X means don’t care. N0 indicates the ADuM110N0 models and N1 indicates the ADuM110N1 models. See the Ordering Guide section. 3 The input pin (VI) on the same side as an unpowered supply must be in a low state to avoid powering the device through its ESD protection circuitry. 2 Rev. 0 | Page 10 of 16 Data Sheet ADuM110N PIN CONFIGURATION AND FUNCTION DESCRIPTIONS VDD1 1 1 VI 2 VDD1 1 3 GND1 4 8 VDD2 ADuM110N 7 TOP VIEW (Not to Scale) GND22 6 VO 5 GND22 MAY BE USED FOR VDD1 . 2 PIN 5 AND PIN 7 ARE INTERNALLY CONNECTED. EITHER OR BOTH MAY BE USED FOR GND2. 13736-004 1 PIN 1 AND PIN 3 ARE INTERNALLY CONNECTED. EITHER OR BOTH Figure 3. Pin Configuration Table 17. Pin Function Descriptions Pin No. 1 2 3 4 5 6 7 8 1 Mnemonic VDD1 VI VDD1 GND1 GND2 VO GND2 VDD2 Description1 Supply Voltage for Isolator Side 1. Logic Input. Supply Voltage for Isolator Side 1. Ground 1. Ground reference for Isolator Side 1. Ground 2. Ground reference for Isolator Side 2. Logic Output. Ground 2. Ground reference for Isolator Side 2. Supply Voltage for Isolator Side 2. Refer to the AN-1109 Application Note for specific layout guidelines. Rev. 0 | Page 11 of 16 ADuM110N Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 14 3 2 1 5V 3.3V 2.5V 1.8V 0 0 20 40 60 80 100 120 140 160 DATA RATE (Mbps) 8 6 4 5V 3.3V 2.5V 1.8V 2 Figure 4. IDD1 Total Supply Current vs. Data Rate at Various Voltages 0 –40 –20 0 20 40 60 80 100 120 140 TEMPERATURE (°C) Figure 6. Propagation Delay, tPLH vs. Temperature at Various Voltages 5 14 3 2 1 5V 3.3V 2.5V 1.8V 0 0 20 40 60 80 100 DATA RATE (Mbps) 120 140 160 10 8 6 4 5V 3.3V 2.5V 1.8V 2 0 –40 Figure 5. IDD2 Total Supply Current vs. Data Rate at Various Voltages –20 0 20 40 60 80 TEMPERATURE (°C) 100 120 140 13736-015 PROPAGATION DELAY, tPHL (ns) 12 4 13736-013 IDD2 TOTAL SUPPLY CURRENT (mA) 10 13736-014 PROPAGATION DELAY, tPLH (ns) 12 4 13736-012 IDD1 TOTAL SUPPLY CURRENT (mA) 5 Figure 7. Propagation Delay, tPHL vs. Temperature at Various Voltages Rev. 0 | Page 12 of 16 Data Sheet ADuM110N APPLICATIONS INFORMATION OVERVIEW PRINTED CIRCUIT BOARD (PCB) LAYOUT The ADuM110N uses a high frequency carrier to transmit data across the isolation barrier using iCoupler chip scale transformer coils separated by layers of polyimide isolation. Using an on-off keying (OOK) technique and the differential architecture shown in Figure 9 and Figure 10, the ADuM110N has very low propagation delay and high speed. Internal regulators and input/output design techniques allow logic and supply voltages over a wide range from 1.7 V to 5.5 V, offering voltage translation of 1.8 V, 2.5 V, 3.3 V, and 5 V logic. The architecture is designed for high common-mode transient immunity and high immunity to electrical noise and magnetic interference. Radiated emissions are minimized with a spread spectrum OOK carrier and other techniques. The ADuM110N digital isolator requires no external interface circuitry for the logic interfaces. Power supply bypassing is strongly recommended at the input and output supply pins (see Figure 8). Bypass capacitors are most conveniently connected between Pin 1 and Pin 4 for VDD1 and between Pin 5 and Pin 8 for VDD2. The recommended bypass capacitor value is between 0.01 μF and 0.1 μF. The total lead length between both ends of the capacitor and the input power supply pin must not exceed 10 mm. Figure 9 shows the waveforms for the ADuM110N0 models, which have the condition of the fail-safe output state equal to low, where the carrier waveform is off when the input state is low. If the input side is off or not operating, the fail-safe output state of low (noted by a 0 in the model number) sets the output to low. For the ADuM110N1 models, which have a fail-safe output state of high, Figure 10 shows the conditions where the carrier waveform is off when the input state is high. When the input side is off or not operating, the fail-safe output state of high (noted by a 1 in the model number) sets the output to high. See the Ordering Guide for the model numbers that have the fail-safe output state of low or the fail-safe output state of high. VDD2 VIA VDD1 GND2 VOA GND1 GND2 13736-005 VDD1 Figure 8. Recommended PCB Layout In applications involving high common-mode transients, ensure that board coupling across the isolation barrier is minimized. Furthermore, design the board layout such that any coupling that does occur equally affects all pins on a given component side. Failure to ensure this can cause voltage differentials between pins exceeding the Absolute Maximum Ratings of the device, thereby leading to latch-up or permanent damage. See the AN-1109 Application Note for board layout guidelines. REGULATOR REGULATOR TRANSMITTER RECEIVER VIN GND1 GND2 13736-007 VOUT Figure 9. Operational Block Diagram of a Single Channel with a Low Fail-Safe Output State REGULATOR REGULATOR TRANSMITTER RECEIVER VIN GND1 GND2 Figure 10. Operational Block Diagram of a Single Channel with a High Fail-Safe Output State Rev. 0 | Page 13 of 16 13736-008 VOUT ADuM110N Data Sheet PROPAGATION DELAY RELATED PARAMETERS Propagation delay is a parameter that describes the time it takes a logic signal to propagate through a component. The propagation delay to a Logic 0 output may differ from the propagation delay to a Logic 1 output. INPUT (VI) 50% tPHL 13736-009 tPLH OUTPUT (VO) 50% Figure 11. Propagation Delay Parameters Pulse width distortion is the maximum difference between these two propagation delay values and is an indication of how accurately the timing of the input signal is preserved. Propagation delay skew is the maximum amount the propagation delay differs between multiple ADuM110N components operating under the same conditions Figure 12 shows the eye diagram for the ADuM110N. The measurement was taken using an Agilent 81110A pulse pattern generator at 150 Mbps with pseudorandom bit sequences (PRBS) 2(n − 1), n = 14, for 5 V supplies. Jitter was measured with the Tektronix Model 5104B oscilloscope, 1 GHz, 10 GS/sec with the DPOJET jitter and eye diagram analysis tools. The result shows a typical measurement on the ADuM110N with 380 ps p-p jitter. 5 VOLTAGE (V) 4 3 1 0 5 10 13736-010 0 TIME (ns) Surface tracking is addressed in electrical safety standards by setting a minimum surface creepage based on the working voltage, the environmental conditions, and the properties of the insulation material. Safety agencies perform characterization testing on the surface insulation of components that allows the components to be categorized in different material groups. Lower material group ratings are more resistant to surface tracking and, therefore, can provide adequate lifetime with smaller creepage. The minimum creepage for a given working voltage and material group is in each system level standard and is based on the total rms voltage across the isolation, pollution degree, and material group. The material group and creepage for the ADuM110N isolators are presented in Table 9. The lifetime of insulation caused by wear out is determined by its thickness, material properties, and the voltage stress applied. It is important to verify that the product lifetime is adequate at the application working voltage. The working voltage supported by an isolator for wear out may not be the same as the working voltage supported for tracking. It is the working voltage applicable to tracking that is specified in most standards. Testing and modeling have shown that the primary driver of longterm degradation is displacement current in the polyimide insulation causing incremental damage. The stress on the insulation can be broken down into broad categories, such as: dc stress, which causes very little wear out because there is no displacement current, and an ac component time varying voltage stress, which causes wear out. The ratings in certification documents are usually based on 60 Hz sinusoidal stress because this reflects isolation from line voltage. However, many practical applications have combinations of 60 Hz ac and dc across the barrier as shown in Equation 1. Because only the ac portion of the stress causes wear out, the equation can be rearranged to solve for the ac rms voltage, as is shown in Equation 2. For insulation wear out with the polyimide materials used in these products, the ac rms voltage determines the product lifetime. 2 –5 Surface Tracking Insulation Wear Out JITTER MEASUREMENT –10 inside the insulation material cause long-term insulation degradation. Figure 12. Eye Diagram INSULATION LIFETIME All insulation structures eventually break down when subjected to voltage stress over a sufficiently long period. The rate of insulation degradation is dependent on the characteristics of the voltage waveform applied across the insulation as well as on the materials and material interfaces. The two types of insulation degradation of primary interest are breakdown along surfaces exposed to the air and insulation wear out. Surface breakdown is the phenomenon of surface tracking, and the primary determinant of surface creepage requirements in system level standards. Insulation wear out is the phenomenon where charge injection or displacement currents VRMS VAC RMS2 VDC2 (1) VACRMS VRMS2 VDC2 (2) or where: VAC RMS is the time varying portion of the working voltage. VDC is the dc offset of the working voltage. VRMS is the total rms working voltage. Rev. 0 | Page 14 of 16 Data Sheet ADuM110N Calculation and Use of Parameters Example The following example frequently arises in power conversion applications. Assume that the line voltage on one side of the isolation is 240 VAC RMS and a 400 VDC bus voltage is present on the other side of the isolation barrier. The isolator material is polyimide. To establish the critical voltages in determining the creepage, clearance and lifetime of a device, see Figure 13 and the following equations. This is the working voltage used together with the material group and pollution degree when looking up the creepage required by a system standard. To determine if the lifetime is adequate, obtain the time varying portion of the working voltage. To obtain the ac rms voltage, use Equation 2. VACRMS VRMS VDC 2 2 VACRMS = 240 V rms In this case, the ac rms voltage is simply the line voltage of 240 V rms. This calculation is more relevant when the waveform is not sinusoidal. The value is compared to the limits for working voltage in Table 15 for the expected lifetime, less than a 60 Hz sine wave, and it is well within the limit for a 50-year service life. VAC RMS VPEAK VRMS VDC 13736-011 ISOLATION VOLTAGE VACRMS 4662 4002 TIME Note that the dc working voltage limit in Table 15 is set by the creepage of the package as specified in IEC 60664-1. This value can differ for specific system level standards. Figure 13. Critical Voltage Example The working voltage across the barrier from Equation 1 is VRMS = VAC RMS2 VDC2 VRMS = 2402 4002 VRMS = 466 V Rev. 0 | Page 15 of 16 ADuM110N Data Sheet OUTLINE DIMENSIONS 5.00 (0.1968) 4.80 (0.1890) 1 5 6.20 (0.2441) 5.80 (0.2284) 4 1.27 (0.0500) BSC 0.25 (0.0098) 0.10 (0.0040) COPLANARITY 0.10 SEATING PLANE 1.75 (0.0688) 1.35 (0.0532) 0.51 (0.0201) 0.31 (0.0122) 0.50 (0.0196) 0.25 (0.0099) 45° 8° 0° 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.0157) COMPLIANT TO JEDEC STANDARDS MS-012-AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. 012407-A 8 4.00 (0.1574) 3.80 (0.1497) Figure 14. 8-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-8) Dimensions shown in millimeters and (inches) ORDERING GUIDE Model1 ADuM110N1BRZ ADuM110N1BRZ-RL7 ADuM110N0BRZ ADuM110N0BRZ-RL7 1 Temperature Range −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C No. of Inputs, VDD1 Side 1 1 1 1 No. of Inputs, VDD2 Side 0 0 0 0 Withstand Voltage Rating (kV rms) 3.0 3.0 3.0 3.0 Z = RoHS Compliant Part. ©2015 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D13736-0-10/15(0) Rev. 0 | Page 16 of 16 Fail-Safe Output State High High Low Low Package Description 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N Package Option R-8 R-8 R-8 R-8