74HC595; 74HCT595
8-bit serial-in, serial or parallel-out shift register with output
latches; 3-state
Rev. 8 — 25 February 2016
Product data sheet
1. General description
The 74HC595; 74HCT595 is an 8-bit serial-in/serial or parallel-out shift register with a
storage register and 3-state outputs. Both the shift and storage register have separate
clocks. The device features a serial input (DS) and a serial output (Q7S) to enable
cascading and an asynchronous reset MR input. A LOW on MR will reset the shift register.
Data is shifted on the LOW-to-HIGH transitions of the SHCP input. The data in the shift
register is transferred to the storage register on a LOW-to-HIGH transition of the STCP
input. If both clocks are connected together, the shift register will always be one clock
pulse ahead of the storage register. Data in the storage register appears at the output
whenever the output enable input (OE) is LOW. A HIGH on OE causes the outputs to
assume a high-impedance OFF-state. Operation of the OE input does not affect the state
of the registers. Inputs include clamp diodes. This enables the use of current limiting
resistors to interface inputs to voltages in excess of VCC.
2. Features and benefits
8-bit serial input
8-bit serial or parallel output
Storage register with 3-state outputs
Shift register with direct clear
100 MHz (typical) shift out frequency
Complies with JEDEC standard no. 7A
Input levels:
For 74HC595: CMOS level
For 74HCT595: TTL level
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
Multiple package options
Specified from 40 C to +85 C and from 40 C to +125 C
3. Applications
Serial-to-parallel data conversion
Remote control holding register
74HC595; 74HCT595
NXP Semiconductors
8-bit serial-in, serial or parallel-out shift register with output latches; 3-state
4. Ordering information
Table 1.
Ordering information
Type number
74HC595D
Package
Temperature range
Name
Description
Version
40 C to +125 C
SO16
plastic small outline package; 16 leads;
body width 3.9 mm
SOT109-1
40 C to +125 C
SSOP16
plastic shrink small outline package; 16 leads;
body width 5.3 mm
SOT338-1
40 C to +125 C
TSSOP16
plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
SOT403-1
40 C to +125 C
DHVQFN16
plastic dual in-line compatible thermal enhanced
very thin quad flat package; no leads; 16 terminals;
body 2.5 3.5 0.85 mm
SOT763-1
74HCT595D
74HC595DB
74HCT595DB
74HC595PW
74HCT595PW
74HC595BQ
74HCT595BQ
5. Functional diagram
'6
6+&3
05
67$*(6+,)75(*,67(5
46
67&3
2(
%,76725$*(5(*,67(5
67$7(2873876
4 4 4 4 4 4 4 4
Fig 1.
PQD
Functional diagram
74HC_HCT595
Product data sheet
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Rev. 8 — 25 February 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
2 of 23
74HC595; 74HCT595
NXP Semiconductors
8-bit serial-in, serial or parallel-out shift register with output latches; 3-state
(1
6+&3 67&3
4
&
'
'
4
4
2(
PQD
PQD
Logic symbol
Fig 3.
67$*(
'
IEC logic symbol
67$*(672
'
4
67$*(
4
'
46
4
))
))
&3
4
'6
5
4
4
Fig 2.
65*
4
05
4
'6
46
&
&3
5
5
6+&3
05
'
4
'
4
/$7&+
/$7&+
&3
&3
67&3
2(
PQD
4
Fig 4.
4 4 4 4 4 4
4
Logic diagram
74HC_HCT595
Product data sheet
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Rev. 8 — 25 February 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
3 of 23
74HC595; 74HCT595
NXP Semiconductors
8-bit serial-in, serial or parallel-out shift register with output latches; 3-state
6. Pinning information
6.1 Pinning
WHUPLQDO
LQGH[DUHD
+&
+&7
9&&
4
+&
+&7
4
4
4
'6
9&&
4
4
2(
4
'6
4
4
2(
4
4
67&3
6+&3
4
4
4
05
*1'
46
6+&3
05
67&3
*1'
46
4
*1'
4
DDR
7UDQVSDUHQWWRSYLHZ
DDR
(1) This is not a supply pin. The substrate is attached to this
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad.
However, if it is soldered, the solder land should remain
floating or be connected to GND.
Fig 5.
Pin configuration SO16, SSOP16 and
TSSOP16
Fig 6.
Pin configuration for DHVQFN16
6.2 Pin description
Table 2.
Pin description
Symbol
Pin
Description
Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7
15, 1, 2, 3, 4, 5, 6, 7
parallel data output
GND
8
ground (0 V)
Q7S
9
serial data output
MR
10
master reset (active LOW)
SHCP
11
shift register clock input
STCP
12
storage register clock input
OE
13
output enable input (active LOW)
DS
14
serial data input
Q0
15
parallel data output 0
VCC
16
supply voltage
74HC_HCT595
Product data sheet
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Rev. 8 — 25 February 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
4 of 23
74HC595; 74HCT595
NXP Semiconductors
8-bit serial-in, serial or parallel-out shift register with output latches; 3-state
7. Functional description
Function table[1]
Table 3.
Control
Input
Output
Function
SHCP STCP OE
MR
DS
Q7S
Qn
X
L
X
L
NC
X
L
a LOW-level on MR only affects the shift registers
X
L
L
X
L
L
empty shift register loaded into storage register
X
X
H
L
X
L
Z
shift register clear; parallel outputs in high-impedance OFF-state
X
L
H
H
Q6S
NC
logic HIGH-level shifted into shift register stage 0. Contents of all
shift register stages shifted through, e.g. previous state of stage 6
(internal Q6S) appears on the serial output (Q7S).
X
L
H
X
NC
QnS
contents of shift register stages (internal QnS) are transferred to
the storage register and parallel output stages
L
H
X
Q6S
QnS
contents of shift register shifted through; previous contents of the
shift register is transferred to the storage register and the parallel
output stages
[1]
H = HIGH voltage state;
L = LOW voltage state;
= LOW-to-HIGH transition;
X = don’t care;
NC = no change;
Z = high-impedance OFF-state.
6+&3
'6
67&3
05
2(
=VWDWH
4
=VWDWH
4
=VWDWH
4
=VWDWH
4
46
PQD
Fig 7.
Timing diagram
74HC_HCT595
Product data sheet
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Rev. 8 — 25 February 2016
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5 of 23
74HC595; 74HCT595
NXP Semiconductors
8-bit serial-in, serial or parallel-out shift register with output latches; 3-state
8. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
Conditions
Min
Max
0.5
+7
VCC
supply voltage
IIK
input clamping current
VI < 0.5 V or VI > VCC + 0.5 V
-
20
mA
IOK
output clamping current
VO < 0.5 V or VO > VCC + 0.5 V
-
20
mA
IO
output current
VO = 0.5 V to (VCC + 0.5 V)
-
25
mA
pin Q7S
Unit
V
-
35
mA
ICC
supply current
-
70
mA
IGND
ground current
70
-
mA
Tstg
storage temperature
pins Qn
total power dissipation
Ptot
65
+150
C
SO16 package
[1]
-
500
mW
SSOP16 package
[2]
-
500
mW
TSSOP16 package
[2]
-
500
mW
DHVQFN16 package
[3]
-
500
mW
[1]
For SO16 package: Ptot derates linearly with 8 mW/K above 70 C.
[2]
For SSOP16 and TSSOP16 packages: Ptot derates linearly with 5.5 mW/K above 60 C.
[3]
For DHVQFN16 package: Ptot derates linearly with 4.5 mW/K above 60 C.
9. Recommended operating conditions
Table 5.
Recommended operating conditions
Symbol Parameter
Conditions
74HC595
74HCT595
Unit
Min
Typ
Max
Min
Typ
Max
2.0
5.0
6.0
4.5
5.0
5.5
V
input voltage
0
-
VCC
0
-
VCC
V
VO
output voltage
0
-
VCC
0
-
VCC
V
t/V
input transition rise and
fall rate
VCC
supply voltage
VI
Tamb
ambient temperature
74HC_HCT595
Product data sheet
VCC = 2.0 V
-
-
625
-
-
-
ns/V
VCC = 4.5 V
-
1.67
139
-
1.67
139
ns/V
VCC = 6.0 V
-
-
83
-
-
-
ns/V
40
+25
+125
40
+25
+125
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Rev. 8 — 25 February 2016
C
© NXP Semiconductors N.V. 2016. All rights reserved.
6 of 23
74HC595; 74HCT595
NXP Semiconductors
8-bit serial-in, serial or parallel-out shift register with output latches; 3-state
10. Static characteristics
Table 6.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
40 C to +85 C
Conditions
40 C to +125 C
Unit
Min
Typ
Max
Min
Max
VCC = 2.0 V
1.5
1.2
-
1.5
-
V
VCC = 4.5 V
3.15
2.4
-
3.15
-
V
VCC = 6.0 V
4.2
3.2
-
4.2
-
V
74HC595
VIH
VIL
VOH
HIGH-level
input voltage
LOW-level
input voltage
HIGH-level
output voltage
VCC = 2.0 V
-
0.8
0.5
-
0.5
V
VCC = 4.5 V
-
2.1
1.35
-
1.35
V
VCC = 6.0 V
-
2.8
1.8
-
1.8
V
IO = 20 A; VCC = 2.0 V
1.9
2.0
-
1.9
-
V
IO = 20 A; VCC = 4.5 V
4.4
4.5
-
4.4
-
V
IO = 20 A; VCC = 6.0 V
5.9
6.0
-
5.9
-
V
IO = 4 mA; VCC = 4.5 V
3.84
4.32
-
3.7
-
V
IO = 5.2 mA; VCC = 6.0 V
5.34
5.81
-
5.2
-
V
IO = 6 mA; VCC = 4.5 V
3.84
4.32
-
3.7
-
V
IO = 7.8 mA; VCC = 6.0 V
5.34
5.81
-
5.2
-
V
IO = 20 A; VCC = 2.0 V
-
0
0.1
-
0.1
V
IO = 20 A; VCC = 4.5 V
-
0
0.1
-
0.1
V
IO = 20 A; VCC = 6.0 V
-
0
0.1
-
0.1
V
VI = VIH or VIL
all outputs
Q7S output
Qn bus driver outputs
VOL
LOW-level
output voltage
VI = VIH or VIL
all outputs
Q7S output
IO = 4 mA; VCC = 4.5 V
-
0.15
0.33
-
0.4
V
IO = 5.2 mA; VCC = 6.0 V
-
0.16
0.33
-
0.4
V
IO = 6 mA; VCC = 4.5 V
-
0.15
0.33
-
0.4
V
Qn bus driver outputs
IO = 7.8 mA; VCC = 6.0 V
-
0.16
0.33
-
0.4
V
II
input leakage
current
VI = VCC or GND; VCC = 6.0 V
-
-
1.0
-
1.0
A
IOZ
OFF-state
output current
VI = VIH or VIL; VCC = 6.0 V;
VO = VCC or GND
-
-
5.0
-
10
A
ICC
supply current
VI = VCC or GND; IO = 0 A;
VCC = 6.0 V
-
-
80
-
160
A
CI
input
capacitance
-
3.5
-
-
-
pF
74HC_HCT595
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 8 — 25 February 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
7 of 23
74HC595; 74HCT595
NXP Semiconductors
8-bit serial-in, serial or parallel-out shift register with output latches; 3-state
Table 6.
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
40 C to +85 C
Conditions
40 C to +125 C
Min
Typ
Max
Min
Max
Unit
74HCT595
VIH
HIGH-level
input voltage
VCC = 4.5 V to 5.5 V
2.0
1.6
-
2.0
-
V
VIL
LOW-level
input voltage
VCC = 4.5 V to 5.5 V
-
1.2
0.8
-
0.8
V
VOH
HIGH-level
output voltage
VI = VIH or VIL; VCC = 4.5 V
4.4
4.5
-
4.4
-
V
3.84
4.32
-
3.7
-
V
3.7
4.32
-
3.7
-
V
-
0
0.1
-
0.1
V
-
0.15
0.33
-
0.4
V
-
0.16
0.33
-
0.4
V
all outputs
IO = 20 A
Q7S output
IO = 4 mA
Qn bus driver outputs
IO = 6 mA
VOL
LOW-level
output voltage
VI = VIH or VIL; VCC = 4.5 V
all outputs
IO = 20 A
Q7S output
IO = 4.0 mA
Qn bus driver outputs
IO = 6.0 mA
II
input leakage
current
VI = VCC or GND; VCC = 5.5 V
-
-
1.0
-
1.0
A
IOZ
OFF-state
output current
VI = VIH or VIL; VCC = 5.5 V;
VO = VCC or GND
-
-
5.0
-
10
A
ICC
supply current
VI = VCC or GND; IO = 0 A;
VCC = 5.5 V
-
-
80
-
160
A
ICC
additional
supply current
per input pin; IO = 0 A; VI = VCC
2.1 V; other inputs at VCC or GND;
VCC = 4.5 V to 5.5 V
pins MR, SHCP, STCP, OE
-
150
675
-
735
A
pin DS
-
25
113
-
123
A
-
3.5
-
-
-
pF
CI
input
capacitance
74HC_HCT595
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 8 — 25 February 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
8 of 23
74HC595; 74HCT595
NXP Semiconductors
8-bit serial-in, serial or parallel-out shift register with output latches; 3-state
11. Dynamic characteristics
Table 7.
Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 13.
Symbol Parameter
25 C
Conditions
40 C to +85 C 40 C to +125 C Unit
Min
Typ[1]
Max
Min
Max
Min
Max
-
52
160
-
200
-
240
ns
-
19
32
-
40
-
48
ns
-
15
27
-
34
-
41
ns
VCC = 2 V
-
55
175
-
220
-
265
ns
VCC = 4.5 V
-
20
35
-
44
-
53
ns
-
16
30
-
37
-
45
ns
VCC = 2 V
-
47
175
-
220
-
265
ns
VCC = 4.5 V
-
17
35
-
44
-
53
ns
-
14
30
-
37
-
45
ns
VCC = 2 V
-
47
150
-
190
-
225
ns
VCC = 4.5 V
-
17
30
-
38
-
45
ns
-
14
26
-
33
-
38
ns
VCC = 2 V
-
41
150
-
190
-
225
ns
VCC = 4.5 V
-
15
30
-
38
-
45
ns
VCC = 6 V
-
12
27
-
33
-
38
ns
VCC = 2 V
75
17
-
95
-
110
-
ns
VCC = 4.5 V
15
6
-
19
-
22
-
ns
VCC = 6 V
13
5
-
16
-
19
-
ns
74HC595
tpd
propagation SHCP to Q7S; see Figure 8
delay
VCC = 2 V
[2]
VCC = 4.5 V
VCC = 6 V
STCP to Qn; see Figure 9
[2]
VCC = 6 V
MR to Q7S; see Figure 11
[3]
VCC = 6 V
ten
enable time OE to Qn; see Figure 12
[4]
VCC = 6 V
tdis
tW
disable time OE to Qn; see Figure 12
pulse width
[5]
SHCP HIGH or LOW;
see Figure 8
STCP HIGH or LOW;
see Figure 9
VCC = 2 V
75
11
-
95
-
110
-
ns
VCC = 4.5 V
15
4
-
19
-
22
-
ns
VCC = 6 V
13
3
-
16
-
19
-
ns
MR LOW; see Figure 11
74HC_HCT595
Product data sheet
VCC = 2 V
75
17
-
95
-
110
-
ns
VCC = 4.5 V
15
6
-
19
-
22
-
ns
VCC = 6 V
13
5
-
16
-
19
-
ns
All information provided in this document is subject to legal disclaimers.
Rev. 8 — 25 February 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
9 of 23
74HC595; 74HCT595
NXP Semiconductors
8-bit serial-in, serial or parallel-out shift register with output latches; 3-state
Table 7.
Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 13.
Symbol Parameter
tsu
set-up time
25 C
Conditions
Min
Typ[1]
40 C to +85 C 40 C to +125 C Unit
Max
Min
Max
Min
Max
DS to SHCP; see Figure 9
VCC = 2 V
50
11
-
65
-
75
-
ns
VCC = 4.5 V
10
4
-
13
-
15
-
ns
VCC = 6 V
9
3
-
11
-
13
-
ns
VCC = 2 V
75
22
-
95
-
110
-
ns
VCC = 4.5 V
15
8
-
19
-
22
-
ns
VCC = 6 V
13
7
-
16
-
19
-
ns
VCC = 2 V
3
6
-
3
-
3
-
ns
VCC = 4.5 V
3
2
-
3
-
3
-
ns
VCC = 6 V
3
2
-
3
-
3
-
ns
VCC = 2 V
50
19
-
65
-
75
-
ns
VCC = 4.5 V
10
7
-
13
-
15
-
ns
VCC = 6 V
9
6
-
11
-
13
-
ns
VCC = 2 V
9
30
-
4.8
-
4
-
MHz
VCC = 4.5 V
30
91
-
24
-
20
-
MHz
35
108
-
28
-
24
-
MHz
-
115
-
-
-
-
-
pF
SHCP to STCP;
see Figure 10
th
trec
fmax
hold time
recovery
time
maximum
frequency
DS to SHCP; see Figure 10
MR to SHCP; see Figure 11
SHCP or STCP;
see Figure 8 and 9
VCC = 6 V
CPD
power
fi = 1 MHz; VI = GND to VCC
dissipation
capacitance
74HC_HCT595
Product data sheet
[6][7]
All information provided in this document is subject to legal disclaimers.
Rev. 8 — 25 February 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
10 of 23
74HC595; 74HCT595
NXP Semiconductors
8-bit serial-in, serial or parallel-out shift register with output latches; 3-state
Table 7.
Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 13.
Symbol Parameter
25 C
Conditions
40 C to +85 C 40 C to +125 C Unit
Min
Typ[1]
Max
Min
Max
Min
Max
[2]
-
25
42
-
53
-
63
ns
[2]
-
24
40
-
50
-
60
ns
[3]
-
23
40
-
50
-
60
ns
enable time OE to Qn; see Figure 12
[4]
-
21
35
-
44
-
53
ns
tdis
disable time OE to Qn; see Figure 12
[5]
tW
pulse width
74HCT595; VCC = 4.5 V to 5.5 V
propagation SHCP to Q7S; see Figure 8
delay
STCP to Qn; see Figure 9
tpd
MR to Q7S; see Figure 11
ten
set-up time
tsu
-
18
30
-
38
-
45
ns
SHCP HIGH or LOW;
see Figure 8
16
6
-
20
-
24
-
ns
STCP HIGH or LOW;
see Figure 9
16
5
-
20
-
24
-
ns
MR LOW; see Figure 11
20
8
-
25
-
30
-
ns
DS to SHCP; see Figure 9
16
5
-
20
-
24
-
ns
SHCP to STCP;
see Figure 10
16
8
-
20
-
24
-
ns
th
hold time
DS to SHCP; see Figure 10
3
2
-
3
-
3
-
ns
trec
recovery
time
MR to SHCP; see Figure 11
10
7
-
13
-
15
-
ns
fmax
maximum
frequency
SHCP and STCP;
see Figure 8 and 9
30
52
-
24
-
20
-
MHz
CPD
power
fi = 1 MHz;
dissipation VI = GND to VCC 1.5 V
capacitance
-
130
-
-
-
-
-
pF
[1]
[7]
Typical values are measured at nominal supply voltage.
[2]
tpd is the same as tPHL and tPLH.
[3]
tpd is the same as tPHL only.
[4]
ten is the same as tPZL and tPZH.
[5]
tdis is the same as tPLZ and tPHZ.
[6]
[6]
CPD is used to determine the dynamic power dissipation (PD in W).
PD = CPD VCC2 fi + (CL VCC2 fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
(CL VCC2 fo) = sum of outputs;
CL = output load capacitance in pF;
VCC = supply voltage in V.
[7]
All 9 outputs switching.
74HC_HCT595
Product data sheet
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74HC595; 74HCT595
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8-bit serial-in, serial or parallel-out shift register with output latches; 3-state
12. Waveforms
IPD[
9,
6+&3LQSXW
90
*1'
W:
W 3+/
W 3/+
92+
90
46RXWSXW
92/
PQD
Measurement points are given in Table 8.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig 8.
Shift clock pulse, maximum frequency and input to output propagation delays
9,
6+&3LQSXW
90
*1'
IPD[
W VX
9,
67&3LQSXW
90
*1'
W:
W 3+/
W 3/+
92+
90
4QRXWSXW
92/
PQD
Measurement points are given in Table 8.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig 9.
Storage clock to output propagation delays
74HC_HCT595
Product data sheet
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74HC595; 74HCT595
NXP Semiconductors
8-bit serial-in, serial or parallel-out shift register with output latches; 3-state
9,
90
6+&3LQSXW
*1'
W VX
W VX
WK
WK
9,
90
'6LQSXW
*1'
92+
90
46RXWSXW
92/
PQD
Measurement points are given in Table 8.
The shaded areas indicate when the input is permitted to change for predictable output performance.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig 10. Data set-up and hold times
9,
90
05LQSXW
*1'
W:
W UHF
9,
6+&3LQSXW
*1'
90
W 3+/
92+
90
46RXWSXW
92/
PQD
Measurement points are given in Table 8.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig 11. Master reset to output propagation delays
74HC_HCT595
Product data sheet
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Rev. 8 — 25 February 2016
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74HC595; 74HCT595
NXP Semiconductors
8-bit serial-in, serial or parallel-out shift register with output latches; 3-state
WU
WI
90
2(LQSXW
W3/=
W3=/
4QRXWSXW
90
/2:WR2))
2))WR/2:
W3+=
W3=+
4QRXWSXW
90
+,*+WR2))
2))WR+,*+
RXWSXWV
HQDEOHG
RXWSXWV
HQDEOHG
RXWSXWV
GLVDEOHG
PVD
Measurement points are given in Table 8.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig 12. Enable and disable times
Table 8.
Measurement points
Type
Input
Output
VM
VM
74HC595
0.5VCC
0.5VCC
74HCT595
1.3 V
1.3 V
74HC_HCT595
Product data sheet
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Rev. 8 — 25 February 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
14 of 23
74HC595; 74HCT595
NXP Semiconductors
8-bit serial-in, serial or parallel-out shift register with output latches; 3-state
9,
W:
QHJDWLYH
SXOVH
90
9
WI
WU
WU
WI
9,
SRVLWLYH
SXOVH
9
90
90
90
W:
9&&
9&&
*
9,
92
5/
6
RSHQ
'87
&/
57
DDG
Test data is given in Table 9.
Definitions for test circuit:
CL = load capacitance including jig and probe capacitance.
RL = load resistance.
RT = termination resistance should be equal to the output impedance Zo of the pulse generator.
S1 = test selection switch.
Fig 13. Test circuit for measuring switching times
Table 9.
Test data
Type
Input
VI
tr, tf
CL
RL
tPHL, tPLH
tPZH, tPHZ
tPZL, tPLZ
74HC595
VCC
6 ns
50 pF
1 k
open
GND
VCC
74HCT595
3V
6 ns
50 pF
1 k
open
GND
VCC
74HC_HCT595
Product data sheet
Load
S1 position
All information provided in this document is subject to legal disclaimers.
Rev. 8 — 25 February 2016
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74HC595; 74HCT595
NXP Semiconductors
8-bit serial-in, serial or parallel-out shift register with output latches; 3-state
13. Package outline
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74HC_HCT595
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 8 — 25 February 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
16 of 23
74HC595; 74HCT595
NXP Semiconductors
8-bit serial-in, serial or parallel-out shift register with output latches; 3-state
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74HC_HCT595
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 8 — 25 February 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
17 of 23
74HC595; 74HCT595
NXP Semiconductors
8-bit serial-in, serial or parallel-out shift register with output latches; 3-state
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74HC_HCT595
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 8 — 25 February 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
18 of 23
74HC595; 74HCT595
NXP Semiconductors
8-bit serial-in, serial or parallel-out shift register with output latches; 3-state
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74HC_HCT595
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 8 — 25 February 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
19 of 23
74HC595; 74HCT595
NXP Semiconductors
8-bit serial-in, serial or parallel-out shift register with output latches; 3-state
14. Abbreviations
Table 10.
Abbreviations
Acronym
Abbreviation
CMOS
Complementary Metal Oxide Semiconductor
DUT
Device Under Test
ESD
ElectroStatic Discharge
HBM
Human Body Model
LSTTL
Low-power Schottky Transistor-Transistor Logic
MM
Machine Model
15. Revision history
Table 11.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
74HC_HCT595 v.8
20160225
Product data sheet
-
74HC_HCT595 v.7
Modifications:
74HC_HCT595 v.7
Modifications:
74HC_HCT595 v.6
Modifications:
•
Type numbers 74HC595N and 74HCT595N (SOT38-4) removed.
20150126
•
-
74HC_HCT595 v.6
Table 7: Power dissipation capacitance condition for 74HCT595 is corrected.
20111212
•
Product data sheet
Product data sheet
-
74HC_HCT595 v.5
Legal pages updated.
74HC_HCT595 v.5
20110628
Product data sheet
-
74HC_HCT595 v.4
74HC_HCT595 v.4
20030604
Product specification
-
74HC_HCT595_CNV v.3
74HC_HCT595_CNV v.3
19980604
Product specification
-
-
74HC_HCT595
Product data sheet
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Rev. 8 — 25 February 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
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74HC595; 74HCT595
NXP Semiconductors
8-bit serial-in, serial or parallel-out shift register with output latches; 3-state
16. Legal information
16.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
16.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
16.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
74HC_HCT595
Product data sheet
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
All information provided in this document is subject to legal disclaimers.
Rev. 8 — 25 February 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
21 of 23
74HC595; 74HCT595
NXP Semiconductors
8-bit serial-in, serial or parallel-out shift register with output latches; 3-state
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
16.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
17. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
74HC_HCT595
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 8 — 25 February 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
22 of 23
74HC595; 74HCT595
NXP Semiconductors
8-bit serial-in, serial or parallel-out shift register with output latches; 3-state
18. Contents
1
2
3
4
5
6
6.1
6.2
7
8
9
10
11
12
13
14
15
16
16.1
16.2
16.3
16.4
17
18
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
Pinning information . . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
Functional description . . . . . . . . . . . . . . . . . . . 5
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6
Recommended operating conditions. . . . . . . . 6
Static characteristics. . . . . . . . . . . . . . . . . . . . . 7
Dynamic characteristics . . . . . . . . . . . . . . . . . . 9
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 16
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 20
Legal information. . . . . . . . . . . . . . . . . . . . . . . 21
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 21
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Contact information. . . . . . . . . . . . . . . . . . . . . 22
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP Semiconductors N.V. 2016.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 25 February 2016
Document identifier: 74HC_HCT595