ADuM3211-DSCC: Military Data Sheet

REVISIONS
LTR
DESCRIPTION
DATE
Prepared in accordance with ASME Y14.24
APPROVED
Vendor item drawing
REV
PAGE
REV
PAGE
18
19
REV STATUS
OF PAGES
20
21
REV
PAGE
1
2
PMIC N/A
PREPARED BY
RICK OFFICER
Original date of drawing
YY-MM-DD
CHECKED BY
RAJESH PITHADIA
15-07-20
4
A
REV
5
6
7
8
9
10
11
12
13
14
15
16
17
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
http://www.landandmaritime.dla.mil/
TITLE
MICROCIRCUIT, LINEAR, DUAL CHANNEL
DIGITAL ISOLATOR, ENHANCED SYSTEM
LEVEL ESD RELIABILITY, MONOLITHIC SILICON
APPROVED BY
CHARLES F. SAFFLE
SIZE
AMSC N/A
3
CODE IDENT. NO.
DWG NO.
V62/14628
16236
PAGE
1
OF
21
5962-V069-15
1. SCOPE
1.1 Scope. This drawing documents the general requirements of a dual channel digital isolator, enhanced system level electrostatic
discharge (ESD) reliability microcircuit, with an operating temperature range of -55C to +125C.
1.2 Vendor Item Drawing Administrative Control Number. The manufacturer’s PIN is the item of identification. The vendor item
drawing establishes an administrative control number for identifying the item on the engineering documentation:
V62/14628
-
Drawing
number
01
X
E
Device type
(See 1.2.1)
Case outline
(See 1.2.2)
Lead finish
(See 1.2.3)
1.2.1 Device type(s).
Device type
Generic
01
Circuit function
ADUM3211TRZ-EP
Dual channel digital isolator, enhanced system
level ESD reliability
1.2.2 Case outline(s). The case outline(s) are as specified herein.
Outline letter
Number of pins
X
8
JEDEC PUB 95
Package style
MS-012-AA
Small outline package
1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacturer:
Finish designator
A
B
C
D
E
Z
DLA LAND AND MARITIME
COLUMBUS, OHIO
Material
Hot solder dip
Tin-lead plate
Gold plate
Palladium
Gold flash palladium
Other
SIZE
A
CODE IDENT NO.
16236
REV
DWG NO.
V62/14628
PAGE
2
1.3 Absolute maximum ratings.
1/
Supply voltages range (VDD1, VDD2) ......................................................................... -0.5 V to +7.0 V 2/
Input voltage (VIA, VIB) .............................................................................................. -0.5 V to VDDI + 0.5 V 2/ 3/
Output voltage (VOA, VOB) ........................................................................................ -0.5 V to VDDO + 0.5 V 2/ 3/
Average output current per pin (IO) ............................................................................ -22 mA to +22 mA 4/
Common mode transients (CMH, CML) ...................................................................... -100 kV/s to +100 kV/s 5/
Storage temperature range (TSTG) ............................................................................ -55C to +150C
1.4 Recommended operating conditions. 6/
Supply voltages (VDD1, VDD2) ................................................................................... 3 V to 5.5 V 7/
Maximum input signal rise and fall times .................................................................... 1 ms
Start-up current (IDD1, IDD2) ...................................................................................... 20 mA
Operating free-air temperature range (TA) ................................................................. -55C to +125C
1.5 Package characteristics.
12
Resistance (input to output) (RI-O) ............................................................................. 10
 typical 8/
Capacitance (input to output) (CI-O) (f = 1 MHz) ........................................................ 1.0 pF typical 8/
Input capacitance (CI) ................................................................................................ 4.0 pF typical
Thermal resistance, junction to case (JCI) side 1 ..................................................... 46C/W typical
Thermocouple located at center of package underside
Thermal resistance, junction to case (JCO) side 2 .................................................... 41C/W typical
1/
2/
3/
4/
5/
6/
7/
8/
Stresses beyond those listed under “absolute maximum rating” may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions beyond those indicated under
“recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may
affect device reliability.
Each voltage is relative to its respective ground.
VDDI and VDDO refer to the supply voltages on the input and output sides of a given channel, respectively.
See figure 4 for maximum allowable current values for various temperatures.
Refers to common mode transients across the insulation barrier. Common mode transients exceeding the absolute maximum
rating can cause latch up or permanent damage.
Use of this product beyond the manufacturers design rules or stated parameters is done at the user’s risk. The manufacturer
and/or distributor maintain no responsibility or liability for product used beyond the stated limits.
All voltages are relative to their respective ground.
The device is considered a 2 terminal device. Pin 1 through pin 4 are shorted together, and pin 5 through pin 8 are
shorted together.
DLA LAND AND MARITIME
COLUMBUS, OHIO
SIZE
A
CODE IDENT NO.
16236
REV
DWG NO.
V62/14628
PAGE
3
2. APPLICABLE DOCUMENTS
JEDEC Solid State Technology Association
JEDEC PUB 95
–
Registered and Standard Outlines for Semiconductor Devices
(Copies of these documents are available online at http:/www.jedec.org or from JEDEC – Solid State Technology Association,
3103 North 10th Street, Suite 240–S, Arlington, VA 22201-2107).
3. REQUIREMENTS
3.1 Marking. Parts shall be permanently and legibly marked with the manufacturer’s part number as shown in 6.3 herein and as
follows:
A.
B.
C.
Manufacturer’s name, CAGE code, or logo
Pin 1 identifier
ESDS identification (optional)
3.2 Unit container. The unit container shall be marked with the manufacturer’s part number and with items A and C (if applicable)
above.
3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are
as specified in 1.3, 1.4, and table I herein.
3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein.
3.5 Diagrams.
3.5.1 Case outline. The case outline shall be as shown in 1.2.2 and figure 1.
3.5.2 Terminal connections. The terminal connections shall be as shown in figure 2.
3.5.3 Truth table. The truth table shall be as shown in figure 3.
3.5.4 Thermal derating curve. The thermal derating curve shall be as shown in figure 4.
DLA LAND AND MARITIME
COLUMBUS, OHIO
SIZE
A
CODE IDENT NO.
16236
REV
DWG NO.
V62/14628
PAGE
4
TABLE I. Electrical performance characteristics. 1/
Test
Supply current
Symbol
IDD1
Conditions 2/
VDD1 = VDD2 = 5 V,
unless otherwise specified
Temperature,
TA
Device
type
Min
1 Mbps
-55C to +125C
01
10 Mbps
3.0 typical
8.7
-55C to +125C
6.4 typical
+25C
1.8
-55C to +125C
1.3 typical
+25C
10 Mbps
4.1
-55C to +125C
3.1 typical
+25C
25 Mbps
mA
4.0
+25C
1 Mbps
Max
1.5
-55C to +125C
25 Mbps
Unit
1.1 typical
+25C
IDD2
Limits
8.0
-55C to +125C
6.1 typical
+25C
Switching specifications.
Data rate
Propagation delay
tPHL,
Within PWD limit
-55C to +125C
01
50% input to 50% output
-55C to +125C
01
|tPLH –tPHL|
-55C to +125C
01
+25C
01
20
25
Mbps
50
ns
3
ns
tPLH
Pulse width distortion
PWD
Pulse width distortion
change vs temperature
5 typical
ps/C
Pulse width
PW
Within PWD limit
-55C to +125C
01
Propagation delay skew
tPSK
Between any two units
-55C to +125C
01
18
ns
Channel matching:
codirectional
tPSKCD
-55C to +125C
01
3
ns
Channel matching:
opposing directional
tPSKOD
-55C to +125C
01
18
ns
Output rise/fall time
t R / tF
+25C
01
10% to 90%
40
ns
2.5 typical
ns
See footnotes at end of table.
DLA LAND AND MARITIME
COLUMBUS, OHIO
SIZE
A
CODE IDENT NO.
16236
REV
DWG NO.
V62/14628
PAGE
5
TABLE I. Electrical performance characteristics – Continued. 1/
Test
Symbol
Conditions 2/
VDD1 = VDD2 = 5 V,
unless otherwise specified
Temperature,
TA
Device
type
Limits
Min
Unit
Max
DC specifications.
Logic high input
threshold
VIH
-55C to +125C
01
Logic low input
threshold
VIL
-55C to +125C
01
Logic high output
voltages
VOH
-55C to +125C
01
IOx = -20 A, VIx = VIxH
0.7
VDDx
0.3
VDDx
VOL
-55C to +125C
IOx = 20 A, VIx = VIxL
-55C to +125C
VDDx
– 0.5
VDDX – 0.2
typical
01
II
0 V  VIx  VDDx
-55C to +125C
V
0.4
-55C to +125C
0.2 typical
+25C
Input current per
channel
0.1
0.0 typical
+25C
IOx = 4 mA, VIx = VIxL
V
VDDX typical
+25C
Logic low output
voltages
V
VDDx
– 0.1
+25C
IOx = -4 mA, VIx = VIxH
V
01
-10
+10
A
+0.01 typical
+25C
Supply current per channel.
Quiescent input supply
current
-55C to +125C
IDDI(Q)
01
-55C to +125C
IDDO(Q)
mA
0.4 typical
+25C
Quiescent output
supply current
0.8
01
+25C
0.8
mA
0.4 typical
See footnotes at end of table.
DLA LAND AND MARITIME
COLUMBUS, OHIO
SIZE
A
CODE IDENT NO.
16236
REV
DWG NO.
V62/14628
PAGE
6
TABLE I. Electrical performance characteristics – Continued. 1/
Test
Symbol
Conditions 2/
VDD1 = VDD2 = 5 V,
unless otherwise specified
Temperature,
TA
Device
type
Limits
Min
Unit
Max
DC specifications – continued.
Supply current per channel – continued.
Dynamic input supply
current
IDDI(D)
+25C
01
0.19 typical
mA/
Mbps
Dynamic output supply
current
IDDO(D)
+25C
01
0.05 typical
mA/
Mbps
VIx = VDDx, VCM = 1000 V,
-55C to +125C
01
25
kV/s
transient magnitude = 800 V
+25C
AC specifications.
Common mode 3/
transient immunity
Refresh rate
|CM|
fr
+25C
35 typical
01
1.2 typical
Mbps
See footnotes at end of table.
DLA LAND AND MARITIME
COLUMBUS, OHIO
SIZE
A
CODE IDENT NO.
16236
REV
DWG NO.
V62/14628
PAGE
7
TABLE I. Electrical performance characteristics – Continued. 1/
Test
Supply current
Symbol
IDD1
Conditions 4/
VDD1 = VDD2 = 3.3 V,
unless otherwise specified
Temperature,
TA
Device
type
Min
1 Mbps
-55C to +125C
01
10 Mbps
1.8 typical
5.4
-55C to +125C
3.8 typical
+25C
1.6
-55C to +125C
0.8 typical
+25C
10 Mbps
2.5
-55C to +125C
1.9 typical
+25C
25 Mbps
mA
2.6
+25C
1 Mbps
Max
1.3
-55C to +125C
25 Mbps
Unit
0.7 typical
+25C
IDD2
Limits
5.0
-55C to +125C
3.7 typical
+25C
Switching specifications.
Data rate
Propagation delay
tPHL,
Within PWD limit
-55C to +125C
01
50% input to 50% output
-55C to +125C
01
|tPLH –tPHL|
-55C to +125C
01
+25C
01
20
25
Mbps
60
ns
4
ns
tPLH
Pulse width distortion
PWD
Pulse width distortion
change vs temperature
5 typical
ps/C
Pulse width
PW
Within PWD limit
-55C to +125C
01
Propagation delay skew
tPSK
Between any two units
-55C to +125C
01
22
ns
Channel matching:
codirectional
tPSKCD
-55C to +125C
01
3
ns
Channel matching:
opposing directional
tPSKOD
-55C to +125C
01
20
ns
Output rise/fall time
t R / tF
+25C
01
10% to 90%
40
ns
3.0 typical
ns
See footnotes at end of table.
DLA LAND AND MARITIME
COLUMBUS, OHIO
SIZE
A
CODE IDENT NO.
16236
REV
DWG NO.
V62/14628
PAGE
8
TABLE I. Electrical performance characteristics – Continued. 1/
Test
Symbol
Conditions 4/
VDD1 = VDD2 = 3.3 V,
unless otherwise specified
Temperature,
TA
Device
type
Limits
Min
Unit
Max
DC specifications.
Logic high input
threshold
VIH
-55C to +125C
01
Logic low input
threshold
VIL
-55C to +125C
01
Logic high output
voltages
VOH
-55C to +125C
01
IOx = -20 A, VIx = VIxH
0.7
VDDx
0.3
VDDx
VOL
-55C to +125C
IOx = 20 A, VIx = VIxL
-55C to +125C
VDDx
– 0.5
VDDX – 0.2
typical
01
II
0 V  VIx  VDDx
-55C to +125C
V
0.4
-55C to +125C
0.2 typical
+25C
Input current per
channel
0.1
0.0 typical
+25C
IOx = 2 mA, VIx = VIxL
V
VDDX typical
+25C
Logic low output
voltages
V
VDDx
– 0.1
+25C
IOx = -2 mA, VIx = VIxH
V
01
-10
+10
A
+0.01 typical
+25C
Supply current per channel.
Quiescent input supply
current
-55C to +125C
IDDI(Q)
01
-55C to +125C
IDDO(Q)
mA
0.3 typical
+25C
Quiescent output
supply current
0.5
01
+25C
0.5
mA
0.3 typical
See footnotes at end of table.
DLA LAND AND MARITIME
COLUMBUS, OHIO
SIZE
A
CODE IDENT NO.
16236
REV
DWG NO.
V62/14628
PAGE
9
TABLE I. Electrical performance characteristics – Continued. 1/
Test
Symbol
Conditions 4/
VDD1 = VDD2 = 3.3 V,
unless otherwise specified
Temperature,
TA
Device
type
Limits
Min
Unit
Max
DC specifications – continued.
Supply current per channel – continued.
Dynamic input supply
current
IDDI(D)
+25C
01
0.10 typical
mA/
Mbps
Dynamic output supply
current
IDDO(D)
+25C
01
0.03 typical
mA/
Mbps
VIx = VDDx, VCM = 1000 V,
-55C to +125C
01
25
kV/s
transient magnitude = 800 V
+25C
AC specifications.
Common mode 3/
transient immunity
Refresh rate
|CM|
fr
+25C
35 typical
01
1.1 typical
Mbps
See footnotes at end of table.
DLA LAND AND MARITIME
COLUMBUS, OHIO
SIZE
A
CODE IDENT NO.
16236
REV
DWG NO.
V62/14628
PAGE
10
TABLE I. Electrical performance characteristics – Continued. 1/
Test
Supply current
Symbol
IDD1
Conditions 5/
VDD1 = 5 V, VDD2 = 3.3 V,
unless otherwise specified
Temperature,
TA
Device
type
Min
1 Mbps
-55C to +125C
01
10 Mbps
2.9 typical
8.7
-55C to +125C
6.4 typical
+25C
1.6
-55C to +125C
0.8 typical
+25C
10 Mbps
2.5
-55C to +125C
1.9 typical
+25C
25 Mbps
mA
4.0
+25C
1 Mbps
Max
1.5
-55C to +125C
25 Mbps
Unit
1.1 typical
+25C
IDD2
Limits
5.0
-55C to +125C
3.7 typical
+25C
Switching specifications.
Data rate
Propagation delay
tPHL,
Within PWD limit
-55C to +125C
01
50% input to 50% output
-55C to +125C
01
|tPLH –tPHL|
-55C to +125C
01
+25C
01
15
25
Mbps
55
ns
3
ns
tPLH
Pulse width distortion
PWD
Pulse width distortion
change vs temperature
5 typical
ps/C
Pulse width
PW
Within PWD limit
-55C to +125C
01
Propagation delay skew
tPSK
Between any two units
-55C to +125C
01
22
ns
Channel matching:
codirectional
tPSKCD
-55C to +125C
01
3
ns
Channel matching:
opposing directional
tPSKOD
-55C to +125C
01
20
ns
Output rise/fall time
t R / tF
+25C
01
10% to 90%
40
ns
3.0 typical
ns
See footnotes at end of table.
DLA LAND AND MARITIME
COLUMBUS, OHIO
SIZE
A
CODE IDENT NO.
16236
REV
DWG NO.
V62/14628
PAGE
11
TABLE I. Electrical performance characteristics – Continued. 1/
Test
Symbol
Conditions 5/
VDD1 = 5 V, VDD2 = 3.3 V,
unless otherwise specified
Temperature,
TA
Device
type
Limits
Min
Unit
Max
DC specifications.
Logic high input
threshold
VIH
-55C to +125C
01
Logic low input
threshold
VIL
-55C to +125C
01
Logic high output
voltages
VOH
-55C to +125C
01
IOx = -20 A, VIx = VIxH
0.7
VDDx
0.3
VDDx
VDDX typical
-55C to +125C
VDDx
– 0.5
+25C
Logic low output
voltages
VOL
IOx = 20 A, VIx = VIxL
-55C to +125C
VDDX – 0.2
typical
01
II
0 V  VIx  VDDx
-55C to +125C
V
0.4
-55C to +125C
0.2 typical
+25C
Input current per
channel
0.1
0.0 typical
+25C
IOx = 2 mA, VIx = VIxL
V
V
VDDx
– 0.1
+25C
IOx = -2 mA, VIx = VIxH
V
01
-10
+10
A
+0.01 typical
+25C
Supply current per channel.
Quiescent input supply
current
-55C to +125C
IDDI(Q)
01
-55C to +125C
IDDO(Q)
mA
0.4 typical
+25C
Quiescent output
supply current
0.8
01
+25C
0.5
mA
0.3 typical
See footnotes at end of table.
DLA LAND AND MARITIME
COLUMBUS, OHIO
SIZE
A
CODE IDENT NO.
16236
REV
DWG NO.
V62/14628
PAGE
12
TABLE I. Electrical performance characteristics – Continued. 1/
Test
Symbol
Conditions 5/
VDD1 = 5 V, VDD2 = 3.3 V,
unless otherwise specified
Temperature,
TA
Device
type
Limits
Min
Unit
Max
DC specifications – continued.
Supply current per channel – continued.
Dynamic input supply
current
IDDI(D)
+25C
01
0.19 typical
mA/
Mbps
Dynamic output supply
current
IDDO(D)
+25C
01
0.03 typical
mA/
Mbps
VIx = VDDx, VCM = 1000 V,
-55C to +125C
01
25
kV/s
transient magnitude = 800 V
+25C
AC specifications.
Common mode 3/
transient immunity
Refresh rate
|CM|
fr
+25C
35 typical
01
1.2 typical
Mbps
See footnotes at end of table.
DLA LAND AND MARITIME
COLUMBUS, OHIO
SIZE
A
CODE IDENT NO.
16236
REV
DWG NO.
V62/14628
PAGE
13
TABLE I. Electrical performance characteristics – Continued. 1/
Test
Supply current
Symbol
IDD1
Conditions 6/
VDD1 = 3.3 V, VDD2 = 5.0 V,
unless otherwise specified
1 Mbps
Temperature,
TA
Device
type
Min
-55C to +125C
01
1.8 typical
5.4
-55C to +125C
3.8 typical
+25C
1 Mbps
1.8
-55C to +125C
1.3 typical
+25C
10 Mbps
4.1
-55C to +125C
3.1 typical
+25C
25 Mbps
mA
2.6
+25C
IDD2
Max
1.3
-55C to +125C
25 Mbps
Unit
0.7 typical
+25C
10 Mbps
Limits
8.0
-55C to +125C
6.1 typical
+25C
Switching specifications.
Data rate
Propagation delay
tPHL,
Within PWD limit
-55C to +125C
01
50% input to 50% output
-55C to +125C
01
|tPLH –tPHL|
-55C to +125C
01
+25C
01
15
25
Mbps
55
ns
4
ns
tPLH
Pulse width distortion
PWD
Pulse width distortion
change vs temperature
5 typical
ps/C
Pulse width
PW
Within PWD limit
-55C to +125C
01
Propagation delay skew
tPSK
Between any two units
-55C to +125C
01
22
ns
Channel matching:
codirectional
tPSKCD
-55C to +125C
01
3
ns
Channel matching:
opposing directional
tPSKOD
-55C to +125C
01
20
ns
Output rise/fall time
t R / tF
+25C
01
10% to 90%
40
ns
2.5 typical
ns
See footnotes at end of table.
DLA LAND AND MARITIME
COLUMBUS, OHIO
SIZE
A
CODE IDENT NO.
16236
REV
DWG NO.
V62/14628
PAGE
14
TABLE I. Electrical performance characteristics – Continued. 1/
Test
Symbol
Conditions 6/
VDD1 = 3.3 V, VDD2 = 5.0 V,
unless otherwise specified
Temperature,
TA
Device
type
Limits
Min
Unit
Max
DC specifications.
Logic high input
threshold
VIH
-55C to +125C
01
Logic low input
threshold
VIL
-55C to +125C
01
Logic high output
voltages
VOH
-55C to +125C
01
IOx = -20 A, VIx = VIxH
0.7
VDDx
0.3
VDDx
VDDX typical
-55C to +125C
VDDx
– 0.5
+25C
Logic low output
voltages
VOL
IOx = 20 A, VIx = VIxL
-55C to +125C
VDDX – 0.2
typical
01
II
0 V  VIx  VDDx
-55C to +125C
V
0.4
-55C to +125C
0.2 typical
+25C
Input current per
channel
0.1
0.0 typical
+25C
IOx = 2 mA, VIx = VIxL
V
V
VDDx
– 0.1
+25C
IOx = -2 mA, VIx = VIxH
V
01
-10
+10
A
+0.01 typical
+25C
Supply current per channel.
Quiescent input supply
current
-55C to +125C
IDDI(Q)
01
-55C to +125C
IDDO(Q)
mA
0.4 typical
+25C
Quiescent output
supply current
0.8
01
+25C
0.8
mA
0.5 typical
See footnotes at end of table.
DLA LAND AND MARITIME
COLUMBUS, OHIO
SIZE
A
CODE IDENT NO.
16236
REV
DWG NO.
V62/14628
PAGE
15
TABLE I. Electrical performance characteristics – Continued. 1/
Test
Symbol
Conditions 6/
VDD1 = 3.3 V, VDD2 = 5.0 V,
unless otherwise specified
Temperature,
TA
Device
type
Limits
Min
Unit
Max
DC specifications – continued.
Supply current per channel – continued.
Dynamic input supply
current
IDDI(D)
+25C
01
0.10 typical
mA/
Mbps
Dynamic output supply
current
IDDO(D)
+25C
01
0.05 typical
mA/
Mbps
VIx = VDDx, VCM = 1000 V,
-55C to +125C
01
25
kV/s
transient magnitude = 800 V
+25C
AC specifications.
Common mode 3/
transient immunity
Refresh rate
|CM|
fr
+25C
35 typical
01
1.1 typical
Mbps
1/
Testing and other quality control techniques are used to the extent deemed necessary to assure product performance over
the specified temperature range. Product may not necessarily be tested across the full temperature range and all parameters
may not necessarily be tested. In the absence of specific parametric testing, product performance is assured by characterization
and/or design.
2/
Unless otherwise specified, minimum/maximum specification apply over the entire recommended operation range:
4.5 V  VDD1  5.5 V, 4.5 V  VDD2  5.5 V, and -55C  TA  +125C.
Unless otherwise specified, switching specifications are tested with CL = 15 pF and CMOS signal levels.
3/
|CM| is the maximum common mode voltage slew rate that can be sustained while maintaining VO  0.8 VDD.
The common mode voltage slew rates apply to both rising and falling common mode voltage edges.
4/
Unless otherwise specified, minimum/maximum specification apply over the entire recommended operation range:
3.0 V  VDD1  3.6 V, 3.0 V  VDD2  3.6 V, and -55C  TA  +125C.
Unless otherwise specified, switching specifications are tested with CL = 15 pF and CMOS signal levels.
5/
Unless otherwise specified, minimum/maximum specification apply over the entire recommended operation range:
4.5 V  VDD1  5.5 V, 3.0 V  VDD2  3.6 V, and -55C  TA  +125C.
Unless otherwise specified, switching specifications are tested with CL = 15 pF and CMOS signal levels.
6/
Unless otherwise specified, minimum/maximum specification apply over the entire recommended operation range:
3.0 V  VDD1  3.6 V, 4.5 V  VDD2  5.5 V, and -55C  TA  +125C.
Unless otherwise specified, switching specifications are tested with CL = 15 pF and CMOS signal levels.
DLA LAND AND MARITIME
COLUMBUS, OHIO
SIZE
A
CODE IDENT NO.
16236
REV
DWG NO.
V62/14628
PAGE
16
Case X
FIGURE 1. Case outline.
DLA LAND AND MARITIME
COLUMBUS, OHIO
SIZE
A
CODE IDENT NO.
16236
REV
DWG NO.
V62/14628
PAGE
17
Case X – continued.
Dimensions
Inches
Symbol
Millimeters
Min
Max
Min
Max
A
0.0532
0.0688
1.35
1.75
A1
0.0040
0.0098
0.10
0.25
b
0.0122
0.0201
0.31
0.51
c
0.0067
0.0098
0.17
0.25
D
0.1890
0.1968
4.80
5.00
e
0.0500 BSC
1.27 BSC
E
0.1497
0.1574
3.80
4.00
E1
0.2284
0.2441
5.80
6.20
L
0.0157
0.0500
0.40
1.27
n
8 leads
8 leads
NOTE:
1.
2.
Controlling dimensions are millimeter, inch dimensions are given for reference only and are not appropriate
for use in design.
Falls within reference to JEDEC MS-012-AA.
FIGURE 1. Case outline - Continued.
DLA LAND AND MARITIME
COLUMBUS, OHIO
SIZE
A
CODE IDENT NO.
16236
REV
DWG NO.
V62/14628
PAGE
18
Device type
01
Case outline
X
Terminal number
Terminal
symbol
1
VDD1
Supply voltage for isolator side 1, 3.0 V to 5.5 V
2
VOA
Logic output A.
3
VIB
Logic input B.
4
GND1
Ground 1. Ground reference for isolator side 1.
5
GND2
Ground 2. Ground reference for isolator side 2.
6
VOB
Logic output B
7
VIA
Logic input A.
8
VDD2
Description
Supply voltage for isolator side 2, 3.0 V to 5.5 V
FIGURE 2. Terminal connections.
Positive logic
VIA input
See note 1
VIB input
See note 1
VDD1 state
VDD2 state
VOA output
See note 1
VOB output
See note 1
H
H
Powered
Powered
H
H
L
L
Powered
Powered
L
L
H
L
Powered
Powered
H
L
L
H
Powered
Powered
L
H
X
X
Unpowered
Powered
Indeterminate
L
X
X
Powered
Unpowered
L
Indeterminate
NOTE 1.
Notes
Outputs return to the input state
within 1 s of VDDI power
restoration.
Outputs return to the input state
within 1 s of VDDO power
restoration.
H is logic high, L is logic low, and X is don’t care.
FIGURE 3. Truth table.
DLA LAND AND MARITIME
COLUMBUS, OHIO
SIZE
A
CODE IDENT NO.
16236
REV
DWG NO.
V62/14628
PAGE
19
FIGURE 4. Thermal derating curve.
DLA LAND AND MARITIME
COLUMBUS, OHIO
SIZE
A
CODE IDENT NO.
16236
REV
DWG NO.
V62/14628
PAGE
20
4. VERIFICATION
4.1 Product assurance requirements. The manufacturer is responsible for performing all inspection and test requirements as
indicated in their internal documentation. Such procedures should include proper handling of electrostatic sensitive devices,
classification, packaging, and labeling of moisture sensitive devices, as applicable.
5. PREPARATION FOR DELIVERY
5.1 Packaging. Preservation, packaging, labeling, and marking shall be in accordance with the manufacturer’s standard commercial
practices for electrostatic discharge sensitive devices.
6. NOTES
6.1 ESDS. Devices are electrostatic discharge sensitive and are classified as ESDS class 1 minimum.
6.2 Configuration control. The data contained herein is based on the salient characteristics of the device manufacturer’s data book.
The device manufacturer reserves the right to make changes without notice. This drawing will be modified as changes are provided.
6.3 Suggested source(s) of supply. Identification of the suggested source(s) of supply herein is not to be construed as a guarantee
of present or continued availability as a source of supply for the item. DLA Land and Maritime maintains an online database of all
current sources of supply at http://www.landandmaritime.dla.mil/Programs/Smcr/.
Vendor item drawing
administrative control
number 1/
Device
manufacturer
CAGE code
Vendor part number
V62/14628-01XE
24355
ADUM3211TRZ-EP
1/ The vendor item drawing establishes an administrative control number
for identifying the item on the engineering documentation.
CAGE code
24355
DLA LAND AND MARITIME
COLUMBUS, OHIO
Source of supply
Analog Devices
Route 1 Industrial Park
P.O. Box 9106
Norwood, MA 02062
Point of contact: Raheen Business Park
Limerick, Ireland
SIZE
A
CODE IDENT NO.
16236
REV
DWG NO.
V62/14628
PAGE
21