ADuM3401 DSCC: Military Data Sheet

REVISIONS
LTR
DESCRIPTION
DATE
Prepared in accordance with ASME Y14.24
APPROVED
Vendor item drawing
REV
PAGE
REV
PAGE
18
19
REV STATUS
OF PAGES
20
21
22
23
24
25
1
2
3
REV
PAGE
PMIC N/A
PREPARED BY
RICK OFFICER
Original date of drawing
YY-MM-DD
CHECKED BY
RAJESH PITHADIA
15-10-01
A
REV
5
6
7
8
9
10
11
12
13
14
15
16
17
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
http://www.landandmaritime.dla.mil/
TITLE
MICROCIRCUIT, LINEAR, QUAD CHANNEL
DIGITAL ISOLATOR, MONOLITHIC SILICON
APPROVED BY
CHARLES F. SAFFLE
SIZE
AMSC N/A
4
CODE IDENT. NO.
DWG NO.
V62/14630
16236
PAGE
1
OF
25
5962-V102-15
1. SCOPE
1.1 Scope. This drawing documents the general requirements of a high performance quad channel, digital isolator microcircuit, with
an operating temperature range of -55C to +125C.
1.2 Vendor Item Drawing Administrative Control Number. The manufacturer’s PIN is the item of identification. The vendor item
drawing establishes an administrative control number for identifying the item on the engineering documentation:
V62/14630
-
Drawing
number
01
X
E
Device type
(See 1.2.1)
Case outline
(See 1.2.2)
Lead finish
(See 1.2.3)
1.2.1 Device type(s).
Device type
Generic
01
ADUM3401
Circuit function
Quad channel, digital isolator
1.2.2 Case outline(s). The case outline(s) are as specified herein.
Outline letter
Number of pins
X
16
JEDEC PUB 95
Package style
MS-013-AA
Small outline surface mount
1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacturer:
Finish designator
A
B
C
D
E
Z
DLA LAND AND MARITIME
COLUMBUS, OHIO
Material
Hot solder dip
Tin-lead plate
Gold plate
Palladium
Gold flash palladium
Other
SIZE
A
CODE IDENT NO.
16236
REV
DWG NO.
V62/14630
PAGE
2
1.3 Absolute maximum ratings.
1/
Supply voltages (VDD1, VDD2) ................................................................................... -0.5 V to +7.0 V 2/
Input voltages (VIA, VIB, VIC, VID, VE1, VE2) ............................................................. -0.5 V to VDDI + 0.5 V 2/ 3/
Output voltage (VOA, VOB, VOC, VOD) ...................................................................... -0.5 V to VDDO + 0.5 V 2/ 3/
Average output current per pin: 4/
Side 1 (IO1) ............................................................................................................ -18 mA to +18 mA
Side 2 (IO2) ............................................................................................................ -22 mA to +22 mA
Common mode transients (CMH, CML) ...................................................................... -100 kV/s to +100 kV/s 5/
Storage temperature range (TSTG) ............................................................................ -65C to +150C
1.4 Recommended operating conditions. 6/
Supply voltages (VDD1, VDD2) ................................................................................... 3.135 V to 5.5 V 2/
Input signal rise and fall times .................................................................................... 1.0 ms
Operating temperature range (TA) ............................................................................. -55C to +125C
1.5 Package characteristics.
12
Resistance (input to output) (RIO) .............................................................................. 10
 typical 7/
Capacitance (input to output) (CIO) with f = 1 MHz .................................................... 2.2 pF typical 7/
Input capacitance (CI) ................................................................................................ 4.0 pF typical 8/
Integrated circuit junction to case thermal resistance:
Thermocouple located at center of package underside.
Side 1 (JCI) ....................................................................................................... 33C/W typical
Side 2 (JCO) ...................................................................................................... 28C/W typical
1/
2/
3/
4/
5/
6/
7/
8/
Stresses beyond those listed under “absolute maximum rating” may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions beyond those indicated under
“recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may
affect device reliability.
All voltages are relative to their respective ground.
VDDI and VDDO refer to the supply voltages on the input and output sides of a given channel, respectively.
See figure 5 for maximum rated current values for various temperatures.
Refers to common mode transients across the insulation barrier. Common mode transients exceeding the absolute maximum
ratings can cause latch up or permanent damage.
Use of this product beyond the manufacturers design rules or stated parameters is done at the user’s risk. The manufacturer
and/or distributor maintain no responsibility or liability for product used beyond the stated limits.
Device considered a 2 terminal device; VDD1 pin to GND1 pin are shorted together, and GND2 pin to VDD2 pin are shorted
together.
Input capacitance is from any input data pin to ground.
DLA LAND AND MARITIME
COLUMBUS, OHIO
SIZE
A
CODE IDENT NO.
16236
REV
DWG NO.
V62/14630
PAGE
3
2. APPLICABLE DOCUMENTS
JEDEC Solid State Technology Association
JEDEC PUB 95
–
Registered and Standard Outlines for Semiconductor Devices
(Copies of these documents are available online at http:/www.jedec.org or from JEDEC – Solid State Technology Association,
3103 North 10th Street, Suite 240–S, Arlington, VA 22201-2107).
3. REQUIREMENTS
3.1 Marking. Parts shall be permanently and legibly marked with the manufacturer’s part number as shown in 6.3 herein and as
follows:
A.
B.
C.
Manufacturer’s name, CAGE code, or logo
Pin 1 identifier
ESDS identification (optional)
3.2 Unit container. The unit container shall be marked with the manufacturer’s part number and with items A and C (if applicable)
above.
3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are
as specified in 1.3, 1.4, and table I herein.
3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein.
3.5 Diagrams.
3.5.1 Case outline. The case outline shall be as shown in 1.2.2 and figure 1.
3.5.2 Terminal connections. The terminal connections shall be as shown in figure 2.
3.5.3 Truth table. The truth table shall be as shown in figure 3.
3.5.4 Logic diagram. The logic diagram shall be as shown in figure 4.
3.5.5 Thermal derating curve. The thermal derating curve shall be as shown in figure 5.
3.5.6 Data rate graphs. The data rate graphs shall be as shown in figures 6 through 10.
DLA LAND AND MARITIME
COLUMBUS, OHIO
SIZE
A
CODE IDENT NO.
16236
REV
DWG NO.
V62/14630
PAGE
4
TABLE I. Electrical performance characteristics. 1/
Test
Symbol
Conditions
Temperature,
TA
5 V operation 2/
Device
type
Limits
Min
Unit
Max
DC specifications
Input supply current
per channel,
quiescent
IDDI (Q)
Output supply current
per channel,
quiescent
IDDO (Q)
Total supply current
VDD1 supply current
-55C to +125C
01
01
DC to 2 Mbps
IDD1(Q)
DC to 1 MHz logical signal
frequency
-55C to +125C
01
IDD2(Q)
DC to 1 MHz logical signal
frequency
-55C to +125C
VDD1 supply current
3/
10 Mbps
IDD1(10)
5 MHz logical signal frequency
-55C to +125C
IDD2(10)
5 MHz logical signal frequency
-55C to +125C
mA
2.4
mA
1.6 typical
01
10.6
mA
7.4 typical
+25C
VDD2 supply current
3.2
01
+25C
Total supply current
mA
2.5 typical
+25C
VDD2 supply current
0.35
0.29 typical
+25C
3/
mA
0.57 typical
+25C
-55C to +125C
0.83
01
6.5
mA
4.4 typical
+25C
DC specifications
Input leakage per
channel
II
0 V  VIX  VDDX
-55C to +125C
01
IPU
-55C to +125C
VEX = 0 V
01
-55C to +125C
IOZ
A
-10
-3 typical
+25C
Tristate leakage current
per channel
A
+10
+0.01 typical
+25C
VEX input pull up
current
-10
01
-10
A
+10
+0.01 typical
+25C
Logic high input
threshold
VIH, VEH
-55C to +125C
01
Logic low input
threshold
VIL, VEL
-55C to +125C
01
2.0
V
0.8
V
See footnotes at end of table.
DLA LAND AND MARITIME
COLUMBUS, OHIO
SIZE
A
CODE IDENT NO.
16236
REV
DWG NO.
V62/14630
PAGE
5
TABLE I. Electrical performance characteristics – Continued. 1/
Test
Symbol
Conditions
Temperature,
TA
5 V operation 2/
Device
type
Limits
Min
Unit
Max
DC specifications – continued.
Logic high output
voltages
VOAH,
IOX = -20 A, VIX = VIXH
4/ 5/
-55C to +125C
01
VOBH
VOCH,
IOX = -4 mA, VIX = VIXH
4/ 5/
+25C
5.0 typical
-55C to +125C
(VDD1 or VDD2)
– 0.4
+25C
4.8 typical
VODH
Logic low output
voltage
VOAL,
IOX = 20 A, VIX = VIXL
4/ 6/
VOBL
VOCL,
-55C to +125C
01
4/ 6/
VODL
0.04 typical
0.4
-55C to +125C
4/ 6/
V
0.1
-55C to +125C
+25C
IOX = 4 mA, VIX = VIXL
0.1
0.0 typical
+25C
IOX = 400 A, VIX = VIXL
V
(VDD1 or VDD2)
– 0.1
0.2 typical
+25C
Switching specifications.
Minimum pulse width
PW
Maximum data rate
Propagation delay
tPHL,
CL = 15 pF, CMOS signal levels
-55C to +125C
01
CL = 15 pF, CMOS signal levels
-55C to +125C
01
10
CL = 15 pF, CMOS signal levels
-55C to +125C
01
20
tPLH
Pulse width distortion
|tPLH – tPHL|
PWD
Pulse width distortion
|tPLH – tPHL|
change versus
temperature
Propagation delay
skew
tPSK
100
ns
Mbps
50
ns
32 typical
+25C
CL = 15 pF, CMOS signal levels
-55C to +125C
01
CL = 15 pF, CMOS signal levels
+25C
01
CL = 15 pF, CMOS signal levels
-55C to +125C
01
3
5 typical
ns
ps/C
15
ns
See footnotes at end of table.
DLA LAND AND MARITIME
COLUMBUS, OHIO
SIZE
A
CODE IDENT NO.
16236
REV
DWG NO.
V62/14630
PAGE
6
TABLE I. Electrical performance characteristics – Continued. 1/
Test
Symbol
Conditions
Temperature,
TA
5 V operation 2/
Device
type
Limits
Min
Unit
Max
Switching specifications – continued.
Channel to channel
matching,
codirectional channels
tPSKCD
CL = 15 pF, CMOS signal levels
-55C to +125C
01
3
ns
Channel to channel
matching,
opposing directional
channels
tPSKOD
CL = 15 pF, CMOS signal levels
-55C to +125C
01
6
ns
Output propagation
delay, disable
(high/low to high
impedance)
tPHZ,
CL = 15 pF, CMOS signal levels
-55C to +125C
01
8
ns
Output propagation
delay, enable
(high impedance to
high/low)
tPZH,
8
ns
Output rise/fall time
(10% to 90%)
t R / tF
CL = 15 pF, CMOS signal levels
2.5 typical
ns
Common mode 7/
transient immunity
logic high output
|CMH|
VIX = VDD1/VDD2, VCM = 1000 V,
transient magnitude = 800 V
Common mode 7/
transient immunity
logic low output
|CML|
Refresh rate
fr
Dynamic supply current
per channel, input
IDDI(D)
Dynamic supply current
per channel, output
IDDO(D)
tPLZ
6 typical
+25C
-55C to +125C
CL = 15 pF, CMOS signal levels
tPZL
01
6 typical
+25C
+25C
01
-55C to +125C
01
-55C to +125C
kV/s
35 typical
+25C
VIX = 0 V, VCM = 1000 V,
transient magnitude = 800 V
25
01
25
kV/s
35 typical
+25C
+25C
01
1.2 typical
Mbps
8/
+25C
01
0.20 typical
mA/
Mbps
8/
+25C
01
0.05 typical
mA/
Mbps
See footnotes at end of table.
DLA LAND AND MARITIME
COLUMBUS, OHIO
SIZE
A
CODE IDENT NO.
16236
REV
DWG NO.
V62/14630
PAGE
7
TABLE I. Electrical performance characteristics – Continued. 1/
Test
Symbol
Conditions
Temperature,
TA
3.3 V operation 9/
Device
type
Limits
Min
Unit
Max
DC specifications
Input supply current
per channel,
quiescent
IDDI (Q)
Output supply current
per channel,
quiescent
IDDO (Q)
Total supply current
VDD1 supply current
-55C to +125C
01
01
DC to 2 Mbps
IDD1(Q)
DC to 1 MHz logical signal
frequency
-55C to +125C
01
IDD2(Q)
DC to 1 MHz logical signal
frequency
-55C to +125C
VDD1 supply current
3/
10 Mbps
IDD1(10)
5 MHz logical signal frequency
-55C to +125C
IDD2(10)
5 MHz logical signal frequency
-55C to +125C
mA
1.5
mA
0.9 typical
01
5.6
mA
4.1 typical
+25C
VDD2 supply current
1.9
01
+25C
Total supply current
mA
1.4 typical
+25C
VDD2 supply current
0.27
0.19 typical
+25C
3/
mA
0.31 typical
+25C
-55C to +125C
0.49
01
3.3
mA
2.5 typical
+25C
DC specifications
Input leakage per
channel
II
0 V  VIX  VDDX
-55C to +125C
01
IPU
-55C to +125C
VEX = 0 V
01
-55C to +125C
IOZ
A
-10
-3 typical
+25C
Tristate leakage current
per channel
A
+10
+0.01 typical
+25C
VEX input pull up
current
-10
01
-10
A
+10
+0.01 typical
+25C
Logic high input
threshold
VIH, VEH
-55C to +125C
01
Logic low input
threshold
VIL, VEL
-55C to +125C
01
1.6
V
0.4
V
See footnotes at end of table.
DLA LAND AND MARITIME
COLUMBUS, OHIO
SIZE
A
CODE IDENT NO.
16236
REV
DWG NO.
V62/14630
PAGE
8
TABLE I. Electrical performance characteristics – Continued. 1/
Test
Symbol
Conditions
Temperature,
TA
3.3 V operation 9/
Device
type
Limits
Min
Unit
Max
DC specifications – continued.
Logic high output
voltages
VOAH,
IOX = -20 A, VIX = VIXH
4/ 5/
-55C to +125C
01
VOBH
3.3
+25C
VOCH,
IOX = -4 mA, VIX = VIXH
4/ 5/
Logic low output
voltage
VOAL,
IOX = 20 A, VIX = VIXL
4/ 6/
VOBL
VOCL,
(VDD1 or VDD2)
– 0.4
+25C
2.8 typical
-55C to +125C
01
4/ 6/
VODL
0.04 typical
0.4
-55C to +125C
4/ 6/
V
0.1
-55C to +125C
+25C
IOX = 4 mA, VIX = VIXL
0.1
0.0 typical
+25C
IOX = 400 A, VIX = VIXL
typical
-55C to +125C
VODH
V
(VDD1 or VDD2)
– 0.1
0.2 typical
+25C
Switching specifications
Minimum pulse width
PW
Maximum data rate
Propagation delay
tPHL,
CL = 15 pF, CMOS signal levels
-55C to +125C
01
CL = 15 pF, CMOS signal levels
-55C to +125C
01
10
CL = 15 pF, CMOS signal levels
-55C to +125C
01
20
tPLH
Pulse width distortion
|tPLH – tPHL|
PWD
Pulse width distortion
|tPLH – tPHL|
change versus
temperature
Propagation delay
skew
tPSK
100
ns
Mbps
50
ns
38 typical
+25C
CL = 15 pF, CMOS signal levels
-55C to +125C
01
CL = 15 pF, CMOS signal levels
+25C
01
CL = 15 pF, CMOS signal levels
-55C to +125C
01
3
5 typical
ns
ps/C
22
ns
See footnotes at end of table.
DLA LAND AND MARITIME
COLUMBUS, OHIO
SIZE
A
CODE IDENT NO.
16236
REV
DWG NO.
V62/14630
PAGE
9
TABLE I. Electrical performance characteristics – Continued. 1/
Test
Symbol
Conditions
Temperature,
TA
3.3 V operation 9/
Device
type
Limits
Min
Unit
Max
Switching specifications – continued.
Channel to channel
matching,
codirectional channels
tPSKCD
CL = 15 pF, CMOS signal levels
-55C to +125C
01
3
ns
Channel to channel
matching,
opposing directional
channels
tPSKOD
CL = 15 pF, CMOS signal levels
-55C to +125C
01
6
ns
Output propagation
delay, disable
(high/low to high
impedance)
tPHZ,
CL = 15 pF, CMOS signal levels
-55C to +125C
01
8
ns
Output propagation
delay, enable
(high impedance to
high/low)
tPZH,
8
ns
Output rise/fall time
(10% to 90%)
t R / tF
CL = 15 pF, CMOS signal levels
Common mode 7/
transient immunity
logic high output
|CMH|
VIX = VDD1/VDD2, VCM = 1000 V,
transient magnitude = 800 V
Common mode 7/
transient immunity
logic low output
|CML|
Refresh rate
fr
Dynamic supply current
per channel, input
IDDI(D)
Dynamic supply current
per channel, output
IDDO(D)
tPLZ
6 typical
+25C
-55C to +125C
CL = 15 pF, CMOS signal levels
tPZL
01
6 typical
+25C
+25C
01
-55C to +125C
01
-55C to +125C
25
ns
kV/s
35 typical
+25C
VIX = 0 V, VCM = 1000 V,
transient magnitude = 800 V
3 typical
01
25
kV/s
35 typical
+25C
+25C
01
1.1 typical
Mbps
8/
+25C
01
0.10 typical
mA/
Mbps
8/
+25C
01
0.03 typical
mA/
Mbps
See footnotes at end of table.
DLA LAND AND MARITIME
COLUMBUS, OHIO
SIZE
A
CODE IDENT NO.
16236
REV
DWG NO.
V62/14630
PAGE
10
TABLE I. Electrical performance characteristics – Continued. 1/
Test
Symbol
Conditions
5 V / 3.3 V or
3.3 V / 5 V operation 10/
Temperature,
TA
Device
type
Limits
Min
Unit
Max
DC specifications
Input supply current
per channel,
quiescent
IDDI (Q)
5 V / 3.3 V operation
-55C to +125C
01
0.49
-55C to +125C
0.31 typical
+25C
Output supply current
per channel,
quiescent
IDDO (Q)
5 V / 3.3 V operation
-55C to +125C
01
VDD1 supply current
3/
DC to 2 Mbps
IDD1(Q)
DC to 1 MHz logical signal
frequency, 5 V / 3.3 V operation
-55C to +125C
0.19 typical
01
IDD2(Q)
DC to 1 MHz logical signal
frequency, 5 V / 3.3 V operation
-55C to +125C
1.4 typical
01
VDD1 supply current
3/
10 Mbps
IDD1(10)
5 MHz logical signal frequency,
5 V / 3.3 V operation
-55C to +125C
1.6 typical
01
+25C
5 MHz logical signal frequency,
3.3 V / 5 V operation
mA
2.4
-55C to +125C
+25C
Total supply current
1.5
0.9 typical
+25C
DC to 1 MHz logical signal
frequency, 3.3 V / 5 V operation
mA
1.9
-55C to +125C
+25C
VDD2 supply current
3.2
2.5 typical
+25C
DC to 1 MHz logical signal
frequency, 3.3 V / 5 V operation
mA
0.35
-55C to +125C
+25C
Total supply current
0.27
0.29 typical
+25C
3.3 V / 5 V operation
mA
0.57 typical
+25C
3.3 V / 5 V operation
0.83
10.6
7.4 typical
5.6
-55C to +125C
+25C
mA
4.1 typical
See footnotes at end of table.
DLA LAND AND MARITIME
COLUMBUS, OHIO
SIZE
A
CODE IDENT NO.
16236
REV
DWG NO.
V62/14630
PAGE
11
TABLE I. Electrical performance characteristics – Continued. 1/
Test
Symbol
Conditions
Temperature,
TA
5 V / 3.3 V or
3.3 V / 5 V operation 10/
Device
type
Limits
Min
Unit
Max
DC specifications – continued.
Total supply current
VDD2 supply current
3/
10 Mbps
IDD2(10)
5 MHz logical signal frequency,
5 V / 3.3 V operation
-55C to +125C
01
3.3
2.5 typical
+25C
5 MHz logical signal frequency,
3.3 V / 5 V operation
6.5
-55C to +125C
4.4 typical
+25C
Input leakage per
channel
II
0 V  VIX  VDDX
-55C to +125C
01
-10
IPU
-55C to +125C
VEX = 0 V
01
-55C to +125C
IOZ
-3 typical
01
-10
VIH,
5 V / 3.3 V operation
VEH
3.3 V / 5 V operation
Logic low input
threshold
VIL, VEL
5 V / 3.3 V operation
Logic high output
voltages
VOAH,
-55C to +125C
01
2.0
-55C to +125C
IOX = -4 mA, VIX = VIXH
V
01
0.8
V
0.4
4/ 5/
-55C to +125C
VOBH
VOCH,
A
1.6
3.3 V / 5 V operation
IOX = -20 A, VIX = VIXH
+10
+0.01 typical
+25C
Logic high input
threshold
A
A
-10
+25C
Tristate leakage current
per channel
+10
+0.01 typical
+25C
VEX input pull up
current
mA
4/ 5/
01
(VDD1 or VDD2)
– 0.1
+25C
(VDD1 or VDD2)
typical
-55C to +125C
(VDD1 or VDD2)
– 0.4
+25C
(VDD1 or VDD2)
– 0.2 typical
VODH
V
See footnotes at end of table.
DLA LAND AND MARITIME
COLUMBUS, OHIO
SIZE
A
CODE IDENT NO.
16236
REV
DWG NO.
V62/14630
PAGE
12
TABLE I. Electrical performance characteristics – Continued. 1/
Test
Symbol
Conditions
Temperature,
TA
5 V / 3.3 V or
3.3 V / 5 V operation 10/
Device
type
Limits
Min
Unit
Max
DC specifications – continued.
Logic low output
voltage
VOAL,
IOX = 20 A, VIX = VIXL
4/ 6/
VOBL
VOCL,
-55C to +125C
01
4/ 6/
VODL
0.1
-55C to +125C
0.04 typical
+25C
IOX = 4 mA, VIX = VIXL
0.4
-55C to +125C
4/ 6/
V
0.0 typical
+25C
IOX = 400 A, VIX = VIXL
0.1
0.2 typical
+25C
Switching specifications
Minimum pulse width
PW
Maximum data rate
Propagation delay
tPHL,
CL = 15 pF, CMOS signal levels
-55C to +125C
01
CL = 15 pF, CMOS signal levels
-55C to +125C
01
10
CL = 15 pF, CMOS signal levels
-55C to +125C
01
15
tPLH
Pulse width distortion
|tPLH – tPHL|
PWD
Pulse width distortion
|tPLH – tPHL|
change versus
temperature
Propagation delay
skew
tPSK
100
ns
Mbps
50
ns
35 typical
+25C
CL = 15 pF, CMOS signal levels
-55C to +125C
01
CL = 15 pF, CMOS signal levels
+25C
01
CL = 15 pF, CMOS signal levels
-55C to +125C
01
3
5 typical
22
ns
ps/C
ns
See footnotes at end of table.
DLA LAND AND MARITIME
COLUMBUS, OHIO
SIZE
A
CODE IDENT NO.
16236
REV
DWG NO.
V62/14630
PAGE
13
TABLE I. Electrical performance characteristics – Continued. 1/
Test
Symbol
Conditions
Temperature,
TA
5 V / 3.3 V or
3.3 V / 5 V operation 10/
Device
type
Limits
Min
Unit
Max
Switching specifications – continued.
Channel to channel
matching,
codirectional channels
tPSKCD
CL = 15 pF, CMOS signal levels
-55C to +125C
01
3
ns
Channel to channel
matching,
opposing directional
channels
tPSKOD
CL = 15 pF, CMOS signal levels
-55C to +125C
01
6
ns
Output propagation
delay, disable
(high/low to high
impedance)
tPHZ,
CL = 15 pF, CMOS signal levels
-55C to +125C
01
8
ns
Output propagation
delay, enable
(high impedance to
high/low)
tPZH,
8
ns
Output rise/fall time
(10% to 90%)
t R / tF
tPLZ
6 typical
+25C
-55C to +125C
CL = 15 pF, CMOS signal levels
tPZL
01
6 typical
+25C
+25C
CL = 15 pF, CMOS signal levels,
5 V / 3.3 V operation
01
|CMH|
Common mode 7/
transient immunity
logic low output
|CML|
Refresh rate
fr
ns
2.5 typical
CL = 15 pF, CMOS signal levels,
3.3 V / 5 V operation
Common mode 7/
transient immunity
logic high output
3 typical
VIX = VDD1/VDD2, VCM = 1000 V,
transient magnitude = 800 V
-55C to +125C
01
-55C to +125C
01
+25C
25
kV/s
35 typical
+25C
5 V / 3.3 V operation
kV/s
35 typical
+25C
VIX = 0 V, VCM = 1000 V,
transient magnitude = 800 V
25
01
3.3 V / 5 V operation
1.2 typical
Mbps
1.1 typical
See footnotes at end of table.
DLA LAND AND MARITIME
COLUMBUS, OHIO
SIZE
A
CODE IDENT NO.
16236
REV
DWG NO.
V62/14630
PAGE
14
TABLE I. Electrical performance characteristics – Continued. 1/
Test
Symbol
Conditions
Temperature,
TA
5 V / 3.3 V or
3.3 V / 5 V operation 10/
Dynamic supply current
per channel, input
IDDI(D)
Device
type
Min
5 V / 3.3 V operation 8/
+25C
01
3.3 V / 5 V operation 8/
Dynamic supply current
per channel, output
IDDO(D)
Limits
Unit
Max
0.20 typical
mA/
Mbps
0.10 typical
5 V / 3.3 V operation 8/
+25C
01
3.3 V / 5 V operation 8/
0.03 typical
mA/
Mbps
0.05 typical
1/
Testing and other quality control techniques are used to the extent deemed necessary to assure product performance over
the specified temperature range. Product may not necessarily be tested across the full temperature range and all parameters
may not necessarily be tested. In the absence of specific parametric testing, product performance is assured by characterization
and/or design.
2/
All voltages are relative to their respective ground. 4.5 V  VDD1  5.5 V and 4.5 V  VDD2  5.5 V.
Unless otherwise specified, all minimum / maximum specifications apply over the entire recommended operation range.
All typical specifications are at TA = 25C, VDD1 = VDD2 = 5 V.
3/
The supply current values for all four channels are combined when running at identical data rates. Output supply current values
are specified with no output load present. See figures 6 through 8 for information on per channel supply current as a function
of data rate for unloaded and loaded conditions. See figures 9 and 10 for total VDD1 and VDD2 supply currents as a function
of data rate for device channel configurations.
4/
IOX is the channel X output current, where X = A, B, C, or D.
5/
VIXH is the input side logic high.
6/
VIXL is the input side logic low.
7/
CMH is the maximum common mode voltage slew rate that can be sustained while maintaining the (VOUT)  0.8 VDD2.
CML is the maximum common mode voltage slew rate that can be sustained while maintain VOUT  0.8 V.
The common mode voltage slew rates apply to both rising and falling common mode voltage edges.
The transient magnitude is the range over which the common mode is slewed.
8/
Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate.
See figures 6 through 8 for information on per channel supply current for unloaded and loaded conditions.
9/
All voltages are relative to their respective ground. 3.135 V  VDD1  3.6 V and 3.135 V  VDD2  3.6 V.
Unless otherwise specified, all minimum / maximum specifications apply over the entire recommended operation range.
All typical specifications are at TA = 25C, VDD1 = VDD2 = 3.3 V.
10/ All voltages are relative to their respective ground. For 5 V / 3.3 V operation, 4.5 V  VDD1  5.5 V and 3.135 V  VDD2  3.6 V,
and for 3.3 V / 5 V operation, 3.135 V  VDD1  3.6 V and 4.5 V  VDD2  5.5 V.
Unless otherwise specified, all minimum / maximum specifications apply over the entire recommended operation range.
All typical specifications are at TA = 25C, VDD1 = 3.3 V, VDD2 = 5 V or VDD1 = 5 V, VDD2 = 3.3 V.
DLA LAND AND MARITIME
COLUMBUS, OHIO
SIZE
A
CODE IDENT NO.
16236
REV
DWG NO.
V62/14630
PAGE
15
Case X
FIGURE 1. Case outline.
DLA LAND AND MARITIME
COLUMBUS, OHIO
SIZE
A
CODE IDENT NO.
16236
REV
DWG NO.
V62/14630
PAGE
16
Case X – continued.
Dimensions
Inches
Symbol
Millimeters
Min
Max
Min
Max
A
0.0925
0.1043
2.35
2.65
A1
0.0039
0.0118
0.10
0.30
b
0.0122
0.0201
0.31
0.51
c
0.0079
0.0130
0.20
0.33
D
0.3976
0.4134
10.10
10.50
E
0.2913
0.2992
7.40
7.60
E1
0.3937
0.4193
10.00
10.65
e
L
0.0500 BSC
0.0157
n
1.27 BSC
0.0500
0.40
16
1.27
16
NOTES:
1. Controlling dimensions are millimeter, inch dimensions are given for reference only.
2. Falls within JEDEC MS-013 variation AA.
FIGURE 1. Case outline.
DLA LAND AND MARITIME
COLUMBUS, OHIO
SIZE
A
CODE IDENT NO.
16236
REV
DWG NO.
V62/14630
PAGE
17
Device type
01
Case outline
X
Terminal number
Terminal
symbol
1
VDD1
Supply voltage for isolator side 1, 3.135 V to 5.5 V.
2
GND1
Ground 1. Ground reference for isolator side 1.
See note 1
3
VIA
Logic input A.
4
VIB
Logic input B.
5
VIC
Logic input C.
6
VOD
Logic output D.
7
VE1
Output enable 1. Active high logic input.
VOD output is enabled when VE1 is high or disconnected.
Description
VOD output is disabled when VE1 is low.
In noisy environments, connecting VE1 to an external logic
high or low is recommended.
8
GND1
Ground 1. Ground reference for isolator side 1.
See note 1.
9
GND2
Ground 2. Ground reference for isolator side 2.
10
VE2
Output enable 2. Active high logic input.
VOA, VOB, and VOC outputs are enabled when VE2 is high
or disconnected.
VOA, VOB, and VOC outputs are disabled when VE2 is low.
In noisy environments, connecting VE2 to an external logic
high or low is recommended.
11
VID
Logic input D.
12
VOC
Logic output C.
13
VOB
Logic output B.
14
VOA
Logic output A.
15
GND2
Ground 2. Ground reference for isolator side 2.
16
VDD2
Supply voltage for isolator side 2, 3.135 V to 5.5 V.
NOTE:
1. Both GND1 pins are internally connected and connecting both to GND1 is recommended.
Both GND2 pins are internally connected and connecting both to GND2 is recommended.
In noisy environments, connecting output enables (VE1 and VE2) to an external logic high or low is recommended.
FIGURE 2. Terminal connections.
DLA LAND AND MARITIME
COLUMBUS, OHIO
SIZE
A
CODE IDENT NO.
16236
REV
DWG NO.
V62/14630
PAGE
18
Positive logic
VIX input
VEX input
VDDI state
VDDO state
VOX output
H
H or NC
Powered
Powered
H
L
H or NC
Powered
Powered
L
X
L
Powered
Powered
Z
X
H or NC
Unpowered
Powered
H
X
L
Unpowered
Powered
Z
X
X
Powered
Unpowered
Indeterminate
Notes
Outputs return to the input state
within 1 s of VDDI power
restoration.
Outputs return to the input state
within 1 s of VDDO power
restoration if VEX state is H or
NC. Outputs return to high
impedance state within 8 ns of
VDDO power restoration if VEX
state is L.
1/
VIX and VOX refer to the input and output signals of a given channel (A, B, C, or D). VEX refers to the output
enable signal on the same side as the VOX outputs. VDDI and VDDO refer to the supply voltages on the input
and output sides of the given channel, respectively.
2/
H is high, L is low, X is don’t care, and NC is no connect.
3/
In noisy environments, connecting VEX to an external logic high or low is recommended.
FIGURE 3. Truth table.
DLA LAND AND MARITIME
COLUMBUS, OHIO
SIZE
A
CODE IDENT NO.
16236
REV
DWG NO.
V62/14630
PAGE
19
FIGURE 4. Logic diagram.
DLA LAND AND MARITIME
COLUMBUS, OHIO
SIZE
A
CODE IDENT NO.
16236
REV
DWG NO.
V62/14630
PAGE
20
FIGURE 5. Thermal derating curve.
DLA LAND AND MARITIME
COLUMBUS, OHIO
SIZE
A
CODE IDENT NO.
16236
REV
DWG NO.
V62/14630
PAGE
21
FIGURE 6. Typical input supply current per channel versus data rate (no load).
FIGURE 7. Typical output supply current per channel versus data rate (no load).
DLA LAND AND MARITIME
COLUMBUS, OHIO
SIZE
A
CODE IDENT NO.
16236
REV
DWG NO.
V62/14630
PAGE
22
FIGURE 8. Typical output supply current per channel versus data rate (15 pF output load).
FIGURE 9. Typical VDD1 supply current versus data rate for 5 V and 3.3 V operation.
DLA LAND AND MARITIME
COLUMBUS, OHIO
SIZE
A
CODE IDENT NO.
16236
REV
DWG NO.
V62/14630
PAGE
23
FIGURE 10. Typical VDD2 supply current versus data rate for 5 V and 3.3 V operation.
DLA LAND AND MARITIME
COLUMBUS, OHIO
SIZE
A
CODE IDENT NO.
16236
REV
DWG NO.
V62/14630
PAGE
24
4. VERIFICATION
4.1 Product assurance requirements. The manufacturer is responsible for performing all inspection and test requirements as
indicated in their internal documentation. Such procedures should include proper handling of electrostatic sensitive devices,
classification, packaging, and labeling of moisture sensitive devices, as applicable.
5. PREPARATION FOR DELIVERY
5.1 Packaging. Preservation, packaging, labeling, and marking shall be in accordance with the manufacturer’s standard commercial
practices for electrostatic discharge sensitive devices.
6. NOTES
6.1 ESDS. Devices are electrostatic discharge sensitive and are classified as ESDS class 1 minimum.
6.2 Configuration control. The data contained herein is based on the salient characteristics of the device manufacturer’s data book.
The device manufacturer reserves the right to make changes without notice. This drawing will be modified as changes are provided.
6.3 Suggested source(s) of supply. Identification of the suggested source(s) of supply herein is not to be construed as a guarantee
of present or continued availability as a source of supply for the item. DLA Land and Maritime maintains an online database of all
current sources of supply at http://www.landandmaritime.dla.mil/Programs/Smcr/.
Vendor item drawing
administrative control
number 1/
Device
manufacturer
CAGE code
Vendor part number
V62/14630-01XE
24355
ADUM3401TRWZ-EP
1/ The vendor item drawing establishes an administrative control number
for identifying the item on the engineering documentation.
CAGE code
24355
DLA LAND AND MARITIME
COLUMBUS, OHIO
Source of supply
Analog Devices
Route 1 Industrial Park
P.O. Box 9106
Norwood, MA 02062
Point of contact: Raheen Business Park
Limerick, Ireland
SIZE
A
CODE IDENT NO.
16236
REV
DWG NO.
V62/14630
PAGE
25
Similar pages