TLE9222PX Data Sheet (1.7 MB, EN)

TLE9222
TLE9222PX
FlexRay Transceiver
Data Sheet
Rev. 1.0, 2015-06-12
Automotive Power
TLE9222
Table of Contents
1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3
3.1
3.2
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4
4.1
4.1.1
4.1.2
4.1.3
4.2
4.3
4.4
4.5
4.5.1
4.5.2
4.5.3
4.6
4.6.1
4.6.2
4.7
4.7.1
4.7.2
4.7.2.1
4.7.2.2
4.7.3
4.7.4
4.7.5
4.7.6
4.7.7
4.8
4.8.1
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Operation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
BD_Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
BD_Standby Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
BD_Off Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Communication Controller Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Bus Guardian Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Host Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Power Supply Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
VCC Undervoltage Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
VIO Undervoltage Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Power-up and Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Remote Wake-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Bus Wake-up Patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Wake-up by Payload . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Fail Safe Functions and Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Overtemperature detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Bus Error Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
RxD-TxD Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Bus Overcurrent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Transmitter Time-Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
VIO Undervoltage-flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
SPI-error flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Error flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Mode Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
SPI Interface and Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Read-out procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5
5.1
5.2
5.3
General Product Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Thermal Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6
6.1
6.2
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Functional Device Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
7
7.1
7.2
7.3
Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ESD Robustness according to IEC61000-4-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bus Interface Simulation Model Parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Application Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Sheet
2
23
23
24
24
37
37
37
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TLE9222
7.4
7.5
7.6
Implementation of ECU Functional Safety concepts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Minimizing ECU current consumption through BD_Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Further Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
8
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
9
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Data Sheet
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Rev. 1.0, 2015-06-12
FlexRay Transceiver
1
TLE9222
Overview
Features
•
Compliant with the FlexRay Electrical Physical Layer Specification
version 3.0.1 and ISO 17458-4
•
Optimized for time triggered in-vehicle networks with data
transmission rates from 1 Mbit/s up to 10 Mbit/s
•
Supports minimum bit times down to 60 ns
•
Automatic voltage adaptation on the digital interface pins
•
Bus failure protection and error detection
•
Very high ESD robustness; ± 8 kV according to IEC61000-4-2
•
Optimized for high Electromagnetic Compatibility (EMC);
Very low emission and high immunity to interference
•
Green Product (RoHS compliant)
•
AEC Qualified
PG-TSSOP-14
Modes of Operation and Wake-up Features
•
Low power standby operation mode with very low quiescent current consumption
•
Remote wake-up detection via wake-up patterns and a dedicated wake-up frame
Protection and Diagnostic
•
Short-circuit protection on the bus pins
•
Overtemperature protection
•
Undervoltage monitoring of the VCC power supply and the VIO logic voltage level reference
•
Error and wake-up indication on the ERRN output
•
Status register for detailed diagnostic information through a simplified SPI interface
•
Integrated Bus Guardian interface with enhanced safety feedback path
•
Bus pins high impedance when device unpowered
Description
The TLE9222 FlexRay transceiver is designed for data transmission rates from 1 Mbit/s up to 10 Mbit/s
according to the FlexRay Electrical Physical Layer Specification 3.0.1. The Bus Driver (BD) realizes the physical
interface between a FlexRay node and the communication channel. It provides differential transmit and
receive capability to the bus, allowing the node bidirectional time-multiplexed binary data stream transfer. In
Type
Package
Marking
TLE9222PX
PG-TSSOP-14
9222
Data Sheet
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TLE9222
Overview
addition to transmit and receive functions, the TLE9222 provides low power standby operation, supply
voltage monitoring (undervoltage detection) as well as bus failure detection and represents an ESDprotection barrier between the bus and the ECU.
The TLE9222 supports the following FlexRay functional classes:
•
Functional class “Bus driver - bus guardian interface”
•
Functional class “Bus driver logic level adaptation”
•
Functional class “Bus driver remote wakeup”
•
Functional class “Bus driver increased voltage amplitude transmitter”
In BD_Standby mode the quiescent current is decreased to a minimal level while still being able to detect
wake-up requests on the bus.
Fail Safe features, like failure detection and the power supply monitoring, combined with an easy accessible
status register support requirements for safety related applications with extended diagnostic features.
The TLE9222 is internally protected against transients on the bus pins, BP and BM. This makes it possible to
use the TLE9222 for implementing ECUs without additional external bus protection circuitry while fulfilling
ESD and ISO pulse requirements of car manufacturers. With its excellent EMC performance the TLE9222
provides a very high immunity against RF disturbances over a broad frequency range and transmits only a
minimal level of electromagnetic emission onto the bus.
The TLE9222 is integrated in a RoHS compliant PG-TSSOP-14 package. Using the latest Infineon Smart Power
Technology it is especially tailored to withstand the harsh conditions of the automotive environment and
qualification according to the AEC-Q100 standard.
Data Sheet
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TLE9222
Block Diagram
2
Block Diagram
5
Bus Guardian
Interface
Transmitter
10
Host
Interface
Bus-FailureDetector
6
BGE
ERRN
STBN
VIO
State Machine
4
Digital Logic
BP
BM
Failure Logic
13
12
Receiver
RxD
Communication
Controller
Interface
3
2
TxD
VIO
8
SPI
Interface
Wake-Up
Detector
VCC
TxEN
7
14
Power Supply Interface
1
Voltage Monitor
VIO
9
SDO
SCSN
SCLK
11
GND
Figure 1
Data Sheet
TLE9222_BLOCKDIAGRAM_V02
Block diagram
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TLE9222
Pin Configuration
3
Pin Configuration
3.1
Pin Assignment
VIO
1
14
VCC
TxD
2
13
BP
TxEN
3
12
BM
RxD
4
11
GND
BGE
5
10
ERRN
STBN
6
9
SCSN
SCLK
7
8
SDO
TLE9222_PINNING_A_V00
Figure 2
Pin configuration
3.2
Pin Definitions and Functions
Pin
Symbol
Function
1
VIO
Digital Reference Voltage;
Digital reference voltage supply for the logic input and output pins,
100 nF decoupling capacitor to GND recommended.
2
TxD
Transmit Data Input;
Integrated pull-down to GND.
3
TxEN
Transmitter Enable Not Input;
Logical “low” to enable the transmitter output stage,
Integrated pull-up to VIO.
4
RxD
Receive Data Output;
Output voltage level adapted to the voltage level of VIO.
5
BGE
Bus Guardian Enable Input;
Logical “high” to enable the transceiver output stage,
Integrated pull-down to GND.
6
STBN
Standby Not Mode Control Input;
Digital input for mode selection, logical “high” for BD_Normal mode,
Integrated pull-down to GND.
7
SCLK
SPI Clock Input;
Integrated pull-down to GND.
Data Sheet
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TLE9222
Pin Configuration
Pin
Symbol
Function
8
SDO
SPI Data Output;
9
SCSN
SPI Chip Select Not Input;
Integrated pull-up to VIO.
10
ERRN
Error Not Diagnosis Output;
Logical “low“ in failure cases or when wake-up pattern detected.
11
GND
Ground;
12
BM
Bus Line Minus;
Negative input / output terminal of the FlexRay bus.
13
BP
Bus Line Plus;
Positive input / output terminal of the FlexRay bus.
14
VCC
Supply Voltage;
Transceiver 5V supply voltage,
100 nF decoupling capacitors to GND recommended.
Data Sheet
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TLE9222
Functional Description
4
Functional Description
The TLE9222 realizes the physical interface between the FlexRay node and the communication channel.
Differential transmit and receive capability to the FlexRay bus is provided, allowing the node bidirectional
time multiplexed binary data stream transfer.
The differential bus voltage is measured between two signal lines, denoted BP (Bus Plus) and BM (Bus Minus),
defined as uBUS = uBP - uBM. Three different bus states are defined for the FlexRay bus; Idle, Data_0 and
Data_1. For the Idle state no differential voltage is driven to BP or to BM. The common mode bus biasing level
will depend on the operation mode of all nodes on the bus. For the Data_1 state a positive differential voltage
is driven between BP and BM, whereas for the Data_0 state a negative differential voltage is driven between
BP and BM.
4.1
Operation Modes
The TLE9222 supports two functional operation modes, BD_Normal mode and BD_Standby mode. In
addition, the BD_Off condition describes the behavior of the TLE9222 when unsupplied.
Mode transitions of the TLE9222 are triggered by host commands, undervoltage events and during power-up
/ -down, see Figure 3 and Table 1.
2
5
4
BD_OFF
BD_Standby
BD_Normal
1
4
6
3
6
TLE9222_OPERATION_MODES_V01
Figure 3
Operation mode state diagram
Table 1
Operation mode transitions
Nr
Reason for transition
Comment
1
Wake-up detection
–
2
Power-on detection
Supply voltage sufficiently supplied via VCC after being unpowered.
3
Undervoltage detection
After VCC and / or VIO undervoltage detection, BD_Standby mode is forced.
4
Host command
Triggered by host command.
5
Undervoltage recovery
Undervoltage recovery while host command requests BD_Normal mode.
6
Power-off
Supply voltage falls below the power-on threshold.
Data Sheet
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TLE9222
Functional Description
4.1.1
BD_Normal Mode
In BD_Normal mode all interfaces and functions of the TLE9222 are in operating condition. The
communication controller interface is fully active; the RxD output reflects the data on the bus pins, the TxD
drives the data to the transmitter and the TxEN input enables or disables the transmitter. When the
transmitter is activated, fail safe functionality like the transmitter time-out, overtemperature detection and
bus error detection are also enabled. The bus biasing is connected to VCC / 2 via the internal common mode
resistors. With the RxEN flag in the status register the bus states idle or active can be read out through the SPI
interface.
The host interface is active and fully functional, as well as status register read-out on the SPI interface.
Through the bus guardian interface, the transmitter can be activated or disabled.
The wake-up detector is active, but received wake-up information is not flagged while in BD_Normal mode.
The power supply interface including voltage monitor on both VCC and VIO is active. Undervoltage events are
signalled on the ERRN output and in the status register, and trigger a mode transition to BD_Standby mode.
BD_Normal mode can only be entered with a valid host command while both power supplies are within their
operational range.
4.1.2
BD_Standby Mode
After power-up the TLE9222 automatically enters BD_Standby, an idle mode with optimized low power
consumption. In BD_Standby mode neither sending nor receiving data is possible, both the transmitter and
the receiver are disabled. The bus biasing is connected to GND through the internal common mode resistors.
The communication controller interface is inactive. The TxD and the TxEN inputs are not functional. The RxD
output is used for signalling wake-up or error information, depending on the host command. The host
interface is active and fully functional, as well as status register read-out on the SPI interface.
The bus guardian interface is inactive and detection of bus transmission through the RxEN flag in the status
register is not possible. The bus failure detector is not active, no bus failure can be detected.
The wake-up detector is active and signals wake-up requests on the ERRN and RxD outputs while the host
command is BD_Standby mode.
The power supply interface with voltage monitoring on both VCC and VIO is active. If the TLE9222 is forced to
BD_Standby mode because of undervoltage events while the host command is BD_Normal mode, this is
signalled on the ERRN output. Additionally, the information is stored in the status register.
4.1.3
BD_Off Condition
The TLE9222 enters the BD_Off condition when the VCC power supply drops below the uBDPDVCC power-onreset threshold. In this state the transmitter and the receiver are turned off, the wake-up function is not
operational, the RxD and ERRN outputs are “low” and the SDO output is in high impedance state. If the VIO
reference supply is available, the logical inputs are set to their default states as given in Table 2.
Table 2
Logic inputs when unconnected / default states
Input Signal
Default State
TxD
Low
TxEN
High
STBN
Low
BGE
Low
Data Sheet
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TLE9222
Functional Description
Table 2
Logic inputs when unconnected / default states
Input Signal
Default State
SCSN
High
SCLK
Low
4.2
Communication Controller Interface
The communication controller interface is the link between the TLE9222 and the FlexRay communication
controller, comprising three digital signals:
•
TxEN (Transmit Data Enable Not) input
•
TxD (Transmit Data) input
•
RxD (Receive Data) output
BGE
The logical I/O levels of all three digital pins are adapted to the VIO digital reference voltage supply.
High
Low
TxEN
t
High
Low
TxD
t
High
Low
t
uBM
uBPData1 = uBMData0
Bus Voltages
uBiasNon-Low_Power
uBP
uBMData1 = uBPData0
uBDTxActive
uBus = uBP - uBM
uBDTxIdle
uBDTxActive_D0
RxD
Idle
Data 0
Data 1
Data 0
Data 1
Idle
t
High
Low
t
TLE9222_BUS_TRANSMISSION_V01
Figure 4
FlexRay physical layer bus signals
The communication controller interface drives the serial digital data stream available on the TxD input to the
FlexRay bus via the transmitter. Simultaneously the receiver of the TLE9222 monitors the data on the FlexRay
bus and transfers the data to a serial digital data stream back to the RxD output. A logical “low” signal on the
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TLE9222
Functional Description
TxD input drives a Data_0 signal on the FlexRay bus; a Data_0 signal on the FlexRay bus results in a logical
“low” signal on the RxD output. Vice versa a logical “high” on TxD drives a Data_1 signal on the FlexRay bus
and results in a logical “high” signal on the RxD output. The RxD output is also used to signal wake-up events
while the transceiver is in BD_Standby mode.
The TxEN input is only functional in BD_Normal mode and requires a transition from “high” to “low” for
initiating bus transmissions. After TxEN has been set “low” while the BGE input is “high”, a “low” level on the
TxD input enables the transmitter.
For avoiding unintentional blocking of the FlexRay bus in case of failures, the transmitter is protected with a
time-out function. In case a time-out occurs, the transmitter will automatically be disabled and the error will
be signalled by the ERRN output and in the status register. A more detailed description of this fail safe function
is given in Chapter 4.7.3.
4.3
Bus Guardian Interface
The bus guardian interface allows an external supervision device to immediate interrupt any bus transmission
of the TLE9222. A logical “low” signal on the BGE input disables the transmitter of the TLE9222 while operating
in BD_Normal mode, regardless of the signals on the TxD and TxEN inputs.
For increasing the ECU system safety level, an enhanced redundant feedback path has been implemented for
the bus guardian interface. A monitoring circuit directly at the transmitter output stages provides reliable
feedback by setting the ERRN output “low” and indication with the BGE flag in the status register after the
transmitter has been disabled through the Bus Guardian interface.
The logical I/O level of the BGE input is adapted to the digital reference voltage level uVIO. Together with the
TxEN input, the BGE input is monitored for the transmitter time-out function (see Chapter 4.7.3).
Additionally, the status register includes the RxEN (Receive Enable NOT) flag that indicates activity (Data_0 or
Data_1) on the FlexRay bus. This detection is only active in BD_Normal Mode. The RxEN bit can be read out
with the SPI Interface as described in Chapter 4.8.
4.4
Host Interface
The host interface enables the host to control the operation mode of the TLE9222 and to flag status
information. The host interface is implemented using hard wired signals, Option A according to the FlexRay
EPL Spec. 3.0.1.
Table 3
Host Command
STBN
Resulting operation mode
High
BD_Normal
Low
BD_Standby
The STBN (Standby Not) input controls the operation mode of the TLE9222. Unless the TLE9222 is being forced
to BD_Standby mode because of undervoltage events, the host command will set operation mode as given in
Table 3. Mode change by host command is completed within the time dBDModeChange after the host command
is applied. Voltage spikes on the STBN input that are shorter than dBDLogicFilter are filtered out and ignored.
Data Sheet
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Rev. 1.0 2015-06-12
TLE9222
Functional Description
t < dBDLogicFilter
t < dBDLogicFilter
High
dBDLogicFilter
STBN
dBDLogicFilter
uVDig_In_High_STBN
70% VIO
uVDig_In_Low_STBN
30% VIO
Low
dBDModeChange
t
dBDModeChange
BD_Normal mode
BD_Normal mode
BD_Standby mode
Mode transition
Figure 5
TLE9222_MODE_CONTROL_V00
Mode control with the STBN input
The ERRN output is used to signal events detected by the TLE9222 to the host controller. Depending on the
provided host command, the ERRN output indicates errors or wake-up events, see Table 4. The TLE9222
reacts on and signals these events on the ERRN output within the time dReactionTimeERRN. Detailed
information about the detected events as given in Table 4 can be read out from the status register with the SPI
interface as described in Chapter 4.8.
Table 4
STBN
Signalling on the ERRN and RxD pins
ERRN
RxD
Cause / Comment
Effect
BD_Normal mode
High
High
High /
Low1)
Default condition for BD_Normal mode –
High
Low
High /
Low1)
Bus error detected
–
Transmitter time-out detected
Transmitter disabled
Overtemperature event detected
Transmitter disabled
BGE input “low”
Transmitter disabled
SPI error detected
–
BD_Standby mode
Low
High
High
Default condition for BD_Standby mode –
Low
Low
Low
Bus wake-up detected
–
High
Low
High
VCC undervoltage detected
Forced BD_Standby mode
X2)
Low
Low
VIO undervoltage detected
Forced BD_Standby mode, logic inputs
follow default states (see Table 2)
SDO “high impedance”
uVCC below uBDPDVCC
–
BD_OFF condition
X2)
Low
Low
1) Depending on bus state; RxD “low” when Data_0 is detected, RxD “high” when Data_1 is detected or when bus is Idle
2) X = “Don’t care”
Data Sheet
13
Rev. 1.0 2015-06-12
TLE9222
Functional Description
A “low” output level on the ERRN pin is latched. To reset the ERRN event and the status register either a correct
read-out of the status register or a mode change by the host command is required, given that the error
condition has been resolved.
4.5
Power Supply Interface
The TLE9222 is powered by the VCC pin which shall be connected to a voltage supply with nominal 5 V.
Additionally, the TLE9222 provides the VIO reference voltage pin for all digital inputs and outputs. The voltages
at the VCC and VIO pins are monitored for detection of undervoltage events.
4.5.1
VCC Undervoltage Detection
STBN
The TLE9222 detects undervoltage events on the VCC pin if the voltage uVCC falls below the undervoltage
detection threshold uBDUVVCC for a time t > dBDUVVCC_blk. Upon detection the VCC-undervoltage flag and the
error flag are set. In case the TLE9222 is in BD_Normal mode, the transmitter will be disabled and the ERRN
output will go “low” after the time dReactionTimeERRN. After the time dBDUVVCC the TLE9222 will force a
transition to BD_Standby, regardless of the host command (see Figure 6).
High
Low
t
uVCC
dBDUVVCC
uBDUVVCC
t
t < dBDUVVCC_blk
dBDRVCC
dBDUVVCC_blk
Set VCC-undervoltage flag
Set Error flag
Transmitter blocked
Block host command
Forced mode change
ERRN pin „low“
Host command released
BD_Normal mode
BD_Standby mode
According to Host command
TLE9222_VCC_UNDERVOLTAGE_V00
Figure 6
VCC undervoltage detection
The TLE9222 recovers from a VCC undervoltage event after the time t > dBDRVCC following the voltage uVCC rise
above the undervoltage detection threshold uBDUVVCC. This will release the host command and change
operation mode accordingly.
4.5.2
VIO Undervoltage Detection
The VIO undervoltage detection is similar to that on the VCC supply. Undervoltage events on the VIO pin are
detected if the voltage uVIO falls below the undervoltage detection threshold uUVIO for a time t > dBDUVVIO_blk.
Upon detection the VIO-undervoltage flag and the error flag are set. While an undervoltage event is present on
the VIO pin, the reference threshold levels of all digital input and output pins are invalid. Therefore, the
Data Sheet
14
Rev. 1.0 2015-06-12
TLE9222
Functional Description
STBN
TLE9222 blocks the host interface, communication controller interface, SPI interface and the bus guardian
interface. The digital outputs RxD and ERRN are set “low” and all digital input pins follow their default levels
(see Table 2). The SDO output is set to high impedance state. After the time dBDUVVIO the TLE9222 will force a
transition to BD_Standby mode.
High
Low
t
uVIO
dBDUVVIO
uUVIO
t
t < dBDUVVIO_blk
dBDUVVIO_blk
Set VIO-undervoltage flag
Set Error flag
dBDRVIO
Block host command
Forced mode change
Digital inputs set to default
ERRN set „low“, RxD set „low“
SDO set „high impedance“
Release host command
and digital interfaces
BD_Normal mode
BD_Standby mode
According to Host Command
TLE9222_VIO_UNDERVOLTAGE_V00
Figure 7
VIO undervoltage detection
The TLE9222 will recover from a VIO undervoltage event after the time t > dBDRVIO following the voltage uVIO
rise above the undervoltage detection threshold uUVIO. This will release the SPI interface and host command,
and change mode accordingly (see Figure 7).
4.5.3
Power-up and Power-down
The TLE9222 will remain in BD_Off condition as long as the voltage on the VCC supply pin, uVCC, is below the
power-down threshold uBDPDVCC. When uVCC is ramped up higher than uBDPDVCC the TLE9222 powers up and
begins initialization of the BD_Standby mode within the time dBDPower. After both voltages uVCC and uVIO have
risen above their respective undervoltage detection thresholds (uBDUVVCC and uUVIO, respectively), the digital
interfaces will be released and the full functionality of the device will be available. The power-on event can be
identified with the corresponding flag in the status register and mode change according to the host command
will then be initiated (see Figure 8).
Data Sheet
15
Rev. 1.0 2015-06-12
TLE9222
Functional Description
uVCC
V
uBDUVVCC
uVIO
uUVIO
uBDPDVCC
dBDPower
Set Power-on flag
t
dBDRVIO
Release host command
Forced BD_Standby mode
BD_Off mode
According to Host Command
TLE9222_POWER-UP_V00
Figure 8
Power-up behavior
The power-down sequence of the TLE9222 is shown in Figure 9. As the voltage at the VCC supply pin, uVCC, falls
below the undervoltage threshold the VCC-undervoltage flag and the error flag are set. After the detection time
for VCC undervoltage dBDUVVCC the TLE9222 blocks the host command and automatically enters BD_Standby
mode.
uVCC
V
uBDUVVCC
uVIO
uUVIO
uBDPDVCC
Set VCC-undervoltage flag
Set Error flag
t
dBDUVVCC
dBDUVVIO
dBDPower
Block host command
Set VIO-undervoltage flag
Block all digital interfaces
According to Host Command
BD_Standby mode
BD_Off
TLE9222_POWER-DOWN_V00
Figure 9
Power-down behavior
While the TLE9222 is being powered down, the behavior on the digital interface level shift reference pin VIO is
very similar to the VCC supply pin. As uVIO falls below the undervoltage threshold the undervoltage timer is
started and the VIO-undervoltage flag is set. If VCC is not already in undervoltage condition, the error flag is also
set. After the detection time for VIO undervoltage, dBDUVVIO, the TLE9222 blocks the host command (if not
already blocked because of VCC undervoltage) and all digital interfaces and enters BD_Standby mode.
When the voltage at the VCC supply pin, uVCC, falls below the power-on threshold uBDPDVCC the TLE9222 enters
BD_Off condition within the time dBDPower.
Data Sheet
16
Rev. 1.0 2015-06-12
TLE9222
Functional Description
4.6
Remote Wake-up
The TLE9222 detects and signals a remote wake-up request after correct reception of a bus wake-up pattern
or wake-up payload in a FlexRay data frame while operating in BD_Standby mode. When the valid wake-up
pattern or wake-up payload is detected, the TLE9222 signals the request with the remote wake-up flag in the
status register and on the RxD and ERRN outputs within the time dBDWakeupReactionRemote.
The wake-up detector is also active in BD_Normal mode, but wake-up requests are only flagged when the
TLE9222 is in BD_Standby mode.
4.6.1
Bus Wake-up Patterns
A wake-up pattern consists of at least two wake-up symbols. A wake-up symbol on the FlexRay bus is defined
as either a phase of Data_0 followed by a phase of Idle, or alternatively as a phase of Data_0 followed by a
phase of Data_1. A valid remote wake-up event is detected with the reception of at least two consecutive
wake-up symbols on the bus within the time dWUTimeout (see Figure 10 and Figure 11).
Wake-up pattern
Bus Voltages
Wake-up symbol
Wake-up symbol
uBM
uBP
uBus = uBP - uBM
uData0_LP
t
Idle
Data_0
Idle
dWUIdleDetect
dWU0Detect
dWUIdleDetect
Data_0
Idle
dWU0Detect
dWUIdleDetect
dBDWakeupReactionRemote
dWUTimeout
RxD
ERRN
Idle
High
Low
t
TLE9222_WAKEUP_STANDARD_V00
Figure 10
Standard wake-up pattern
The Data_0 phases have to be longer than the time dWU0Detect while the Idle or Data_1 (alternative wake-up
pattern) phases have to be longer than the time dWUIdleDetect. The TLE9222 detects and signals both the
standard and the alternative wake-up patterns without any behavioral differences.
Data Sheet
17
Rev. 1.0 2015-06-12
TLE9222
Functional Description
Wake-up pattern
Wake-up symbol
Wake-up symbol
Bus Voltages
uBM
uBP
uBus = uBP - uBM
uData0_LP
t
Idle
Data_0
Data_1
dWUIdleDetect
dWU0Detect
dWUIdleDetect
Data_0
Data_1
dWU0Detect
dWUIdleDetect
RxD
ERRN
dWUTimeout
Idle
dBDWakeupReactionRemote
High
Low
t
TLE9222_WAKEUP_ALTERNATIVE_V00
Figure 11
Alternative wake-up pattern
4.6.2
Wake-up by Payload
In addition to wake-up detection by wake-up patterns, the TLE9222 also supports wake-up requests by a
specific payload within the data field of a FlexRay communication frame with data transmission rate of
10 Mbit/s.
A dedicated Byte Start Sequence (BSS) is transmitted before each byte of the payload within the FlexRay data
frame. The BSS consists of one “high” bit followed by one “low” bit. For transmitting a “Data_0” byte on the
FlexRay bus, the FlexRay controller sends 10 bits, the “high” bit and the “low” bit as part of the BSS followed
by the eight “low” data bits (HL= BSS; LLLLLLLL= “Data_0”). For sending a “Data_1” byte the FlexRay controller
sends the “high” bit and the “low” bit, followed by the eight consecutive “high” data bits (HL = BSS;
HHHHHHHH = “Data_1”) (see Figure 12).
uBus
„Data_1"
uData0_LP
„Data_0"
t
dWU0Detect
dWUIdleDetect
dWU0Detect
dWUIdleDetect
dWUTimeout
Wake-up payload content:
0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00,
0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00,
0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00,
0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF
Figure 12
Data Sheet
dWUInterrupt
TLE9222_WAKEUP_PAYLOAD_V01
Wake-up by payload
18
Rev. 1.0 2015-06-12
TLE9222
Functional Description
4.7
Fail Safe Functions and Flags
In addition to power supply undervoltage detection, the TLE9222 provides several functions for detection of
local or remote failures with corresponding status flags. These errors are signalled with the ERRN output and
can be read out from the status register. When local errors are detected, the TLE9222 initiates fail safe
procedures for device self protection and prevention of communication channel interruption.
4.7.1
Overtemperature detection
Junction temperature
The transmitter of the TLE9222 is protected against overtemperature events when active in BD_Normal mode.
If the junction temperature rises above the TJ(warning) threshold the temperature-warning flag in the status
register is set. If the junction temperature continues to rise and exceeds the TJ(Shut_Down) threshold, the
transmitter will be disabled and the overtemperature event will be flagged by the temperature-high flag in the
status register and signalled with the ERRN output.
Temperature-warning flag set
TJ(Shut_Down)
TJ(Warning)
Bus
t
TxD
t
High
Low
RxD
t
High
Low
ERRN
t
High
dReactionTimeERRN
Low
t
TLE9222_OVERTEMPERATURE_V00
Figure 13
Overtemperature protection
4.7.2
Bus Error Detector
The bus error detector monitors the FlexRay bus for identifying external failures which may lead to corrupt
data transmission and reception. With the RxD-TxD compare function and the bus overcurrent monitoring,
bus errors are detected and signalled with the bus error flag. The bus error detector is only enabled in
BD_Normal mode while the transmitter is active.
Data Sheet
19
Rev. 1.0 2015-06-12
TLE9222
Functional Description
4.7.2.1
RxD-TxD Compare
When the TLE9222 transmits data on the bus (TxEN “low” and BGE “high”), the digital input data on TxD is
compared with the received data on the RxD output. If the data is not identical, a failure condition is identified.
Both the positive and the negative edges on the TxD input signal triggers an internal comparator to compare
the TxD signal with the RxD signal. The results are stored in an internal error counter. When the internal error
counter exceeds 10 reported comparison failures, the bus error flag will be set. The error counter is reset when
the transmitter is deactivated.
4.7.2.2
Bus Overcurrent
The BP and BM bus pins have implemented current sensors for detection of overcurrent conditions in the
direction in or out of the pins. Detection of overcurrent is the typical signature of a short circuit of one of the
bus lines to the ground or a supply line.
4.7.3
Transmitter Time-Out
For avoiding unintentional blocking of the FlexRay bus in case of e.g. a malfunctioning microcontroller or
short circuits on the PCB, the transmitter is protected with a time-out function. When the transmitter is
activated for bus transmission while in BD_Normal mode, with a “low” signal on TxEN and “high” on BGE, a
timer is started. In case a time-out occurs, the transmitter will automatically be disabled and the failure will
be signaled on the ERRN output and in the status register.
The transmitter timer is reset when the transmitter is deactivated with either TxEN or BGE.
4.7.4
VIO Undervoltage-flag
During VIO undervoltage events, the SPI register is blocked and can not be read out. After undervoltage
recovery, depending on host command and the status of other register flags, the VIO-undervoltage flag may or
may not be set. Please refer to Chapter 4.7.6.
4.7.5
SPI-error flag
The SPI-error flag is used for indication of incorrect SPI read-out procedure, please find detailed description
in Chapter 4.8.1.
4.7.6
Error flag
If any local errors or bus errors are detected, the respective bit in the status register is flagged together with
the error flag (bit 12). If the error flag is set, but no other error contributing flags in the status register set, then
this indicates that a VIO undervoltage event has occurred in the past but recovery has already taken place.
While the error flag is set and the host command on the STBN input is “high”, the ERRN output is “low”.
4.7.7
Mode Flags
The mode flag in the status register indicates the current operating mode of the TLE9222, regardless of the
applied host command. If the TLE9222 is in BD_Standby mode, bit 1 will be “low”. If the current operation
mode is BD_Normal, bit 1 will be “high”. The mode flag will only toggle during an operation mode change, i.e.
not be reset by SPI register read-out. The mode indication can be beneficial for the host when the TLE9222 is
forced to a different mode than requested with the host command during VCC undervoltage events.
Data Sheet
20
Rev. 1.0 2015-06-12
TLE9222
Functional Description
4.8
SPI Interface and Status Register
The TLE9222 has a 16-bit SPI interface for reading out the internal status register. The bits in the register
reflects detailed flags regarding external events such as wake-up and power-on recognition, detection of
errors / warnings and operation mode indication, see Table 5.
Table 5
Bit definition of the status register
Bit
Name
Indication
Comment
Bit 0
Remote wake-up
flag
“Low”: Remote wake-up detected
–
“High”: –
–
Mode flag
”Low”: BD_Standby mode
–
“High”: BD_Normal mode
–
Bit 1
Bit 2
BGE flag
“Low”: Transmitter disabled by Bus Guardian, Error, will trigger Bit 12 → “low”
BGE input “low” in BD_Normal mode
“High”: –
–
“Low”: Bus activity ongoing
Not latched
“High”: Bus idle
–
“Low”: Power-on detected
–
“High”: –
–
“Low”: Bus error detected
Error, will trigger Bit 12 → “low”
“High”: –
–
“Low”: Overtemperature detected
Error, will trigger Bit 12 → “low”
“High”: –
–
“Low”: Transmitter activation time-out
Error, will trigger Bit 12 → “low”
“High”: –
–
“Low”: VCC Undervoltage detected
Error, will trigger Bit 12 → “low”
“High”: –
–
“Low”: VIO Undervoltage detected
Error, will trigger Bit 12 → “low”
“High”: –
–
“Low”: SPI error detected
Error, will trigger Bit 12 → “low”
“High”: –
–
Bit 11 Temperaturewarning flag
“Low”: High temperature warning
–
“High”: –
–
Bit 12 Error flag
“Low”: Error(s) detected
Error, will trigger ERRN output
“low” if signal on STBN is “high”
“High”: No errors detected
–
Bit 13 Reserved
Always ”High”
–
Bit 14 Reserved
Always “Low”
–
Bit 15 Even parity bit
“Low”: Odd parity of Bit 0 to Bit 14
–
“High”: Even parity of Bit 0 to Bit 14
–
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 8
Bit 9
RxEN flag
Power-on flag
Bus-error flag
Temperature-high
flag
Transmitter timeout flag
VCC-undervoltage
flag
VIO-undervoltage
flag
Bit 10 SPI-error flag
Data Sheet
21
Rev. 1.0 2015-06-12
TLE9222
Functional Description
All the flags in the status register are “active low”, the default level is “high”.
The RxEN flag indicates ongoing bus transmission. As soon as the bus state returns to idle, this flag is set
“high”.
The wake-up, power-on and error flags and their corresponding status register bits are latched “low”. A mode
change by host command or a correct SPI status bit register read-out will reset these flags, given that the error
condition has been resolved.
4.8.1
Read-out procedure
The SPI interface of the TLE9222 is enabled by the SCSN (SPI Chip Select Not) input. While SCSN is “high”, the
SDO (SPI Data Output) output is in a high impedance state and clock signals on the SCLK input are ignored.
The read-out procedure is initiated with a “low” signal on SCSN, which will cause the SDO output to be set
“low” (see Figure 13). After the time dSPILead the status register data can be shifted out on the SDO output
synchronized with the rising edge of a clock signal on the SCLK input. With a clock signal period of dSPIClk, the
TLE9222 supports SPI data rates in the range 10 kbit/s to 4 Mbit/sIf a transition on SCSN from “high” to “low”
is detected while SCLK is “high”, this would be identified as a SPI error.
Within the SCSN period, the time dSPISCSN_Low while the signal on SCSN is “low”, exactly 16 clock cycles are
expected for a correct read-out procedure. Incorrect SPI access, with more or less than 16 SCLK cycles or
wrong timing, is protected by the SPI timer. If the read-out time dSPISCSN_Low expires, the SDO output is set to
“high impedance” within the time dSPISDOZ. Additionally the error flag and SPI-error flag in the status register
will be set, while the state of all other latched bits are left unchanged.
SCSN
dSPISCSN_Low
High
Low
t
SCLK
dSPILead
dSPILag
dSPIClk
High
Low
t
SDO
dSPISDOZ
High
High impedance
Bit 0
Bit 1
Bit 2
Bit 3
Bit 13
Bit 14
Bit 15
High impedance
Low
t
TLE9222_SPI_READ-OUT_V00
Figure 14
SPI read-out
After a correct SPI read-out process, the information on the ERRN output and the flags in the status register
are refreshed. Next SPI read-out can be initiated after SCSN is set “high” for the time dSPIInterframe.
The SPI interface is available in both BD_Normal mode and BD_Standby mode, but SPI readout should not
occur at the same time as a mode change with the host interface, the time dBDModeChange must be respected.
The SPI register is also blocked during undervoltage conditions on VIO.
While the TLE9222 is set in BD_Standby with host command (pin STBN = “low”) and no wake-up or errors have
been detected, the SPI interface requires an enable time of dSPILeadStbOK from SCSN goes “low” until the first
rising edge on the clock signal on the SCLK input can be applied.
Data Sheet
22
Rev. 1.0 2015-06-12
TLE9222
General Product Characteristics
5
General Product Characteristics
5.1
Absolute Maximum Ratings
Table 6
Absolute Maximum Ratings 1)
All voltages with respect to ground, positive current flowing into pin; (unless otherwise specified)
Parameter
Symbol
Values
Min.
Typ.
Max.
Unit Note or
Number
Test Condition
Voltages
Supply Voltage VCC
uVCC
-0.3
–
6.0
V
–
P_5.1.1
Digital Reference Voltage VIO
uVIO
-0.3
–
6.0
V
–
P_5.1.2
DC voltage on pin BP
uBP
-40
–
40
V
–
P_5.1.3
DC voltage on pin BM
uBM
-40
–
40
V
–
P_5.1.4
DC voltage on logic input pins TxD,
TxEN, BGE, STBN, SCSN, SCLK
uVLogic_in
-0.3
–
6.0
V
–
P_5.1.5
DC voltage on logic output pins RxD,
ERRN, SDO
uVLogic_out
-0.3
–
uVIO + V
0.3
–
P_5.1.6
Output Current on pin RxD
iRxD
-40
–
40
mA
–
P_5.1.7
Output Current on pin ERRN
iERRN
-40
–
40
mA
–
P_5.1.8
Output Current on pin SDO
iSDO
-40
–
40
mA
–
P_5.1.9
Junction Temperature
Tj
-40
–
150
°C
–
P_5.1.10
Storage Temperature
Tstg
-55
–
150
°C
–
P_5.1.11
-8
–
8
kV
HBM2)
P_5.1.12
kV
HBM2)
P_5.1.13
3)
P_5.1.14
Currents
Temperature
ESD Susceptibility
ESD Susceptibility to GND on BP and BM uESDExt
ESD Susceptibility to GND all other pins uESDInt
ESD Susceptibility to GND all pins
uESDCDM
-2
-750
–
–
2
750
V
CDM
1) Not subject to production test, specified by design.
2) ESD susceptibility, HBM according to ANSI/ESDA/JEDEC JS001 (1.5k Ω, 100 pF).
3) ESD susceptibility, Charged Device Model “CDM” ESDA STM5.3.1 or ANSI/ESD S.5.3.1.
Notes
1. Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
2. Integrated protection functions are designed to prevent IC destruction under fault conditions described in the
data sheet. Fault conditions are considered as “outside” normal operating range. Protection functions are
not designed for continuous repetitive operation.
Data Sheet
23
Rev. 1.0 2015-06-12
TLE9222
General Product Characteristics
5.2
Functional Range
Table 7
Operating Range
Parameter
Symbol
Values
Min.
Typ.
Max.
Unit
Note or
Test Condition
Number
Supply Voltage VCC
uVCC
4.75
–
5.25
V
–
P_5.2.1
Digital Reference Voltage VIO
uVIO
3.0
–
5.25
V
–
P_5.2.2
Junction Temperature
TJ
-40
–
150
°C
–
P_5.2.3
Note: Within the functional or operating range, the IC operates as described in the circuit description. The
electrical characteristics are specified within the conditions given in the Electrical Characteristics table.
5.3
Thermal Resistance
Note: This thermal data was generated in accordance with JEDEC JESD51 standards. For more information, go
to www.jedec.org.
Table 8
Thermal Resistance 1)
Parameter
Symbol
Values
Unit
Note or
Test Condition
Number
Min.
Typ.
Max.
–
120
–
K/W
2)
P_5.3.1
Thermal Resistance
Junction to Ambient
RthJA
Thermal Shutdown Junction Temperature
Thermal warning temp.
TJ(warning)
150
160
170
°C
–
P_5.3.2
Thermal shut-down temp.
TJ(Shut_Down) 170
180
190
°C
–
P_5.3.3
Thermal shutdown hysteresis
∆T
6
–
K
–
P_5.3.4
–
1) Not subject to production test, specified by design.
2) Specified RthJA value is according to Jedec JESD51-2,-7 at natural convection on FR4 2s2p board; The TLE9222 (PGTSSOP-14) was simulated on a 76.2 x 114.3 x 1.5 mm board with 2 inner copper layers (2 x 70µm Cu, 2 x 35µm Cu).
Data Sheet
24
Rev. 1.0 2015-06-12
TLE9222
Electrical Characteristics
6
Electrical Characteristics
6.1
Functional Device Characteristics
Table 9
Electrical Characteristics
uVCC = 4.75 V to 5.25 V; uVIO = 3.0 V to 5.25 V; RDCLOAD = 45 Ohm; CDCLOAD = 100 pF; Tj = -40°C to +150°C
All voltages with respect to ground, positive current flowing into pin (unless otherwise specified)
Parameter
Symbol
Values
Un Note or Test Condition Number
Min. Typ. Max it
.
Current Consumption VCC Power Supply
Current Consumption in
BD_Normal mode
iVCC
–
33
40
mA Transmitter active
P_6.1.1
Current Consumption in
BD_Normal mode
iVCC_idle
–
6
15
mA Transmitter idle;
P_6.1.2
Current Consumption in
BD_Standby mode
iVCC_Stb_150
–
30
40
µA TJ ≤ 150°C;
No bus activity or local
errors detected; Logic
inputs in default states;
ERRN = “high”
P_6.1.3
Current Consumption in
BD_Standby mode
iVCC_Stb_85
–
17
25
µA TJ ≤ 85°C; No bus activity P_6.1.4
or local errors detected;
Logic inputs in default
states; ERRN = “high”
Current Consumption in
BD_Off condition
iVCC_Off
–
–
35
µA Logic inputs in default
states;
P_6.1.5
Current Consumption VIO Reference
Current Consumption in
BD_Normal mode
iVIO
–
0.15 0.5
mA –
P_6.1.6
Current Consumption in
BD_Standby mode
iVIO_Stb
–
1
5
µA No bus activity or local
errors detected; Logic
inputs in default states;
ERRN = “high”
P_6.1.7
Current Consumption in BD_Off
condition
iVIO_Off
–
–
5
µA Logic inputs in default
states
P_6.1.8
4.0
4.25 4.75 V
Undervoltage Detection VCC Power Supply
Undervoltage detection
threshold on VCC
uBDUVVCC
Undervoltage detection
hysteresis on VCC
uBDUVVCC_Hy –
Data Sheet
100
–
–
mV –
P_6.1.9
P_6.1.10
s
25
Rev. 1.0 2015-06-12
TLE9222
Electrical Characteristics
Table 9
Electrical Characteristics (cont’d)
uVCC = 4.75 V to 5.25 V; uVIO = 3.0 V to 5.25 V; RDCLOAD = 45 Ohm; CDCLOAD = 100 pF; Tj = -40°C to +150°C
All voltages with respect to ground, positive current flowing into pin (unless otherwise specified)
Parameter
Symbol
Values
Un Note or Test Condition Number
Min. Typ. Max it
.
Power-on reset threshold
uBDPDVCC
1.5
2.5
3.5
V
Transition time to BD_Standby
mode after power-up
dBDPower
–
50
100
µs VCC > uBDPDVCC
Undervoltage filter time
dBDUVVCC_blk 3
–
10
µs
Undervoltage detection time
dBDUVVCC
3
40
100
µs Time between underP_6.1.14
voltage event and forced
mode change
Undervoltage recovery time
dBDRVCC
3
40
100
µs Time between undervoltage recovery and
forced mode change
P_6.1.15
2.5
2.7
3.0
V
–
P_6.1.16
–
P_6.1.11
P_6.1.12
1)
P_6.1.13
Undervoltage Detection VIO Reference
Undervoltage detection
threshold on VIO
uUVIO
Undervoltage detection
hysteresis on VIO
uBDUVVIO_Hys –
30
–
mV –
P_6.1.17
Undervoltage filter time
dBDUVVIO_blk 1
–
10
µs
1)
P_6.1.18
Undervoltage detection time
dBDUVVIO
1
40
100
µs Time between underP_6.1.19
voltage event and forced
mode change
Undervoltage recovery time
dBDRVIO
1
40
100
µs Time from recovery until P_6.1.20
possible mode change
–
100
%
Relative to uVIO; 2);
iRxDH = -2 mA;
P_6.1.21
–
20
%
Relative to uVIO; 2);
iRxDL = 2 mA;
P_6.1.22
–
250
mV uVIO < uUVIO;
100 kΩ load to GND;
P_6.1.23
–
100
mV 100 kΩ load to GND;
P_6.1.24
Digital Output RxD
High level output voltage
uVDig_Out_High 80
_RxD
Low level output voltage
uVDig_Out_Low_ –
RxD
Output voltage while uVIO is in
undervoltage condition
uVDig_Out_UV_R –
Output voltage while in BD_Off
condition
uVDig_Out_Off_R –
xD
Rise time on the RxD output
dBDRxDR15
–
2
6
ns 20 % → 80% of uVIO;
CBDRxD = 15 pF
P_6.1.25
Fall time on the RxD output
dBDRxDF15
–
2
6
ns 80 % → 20% of uVIO;
CBDRxD = 15 pF
P_6.1.26
Rise time on the RxD output
dBDRxDR25
–
3
8
ns 20 % → 80% of uVIO;
CBDRxD = 25 pF
P_6.1.27
Data Sheet
xD
26
Rev. 1.0 2015-06-12
TLE9222
Electrical Characteristics
Table 9
Electrical Characteristics (cont’d)
uVCC = 4.75 V to 5.25 V; uVIO = 3.0 V to 5.25 V; RDCLOAD = 45 Ohm; CDCLOAD = 100 pF; Tj = -40°C to +150°C
All voltages with respect to ground, positive current flowing into pin (unless otherwise specified)
Parameter
Symbol
Un Note or Test Condition Number
Min. Typ. Max it
.
Fall time on the RxD output
dBDRxDF25
–
3
8
ns 80 % → 20% of uVIO;
CBDRxD = 25 pF
P_6.1.28
Sum of rise and fall time on the
RxD output
dBDRxDR15 + –
dBDRxDF15
4
12
ns CBDRxD = 15 pF;
P_6.1.29
Difference of rise and fall time on |dBDRxDR15 - –
dBDRxDF15|
the RxD output
1
2.5
ns CBDRxD = 15 pF;
P_6.1.30
dBDRxDR25 + –
dBDRxDF25
6
13
ns CBDRxD = 25 pF;
P_6.1.31
Difference of rise and fall time on |dBDRxDR25 - –
dBDRxDF25|
the RxD output
1
2.5
ns CBDRxD = 25 pF;
P_6.1.32
–
100
%
Relative to uVIO; 2);
iERRNH = -2 mA;
P_6.1.33
–
20
%
Relative to uVIO; 2);
iERRNL = 2 mA;
P_6.1.34
–
250
mV uVIO < uUVIO;
100 kΩ load to GND;
P_6.1.35
–
100
mV 100 kΩ load to GND;
P_6.1.36
Sum of rise and fall time on the
RxD output
Values
Digital Output ERRN
High level output voltage
uVDig_Out_High 80
_ERRN
Low level output voltage
uVDig_Out_Low_ –
Output voltage while uVIO is in
undervoltage condition
uVDig_Out_UV_E –
Output voltage while in BD_Off
condition
uVDig_Out_UFF_ –
ERRN
Rise time on the ERRN output
dBDERRNR25 –
3
8
ns
1)
; 20 % → 80% of uVIO;
CBDERRN = 25 pF
P_6.1.37
Fall time on the ERRN output
dBDERRNF25 –
3
8
ns
1)
P_6.1.38
Reaction time on the ERRN pin
dReactionTi –
meERRN
5
30
µs –
P_6.1.39
uVDig_Out_High 80
–
100
%
Relative to uVIO; 2);
iSDOH = -2 mA;
P_6.1.40
–
20
%
Relative to uVIO; 2);
iSDOL = 2 mA;
P_6.1.41
ERRN
RRN
; 80 % → 20% of uVIO;
CBDERRN = 25 pF
Digital Output SDO
High level output voltage
_SDO
Low level output voltage
uVDig_Out_Low_ –
SDO
Leakage current while in high
impedance state
iBDSDOZ
-1
–
1
µA 0V < uSDO < uVIO;
SCSN = “high”
Rise time on the SDO output
dBDSDOR25
–
3
8
ns
1)
; 20 % → 80% of uVIO;
CBDSDO = 25 pF
P_6.1.43
Fall time on the SDO output
dBDSDOF25
–
3
8
ns
1)
P_6.1.44
Data Sheet
27
P_6.1.42
; 80 % → 20% of uVIO;
CBDSDO = 25 pF
Rev. 1.0 2015-06-12
TLE9222
Electrical Characteristics
Table 9
Electrical Characteristics (cont’d)
uVCC = 4.75 V to 5.25 V; uVIO = 3.0 V to 5.25 V; RDCLOAD = 45 Ohm; CDCLOAD = 100 pF; Tj = -40°C to +150°C
All voltages with respect to ground, positive current flowing into pin (unless otherwise specified)
Parameter
Symbol
Values
Un Note or Test Condition Number
Min. Typ. Max it
.
Reaction time for setting SDO
output to “high impedance”
dSPISDOZ
–
–
250
ns
1)
P_6.1.45
Threshold for detecting logical
“high”
uBDLogic_1
–
–
60
%
Relative to uVIO;
P_6.1.46
Threshold for detecting logical
“low”
uBDLogic_0
40
–
–
%
Relative to uVIO;
P_6.1.47
High level input current
iBDLogic_1
20
–
200
µA –
P_6.1.48
Low level input current
iBDLogic_0
-1
–
1
µA –
P_6.1.49
Input capacitance on pin TxD
C_BDTxD
–
–
5
pF
1)
P_6.1.50
Threshold for detecting logical
“high”
uVDig_In_High_T –
–
70
%
Relative to uVIO;
P_6.1.51
Threshold for detecting logical
“low”
uVDig_In_Low_T 30
–
–
%
Relative to uVIO;
P_6.1.52
High level input current
iDig_In_High_TxE -1
–
1
µA –
P_6.1.53
-20
µA –
P_6.1.54
5
pF
1)
P_6.1.55
Digital Input TxD
Digital Input TxEN
xEN
xEN
N
Low level input current
iDig_In_Low_TxE -200 –
N
Input capacitance on pin TxEN
C_BDTxEN
–
–
Maximum transmitter activation
time
dBDTxActive 1500 –
Max
2600 µs –
P_6.1.56
Threshold for detecting logical
“high”
uVDig_In_High_B –
–
70
%
Relative to uVIO;
P_6.1.57
Threshold for detecting logical
“low”
uVDig_In_Low_B 30
–
–
%
Relative to uVIO;
P_6.1.58
High level input current
iDig_In_High_BGE 20
–
200
µA –
P_6.1.59
Low level input current
iDig_In_Low_BGE -1
–
1
µA –
P_6.1.60
Digital Input BGE
GE
GE
Transmitter activation delay BGE, dBDBGEia
Idle → active
–
50
75
ns RDCLOAD = 40 Ω
P_6.1.61
Transmitter deactivation delay
BGE, Active → idle
dBDBGEai
–
50
75
ns RDCLOAD = 40 Ω
P_6.1.62
Input capacitance on pin BGE
C_BDBGE
–
–
5
pF
1)
P_6.1.63
Digital Input STBN
Data Sheet
28
Rev. 1.0 2015-06-12
TLE9222
Electrical Characteristics
Table 9
Electrical Characteristics (cont’d)
uVCC = 4.75 V to 5.25 V; uVIO = 3.0 V to 5.25 V; RDCLOAD = 45 Ohm; CDCLOAD = 100 pF; Tj = -40°C to +150°C
All voltages with respect to ground, positive current flowing into pin (unless otherwise specified)
Parameter
Symbol
Values
Un Note or Test Condition Number
Min. Typ. Max it
.
Threshold for detecting logical
“high”
uVDig_In_High_S –
Threshold for detecting logical
“low”
uVDig_In_Low_S 30
High level input current
iDig_In_High_STB 20
–
70
%
Relative to uVIO;
P_6.1.64
–
–
%
Relative to uVIO;
P_6.1.65
–
200
µA –
P_6.1.66
–
1
µA –
P_6.1.67
–
100
µs –
P_6.1.68
–
6
µs –
P_6.1.69
–
–
5
pF
1)
P_6.1.70
Threshold for detecting logical
“high”
uVDig_In_High_S –
–
70
%
Relative to uVIO;
P_6.1.71
Threshold for detecting logical
“low”
uVDig_In_Low_S 30
–
–
%
Relative to uVIO;
P_6.1.72
High level input current
iDig_In_High_SCL 20
–
200
µA –
P_6.1.73
–
1
µA –
P_6.1.74
TBN
TBN
N
Low level input current
iDig_In_Low_STB -1
Mode transition time after
applying host command
dBDModeChang –
Filter time for detection of host
commands
dBDLogicFilte 2
Input capacitance on pin STBN
C_BDSTBN
N
e
r
Digital Input SCLK
CLK
CLK
K
Low level input current
iDig_In_Low_SCL -1
SPI clock period
dSPIClock
0.25 –
100
µs –
P_6.1.75
SPI enable time
dSPILead
250
–
–
ns –
P_6.1.76
SPI enable time
dSPILeadStbOK 4
–
–
µs BD_Standby mode;
P_6.1.77
No Wake or errors
detected; STBN = “low”;
ERRN = “high”
SPI disable time
dSPILag
–
–
ns CBDSDO = 25 pF
K
250
P_6.1.78
–
–
5
pF
1)
Threshold for detecting logical
“high”
uVDig_In_High_S –
–
70
%
Relative to uVIO;
P_6.1.80
Threshold for detecting logical
“low”
uVDig_In_Low_S 30
–
–
%
Relative to uVIO;
P_6.1.81
Input capacitance on pin SCLK
C_BDSCLK
P_6.1.79
Digital Input SCSN
Data Sheet
CSN
CSN
29
Rev. 1.0 2015-06-12
TLE9222
Electrical Characteristics
Table 9
Electrical Characteristics (cont’d)
uVCC = 4.75 V to 5.25 V; uVIO = 3.0 V to 5.25 V; RDCLOAD = 45 Ohm; CDCLOAD = 100 pF; Tj = -40°C to +150°C
All voltages with respect to ground, positive current flowing into pin (unless otherwise specified)
Parameter
Symbol
Values
Un Note or Test Condition Number
Min. Typ. Max it
.
High level input current
iDig_In_High_SCS -1
–
1
µA –
P_6.1.82
-20
µA –
P_6.1.83
N
Low level input current
iDig_In_Low_SCS -200 –
N
SPI timeout
dSPITimeout
2.1
–
4
ms –
P_6.1.84
SPI Interframe space
dSPIInterframe
10
–
–
µs Break between
consecutive SPI readouts
P_6.1.85
Input capacitance on pin SCSN
C_BDSCSN
–
–
5
pF
1)
P_6.1.86
Absolute differential output
voltage while sending;
Data_0 and Data_1
uBDTxactive
0.9
–
2.0
V
40 Ω < RDCLOAD < 55 Ω; 4)
P_6.1.87
BP short circuit current
Short to GND, Absolute value
iBPGNDShortMa –
20
60
mA –
P_6.1.88
BP short circuit current
Short to -5 V, Absolute value
iBP-5ShortMax
–
40
60
mA –
P_6.1.89
BP short circuit current
Short to 27 V, Absolute value
iBPBAT27ShortM –
25
60
mA –
P_6.1.90
BP short circuit current
Short to BM, Absolute value
iBPBMShortMax –
35
60
mA –
P_6.1.91
BM short circuit current
Short to GND, Absolute value
iBMGNDShortMa –
20
60
mA –
P_6.1.92
BM short circuit current
Short to -5 V, Absolute value
iBM-5ShortMax
–
40
60
mA –
P_6.1.93
BM short circuit current
Short to 27 V, Absolute value
iBMBAT27Short –
25
60
mA –
P_6.1.94
BM short circuit current
Short to BP, Absolute value
iBMBPShortMax –
35
60
mA –
P_6.1.95
Transmitter delay negative
voltage
dBDTx10
–
35
50
ns RDCLOAD = 40 Ω; 3); 4)
P_6.1.96
Transmitter delay positive
voltage
dBDTx01
–
35
50
ns RDCLOAD = 40 Ω; 3); 4)
P_6.1.97
Transmitter delay mismatch
dBDTxAsym
= |dBDTx10 - dBDTx01|
dBDTxAsym
–
–
4
ns RDCLOAD = 40 Ω;
3) 4) 7)
; ;
P_6.1.98
Bus Transmitter, BP and BM
Data Sheet
x
ax
x
Max
30
Rev. 1.0 2015-06-12
TLE9222
Electrical Characteristics
Table 9
Electrical Characteristics (cont’d)
uVCC = 4.75 V to 5.25 V; uVIO = 3.0 V to 5.25 V; RDCLOAD = 45 Ohm; CDCLOAD = 100 pF; Tj = -40°C to +150°C
All voltages with respect to ground, positive current flowing into pin (unless otherwise specified)
Parameter
Symbol
Values
Un Note or Test Condition Number
Min. Typ. Max it
.
Fall time differential bus voltage
(80% → 20%)
dBusTx10
6
13
18.7 ns RDCLOAD = 40 Ω; 4)
5
P_6.1.99
Rise time differential bus voltage dBusTx01
(20% → 80%)
6
13
18.7 ns RDCLOAD = 40 Ω; 4)
5
P_6.1.100
Difference between differential
bus voltage rise time and fall
time
dBusTxDiff
= |dBusTx01 - dBusTx10|
dBusTxDiff
–
–
3
ns RDCLOAD = 40 Ω;
P_6.1.101
Transmitter delay
Idle → active
dBDTxia
–
40
75
ns RDCLOAD = 40 Ω;
P_6.1.102
Transmitter delay
Active → idle
dBDTxai
–
45
75
ns RDCLOAD = 40 Ω;
P_6.1.103
Transmitter delay mismatch
dBDTxDM = dBDTxai - dBDTxia
dBDTxDM
-30
–
30
ns RDCLOAD = 40 Ω;
P_6.1.104
Transition time
Idle → active
dBusTxia
–
10
30
ns RDCLOAD = 40 Ω;
P_6.1.105
Transition time
Active → idle
dBusTxai
–
10
30
ns RDCLOAD = 40 Ω;
P_6.1.106
Receiver threshold for detecting
Data_1
uData1
150
–
300
mV -10 V < uCM < 15 V;
P_6.1.107
Receiver threshold for detecting
Data_0
uData0
-300 –
-150 mV -10 V < uCM < 15 V;
P_6.1.108
Mismatch of receiver thresholds
uData0 |uData1|
-30
–
30
mV (uBP + uBM) / 2 = 2.5 V;
P_6.1.109
Common mode voltage range
uCM = (uBP + uBM) /2
uCM
-10
–
15
V
Filter time for bus idle detection
dBDIdleDete 50
ction
–
200
ns uBus = 900 mV → 30 mV;
P_6.1.111
Filter time for bus active
detection
dBDActivityD 100
etection
–
250
ns uBus = 30 mV → 900 mV;
P_6.1.112
Receiver common mode input
resistance
RCM1, RCM2
10
–
40
kΩ Bus idle; open load;
P_6.1.113
Receiver differential input
resistance
RCM1 + RCM2
20
–
80
kΩ Bus idle; open load;
P_6.1.114
Bus Receiver, BP and BM
Data Sheet
31
5)
;
P_6.1.110
Rev. 1.0 2015-06-12
TLE9222
Electrical Characteristics
Table 9
Electrical Characteristics (cont’d)
uVCC = 4.75 V to 5.25 V; uVIO = 3.0 V to 5.25 V; RDCLOAD = 45 Ohm; CDCLOAD = 100 pF; Tj = -40°C to +150°C
All voltages with respect to ground, positive current flowing into pin (unless otherwise specified)
Parameter
Symbol
Un Note or Test Condition Number
Min. Typ. Max it
.
Absolute differential bus idle
voltage
uBDTxIdle
0
–
30
mV TxEN = “high”;
40 Ω < RDCLOAD < 55 Ω;
P_6.1.115
Idle voltage at BP and BM
BD_Normal mode
uBiasNon-
1.8
2.5
3.2
V
TxEN = “high”; 6);
40 Ω < RDCLOAD < 55 Ω;
P_6.1.116
Idle voltage at BP and BM
BD_Standby mode
uBiasLowPower -100 0
100
mV 40 Ω < RDCLOAD < 55 Ω; 6);
Absolute leakage current on BP
when in BD_Off condition
iBPLeak
–
7
15
µA uBP = uBM = 5 V; All
P_6.1.118
other pins connected to
GND. GND pin connected
directly to 0 V;
Absolute leakage current on BM
when in BD_Off condition
iBMLeak
–
7
15
µA uBP = uBM = 5 V; All
P_6.1.119
other pins connected to
GND. GND pin connected
directly to 0 V;
Absolute BP leakage current loss iBPLeakGND
of GND
–
500
1600 µA uBP = uBM = 0 V;
P_6.1.120
All other pins connected
via 0 Ω to 16 V;
Absolute BM leakage current loss iBMLeakGND
of GND
–
500
1600 µA uBP = uBM = 0 V;
P_6.1.121
All other pins connected
via 0 Ω to 16 V;
Receiver delay, negative edge
dBDRx10
–
60
75
ns CBDRxD = 25 pF;
(see Figure 18);
P_6.1.122
Receiver delay, positive edge
dBDRx01
–
60
75
ns CBDRxD = 25 pF;
(see Figure 18);
P_6.1.123
Receiver delay mismatch
dBDRxAsym
= |dBDRx10 - dBDRx01|
dBDRxAsym
–
–
5
ns (uBP + uBM) / 2 = 2.5 V;
CBDRxD = 25 pF;
7)
; (see Figure 18);
P_6.1.124
Idle reaction time
dBDRxai
50
–
250
ns (see Figure 19);
P_6.1.125
Activity reaction time
dBDRxia
100
–
300
ns (see Figure 19);
P_6.1.126
Idle Loop Delay
dBDTxRxai = dBDTxai + dBDRxai
dBDTxRxai
–
–
325
ns –
P_6.1.127
BP output current, Bus idle
iBPIdle
-5.0
–
5.0
mA -27 V < uBP < 27 V;
P_6.1.128
BM output current, Bus idle
iBMIdle
-5.0
–
5.0
mA -27 V < uBM < 27 V;
P_6.1.129
Input capacitance on pin BP
Data Sheet
Values
LowPower
C_BDBP
–
–
32
30
pF
1)
; uBP = 100 mV;
fTest = 5 MHz;
P_6.1.117
P_6.1.130
Rev. 1.0 2015-06-12
TLE9222
Electrical Characteristics
Table 9
Electrical Characteristics (cont’d)
uVCC = 4.75 V to 5.25 V; uVIO = 3.0 V to 5.25 V; RDCLOAD = 45 Ohm; CDCLOAD = 100 pF; Tj = -40°C to +150°C
All voltages with respect to ground, positive current flowing into pin (unless otherwise specified)
Parameter
Symbol
Values
Un Note or Test Condition Number
Min. Typ. Max it
.
Input capacitance on pin BM
C_BDBM
–
–
30
pF
1)
; uBM = 100 mV;
fTest = 5 MHz;
P_6.1.131
Differential bus input capacitance C_BDBus
–
–
20
pF
1)
P_6.1.132
; uBP - uBM = 100 mV;
fTest = 5 MHz;
Remote Wake-up Detection, BP and BM
Low-power receiver threshold for uData0_LP
detecting Data_0
-400 –
-100 mV –
P_6.1.133
Acceptance time-out of a Data_0 dWU0Detect
phase in wake-up pattern
1
–
4
µs –
P_6.1.134
Acceptance time-out of an Idle or dWUIdleDetect
Data_1 phase in wake-up pattern
1
–
4
µs –
P_6.1.135
Acceptance time-out for wake-up dWUTimeout
pattern recognition
48
–
140
µs –
P_6.1.136
Acceptance time-out for
interruptions
dWUInterruptt
0.13 –
1
µs
8)
P_6.1.137
Reaction time after wake-up
dBDWakeup –
ReactionRemo
100
µs –
P_6.1.138
–
te
1)
2)
3)
4)
5)
6)
7)
8)
Not subject to production test, specified by design.
No undervoltage on VIO. VCC supplied.
For all TxD signals with a sum of rise and fall time (20% - 80% uVIO) of up to 9ns.
The TxD signal is constant for 100 ns ... 4400 ns before the first edge and also in case the test is performed with the
opposite polarity.
Tested on a receiving bus driver. Sending bus driver has a ground offset voltage in the range of [-12.5 V to +12.5 V] and
sends a 50 / 50 pattern.
Bus Driver connected to GND and uVCC = 5 V.
For ±300 mV as well as ±150 mV levels of uBUS.
When the phase that is interrupted was continuously present for at least 870 ns.
Data Sheet
33
Rev. 1.0 2015-06-12
TLE9222
Electrical Characteristics
6.2
Diagrams
RxD
VIO
TxEN
100nF
VCC
TLE9222
TxD
ERRN
100nF
STBN
CBDERRN
BGE
RDCLOAD
BP
CDCLOAD
CBDRxD
SDO
SCSN
BM
GND
CBDSDO
SCLK
TLE9222_TEST_CIRCUIT_V00
Figure 15
Simplified test circuit
100 … 4400 ns
High
TxD
100% VIO
50% VIO
Low
0% VIO
dBDTx10
t
dBDTx01
100 %
uBDTxactive
80 %
uBus
300mV
0V
t
-300mV
20 %
0%
- uBDTxactive
dBusTx10
dBusTx01
(TxEN = „low“ and BGE = „high“)
TLE9222_TRANSMITTER_CHARACTERISTICS_V01
Figure 16
Data Sheet
Transmitter characteristics
34
Rev. 1.0 2015-06-12
TLE9222
Electrical Characteristics
dTxENLOW
High
TxEN
100% VIO
50% VIO
Low
0% VIO
dBDTxia
t
dBDTxai
uBus
0V
-30mV
t
-300mV
- uBDTxactive
dBusTxia
dBusTxai
(TxD = „low“ and BGE = „high“)
TLE9222_TRANSMITTER_CHARACTERISTICS_IA_AI_V00
Figure 17
Transmitter characteristics from “idle” to “active” and vice versa
dBusRx10
dBusRx01
uBusRxData
300mV
uBus
150mV
0V
t
-150mV
-300mV
-uBusRxData
dBusRx0BD
dBusRx1BD
dBDRx10
dBDRx01
High
RxD
100% VIO
50% VIO
Low
0% VIO
t
The Receiver timings are valid for bus signals dBusRx0BD and dBusRx1BD longer than the minimum bit time tBit = 60 ns and for
both polarities
TLE9222_RECEIVER_CHARACTERISTICS_V01
Figure 18
Data Sheet
Receiver timing characteristics
35
Rev. 1.0 2015-06-12
TLE9222
Electrical Characteristics
dBusRxia
dBusRxai
uBus
0V
-30mV
t
-150mV
-300mV
-uBusRx
dBusActive
dBusIdle
dBDRxia
dBDRxai
High
RxD
100% VIO
50% VIO
Low
0% VIO
t
TLE9222_RECEIVER_CHARACTERISTICS_IA_AI_V01
Figure 19
Data Sheet
Receiver characteristics from “idle” to “active” and vice versa
36
Rev. 1.0 2015-06-12
TLE9222
Application Information
7
Application Information
Note: The following information is given as a hint for the implementation of the device only and shall not be
regarded as a description or warranty of a certain functionality, condition or quality of the device.
7.1
ESD Robustness according to IEC61000-4-2
Tests for ESD robustness according to IEC61000-4-2 “Gun test” (150 pF, 330 Ω) have been performed. The
results and test conditions are available in a separate test report.
Table 10
ESD Robustness according to IEC61000-4-2
Performed Test
Result
Unit
Comment
Electrostatic discharge voltage at pin BM and BP versus GND uESDIEC
≥8
kV
Positive pulse
Electrostatic discharge voltage at pin BM and BP versus GND uESDIEC
≤ -8
kV
Negative pulse
7.2
Symbol
Bus Interface Simulation Model Parameter
The simulated value RBDTransmitter describes the equivalent bus driver output impedance.
RBDTransmitter = 50Ω x ( uBus100 – uBus40 ) / ( 2.5 x uBus40 – uBus100 )
uBus100
=
differential output voltage on a 100Ω || 100pF load, while
driving “Data_1” to the bus. Value based on simulation.
uBus40
=
differential output voltage on a 40Ω || 100pF load, while
driving “Data_1” to the bus. Value based on simulation.
TLE9222_SIMULATION_V00
Figure 20
Bus Driver output resistance
Table 11
Simulation Parameters 1)
Parameter
Symbol
Values
Unit Note / Test Condition
Min.
Typ.
Max.
Bus interface simulation resistor
RBDTransmitter
30
100
500
Ω
–
RxD signal difference of rise and
fall time at TP4_CC
–
–
–
5
ns
–
1) Simulated value for reference purposes only.
Data Sheet
37
Rev. 1.0 2015-06-12
TLE9222
Application Information
7.3
Application Example
VBAT
3.3 V
VI
22μF
100nF
VDD
VQ
10μF
TLE42xx
100nF
GND
Application
MicroController
5V
BM BP
100nF
E.g. TC2xx Aurix MCU
VQ
VI
22μF
10μF
TLE42xx
GND
GND
1
100nF
TxD
VIO
TxEN
TLE9222
14
VCC
RxD
BGE
100nF
STBN
Bus Termination
SCLK
13
BP
12
SDO
BM
SCSN
Optional Common
Mode Choke
GND
ERRN
2
3
4
5
6
7
8
9
10
11
ECU
TLE9222_APPLICATION_EXAMPLE_V00
Figure 21
Data Sheet
Simplified Application example
38
Rev. 1.0 2015-06-12
TLE9222
Application Information
7.4
Implementation of ECU Functional Safety concepts
The TLE9222 has been implemented with features for alleviating the development of functional safety
requirements on a system level. The top level objective is to ensure a malfunctioning ECU is put in a safe state,
which for the FlexRay transceiver means no bus disturbance.
This is realized by the Bus Guardian interface, which controls the bus transmitter directly at the driver stages.
The TLE9222 is also implemented with a redundant diagnostic path for detecting the true state of the bus
transmitter. This status is multiplexed back to the ERRN output, which is set “low” when the transmitter is
reliably disabled. By taking advantage of this safety feature, the ECU diagnostic coverage can be increased.
VBAT
VS1
SW1
FB
SCSN
TLF35584
SDI
SCLK
SDO
Multi Voltage Safety
Micro Processor Supply
3
Application
MicroController
SS1
QUC
1
QCO
E.g. TC2xx Aurix MCU
BM BP
SDO
SCLK
VCC
BGE
VDD
SCSN
VIO
TLE9222PX
STBN
ERRN
BP
2
FlexRay
Transceiver
TxD
BM
TxEN
RxD
GND
ECU
TLE9222_APPLICATION_SAFETY_V01
Figure 22
Application diagram
In Figure 22 an application example of an Automotive ECU for safety critical applications is shown. Together
with a Safety MCU Supply IC, e.g. the Infineon TLF35584, that incorporates safe state control functionality, the
BGE input of the TLE9222 is connected to the safe state output. If the Safety Supply IC detects unexpected
behavior at the supply voltages or incorrect MCU behavior through the functional watchdog, the TLE9222
Data Sheet
39
Rev. 1.0 2015-06-12
TLE9222
Application Information
makes sure there is no influence to the FlexRay bus after the BGE input is set “low”. Additionally, the
microcontroller can detect the true state of the transceiver output drivers from the ERRN out, which should
trigger a SPI readout of the status register. By observing the BGE flag being set “low”, the MCU has verified that
the TLE9222 has been safely disconnected from the bus by the Safety Supply IC.
It is recommended to follow these steps for the ECU software implementation. After ECU power-up, the MCU
should test and verify the correct behavior of the fail safe state as a part of its initialization routine, before
releasing the transceiver for bus access and transmission.
7.5
Minimizing ECU current consumption through BD_Standby mode
The very low current consumption of iVCC_Stb_85 and iVCC_Stb_150 of the TLE9222 can only be reached with the
correct system implementation and software control. While operating in ECU low power mode with the
TLE9222 in BD_Standby mode, the logic inputs should be in their default states (See Table 2). This prevents
current to flow through the implemented pull-up / pull-down circuits. Secondly, the logic outputs, RxD and
ERRN, should be in their default condition “high” for BD_Standby mode (See Table 4). After the TLE9222 is set
to BD_Standby mode, it is recommended to perform a SPI readout for verifying correct state transition and to
clear pending diagnosis flags.
A MCU in low-power mode should continuously (by interrupt) or periodically (by polling) monitor the ERRN
output for wake-up information. Even if the wake-up function is not being used, the MCU should clear the flags
of the status register by SPI readout. For simpler ECU implementations, not using the SPI interface, a mode
change cycle to BD_Normal mode and back to BD_Standby mode again has the same effect.
7.6
Further Application Information
•
Please contact us for information regarding the pin FMEA
•
For further information you may contact http://www.infineon.com/
Data Sheet
40
Rev. 1.0 2015-06-12
TLE9222
Package Outlines
8
Package Outlines
Figure 23
PG-TSSOP-14 (PG-TSSOP-14-1)
Green Product (RoHS compliant)
To meet the world-wide customer requirements for environmentally friendly products and to be compliant
with government regulations the device is available as a green product. Green products are RoHS-Compliant
(i.e Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020).
For further information on alternative packages, please visit our website:
http://www.infineon.com/packages.
Data Sheet
41
Dimensions in mm
Rev. 1.0 2015-06-12
TLE9222
Revision History
9
Revision History
Revision
Date
Changes
1.0
2015-06-12
Initial release
Data Sheet
42
Rev. 1.0 2015-06-12
Trademarks of Infineon Technologies AG
AURIX™, C166™, CanPAK™, CIPOS™, CIPURSE™, CoolMOS™, CoolSET™, CORECONTROL™, CROSSAVE™, DAVE™, DI-POL™, EasyPIM™, EconoBRIDGE™,
EconoDUAL™, EconoPIM™, EconoPACK™, EiceDRIVER™, eupec™, FCOS™, HITFET™, HybridPACK™, I2RF™, ISOFACE™, IsoPACK™, LITIX™, MIPAQ™,
ModSTACK™, my-d™, NovalithIC™, OptiMOS™, ORIGA™, POWERCODE™, PRIMARION™, PrimePACK™, PrimeSTACK™, PRO-SIL™, PROFET™, RASIC™,
ReverSave™, SatRIC™, SIEGET™, SINDRION™, SIPMOS™, SmartLEWIS™, SPOC™, SOLID FLASH™, TEMPFET™, thinQ!™, TRENCHSTOP™, TriCore™.
Other Trademarks
Advance Design System™ (ADS) of Agilent Technologies, AMBA™, ARM™, MULTI-ICE™, KEIL™, PRIMECELL™, REALVIEW™, THUMB™, µVision™ of ARM Limited,
UK. AUTOSAR™ is licensed by AUTOSAR development partnership. Bluetooth™ of Bluetooth SIG Inc. CAT-iq™ of DECT Forum. COLOSSUS™, FirstGPS™ of
Trimble Navigation Ltd. EMV™ of EMVCo, LLC (Visa Holdings Inc.). EPCOS™ of Epcos AG. FLEXGO™ of Microsoft Corporation. FlexRay™ is licensed by FlexRay
Consortium. HYPERTERMINAL™ of Hilgraeve Incorporated. IEC™ of Commission Electrotechnique Internationale. IrDA™ of Infrared Data Association
Corporation. ISO™ of INTERNATIONAL ORGANIZATION FOR STANDARDIZATION. MATLAB™ of MathWorks, Inc. MAXIM™ of Maxim Integrated Products, Inc.
MICROTEC™, NUCLEUS™ of Mentor Graphics Corporation. MIPI™ of MIPI Alliance, Inc. MIPS™ of MIPS Technologies, Inc., USA. muRata™ of MURATA
MANUFACTURING CO., MICROWAVE OFFICE™ (MWO) of Applied Wave Research Inc., OmniVision™ of OmniVision Technologies, Inc. Openwave™ Openwave
Systems Inc. RED HAT™ Red Hat, Inc. RFMD™ RF Micro Devices, Inc. SIRIUS™ of Sirius Satellite Radio Inc. SOLARIS™ of Sun Microsystems, Inc. SPANSION™ of
Spansion LLC Ltd. Symbian™ of Symbian Software Limited. TAIYO YUDEN™ of Taiyo Yuden Co. TEAKLITE™ of CEVA, Inc. TEKTRONIX™ of Tektronix Inc.
TOKO™ of TOKO KABUSHIKI KAISHA TA. UNIX™ of X/Open Company Limited. VERILOG™, PALLADIUM™ of Cadence Design Systems, Inc. VLYNQ™ of Texas
Instruments Incorporated. VXWORKS™, WIND RIVER™ of WIND RIVER SYSTEMS, INC. ZETEX™ of Diodes Zetex Limited.
Last Trademarks Update 2011-11-11
www.infineon.com
Edition 2015-06-12
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2014 Infineon Technologies AG.
All Rights Reserved.
Do you have a question about any
aspect of this document?
Email: [email protected]
Document reference
TLE9222_Datasheet_rev_1.0
Legal Disclaimer
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conditions or characteristics. With respect to any
examples or hints given herein, any typical
values stated herein and/or any information
regarding the application of the device, Infineon
Technologies hereby disclaims any and all
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