Dual, 3 V, CMOS, LVDS High Speed Differential Driver ADN4663 ±15 kV ESD protection on output pins 600 Mbps (300 MHz) switching rates Flow-through pinout simplifies PCB layout 300 ps typical differential skew 700 ps maximum differential skew 1.5 ns maximum propagation delay 3.3 V power supply ±355 mV differential signaling Low power dissipation: 23 mW typical Interoperable with existing 5 V LVDS receivers Conforms to TIA/EIA-644 LVDS standard Industrial operating temperature range (−40°C to +85°C) Available in surface-mount (SOIC) package FUNCTIONAL BLOCK DIAGRAM VCC ADN4663 DOUT1+ DIN1 DOUT1– DOUT2+ DIN2 DOUT2– GND 07927-001 FEATURES Figure 1. APPLICATIONS Backplane data transmission Cable data transmission Clock distribution GENERAL DESCRIPTION The ADN4663 is a dual, CMOS, low voltage differential signaling (LVDS) line driver offering data rates of over 600 Mbps (300 MHz), and ultralow power consumption. It features a flow-through pinout for easy PCB layout and separation of input and output signals. The device accepts low voltage TTL/CMOS logic signals and converts them to a differential current output of typically ±3.1 mA for driving a transmission medium such as a twisted-pair cable. The transmitted signal develops a differential voltage of typically ±355 mV across a termination resistor at the receiving end, and this is converted back to a TTL/CMOS logic level by a line receiver. The ADN4663 and a companion receiver offer a new solution to high speed point-to-point data transmission, and a low power alternative to emitter-coupled logic (ECL) or positive emitter-coupled logic (PECL). Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2009 Analog Devices, Inc. All rights reserved. ADN4663 TABLE OF CONTENTS Features .............................................................................................. 1 ESD Caution...................................................................................6 Applications ....................................................................................... 1 Pin Configuration and Function Descriptions..............................7 Functional Block Diagram .............................................................. 1 Typical Performance Characteristics ..............................................8 General Description ......................................................................... 1 Theory of Operation ...................................................................... 11 Revision History ............................................................................... 2 Applications Information .......................................................... 11 Specifications..................................................................................... 3 Outline Dimensions ....................................................................... 12 AC Characteristics........................................................................ 4 Ordering Guide .......................................................................... 12 Absolute Maximum Ratings............................................................ 6 REVISION HISTORY 1/09—Revision 0: Initial Version Rev. 0 | Page 2 of 12 ADN4663 SPECIFICATIONS VCC = 3.0 V to 3.6 V; RL = 100 Ω; CL = 15 pF to GND; all specifications TMIN to TMAX, unless otherwise noted. Table 1. Parameter 1, 2 LVDS OUTPUTS (DOUTx+, DOUTx−) Differential Output Voltage Change in Magnitude of VOD for Complementary Output States Offset Voltage Change in Magnitude of VOS for Complementary Output States Output High Voltage Output Low Voltage INPUTS (DIN1, DIN2) Input High Voltage Input Low Voltage Input High Current Input Low Current Input Clamp Voltage LVDS OUTPUT PROTECTION (DOUTx+, DOUTx−) Output Short-Circuit Current 3 LVDS OUTPUT LEAKAGE (DOUTx+, DOUTx−) Power-Off Leakage POWER SUPPLY Supply Current, Unloaded Supply Current, Loaded ESD PROTECTION DOUTx+, DOUTx− Pins All Pins Except DOUTx+, DOUTx− Symbol Min Typ Max Unit Test Conditions VOD ΔVOD 250 355 1 450 35 mV |mV| See Figure 2 and Figure 4 See Figure 2 and Figure 4 VOS ΔVOS 1.125 1.2 3 1.375 25 V |mV| See Figure 2 and Figure 4 See Figure 2 and Figure 4 1.4 1.1 1.6 V V See Figure 2 and Figure 4 See Figure 2 and Figure 4 VCC 0.8 +10 +10 V V μA μA V VIN = 3.3 V or 2.4 V VIN = GND or 0.5 V ICL = −18 mA −5.7 −8.0 mA DINx = VCC, DOUTx+ = 0 V or DINx = GND, DOUTx− = 0 V ±1 +10 μA VOUT = VCC or GND, VCC = 0 V 8 10 14 20 mA mA No load, DINx = VCC or GND DINx = VCC or GND kV kV Human body model Human body model VOH VOL 0.90 VIH VIL IIH IIL VCL 2.0 GND −10 −10 −1.5 IOS IOFF ICC ICCL −10 ±2 ±1 −0.6 ±15 ±4 1 Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground except VOD, ΔVOD, and ΔVOS. The ADN4663 is a current mode device and functions within data sheet specifications only when a resistive load is applied to the driver outputs. Typical range is 90 Ω to 110 Ω. 3 Output short-circuit current (IOS) is specified as magnitude only; minus sign indicates direction only. 2 Rev. 0 | Page 3 of 12 ADN4663 AC CHARACTERISTICS VCC = 3.0 V to 3.6 V; RL = 100 Ω; CL 1 = 15 pF to GND; all specifications TMIN to TMAX, unless otherwise noted. Table 2. Parameter 2 Differential Propagation Delay High to Low Differential Propagation Delay Low to High Differential Pulse Skew |tPHLD − tPLHD| 5 Channel-to-Channel Skew 6 Differential Part-to-Part Skew 7 Differential Part-to-Part Skew 8 Rise Time Fall Time Maximum Operating Frequency 9 Symbol tPHLD tPLHD tSKD1 tSKD2 tSKD3 tSKD4 tTLH tTHL fMAX Min 0.3 0.3 0 0 0 0 0.2 0.2 Typ 0.8 1.1 0.3 0.4 0.5 0.5 350 1 Max 1.5 1.5 0.7 0.8 1.0 1.2 1.0 1.0 Unit ns ns ns ns ns ns ns ns MHz Conditions/Comments 3, 4 See Figure 3 and Figure 4 See Figure 3 and Figure 4 See Figure 3 and Figure 4 See Figure 3 and Figure 4 See Figure 3 and Figure 4 See Figure 3 and Figure 4 See Figure 3 and Figure 4 See Figure 3 and Figure 4 See Figure 3 CL includes probe and jig capacitance. AC parameters are guaranteed by design and characterization. Generator waveform for all tests, unless otherwise specified: f = 50 MHz, ZO = 50 Ω, tTLH ≤ 1 ns, and tTHL ≤ 1 ns. 4 All input voltages are for one channel, unless otherwise specified. Other inputs are set to GND. 5 tSKD1 = |tPHLD − tPLHD| is the magnitude difference in differential propagation delay time between the positive going edge and the negative going edge of the same channel. 6 tSKD2 is the differential channel-to-channel skew of any event on the same device. 7 tSKD3, differential part-to-part skew, is defined as the difference between the minimum and maximum specified differential propagation delays. This specification applies to devices at the same VCC and within 5°C of each other within the operating temperature range. 8 tSKD4, differential part-to-part skew, is the differential channel-to-channel skew of any event between devices. This specification applies to devices over recommended operating temperatures and voltage ranges, and across process distribution. tSKD4 is defined as |maximum − minimum| differential propagation delay. 9 fMAX generator input conditions: tTLH = tTHL < 1 ns (0% to 100%), 50% duty cycle, 0 V to 3 V. Output criteria: duty cycle = 45% to 55%, VOD > 250 mV, all channels switching. 2 3 Rev. 0 | Page 4 of 12 ADN4663 Test Circuits and Timing Diagrams DOUTx+ VCC VCC RL/2 RL/2 V VOS V VOD 07927-002 DINx DOUTx– Figure 2. Test Circuit for Driver VOD and VOS DOUTx+ VCC CL SIGNAL GENERATOR DINx RL DOUTx– 50Ω 07927-003 CL CL INCLUDES LOAD AND TEST JIG CAPACITANCE. Figure 3. Test Circuit for Driver Propagation Delay, Transition Time, and Maximum Operating Frequency 3V DINx 1.5V 1.5V 0V tPHLD tPLHD VOH DOUTx– 0V (DIFFERENTIAL) VOD 0V DOUTx+ VOL 80% 0V 0V VDIFF = DOUT+ – DOUT– 20% 20% tTHL tTHL Figure 4. Driver Propagation Delay and Transition Time Waveforms Rev. 0 | Page 5 of 12 07927-004 VDIFF 80% ADN4663 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. All voltages are relative to their respective ground. Table 3. Parameter VCC to GND Input Voltage (DINx) to GND Output Voltage (DOUTx+, DOUTx−) to GND Short-Circuit Duration (DOUTx+, DOUTx−) to GND Operating Temperature Range Industrial Storage Temperature Range Junction Temperature (TJ max) Power Dissipation SOIC Package θJA Thermal Impedance Reflow Soldering Peak Temperature Pb-Free Rating −0.3 V to +4 V −0.3 V to VCC + 0.3 V −0.3 V to VCC + 0.3 V Continuous Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION −40°C to +85°C −65°C to +150°C 150°C (TJ max − TA)/θJA 149.5°C/W 260°C ± 5°C Rev. 0 | Page 6 of 12 ADN4663 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 ADN4663 7 3 TOP VIEW (Not to Scale) DOUT1+ DIN2 6 DOUT2+ GND 4 5 DOUT2– 8 07927-005 DOUT1– VCC DIN1 Figure 5. Pin Configuration Table 4. Pin Function Descriptions Pin No. 1 Mnemonic VCC 2 3 4 5 DIN1 DIN2 GND DOUT2− 6 DOUT2+ 7 DOUT1+ 8 DOUT1− Description Power Supply Input. The part can be operated from 3.0 V to 3.6 V, and the supply should be decoupled with a 10 μF solid tantalum capacitor in parallel with a 0.1 μF capacitor to GND. Driver Channel 1 Logic Input. Driver Channel 2 Logic Input. Ground reference point for all circuitry on the part. Channel 2 Inverting Output Current Driver. When DIN2 is high, current flows into DOUT2−. When DIN2 is low, current flows out of DOUT2−. Channel 2 Noninverting Output Current Driver. When DIN2 is high, current flows out of DOUT2+. When DIN2 is low, current flows into DOUT2+. Channel 1 Noninverting Output Current Driver. When DIN1 is high, current flows out of DOUT1+. When DIN1 is low, current flows into DOUT1+. Channel 1 Inverting Output Current Driver. When DIN1 is high, current flows into DOUT1−. When DIN1 is low, current flows out of DOUT1−. Rev. 0 | Page 7 of 12 ADN4663 TYPICAL PERFORMANCE CHARACTERISTICS 325.0 1.414 1.413 3.2 3.3 3.4 3.5 3.6 POWER SUPPLY VOLTAGE, VCC (V) DIFFERENTIAL OUTPUT VOLTAGE, VOD (mV) 3.3 3.4 3.5 3.6 POWER SUPPLY VOLTAGE, VCC (V) OFFSET VOLTAGE, VOS (mV) –4.1 3.5 3.6 POWER SUPPLY VOLTAGE, VCC (V) 07927-008 SHORT-CIRCUIT CURRENT, I OS (mA) –4.0 3.4 3.6 400 350 300 90 1.252 3.3 3.5 TA = 25°C VCC = 3.3V TA = 25°C VIN = GND OR VCC VOUT = 0V 3.2 3.4 100 110 120 130 140 150 3.6 Figure 10. Differential Output Voltage vs. Load Resistor –3.9 3.1 3.3 LOAD RESISTOR, RL (Ω) Figure 7. Output Low Voltage vs. Power Supply Voltage –4.2 3.0 3.2 450 250 07927-007 OUTPUT LOW VOLTAGE, VOL (V) 1.088 3.2 3.1 POWER SUPPLY VOLTAGE, VCC (V) 500 1.089 3.1 324.2 Figure 9. Differential Output Voltage vs. Power Supply Voltage TA = 25°C RL = 100Ω 1.087 3.0 324.4 324.0 3.0 Figure 6. Output High Voltage vs. Power Supply Voltage 1.090 324.6 07927-010 3.1 324.8 07927-011 1.412 3.0 TA = 25°C RL = 100Ω 07927-009 DIFFERENTIAL OUTPUT VOLTAGE, VOD (mV) TA = 25°C RL = 100Ω 07927-006 OUTPUT HIGH VOLTAGE, VOH (V) 1.415 Figure 8. Output Short-Circuit Current vs. Power Supply Voltage TA = 25°C RL = 100Ω 1.251 1.250 1.249 3.0 3.1 3.2 3.3 3.4 3.5 POWER SUPPLY VOLTAGE, VCC (V) Figure 11. Offset Voltage vs. Power Supply Voltage Rev. 0 | Page 8 of 12 ADN4663 13 ONE CHANNEL SWITCHING 9 7 5 0.01 0.1 1 10 100 1k SWITCHING FREQUENCY (MHz) 1200 DIFFERENTIAL PROPAGATION DELAY (ns) 11.5 11.0 10.5 3.1 3.2 3.3 3.4 3.5 3.6 POWER SUPPLY VOLTAGE, VCC (V) DIFFERENTIAL SKEW, tSKD1 (ps) 12 11 10 35 60 TEMPERATURE (°C) 3.5 3.6 tPLHD 1100 tPHLD 1000 100 VCC = 3.3V f = 1MHz CL = 15pF VIN = 0V TO 3V RL = 100Ω PER DRIVER –15 3.4 –20 0 20 40 60 80 100 Figure 16. Differential Propagation Delay vs. Ambient Temperature 13 10 –40 3.3 AMBIENT TEMPERATURE, TA (°C) 85 07927-014 POWER SUPPLY CURRENT, ICC (mA) 14 3.2 VCC = 3.3V f = 1MHz CL = 15pF RL = 100Ω PER DRIVER 900 –40 Figure 13. Power Supply Current vs. Power Supply Voltage 15 3.1 Figure 15. Differential Propagation Delay vs. Power Supply Voltage TA = 25°C f = 1MHz CL = 15pF VIN = 0V TO 3.3V RL = 100Ω PER DRIVER 10.0 3.0 1000 POWER SUPPLY VOLTAGE, VCC (V) 07927-013 POWER SUPPLY CURRENT, ICC (mA) 12.0 tPLHD 900 3.0 Figure 12. Power Supply Current vs. Switching Frequency 12.5 tPHLD 07927-016 11 1100 07927-015 BOTH CHANNELS SWITCHING TA = 25°C f = 1MHz CL = 15pF RL = 100Ω PER DRIVER Figure 14. Power Supply Current vs. Ambient Temperature 80 TA = 25°C f = 1MHz CL = 15pF RL = 100Ω PER DRIVER 60 40 20 0 3.0 3.1 3.2 3.3 3.4 3.5 POWER SUPPLY VOLTAGE, VCC (V) Figure 17. Differential Skew vs. Power Supply Voltage Rev. 0 | Page 9 of 12 3.6 07927-017 15 DIFFERENTIAL PROPAGATION DELAY (ns) 17 1200 TA = 25°C CL = 15pF VCC = 3.3V VIN = 0V TO 3.3V RL = 100Ω PER DRIVER 07927-012 POWER SUPPLY CURRENT, ICC (mA) 19 ADN4663 TRANSITION TIME (ps) 30 20 380 tTLH 360 tTHL 340 10 0 –40 –20 0 20 40 60 80 100 AMBIENT TEMPERATURE, TA (°C) Figure 18. Differential Skew vs. Ambient Temperature 400 TA = 25°C f = 1MHz CL = 15pF RL = 100Ω PER DRIVER 380 tTLH 360 tTHL 340 320 3.0 3.1 3.2 3.3 3.4 3.5 POWER SUPPLY VOLTAGE, VCC (V) 320 –40 –20 0 20 40 60 80 AMBIENT TEMPERATURE, TA (°C) Figure 20. Transition Time vs. Ambient Temperature 3.6 07927-019 TRANSITION TIME (ps) VCC = 3.3V f = 1MHz CL = 15pF RL = 100Ω PER DRIVER Figure 19. Transition Time vs. Power Supply Voltage Rev. 0 | Page 10 of 12 100 07927-020 40 400 VCC = 3.3V f = 1MHz CL = 15pF RL = 100Ω PER DRIVER 07927-018 DIFFERENTIAL SKEW, tSKD1 (ps) 50 ADN4663 THEORY OF OPERATION When DINx is high (Logic 1), current flows out of the DOUTx+ pin (current source) through RT and back into the DOUTx− pin (current sink). At the receiver, this current develops a positive differential voltage across RT (with respect to the inverting input) and results in a Logic 1 at the receiver output. When DINx is low, DOUTx+ sinks current and DOUTx− sources current; a negative differential voltage across RT results in a Logic 0 at the receiver output. The output drive current is between ±2.5 mA and ±4.5 mA (typically ±3.55 mA), developing between ±250 mV and ±450 mV across a 100 Ω termination resistor. The received voltage is centered around the receiver offset of 1.2 V. Therefore, the noninverting receiver input is typically (1.2 V + [355 mV/2]) = 1.377 V, and the inverting receiver input is (1.2 V − [355 mV/2]) = 1.023 V for Logic 1. For Logic 0, the inverting and noninverting output voltages are reversed. Note that because the differential voltage reverses polarity, the peak-to-peak voltage swing across RT is twice the differential voltage. A current mode device simply reverses a constant current between its two outputs, with no significant overlap currents. This is similar to emitter-coupled logic (ECL) and positive emitter-coupled logic (PECL), but without the high quiescent current of ECL and PECL. APPLICATIONS INFORMATION Figure 21 shows a typical application for point-to-point data transmission using the ADN4663 as the driver and a LVDS receiver. +3.3V + 10µF TANTALUM 0.1µF + VCC VCC ADN4663 Rev. 0 | Page 11 of 12 DOUTx+ RT 100Ω DINx Current mode drivers offer considerable advantages over voltage mode drivers such as RS-422 drivers. The operating current remains fairly constant with increased switching frequency, whereas that of voltage mode drivers increase exponentially in most cases. This is caused by the overlap as internal gates switch between high and low, which causes currents to flow from the device power supply to ground. +3.3V DOUTx– GND DIN+ LVDS RECEIVER DOUT DIN– GND Figure 21. Typical Application Circuit 07927-021 The ADN4663 is a dual line driver for low voltage differential signaling. It takes a single-ended 3 V logic signal and converts it to a differential current output. The data can then be transmitted for considerable distances, over media such as a twisted-pair cable or PCB backplane, to an LVDS receiver, where it develops a voltage across a terminating resistor, RT. This resistor is chosen to match the characteristic impedance of the medium, typically around 100 Ω. The differential voltage is detected by the receiver and converted back into a single-ended logic signal. ADN4663 OUTLINE DIMENSIONS 5.00 (0.1968) 4.80 (0.1890) 1 5 6.20 (0.2441) 5.80 (0.2284) 4 1.27 (0.0500) BSC 0.25 (0.0098) 0.10 (0.0040) COPLANARITY 0.10 SEATING PLANE 0.50 (0.0196) 0.25 (0.0099) 1.75 (0.0688) 1.35 (0.0532) 0.51 (0.0201) 0.31 (0.0122) 45° 8° 0° 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.0157) COMPLIANT TO JEDEC STANDARDS MS-012-A A CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. 012407-A 8 4.00 (0.1574) 3.80 (0.1497) Figure 22. 8-Lead Standard Small Outline Package [SOIC(N)] (R-8) Dimensions shown in millimeters and (inches) ORDERING GUIDE Model ADN4663BRZ 1 ADN4663BRZ-REEL71 1 Temperature Range −40°C to +85°C −40°C to +85°C Package Description 8-Lead Standard Small Outline Package [SOIC-N] 8-Lead Standard Small Outline Package [SOIC-N] Z = RoHS Compliant Part. ©2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07927-0-1/09(0) Rev. 0 | Page 12 of 12 Package Option R-8 R-8