ADSP-BF548 EZ-KIT Lite® Evaluation System Manual Revision 1.4, July 2012 Part Number 82-000206-01 Analog Devices, Inc. One Technology Way Norwood, Mass. 02062-9106 a Copyright Information © 2012 Analog Devices, Inc., ALL RIGHTS RESERVED. This document may not be reproduced in any form without prior, express written consent from Analog Devices, Inc. Printed in the USA. Disclaimer Analog Devices, Inc. reserves the right to change this product without prior notice. Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use; nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under the patent rights of Analog Devices, Inc. Trademark and Service Mark Notice The Analog Devices logo, Blackfin, CrossCore, EngineerZone, EZ-Extender, EZ-KIT Lite, Lockbox, and VisualDSP++ are registered trademarks of Analog Devices, Inc. All other brand and product names are trademarks or service marks of their respective owners. Regulatory Compliance The ADSP-BF548 EZ-KIT Lite is designed to be used solely in a laboratory environment. The board is not intended for use as a consumer end product or as a portion of a consumer end product. The board is an open system design which does not include a shielded enclosure and therefore may cause interference to other electrical devices in close proximity. This board should not be used in or near any medical equipment or RF devices. The ADSP-BF548 EZ-KIT Lite has been certified to comply with the essential requirements of the European EMC directive 2004/108/EC and therefore carries the “CE” mark. The ADSP-BF548 EZ-KIT Lite has been appended to Analog Devices, Inc. EMC Technical File (EMC TF) referenced DSPTOOLS1, issue 2 dated June 4, 2008 and was declared CE compliant by an appointed Notified Body (No.0673) as listed below. Notified Body Statement of Compliance: NB600ANA2.ABS dated June 4, 2008. Issued by: Technology International (Europe) Limited 60 Shrivenham Hundred Business Park Shrivenham, Swindon, SN6 8TY, UK The EZ-KIT Lite evaluation system contains ESD (electrostatic discharge) sensitive devices. Electrostatic charges readily accumulate on the human body and equipment and can discharge without detection. Permanent damage may occur on devices subjected to high-energy discharges. Proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Store unused EZ-KIT Lite boards in the protective shipping package. CONTENTS PREFACE Product Overview ....................................................................... xiii Purpose of This Manual ................................................................ xv Intended Audience ....................................................................... xvi Manual Contents ......................................................................... xvi What’s New in This Manual ........................................................ xvii Technical Support ....................................................................... xvii Supported Processors .................................................................. xviii Product Information .................................................................... xix Analog Devices Web Site ........................................................ xix EngineerZone .......................................................................... xx Related Documents ....................................................................... xx Notation Conventions .................................................................. xxi USING THE ADSP-BF548 EZ-KIT LITE Package Contents .......................................................................... 1-3 Default Configuration ................................................................... 1-4 CCES Install and Session Startup .................................................. 1-5 Session Startup ........................................................................ 1-6 ADSP-BF548 EZ-KIT Lite Evaluation System Manual v Contents VisualDSP++ Install and Session Startup ....................................... 1-9 CCES Evaluation License ........................................................... 1-11 VisualDSP++ Evaluation License ................................................. 1-11 Lockbox Key Security Features .................................................... 1-12 Memory Map ............................................................................. 1-13 DDR Interface ........................................................................... 1-15 Burst Flash Memory Interface ..................................................... 1-17 NAND Flash Interface ................................................................ 1-18 SPI Interface .............................................................................. 1-18 SD Interface ............................................................................... 1-19 EPPI Interface ............................................................................ 1-20 LCD Module Interface ............................................................... 1-21 Touchscreen Interface ................................................................. 1-22 Keypad Interface ......................................................................... 1-23 Rotary Encoder Interface ............................................................ 1-24 Ethernet Interface ....................................................................... 1-24 Audio Interface ........................................................................... 1-25 ATAPI Interface .......................................................................... 1-26 USB OTG Interface .................................................................... 1-27 UART Interface .......................................................................... 1-27 CAN Interface ............................................................................ 1-28 Host Interface ............................................................................ 1-29 RTC Interface ............................................................................ 1-30 LEDs and Push Buttons .............................................................. 1-31 vi ADSP-BF548 EZ-KIT Lite Evaluation System Manual Contents JTAG Interface ........................................................................... 1-31 Expansion Interface ..................................................................... 1-32 Power Measurements ................................................................... 1-33 Board Design Database ............................................................... 1-33 Power-On-Self Test ..................................................................... 1-33 Example Programs ...................................................................... 1-34 ADSP-BF548 EZ-KIT LITE HARDWARE REFERENCE System Architecture ...................................................................... 2-2 Programmable Flags ...................................................................... 2-3 Push Button and Switch Settings ................................................. 2-15 Boot Mode Select Switch (SW1) ............................................ 2-15 Keypad Enable Switch (SW2) ................................................ 2-16 Rotary Encoder with Momentary Switch (SW3) ..................... 2-17 Rotary Encoder Enable Switch (SW4) .................................... 2-17 Push Button Enable Switch (SW5) ......................................... 2-18 CAN0 Enable Switch (SW6) .................................................. 2-18 UART Enable Switch (SW7) .................................................. 2-19 Audio Loopback Test Switch (SW8) ....................................... 2-19 Reset Push Button (SW9) ...................................................... 2-20 Programmable Flag Push Buttons (SW10–13) ........................ 2-20 LCD/PPI Configuration Switch (SW14) ................................ 2-21 CAN1 Enable Switch (SW15) ................................................ 2-22 Peripheral Control Enable (SW16) ......................................... 2-22 LCD Module Configuration (SW17) ..................................... 2-23 ADSP-BF548 EZ-KIT Lite Evaluation System Manual vii Contents Jumpers ...................................................................................... 2-25 UART1 Loopback Jumper (JP1) ............................................ 2-26 SPI1 Enable Jumper (JP2) ..................................................... 2-26 Ethernet Speed Select Jumper (JP3) ....................................... 2-27 VDDINT Power Jumper (JP4) .............................................. 2-27 VDDEXT Power Jumper (JP5) .............................................. 2-28 VDDDDR Power Jumper (JP6) ............................................ 2-28 MOSI1 Out Jumper (JP7) ..................................................... 2-29 MOSI1 In Jumper (JP8) ........................................................ 2-29 USB OTG Power Jumper (JP11) ........................................... 2-30 PPI1FS3 Pull-down Jumper (JP12) ........................................ 2-30 LEDs ......................................................................................... 2-31 User LEDs (LED1–6) ........................................................... 2-31 Power LED (LED7) .............................................................. 2-32 Reset LED (LED8) ............................................................... 2-32 Ethernet Link/Activity LED (LED9) ..................................... 2-32 Connectors ................................................................................. 2-33 Expansion Interface Connectors (J1–3) .................................. 2-34 Ethernet Connector (J4) ....................................................... 2-34 SD Memory Card Connector (J5) ......................................... 2-35 RS-232 Connector (J6) ......................................................... 2-35 Power Connector (J7) ........................................................... 2-35 Dual Audio Connectors (J8 and J9) ....................................... 2-36 Audio Connector (J10) ......................................................... 2-36 viii ADSP-BF548 EZ-KIT Lite Evaluation System Manual Contents CAN Connectors (J11 and J12) ............................................. 2-36 Battery Holder (J13) ............................................................. 2-37 ATAPI Connector (J14) ......................................................... 2-37 Keypad Connector (P1) ......................................................... 2-37 Host Interface Connector (P3) ............................................... 2-38 USB OTG Connector (P4) .................................................... 2-38 LCD Backlight Connector (P5) ............................................. 2-38 SPORT2 Connector (P6) ....................................................... 2-39 SPORT3 Connector (P7) ....................................................... 2-39 PPI1 Connector (P8) ............................................................. 2-39 SPI Connector (P9) ............................................................... 2-40 Two-Wire Interface Connector (P10) ..................................... 2-40 TIMERS Connector (P11) .................................................... 2-40 UART3 Connector (P12) ...................................................... 2-41 LCD Touchscreen Connector (P14) ....................................... 2-41 LCD Data Connector (P15) .................................................. 2-41 USB Debug Agent Connector (ZJ1) ....................................... 2-42 JTAG Connector (ZP4) ......................................................... 2-42 ADSP-BF548 EZ-KIT LITE BILL OF MATERIALS ADSP-BF548 EZ-KIT LITE SCHEMATIC INDEX ADSP-BF548 EZ-KIT Lite Evaluation System Manual ix Contents x ADSP-BF548 EZ-KIT Lite Evaluation System Manual PREFACE Thank you for purchasing the ADSP-BF548 EZ-KIT Lite®, Analog Devices, Inc. evaluation system for Blackfin® processors. Blackfin processors embody a type of embedded processor designed specifically to meet the computational demands and power constraints of today’s embedded audio, video, and communications applications. They deliver breakthrough signal-processing performance and power efficiency within a reduced instruction set computing (RISC) programming model. Blackfin processors support a media instruction set computing (MISC) architecture. This architecture is the natural merging of RISC, media functions, and digital signal processing (DSP) characteristics. Blackfin processors deliver signal-processing performance in a microprocessor-like environment. Based on the Micro Signal Architecture (MSA), Blackfin processors combine a 32-bit RISC instruction set, dual 16-bit multiply accumulate (MAC) DSP functionality, and eight-bit video processing performance that had previously been the exclusive domain of very-long instruction word (VLIW) media processors. ADSP-BF548 EZ-KIT Lite Evaluation System Manual xi The evaluation board is designed to be used in conjunction with the CrossCore® Embedded Studio (CCES) and VisualDSP++® development environments to test the ADSP-BF548 processor capabilities. The development environment facilitates advanced application code development and debug, such as: • Create, compile, assemble, and link application programs written in C++, C, and ADSP-BF548 assembly • Load, run, step, halt, and set breakpoints in application programs • Read and write data and program memory • Read and write core and peripheral registers • Plot memory Access to the ADSP-BF548 processor from a personal computer (PC) is achieved through a USB port or an optional JTAG emulator. The USB interface gives unrestricted access to the ADSP-BF548 processor and the evaluation board peripherals. Analog Devices JTAG emulators offer faster communication between the host PC and target hardware. Analog Devices carries a wide range of in-circuit emulation products. To learn more about Analog Devices emulators and processor development tools, go to http://www.analog.com/dsp/tools. The ADSP-BF548 EZ-KIT Lite provides example programs to demonstrate the evaluation board capabilities. xii ADSP-BF548 EZ-KIT Lite Evaluation System Manual Preface Product Overview The board features: • Analog Devices ADSP-BF548 Blackfin processor • Core performance up to 600 MHz • External bus performance up to 133 MHz • 400-pin mini-BGA package • 25 MHz crystal • Double data rate (DDR) synchronous dynamic random access memory (SDRAM) • Micron MT46V32M16 – 64 MB (8M x 16-bits x 4 banks) • Burst flash memory • Intel PC28F128P33T85A – 16 MB (8M x 16-bits) • NAND flash memory • ST Micro NAND02 – 2 Gb • SPI flash memory • ST Micro M25P16 – 16 Mb • Advanced technology attachment packet interface (ATAPI) • 80 GB HDD • TFT LCD display with touchscreen • Sharp LQ043T1DG01 – 480 x 272, 4.3” touchscreen LCD • Analog Devices AD7877 – touchscreen controller ADSP-BF548 EZ-KIT Lite Evaluation System Manual xiii Product Overview • Analog audio interface • Analog Devices AD1980 SoundMAX codec • 6 DAC channels for 5.1 surround • 1 input stereo MIC jack • 1 input stereo LINE IN • 1 output stereo LINE jack OUT/ HEAD PHONE OUT jack • 1 output stereo SURROUND jack • 1 output center and LFE jack • Ethernet interface • SMSC LAN9218 device • 10-BaseT and 100-BaseTX Ethernet controller • Integrated PHY and MAC • HP Auto-MDIX • Keypad • ACT components – 4 x 4 keypad assembly • Thumbwheel • CTS Corp rotary encoder • Universal asynchronous receiver/transmitter (UART) • ADM3202 RS-232 line driver/receiver • DB9 female connector xiv ADSP-BF548 EZ-KIT Lite Evaluation System Manual Preface • LEDs • 10 LEDs: 1 power (green), 1 board reset (red), 1 USB (red), 6 general-purpose (amber), and 1 USB monitor (amber) • Push buttons • 5 push buttons: 1 reset, 4 programmable flags with debounce logic • Expansion interface: all ADSP-BF548 processor signals • Other features • JTAG ICE 14-pin header • USB OTG connector • HOST interface connector • Blackfin power measurement jumpers • PPI1 IDC connector • SPORT2 and SPORT3 IDC connectors • TWI, SPI, timers, UART3 IDC connectors For information about the hardware components of the EZ-KIT Lite, refer to Chapter 2, “ADSP-BF548 EZ-KIT Lite Hardware Reference”. Purpose of This Manual The ADSP-BF548 EZ-KIT Lite Evaluation System Manual provides instructions for installing the product hardware (board). The text describes operation and configuration of the board components and provides guidelines for running your own code on the ADSP-BF548 EZ-KIT ADSP-BF548 EZ-KIT Lite Evaluation System Manual xv Intended Audience Lite. Finally, a schematic and a bill of materials are provided as a reference for future designs. VisualDSP++ users should use this manual in conjunction with the Getting Started with ADSP-BF548 EZ-KIT Lite, which familiarizes users with the hardware capabilities of the evaluation system and demonstrates how to access these capabilities in the VisualDSP++ environment. Intended Audience The primary audience for this manual is a programmer who is familiar with Analog Devices processors. This manual assumes that the audience has a working knowledge of the appropriate processor architecture and instruction set. Programmers who are unfamiliar with Analog Devices processors can use this manual but should supplement it with other texts that describe your target architecture. For the locations of these documents, see “Related Documents”. Programmers who are unfamiliar with CCES or VisualDSP++ should refer to the online help and user’s manuals. Manual Contents The manual consists of: • Chapter 1, “Using the ADSP-BF548 EZ-KIT Lite” on page 1-1 Describes EZ-KIT Lite functionality from a programmer’s perspective and provides an easy-to-access memory map. • Chapter 2, “ADSP-BF548 EZ-KIT Lite Hardware Reference” on page 2-1 Provides information on the EZ-KIT Lite hardware components. xvi ADSP-BF548 EZ-KIT Lite Evaluation System Manual Preface • Appendix A, “ADSP-BF548 EZ-KIT Lite Bill Of Materials” on page A-1 Provides a list of components used to manufacture the EZ-KIT Lite board. • Appendix B, “ADSP-BF548 EZ-KIT Lite Schematic” on page B-1 Provides the resources to allow EZ-KIT Lite board-level debugging or to use as a reference design. Appendix B is part of the online help. What’s New in This Manual This is revision 1.4 of the ADSP-BF548 EZ-KIT Lite Evaluation System Manual. The manual has been updated to include CCES information. In addition, modifications and corrections based on errata reports against the previous manual revision have been made. For the latest version of this manual, please refer to the Analog Devices Web site. Technical Support You can reach Analog Devices processors and DSP technical support in the following ways: • Post your questions in the processors and DSP support community at EngineerZone®: http://ez.analog.com/community/dsp • Submit your questions to technical support directly at: http://www.analog.com/support ADSP-BF548 EZ-KIT Lite Evaluation System Manual xvii Supported Processors • E-mail your questions about processors, DSPs, and tools development software from CrossCore Embedded Studio or VisualDSP++: Choose Help > Email Support. This creates an e-mail to [email protected] and automatically attaches your CrossCore Embedded Studio or VisualDSP++ version information and license.dat file. • E-mail your questions about processors and processor applications to: [email protected] or [email protected] (Greater China support) • In the USA only, call 1-800-ANALOGD (1-800-262-5643) • Contact your Analog Devices sales office or authorized distributor. Locate one at: www.analog.com/adi-sales • Send questions by mail to: Processors and DSP Technical Support Analog Devices, Inc. Three Technology Way P.O. Box 9106 Norwood, MA 02062-9106 USA Supported Processors This evaluation system supports Analog Devices ADSP-BF548 Blackfin embedded processors. xviii ADSP-BF548 EZ-KIT Lite Evaluation System Manual Preface Product Information Product information can be obtained from the Analog Devices Web site and the online help system. Analog Devices Web Site The Analog Devices Web site, www.analog.com, provides information about a broad range of products—analog integrated circuits, amplifiers, converters, and digital signal processors. To access a complete technical library for each processor family, go to http://www.analog.com/processors/technical_library. The manuals selection opens a list of current manuals related to the product as well as a link to the previous revisions of the manuals. When locating your manual title, note a possible errata check mark next to the title that leads to the current correction report against the manual. Also note, myAnalog is a free feature of the Analog Devices Web site that allows customization of a Web page to display only the latest information about products you are interested in. You can choose to receive weekly e-mail notifications containing updates to the Web pages that meet your interests, including documentation errata against all manuals. myAnalog provides access to books, application notes, data sheets, code examples, and more. Visit myAnalog (found on the Analog Devices home page) to sign up. If you are a registered user, just log on. Your user name is your e-mail address. ADSP-BF548 EZ-KIT Lite Evaluation System Manual xix Related Documents EngineerZone EngineerZone is a technical support forum from Analog Devices. It allows you direct access to ADI technical support engineers. You can search FAQs and technical information to get quick answers to your embedded processing and DSP design questions. Use EngineerZone to connect with other DSP developers who face similar design challenges. You can also use this open forum to share knowledge and collaborate with the ADI support team and your peers. Visit http://ez.analog.com to sign up. Related Documents For additional information about the product, refer to the following publications. Table 1. Related Processor Publications xx Title Description ADSP-BF542/BF544/BF547/BF548/BF549 Blackfin Embedded Processor Data Sheet General functional description, pinout, and timing of the processor ADSP-BF54x Blackfin Processor Hardware Reference Description of the internal processor architecture and all register functions Blackfin Processor Programming Reference Description of all allowed processor assembly instructions ADSP-BF548 EZ-KIT Lite Evaluation System Manual Preface Notation Conventions Text conventions used in this manual are identified and described as follows. Example Description Close command (File menu) Titles in reference sections indicate the location of an item within the development environment’s menu system (for example, the Close command appears on the File menu). {this | that} Alternative required items in syntax descriptions appear within curly brackets and separated by vertical bars; read the example as this or that. One or the other is required. [this | that] Optional items in syntax descriptions appear within brackets and separated by vertical bars; read the example as an optional this or that. [this,…] Optional item lists in syntax descriptions appear within brackets delimited by commas and terminated with an ellipse; read the example as an optional comma-separated list of this. .SECTION Commands, directives, keywords, and feature names are in text with letter gothic font. filename Non-keyword placeholders appear in text with italic style format. Note: For correct operation, ... A Note provides supplementary information on a related topic. In the online version of this book, the word Note appears instead of this symbol. Caution: Incorrect device operation may result if ... Caution: Device damage may result if ... A Caution identifies conditions or inappropriate usage of the product that could lead to undesirable results or product damage. In the online version of this book, the word Caution appears instead of this symbol. Warning: Injury to device users may result if ... A Warning identifies conditions or inappropriate usage of the product that could lead to conditions that are potentially hazardous for the devices users. In the online version of this book, the word Warning appears instead of this symbol. ADSP-BF548 EZ-KIT Lite Evaluation System Manual xxi Notation Conventions xxii ADSP-BF548 EZ-KIT Lite Evaluation System Manual 1 USING THE ADSP-BF548 EZ-KIT LITE This chapter provides specific information to assist you with development of programs for the ADSP-BF548 EZ-KIT Lite evaluation system. The following topics are covered. • “Package Contents” on page 1-3 • “Default Configuration” on page 1-4 • “CCES Install and Session Startup” on page 1-5 • “VisualDSP++ Install and Session Startup” on page 1-9 • “CCES Evaluation License” on page 1-11 • “VisualDSP++ Evaluation License” on page 1-11 • “Lockbox Key Security Features” on page 1-12 • “Memory Map” on page 1-13 • “DDR Interface” on page 1-15 • “Burst Flash Memory Interface” on page 1-17 • “NAND Flash Interface” on page 1-18 • “SPI Interface” on page 1-18 • “SD Interface” on page 1-19 • “EPPI Interface” on page 1-20 ADSP-BF548 EZ-KIT Lite Evaluation System Manual 1-1 • “LCD Module Interface” on page 1-21 • “Touchscreen Interface” on page 1-22 • “Keypad Interface” on page 1-23 • “Rotary Encoder Interface” on page 1-24 • “Ethernet Interface” on page 1-24 • “Audio Interface” on page 1-25 • “ATAPI Interface” on page 1-26 • “USB OTG Interface” on page 1-27 • “UART Interface” on page 1-27 • “CAN Interface” on page 1-28 • “Host Interface” on page 1-29 • “RTC Interface” on page 1-30 • “LEDs and Push Buttons” on page 1-31 • “JTAG Interface” on page 1-31 • “Expansion Interface” on page 1-32 • “Power Measurements” on page 1-33 • “Board Design Database” on page 1-33 • “Power-On-Self Test” on page 1-33 • “Example Programs” on page 1-34 For information about the graphical user interface, including the boot loading, target options, and other facilities of the EZ-KIT Lite system, refer to the online help. 1-2 ADSP-BF548 EZ-KIT Lite Evaluation System Manual Using the ADSP-BF548 EZ-KIT Lite For more detailed information about the ADSP-BF548 Blackfin processor, see documents referred to at “Related Documents”. Package Contents Your ADSP-BF548 EZ-KIT Lite evaluation system package contains the following items. • ADSP-BF548 EZ-KIT Lite board • Universal 7.5V DC power supply • Secure digital (SD) memory card • USB high-speed flash drive • 7-foot Ethernet crossover cable • 7-foot Ethernet patch cable • Four 6-foot 3.5 mm male-to-male audio cables • 3.5 mm headphones • 10-foot USB A-B male cable for USB Debug Agent • 5-in-1cable and connectors for USB on-the-go (OTG) applications • Ethernet loopback connector • CAN loopback cable If any item is missing, contact the vendor where you purchased your EZ-KIT Lite or contact Analog Devices, Inc. ADSP-BF548 EZ-KIT Lite Evaluation System Manual 1-3 Default Configuration Default Configuration The EZ-KIT Lite evaluation system contains ESD (electrostatic discharge) sensitive devices. Electrostatic charges readily accumulate on the human body and equipment and can discharge without detection. Permanent damage may occur on devices subjected to high-energy discharges. Proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Store unused EZ-KIT Lite boards in the protective shipping package. The ADSP-BF548 EZ-KIT Lite board is designed to run outside your personal computer as a standalone unit. You do not have to open your computer case. When removing the EZ-KIT Lite board from the package, handle the board carefully to avoid the discharge of static electricity, which can damage some components. Figure 1-1 shows the default jumper settings, switches, connector locations, and LEDs used in installation. Confirm that your board is in the default configuration before using the board. Figure 1-1. EZ-KIT Lite Hardware Setup 1-4 ADSP-BF548 EZ-KIT Lite Evaluation System Manual Using the ADSP-BF548 EZ-KIT Lite CCES Install and Session Startup For information about CCES and to download the software, go to www.analog.com/CCES. A link for the ADSP-BF548 EZ-KIT Lite Board Support Package (BSP) for CCES can be found at http://www.analog.com/Blackfin/EZKits. Follow these instructions to ensure correct operation of the product software and hardware. Step 1: Connect the EZ-KIT Lite board to a personal computer (PC) running CCES using one of two options: an Analog Devices emulator or via the debug agent. Using an Emulator: 1. Plug one side of the USB cable into the USB connector of the emulator. Plug the other side into a USB port of the PC running CCES. 2. Attach the emulator to the header connector ZP4 (labeled JTAG) on the EZ-KIT Lite board. Using the on-board Debug Agent: 1. Plug one side of the USB cable into the USB connector of the debug agent ZJ1 (labeled USB). 2. Plug the other side of the cable into a USB port of the PC running CCES. ADSP-BF548 EZ-KIT Lite Evaluation System Manual 1-5 CCES Install and Session Startup Step 2: Attach the provided cord and appropriate plug to the 7.5V power adaptor. 1. Plug the jack-end of the power adaptor into the power connector J7 (labeled 7.5V) on the EZ-KIT Lite board. 2. Plug the other side of the power adaptor into a power outlet. The power LED (labeled LED7) is lit green when power is applied to the board. 3. Power the emulator (if used). Plug the jack-end of the assembled power adaptor into the emulator and plug the other side of the power adaptor into a power outlet. The enable/power is lit green when power is applied. Step 3 (if connected through the debug agent): Verify that the yellow USB monitor LED (labeled ZLED3) is on. This signifies that the board is communicating properly with the host PC and ready to run CCES. Session Startup It is assumed that the CrossCore Embedded Studio software is installed and running on your PC. If you connect the board or emulator first (before installing Note: CCES) to the PC, the Windows driver wizard may not find the board drivers. 1. Navigate to the CCES environment via the Start menu. Note that CCES is not connected to the target board. 1-6 ADSP-BF548 EZ-KIT Lite Evaluation System Manual Using the ADSP-BF548 EZ-KIT Lite 2. Use the system configuration utility to connect to the EZ-KIT Lite board. If a debug configuration exists already, select the appropriate configuration and click Apply and Debug or Debug. Go to step 8. To create a debug configuration, do one of the following: • Click the down arrow next to the little bug icon, select Debug Configurations • Choose Run > Debug Configurations. The Debug Configuration dialog box appears. 3. Select CrossCore Embedded Studio Application and click (New launch configuration). The Select Processor page of the Session Wizard appears. 4. Ensure Blackfin is selected in Processor family. In Processor type, select ADSP-BF548. Click Next. The Select Connection Type page of the Session Wizard appears. 5. Select one of the following: • For standalone debug agent connections, EZ-KIT Lite and click Next. • For emulator connections, Emulator and click Next. The Select Platform page of the Session Wizard appears. ADSP-BF548 EZ-KIT Lite Evaluation System Manual 1-7 CCES Install and Session Startup 6. Do one of the following: • For standalone debug agent connections, ensure that the selected platform is ADSP-BF548 EZ-KIT Lite via Debug Agent. • For emulator connections, choose the type of emulator that is connected to the board. 7. Click Finish to close the wizard. The new debug configuration is created and added to the program(s) to load list. 8. In the Program(s) to load section, choose the program to load when connecting to the board. If not loading any program upon connection to the target, do not make any changes. Note that while connected to the target, there is no way to choose a program to download. To load a program once connected, terminate the session. a configuration, go to the Debug Configurations dialog Toboxdelete and select the configuration to delete. Click and choose Yes when asked if you wish to delete the selected launch configuration. Then Close the dialog box. from the target board, click the terminate button To(reddisconnect box) or choose Run > Terminate. To delete a session, choose Target > Session > Session List. Select the session name from the list and click Delete. Click OK. 1-8 ADSP-BF548 EZ-KIT Lite Evaluation System Manual Using the ADSP-BF548 EZ-KIT Lite VisualDSP++ Install and Session Startup For information about VisualDSP++ and to download the software, go to www.analog.com/VisualDSP. are two USB interfaces on the ADSP-BF548 EZ-KIT Lite. There Be sure to use the debugger’s interface (labelled , ZJ1 USB Debug Agent) when connecting your computer to the board with provided USB cable. The other USB interface (labelled USB-OTG) is for applications use. 1. Verify that the yellow USB monitor LED (ZLED3, located near the USB connector) is lit. This signifies that the board is communicating properly with the host PC and is ready to run VisualDSP++. 2. If you are running VisualDSP++ for the first time, navigate to the VisualDSP++ environment via the Start > Programs menu. The main window appears. Note that VisualDSP++ does not connect to any session. Skip the rest of this step to step 3. If you have run VisualDSP++ previously, the last opened session appears on the screen. You can override the default behavior and force VisualDSP++ to start a new session by pressing and holding down the Ctrl key while starting VisualDSP++. Do not release the Ctrl key until the Session Wizard appears on the screen. Go to step 4. 3. To connect to a new EZ-KIT Lite session, start Session Wizard by selecting one of the following. • From the Session menu, New Session. • From the Session menu, Session List. Then click New Session from the Session List dialog box. • From the Session menu, Connect to Target. ADSP-BF548 EZ-KIT Lite Evaluation System Manual 1-9 VisualDSP++ Install and Session Startup 4. The Select Processor page of the wizard appears on the screen. Ensure Blackfin is selected in Processor family. In Choose a target processor, select ADSP-BF548. Click Next. 5. The Select Connection Type page of the wizard appears on the screen. Select EZ-KIT Lite and click Next. 6. The Select Platform page of the wizard appears on the screen. Ensure that the selected platform is ADSP-BF548 EZ-KIT Lite via Debug Agent. Specify your own Session name for your session or accept the default name. The session name can be a string of any length; although, the box displays approximately 32 characters. The session name can include space characters. If you do not specify a session name, VisualDSP++ creates a session name by combining the name of the selected platform with the selected processor. The only way to change a session name later is to delete the session and to open a new session. Click Next. 7. The Finish page of the wizard appears on the screen. The page displays your selections. Check the selections. If you are not satisfied, click Back to make changes; otherwise, click Finish. VisualDSP++ creates the new session and connects to the EZ-KIT Lite. Once connected, the main window’s title is changed to include the session name set in step 6. disconnect from a session, click the disconnect button Toor select Session > Disconnect from Target. To delete a session, select Session > Session List. Select the session name from the list and click Delete. Click OK. 1-10 ADSP-BF548 EZ-KIT Lite Evaluation System Manual Using the ADSP-BF548 EZ-KIT Lite CCES Evaluation License The ADSP-BF548 EZ-KIT Lite software is part of the Board Support Package (BSP) for the Blackfin ADSP-BF54x family. The EZ-KIT Lite is a licensed product that offers an unrestricted evaluation license for 90 days after activation. Once the evaluation period ends, the evaluation license becomes permanently disabled. If the evaluation license is installed but not activated, it allows 10 days of unrestricted use and then becomes disabled. The license can be re-enabled by activation. An evaluation license can be upgraded to a full license. Licenses can be purchased from: • Analog Devices directly. Call (800) 262-5645 or 781-937-2384 or go to: http://www.analog.com/buyonline. • Analog Devices, Inc. local sales office or authorized distributor. To locate one, go to: http://www.analog.com/salesdir/continent.asp. EZ-KIT Lite hardware must be connected and powered up to The use CCES with a valid evaluation or full license. VisualDSP++ Evaluation License The ADSP-BF548 EZ-KIT Lite installation is part of the VisualDSP++ installation. The EZ-KIT Lite is a licensed product that offers an unrestricted evaluation license for the first 90 days. Once the initial unrestricted 90-day evaluation license expires: • VisualDSP++ restricts a connection to the ADSP-BF548 EZ-KIT Lite via the USB debug agent interface only. Connections to simulators and emulation products are no longer allowed. ADSP-BF548 EZ-KIT Lite Evaluation System Manual 1-11 Lockbox Key Security Features • The linker restricts a user’s program to 60 KB of memory for code space with no restrictions for data space. avoid errors when opening VisualDSP++, the EZ-KIT Lite Tohardware must be connected and powered up. This is true for using VisualDSP++ with a valid evaluation or full license. Lockbox Key Security Features Blackfin processors feature Lockbox® secure technology: hardware-enabled code security and content protection for one-time programmable (OTP) memory. Customers purchasing Blackfin processors can program their own customer public key in OTP. The ADSP-BF548 EZ-KIT Lites are evaluation boards with the Lockbox key pre-programmed and publicly documented—the burden of key generation and OTP programming of public keys is removed from the customer. Customers can still program other areas of OTP memory on the ADSP-BF548 EZ-KIT Lite. Analog Devices publicly document the EZ-KIT Lite’s public and private key pair for customer evaluation and support of the Lockbox feature, all while avoiding any keys information exchange. As a result, there is no confidentiality associated with the Lockbox key on EZ-KIT Lites. To demonstrate Lockbox features using an EZ-KIT Lite, you must use the keys that are provided pre-programmed on your EZ-KIT Lite. the EZ-KIT Lite key pair to generate a demo and then provide Use the keys to the demo users. Note that the EZ-KIT Lite cannot be used to secure any confidential information. If you wish to create a demo with confidential keys, you must build your own Blackfin board and personalize it with your own keys. 1-12 ADSP-BF548 EZ-KIT Lite Evaluation System Manual Using the ADSP-BF548 EZ-KIT Lite Memory Map The ADSP-BF548 processor has internal static random access memory (SRAM), used for instruction or data storage; see Table 1-1. The internal memory details can be found in the ADSP-BF54x Blackfin Processor Hardware Reference. The ADSP-BF548 EZ-KIT Lite board includes five types of external memory: double data rate (DDR), serial peripheral interconnect (SPI), burst flash, NAND, and secure digital (SD); see Table 1-2. For more information about a specific memory type, refer to the respective section in this chapter. Table 1-1. EZ-KIT Lite Internal Memory Map Start Address Content 0xEF00 0000 BOOT ROM (4K BYTE) 0xEF00 1000 Reserved 0xFEB0 0000 L2 SRAM (128K BYTE) 0xFEB2 0xFF40 0xFF40 0xFF40 0xFF50 0xFF50 0xFF50 0xFF60 0xFF60 0xFF60 0xFF60 0xFF61 0xFF61 0xFF70 0xFF70 0000 0000 4000 8000 0000 4000 8000 0000 4000 8000 C000 0000 4000 0000 1000 Reserved 0xFF80 0000 L1 DATA BANKA SRAM (16K BYTE) 0xFF80 4000 L1 DATA BANKA SRAM/CACHE (16K BYTE) ADSP-BF548 EZ-KIT Lite Evaluation System Manual 1-13 Memory Map Table 1-1. EZ-KIT Lite Internal Memory Map (Cont’d) Start Address Content 0xFF80 8000 Reserved 0xFF90 0000 L1 DATA BANKB SRAM (16K BYTE) 0xFF90 4000 L1 DATA BANKB SRAM/CACHE (16K BYTE) 0xFF90 8000 Reserved 0xFFA0 0000 L1 DATA BANKA LOWER SRAM (16K BYTE) 0xFFA0 4000 L1 DATA BANKA UPPER SRAM (16K BYTE) 0xFFA0 8000 Reserved 0xFFA0 C000 Reserved 0xFFA1 0000 L1 INSTRUCTION SRAM/CACHE (16K BYTE) 0xFFA1 0xFFA1 0xFFA1 0xFFA2 4000 8000 C000 0000 L1 INSTRUCTION BANKB ROM (64K BYTE) 0xFFA2 4000 Reserved 0xFFB0 0000 L1 SCRATCHPAD SRAM (4K BYTE) 0xFFB0 1000 Reserved 0xFFC0 0000 SYSTEM MMR REGISTERS 0xFFE0 0000 CORE MMR REGISTERS Table 1-2. EZ-KIT Lite External Memory Map Start Address End Address Content 0x0000 0000 0x03FF FFFF SDRAM bank 0 (SDRAM) See “DDR Interface” on page 1-15. 0x2000 0000 0x20FF FFFF ASYNC memory bank 0 See “Burst Flash Memory Interface” on page 1-17. 0x2400 0000 0x2400 007F ASYNC memory bank 1 See “Ethernet Interface” on page 1-24. 0x2800 0000 0x2BFF FFFF ASYNC memory bank 2 1-14 ADSP-BF548 EZ-KIT Lite Evaluation System Manual Using the ADSP-BF548 EZ-KIT Lite Table 1-2. EZ-KIT Lite External Memory Map (Cont’d) Start Address End Address Content 0x2C00 0000 0x2FFF FFFF ASYNC memory bank 3 0x3000 0000 0xEEFF FFFF Reserved DDR Interface The ADSP-BF548 processor holds a built-in double data rate (DDR) SDRAM controller, which connects to a Micron MT46V32M16 32M x 16 bits (64 MB) DDR memory chip. The controller connects to the DDR memory bank 0 via the DDRCS0 signal of the processor. The DDR memory chip is the only device connected to the processor’s DDR interface. The DDR interface can operate at a maximum system clock (SCLK) frequency of 133 MHz. There is a trade-off between selecting the maximum core clock (CCLK) of the processor and the maximum system clock. Consequently, the respective control registers must be initialized appropriately to get either maximum CCLK or maximum SCLK. When you are in a CCES or VisualDSP++ session and connected to the EZ-KIT Lite board via the USB debug agent, the DDR registers are configured automatically with values listed in Table 1-3 each time the processor is being reset. The values are used whenever DDR bank 0 is accessed through the debugger (for example, when viewing memory windows or loading a program). ADSP-BF548 EZ-KIT Lite Evaluation System Manual 1-15 DDR Interface To disable the automatic setting of the DDR registers, do one of the following: • CCES users, choose Target > Settings > Target Options and clear the Use XML reset values check box. • VisualDSP++ users, choose Settings > Target Options and clear the Use XML reset values check box. For more information on changing the reset values, refer to the online help. Table 1-4 shows configuration of the PLL registers using a 120 MHz SCLK and a 133 MHz SCLK. The PLL_CTL and PLL_DIV registers need to be initialized in the user code to achieve maximum performance. Please remember that the DDR control register values in Table 1-3 are for the SCLK set between 83 MHz and 133 MHz. Table 1-3. DDR Default Settings With an 83 MHz to 133 MHz SCLK Register Value Function EBIU_DDRCTL0 0x218A8287 Calculated with SCLK = 83 MHz to 133 MHz 16-bit data path External buffering timing disabled tRC = 8 SCLK cycles tRAS = 6 SCLK cycles tRP = 2 SCLK cycles tRFC = 10 SCLK cycles tREFI = 0x0287 clock cycles EBIU_DDRCTL1 0x20022222 = 2 SCLK cycles Device size = 512 Mbit Device width = 16 bits Ext. banks = CS0 only Data width = 16 bits tWR = 2 SCLK cycles tMRD = 2 SCLK cycles tRCD = 2 SCLK cycles 1-16 tWTR ADSP-BF548 EZ-KIT Lite Evaluation System Manual Using the ADSP-BF548 EZ-KIT Lite Table 1-3. DDR Default Settings With an 83 MHz to 133 MHz SCLK (Cont’d) Register Value Function EBIU_DDRCTL2 0x00000021 Processor default values EBIU_AMGCTL 0x0009 Enables the EBIU of the processor to generate a clock out for all memory banks Table 1-4. PLL Register Settings Register SCLK = 133 MHz CCLK = 400 MHz SCLK = 120 MHz CCLK = 600 MHz PLL_CTL 0x2000 0x3000 PLL_DIV 0x3 0x5 An example program is included in the EZ-KIT Lite installation directory to demonstrate how to setup and access the DDR interface. For more information on how to initialize the registers after a reset, search the online help for “reset values”. Burst Flash Memory Interface The burst flash memory interface of the ADSP-BF548 EZ-KIT Lite holds a 16 MB (16M x 16-bits) Intel PC28F128K3C115 chip. Flash memory connects gluelessly to the processor and is mapped to the processor’s external bank 0. This is accomplished by mapping the flash memory’s chip enable pin to the AMS0 memory select pin of the processor. The address range for flash memory is 0x2000 0000 to 0x20FF FFFF. Flash memory is pre-loaded with boot code for the blink and power-on-self test (POST) programs. For more information, refer to “Power-On-Self Test” on page 1-33. ADSP-BF548 EZ-KIT Lite Evaluation System Manual 1-17 NAND Flash Interface By default, the EZ-KIT Lite boots from 16-bit burst flash memory. The processor boots from the burst flash if the boot mode select switch (SW1) is set to a position of 1 (see “Boot Mode Select Switch (SW1)” on page 2-15). The flash memory code can be modified. For instructions, refer to the online help and example program included in the EZ-KIT Lite installation directory. NAND Flash Interface The ADSP-BF548 processor is equipped with an internal NAND flash controller, which allows the 2 Gbit ST Micro NAND02 device to be attached gluelessly to the processor. NAND flash is attached via the processor’s specific NAND flash control lines and external eight-bit data bus on the EBIU interface. NAND flash shares the data bus with burst flash memory, Ethernet controller, ATAPI hard drive, and expansion interface. You can write to each of the mentioned peripherals, one peripheral at a time. Refer to the ST Microelectronics Web site at http://www.st.com for more information. An example program is included in the EZ-KIT Lite installation directory to demonstrate how to setup and access the NAND flash interface. SPI Interface The ADSP-BF548 processor has three serial peripheral interconnect (SPI) ports that share multi-function I/O pins. The processor’s SPI port 0 connects directly to serial flash memory, AD7877 touchscreen controller, and expansion interface. 1-18 ADSP-BF548 EZ-KIT Lite Evaluation System Manual Using the ADSP-BF548 EZ-KIT Lite Serial flash memory is a 16 Mb ST Micro M25P16 device, which is selected using the SPI0SEL1 flag pin of the processor. SPI flash memory is pre-loaded with boot code for the blink and POST programs. For more information, refer to “Power-On-Self Test” on page 1-33. By default the EZ-KIT Lite boots from the 16-bit flash burst memory. The SPI flash can be used to boot up the processor by setting the boot mode select switch (SW1) to position 3 (see “Boot Mode Select Switch (SW1)” on page 2-15). The SPI flash code can be modified. For instructions, refer to the online help and example program included in the EZ-KIT Lite installation directory. The AD7877 touchscreen controller for the LCD can be selected using the SPI0SEL2 flag pin of the processor. For more information, refer to “Touchscreen Interface” on page 1-22. SPI ports 0 and 2 of the processor also connect to the expansion interface and can be accessed with an EZ-Extender® board that interfaces with the ADSP-BF548 EZ-KIT Lite. When using SPI port 0, use the processor’s SPI0SEL3 flag pin on an EZ-Extender because SPI0SEl1 and SPI0SEL2 are dedicated for the serial flash and touchscreen controller, respectively. Refer to the ST Microelectronics Web site at http://www.st.com for more information. SD Interface The ADSP-BF548 processor has a secure digital (SD) interface. The interface consists of a CLK pin, a command pin, and a four-bit data bus. The SD interface of the processor gluelessly connects to the on-board memory. The SD interface pins are not shared with other peripherals on the board. The memory can be written to in both one-bit and four-bit modes. The EZ-KIT Lite is accompanied with a 256 MB SD memory card plugged into the SD memory card connector (J5). For more information, refer to “SD Memory Card Connector (J5)” on page 2-35. ADSP-BF548 EZ-KIT Lite Evaluation System Manual 1-19 EPPI Interface An example program is included in the EZ-KIT Lite installation directory to demonstrate how to setup and access the SD interface. EPPI Interface The ADSP-BF548 processor provides up to three enhanced parallel peripheral interfaces (EPPIs), supporting data widths up to 24 bits. Each EPPI interface is a half-duplex, bi-directional bus consisting of up to 24 bits of data, a dedicated clock, and synchronization signals. The EZ-KIT Lite board utilizes two EPPI ports. One port connects to a TFT LCD module, while the other port connects to the expansion interface and STAMP connector. The PPI0 interface is configured to output 18-bit or 24-bit data to an LCD module (see “LCD Module Interface” on page 1-21). The PPI0 interface also connects to the expansion interface and can be used with an EZ-Extender board. When using the PPI0 interface with an EZ-Extender board, the PPI0 signals can be disconnected from the LCD module via the SW14 and SW17 switches. Refer to “LCD/PPI Configuration Switch (SW14)” on page 2-21 and “LCD Module Configuration (SW17)” on page 2-23 for more information. The PPI1 interface connects to the LCD, STAMP connector, and expansion interface. Since the PPI1 signals are connected to multi-function pins, the signals also can be configured for the host port and keypad interfaces. Refer to “Keypad Interface” on page 1-23 for more information. The PPI1 interface has a dedicated clock, generated either internally or externally and configured independently by software via the PPI1_SEL signal, which connects to PJ13. The clock source is the on-board 27 MHz oscillator or an external source via the expansion interface. The PPI1_SEL signal is configured via the SW14 switch. Refer to “LCD/PPI Configuration Switch (SW14)” on page 2-21 for more information. 1-20 ADSP-BF548 EZ-KIT Lite Evaluation System Manual Using the ADSP-BF548 EZ-KIT Lite LCD Module Interface The EZ-KIT Lite features a Sharp LQ043T1DG01 TFT LCD module. This is a 4.3” landscape display with a resolution of 480 x 272 and a color depth of 18 or 24 bits. Table 1-5 lists the register values when the PPI0 interface is configured for the LCD module. The values are obtained from the timing characteristics section of the LQ043T1DG01 data sheet. Table 1-5. LCD Module Interface Settings EPPI Register Name Data Sheet Symbol Value EPPI0_LINE Samples per line TH 525 EPPI0_FRAME Lines per frame TV 286 EPPI0_FS1W_HBL Frame sync 1 width THp 41 EPPI0_FS1P_AVPL Frame sync 1 period TH 525 EPPI0_HDELAY Horizontal delay THp EPPI0_HCOUNT Horizontal transfer count THd EPPI0_FS2W_LVB Frame sync 2 width TH EPPI0_FS2P_LAVF Frame sync 2 period H EPPI0_VDELAY Vertical delay TVp EPPI0_VCOUNT Vertical transfer count TVd 272 EPPI0_CLKDIV Clock divide register N/A 0x07 EPPI0_CONTROL Control N/A 0x12EE2F Control N/A 0x136E2F + THf 43 (41 + 2) 480 x TVp x TV + TVf 5250 (525 x 10) 150150 (525 x 286) 12 (10 + 2) (18 bit) EPPI0_CONTROL (24 bit) ADSP-BF548 EZ-KIT Lite Evaluation System Manual 1-21 Touchscreen Interface The LCD module connects to the EPPI0 port. The LCD interface can be configured to run in either 18-bit or 24-bit mode: • In 24-bit mode, 16M colors are possible, and the PPI data is mapped as eight bits each of red, green, and blue. The D5–D0 signals of EPPI1 are not available because the signals share pins with D18–23 of EPPI0. • In 18-bit mode, 256K colors are possible, and the PPI data is mapped as six bits each of red, green, and blue. Since the LCD is a 24-bit display, the lower two least significant bits of red, green, and blue are tied low. Refer to “LCD Module Configuration (SW17)” on page 2-23 for information on how to configure the board for 18-bit or 24-bit mode. The LCD module can be disconnected from PPI0 by disabling signals on SW14 and SW17. Refer to “LCD/PPI Configuration Switch (SW14)” on page 2-21 and “LCD Module Configuration (SW17)” on page 2-23 for more information. The DISP signal is generated internally by software via PE3. An example program is included in the EZ-KIT Lite installation directory to demonstrate how to setup and access the LCD module. Touchscreen Interface The AD7877 touchscreen controller connects to the SPI0 interface. The controller provides the X and Y positions, as well as a measurement for the pressure applied to the touchscreen. The touchscreen can be used with either a stylus or a finger. 1-22 ADSP-BF548 EZ-KIT Lite Evaluation System Manual Using the ADSP-BF548 EZ-KIT Lite The AD7877touchscreen controller connects to the SPI0 interface via the SPI0SEL2 control signal. Two interrupt signals connect to the device: • The data available output (DAV) signal is mapped to PB4 and is used to notify the ADSP-BF548 processor that the new ADC data is available in the results register. • The pen interrupt (PENIRQ) signal is mapped to PB5 and is used to notify the ADSP-BF548 processor that the screen has been touched. Refer to “LCD/PPI Configuration Switch (SW14)” on page 2-21 for information on how to configure the interrupt signals. The STOPACQ pin connects to PPI0FS1. The STOPACQ signal is used to ensure that an acquisition never occurs during the noisy period when the LCD is being updated. An example program is included in the EZ-KIT Lite installation directory to demonstrate how to setup and access the touchscreen controller. Keypad Interface The EZ-KIT Lite features a 4 x 4 keypad assembly connected to the keypad interface of the ADSP-BF548 processor. The keypad connects to the EZ-KIT Lite via a nine-pin connector (P1). The keypad interface of the processor shares the same multi-function pins as the EPPI1 port and the host interface. Consequently, the same keypad pins connect to the host connector, PPI connector, and expansion interface. If you need to use the processor’s pins for functions other than keypad, simply disconnect the keypad via the eight-position keypad switch (SW2). For more information, see “Keypad Enable Switch (SW2)” on page 2-16. An example program is included in the EZ-KIT Lite installation directory to demonstrate how to setup and access the keypad interface. ADSP-BF548 EZ-KIT Lite Evaluation System Manual 1-23 Rotary Encoder Interface Rotary Encoder Interface The ADSP-BF548 processor has a built-in, up-down counter with support for a rotary encoder. The three-wire rotary encoder interface connects to the rotary switch (SW3) and host connector. The rotary encoder can be turned clockwise for the up function, counter clockwise for the down function, or can be used as a push button for clearing the counter. If you need to use the processor pins for the host interface, disconnect the rotary encoder switch via the four-position rotary enable switch (SW4). For more information, see “Rotary Encoder Enable Switch (SW4)” on page 2-17. An example program is included in the EZ-KIT Lite installation directory to demonstrate how to setup and access the rotary encoder interface. Ethernet Interface The EZ-KIT Lite has a fully functional, high-performance, single-chip Ethernet controller with HP Auto-MDIX and is fully compliant with IEEE 802.2/802.2u standards. The SMSC LAN9218 chip contains an integrated Ethernet MAC and PHY, supports 10BASE-T and 100BASE-TX operations. The part is attached gluelessly to the ADSP-BF548 processor via the asynchronous memory bus and is mapped directly to the processor’s AMS1 memory bank. The valid address range for the Ethernet chip access is 0x2400 0000 through 0x2400 007F. The IRQ signal of the Ethernet chip is mapped to the PE8 flag pin of the processor and is connected via the SW16 switch position 3. If PE8 needs to be used elsewhere on the board, turn off the SW16 switch to disconnect it from the Ethernet chip. For more information, see “Peripheral Control Enable (SW16)” on page 2-22. The Ethernet chip is pre-loaded with a MAC address for the EZ-KIT Lite. The MAC address is stored in the Ethernet serial ROM (U12) and can be 1-24 ADSP-BF548 EZ-KIT Lite Evaluation System Manual Using the ADSP-BF548 EZ-KIT Lite found on a sticker on the bottom side of the EZ-KIT Lite. The serial ROM is connected directly to the LAN9218 and is accessed via the Ethernet chip only. The PHY portion of the Ethernet chip connects to a Pulse HX1188 (U15) magnetics, then to a standard RJ-45 Ethernet connector (J4). For more information, see “Ethernet Connector (J4)” on page 2-34. Example programs are included in the EZ-KIT Lite installation directory to demonstrate the Ethernet interface. Audio Interface The audio interface of the EZ-KIT Lite consists of an Analog Devices AD1980 audio codec and its associated passive components. The AD1980 is a AC’97 2.3 compliant SoundMAX codec that supports 5.1 surround sound. The codec carries integrated DACs and requires minimal external circuitry. The codec connects to the ADSP-BF548 processor via the processor’s serial port 0; the port is dedicated for the audio interface and does not connect to anything else on the board. The codec connects to multiple connectors which allow you to get audio IN and OUT signals. Connector J10 can be used as a line or head phone out. J10 also can be configured via software as the front surround left and right channel or a 5.1 surround system. Connector J9 has two locations for plugging in 3.5 mm cables. The top location is the center channel on the left channel and the LFE out on the right channel. The bottom location of J9 is left and right back surround channels for a 5.1 surround system. Similarly to J9, J8 has two locations for 3.5 mm cables. The top location is for a stereo microphone, and the bottom location is for a stereo line in. For more information, see “Dual Audio Connectors (J8 and J9)” on page 2-36 and “Audio Connector (J10)” on page 2-36. ADSP-BF548 EZ-KIT Lite Evaluation System Manual 1-25 ATAPI Interface The EZ-KIT Lite is shipped with a headphone and multiple 3.5 mm cables, which allow you to run the example programs provided in the EZ-KIT Lite installation directory and learn about the audio interface. For more information on the AD1980 codec, go to AD1980. ATAPI Interface The ADSP-BF548 processor has a built-in advanced technology attachment packet interface (ATA/ATAPI-6) controller that can be attached to any peripherals that support ATAPI standards. The EZ-KIT Lite is shipped with a 2.5” Toshiba 5V 80GB ATAPI hard disk drive. The ATAPI interface shares pins with other peripherals on the EZ-KIT Lite. Consequently, the ATAPI interface of the processor can connect to an ATAPI device (hard drive) via the PPI port pins or the external address and data bus. The EZ-KIT Lite is wired such that it connects the ATAPI hard drive to the processor via the external address and data bus. Two external 5V tolerant bus switches (U4 and U24) are used between the 3.3V processor signals and the 5V ATPI hard drive. U24 connects to all control signals of the ATAPI controller and is always enabled. U4 connects to the 16-bit data bus of the processor and is enabled with simple signal conditioning: • When you write data to the hard drive, the FET switch U4 automatically connects the two devices together. • When you do not use the ATAPI interface, the FET switch U4 is disconnected, and the processor does not see the capacitive load or the net traces associated with the hard disk drive. Example programs are included in the EZ-KIT Lite installation directory to demonstrate the ATAPI controller and hard disk drive operations. For more information about Toshiba MK4032GAX, refer to the data sheet provided by the product’s manufacturer. 1-26 ADSP-BF548 EZ-KIT Lite Evaluation System Manual Using the ADSP-BF548 EZ-KIT Lite For more information on the ATAPI interface, refer to the ADSP-BF54x Blackfin Processor Hardware Reference. USB OTG Interface The ADSP-BF548 processor has a built-in, high-speed USB on-the-go (OTG) interface and integrated PHY. This interface connects to a 24 MHz clock (U13), has surge protection, and can be configured as a host or device. When in device mode, the USB 5V regulator (VR1) and FET switch (U39) are turned OFF. When in host mode, the USB 5V regulator and FET are turned ON and can supply 5V at 500 mA. The control mechanism to turn the two devices ON and OFF are via the PE7 flag pin of the processor. By default PE7 is set low or a logic ‘0’ via a pull-down resistor, and both devices are turned OFF. If you are not using the USB OTG interface and would like to use the PE7 flag pin for other purposes, turn OFF position 2 on the SW16 switch. This disconnects the PE7 flag pin from both the VR1 regulator and U39 FET. For more information, see “Peripheral Control Enable (SW16)” on page 2-22. The USB OTG interface has a mini-AB connector (P4); cables that plug into P4 are shipped with the EZ-KIT Lite. Use the example programs in the EZ-KIT Lite installation directory to learn about the ADSP-BF548 processor’s device and host modes. For more information on the USB interface, refer to the ADSP-BF548 Blackfin Processor Hardware Reference. UART Interface The ADSP-BF548 processor has four built-in universal asynchronous receiver transmitters (UARTs). UART3–0 share the same processor pins as other peripherals on the EZ-KIT Lite. As a result, not all of the UARTs are available on the board: UART0 is not available on the board. ADSP-BF548 EZ-KIT Lite Evaluation System Manual 1-27 CAN Interface has full RS-232 functionality via the Analog Devices 3.3V ADM3202 (U32) line driver and receiver. The UART can be disconnected from the ADM3202 bit by turning OFF all positions on the SW7 switch. See “UART Enable Switch (SW7)” on page 2-19. When using UART1, jumpers JP1 and JP12 should not be installed. JP1 is a UART loopback jumper and should be installed only when running the POST program. JP12 is installed when you are not using the UART and need to use PP1FS3. See “UART1 Loopback Jumper (JP1)” on page 2-26 and “PPI1FS3 Pull-down Jumper (JP12)” on page 2-30 for more information. UART1 UART2 and UART3 are connected to the expansion interface. UART3 of the processor also is available via a STAMP connector (P12). See “UART3 Connector (P12)” on page 2-41. Example programs are included in the EZ-KIT Lite installation directory to demonstrate UART and RS-232 operations. For more information on the UART interface, refer to the ADSP-BF548 Blackfin Processor Hardware Reference. CAN Interface The Controller Area Network (CAN) interface contains two Philips TJA1041 high-speed CAN transceivers. The two transceivers are connected to the CAN0 and CAN1 ports of the processor. Either of the CAN ports can be used to transmit or receive data. The PC0 programmable flag connects to the error and power-on indication output of CAN0 (CAN0_ERR). The PC5 programmable flag connects to the error and power-on indication output of CAN1 (CAN1_ERR). The transmit and receive pins for both transceivers connect to the dedicated CAN0 and CAN1 transmit and receive pins of the processor. The CAN0 interface can be disconnected from the processor by turning OFF positions 1 though 4 of the SW6 switch. Similarly, the CAN1 interface can be disconnected from the processor by turning OFF positions 1 though 4 of 1-28 ADSP-BF548 EZ-KIT Lite Evaluation System Manual Using the ADSP-BF548 EZ-KIT Lite the SW15 switch. When OFF, the signals can be used elsewhere on the board. See “CAN0 Enable Switch (SW6)” on page 2-18 and “CAN1 Enable Switch (SW15)” on page 2-22 for more information. The CAN interface contains two 4-position modular connectors (see “CAN Connectors (J11 and J12)” on page 2-36). Example programs are included in the EZ-KIT Lite installation directory to demonstrate CAN circuit operation. Host Interface The host DMA port of the Blackfin processor is available via a IDC 16x2 header (P3) on the EZ-KIT Lite. The port allows a host device external to the Blackfin processor to be a DMA master and transfer data back and forth. When using the host interface port, the host device is the master, and the Blackfin processor is a DMA slave device. Since the host signals share pins with other peripherals on the EZ-KIT Lite, certain switches and jumpers must be OFF in order to use the host interface. When turning the switches or jumpers OFF, you disable the respective peripherals and are not able to evaluate the peripherals at the same time as the host interface. Table 1-6 describes the jumpers and switches that must be OFF, the respective host interface signal associated with these jumpers or switches, and the peripherals that are affected by turning these jumpers or switches OFF. ADSP-BF548 EZ-KIT Lite Evaluation System Manual 1-29 RTC Interface Table 1-6. Host Interface Switch or Jumper: Host Signals Affected: EZ-KIT Lite Peripheral Affected: SW2 (all OFF) PPI1D[8:15]/HPD[0:7] Keypad disabled SW4 (all OFF) HPACK, HPA, #HPCE Rotary encoder disabled SW5 (position 4 OFF) HPWAIT Push button 4 disabled PPI1D[0:5]/HPD[8:13] LCD 24-bit mode disabled; LCD 18-bit mode operational #HPCE, #HPRD, #HPWR STAMP interface disabled; LED1—2 can not be used as global status indicators. SW17 (position 3 OFF) JP2 (OFF) RTC Interface The ADSP-BF548 processor has a real-time clock (RTC) and a watchdog timer. Typically the RTC interface is used to implement a real-time watch or a life counter of the time elapsed since the last system reset. The EZ-KIT Lite is equipped with a Panasonic lithium coin 3V 24 MM battery with a 1000 mAh. The 3V battery and the 3.3V supply of the board are connected to the RTC power pin of the processor. When the EZ-KIT Lite is powered, it uses the board power to supply voltage to the RTC pin. When the EZ-KIT Lite is not powered, it uses the lithium battery to maintain the power to the RTC pin. The battery allows you to evaluate RTC functionality for the life of the EZ-KIT Lite. You can calculate your application’s specific power requirements and use a much smaller battery in a custom design. Example programs are included in the EZ-KIT Lite installation directory to demonstrate the RTC features. 1-30 ADSP-BF548 EZ-KIT Lite Evaluation System Manual Using the ADSP-BF548 EZ-KIT Lite EZ-KIT Lite is shipped with a protective Mylar sheet placed The between the coin battery and the positive pin of the battery holder. Please remember to remove the Mylar sheet before trying to use RTC functionality of the processor. For more information on the RTC and watchdog timer, refer to the ADSP-BF548 Blackfin Processor Hardware Reference. LEDs and Push Buttons The EZ-KIT Lite provides four push buttons and six LEDs for general-purpose I/O. The six LEDs, labeled LED1 through LED6, are accessed via the PG6–11 pins of the processor. For information on how to program the pins, refer to the ADSP-BF548 Blackfin Processor Hardware Reference. The four general-purpose push button are labeled PB1 through PB4. The status of each individual button can be read through programmable flag (PF) inputs, PF8–11. A PF reads 1 when a corresponding switch is being pressed. When the switch is released, the PF reads 0. A connection between the push button and PF input is established through the SW5 DIP switch. See “Push Button Enable Switch (SW5)” on page 2-18 for details. An example program is included in the EZ-KIT Lite installation directory to demonstrate functionality of the LEDs and push buttons. JTAG Interface The JTAG emulation port allows an emulator to access the processor’s internal and external memory through a six-pin interface. The JTAG emulator port of the processor can be accessed via the on-board USB Debug Agent or with an external emulator via the JTAG connector (ZP4). When an external emulator connects to the board, the on-board USB Debug ADSP-BF548 EZ-KIT Lite Evaluation System Manual 1-31 Expansion Interface Agent is disabled. See “JTAG Connector (ZP4)” on page 2-42 for more information. For more information on emulators, contact Analog Devices or go to: http://www.analog.com/processors/tools/blackfin. Expansion Interface The expansion interface consists of three 90-pin connectors, J1—3. These connectors contain a majority of the ADSP-BF548 processor’s signals. For the pinout of the connectors, go to “ADSP-BF548 EZ-KIT Lite Schematic” on page B-1. The expansion interface allows an EZ-Extender or a custom-design daughter board to be tested across various hardware platforms. The mechanical dimensions of the expansion connectors can be obtained by contacting Technical Support. Analog Devices offers many EZ-Extender products. For more information about EZ-Extenders, visit the Analog Devices Web site at: http://www.analog.com/processors/tools/blackfin. Limits to current and interface speed must be taken into consideration when using the expansion interface. Because current for the expansion interface is sourced from the EZ-KIT Lite, the current should be limited to 1A for both the 5V and 3.3V planes. If more current is required, then a separate power connector and a regulator must be designed on a daughter card. Additional circuitry can add extra loading to signals, decreasing their maximum effective speed. Devices does not support and is not responsible for the Analog effects of additional circuitry. 1-32 ADSP-BF548 EZ-KIT Lite Evaluation System Manual Using the ADSP-BF548 EZ-KIT Lite Power Measurements Several locations are provided for measuring the current draw from various power planes. Precision 0.05 ohm shunt resistors are available on the VDDINT, VDDEXT, and VDDDDR pins. For current draw measuments, the associated jumper (JP4, JP5, or JP6) should be removed. Once the jumper is removed, the voltage across the resistor can be measured using an oscilloscope. Once voltage is measured, current can be calculated by dividing the voltage by 0.05. For the highest accuracy, a differential probe should be used for measuring the voltage across the resistor. For more information, see “VDDINT Power Jumper (JP4)”, “VDDEXT Power Jumper (JP5)”, and “VDDDDR Power Jumper (JP6)”. Board Design Database A .zip file containing all of the electronic information required for the design, layout, fabrication and assembly of the product is available for download from the Analog Devices board design database at: http://www.analog.com/board-design-database. Power-On-Self Test Once assembled, each EZ-KIT Lite is fully tested for an extended period of time with a power-on-self test (POST). The POST tests all EZ-KIT Lite peripherals and validates functionality as well as connectivity to the processor. The POST is loaded into burst flash memory (U5) and can be activated by resetting the board and pressing the associated push button(s). The POST also can be used as a reference for a custom software design or hardware troubleshooting. When running the POST, you may need to place switches and jumpers in specific test modes. In some instances, such as Ethernet, you may need to ADSP-BF548 EZ-KIT Lite Evaluation System Manual 1-33 Example Programs plug in an Ethernet loopback connector (provided with the EZ-KIT Lite) to run the POST. The user LEDs (LED1–6) will convey whether the specific tests have passed or failed. The POST program is included in the EZ-KIT Lite installation directory. For more information, refer to the readme file in the POST directory. The POST program is only available when using VisualDSP++. Example Programs Example programs are provided with the ADSP-BF548 EZ-KIT Lite to demonstrate various capabilities of the product. The programs are included in the product installation kit and can be found in the Examples folder of the installation. Refer to a readme file provided with each example for more information. CCES users are encouraged to use the example browser to find examples included with the EZ-KIT Lite Board Support Package. 1-34 ADSP-BF548 EZ-KIT Lite Evaluation System Manual 2 ADSP-BF548 EZ-KIT LITE HARDWARE REFERENCE This chapter describes the hardware design of the ADSP-BF548 EZ-KIT Lite board. The following topics are covered. • “System Architecture” on page 2-2 Describes the ADSP-BF548 EZ-KIT Lite board configuration and explains how the board components interface with the processor. • “Programmable Flags” on page 2-3 Shows the locations and describes the programming flags (PFs). • “Push Button and Switch Settings” on page 2-15 Shows the location and describes the push buttons and switches. • “Jumpers” on page 2-25 Shows the location and describes the configuration jumpers. • “LEDs” on page 2-31 Shows the location and describes the LEDs. • “Connectors” on page 2-33 Shows the locations and provides part numbers for the on-board connectors. In addition, the manufacturer and part number information is provided for the mating parts. ADSP-BF548 EZ-KIT Lite Evaluation System Manual 2-1 System Architecture System Architecture This section describes the processor’s configuration on the EZ-KIT Lite board (Figure 2-1). 25 MHz Oscillator JTAG Header 32.768 KHz Oscillator USB OTG Mini AB Conn JTAG Port Debug Agent USB Conn RTC 64 MB DDR 16 MB Burst Flash (32M x 16) (8M x 16 ) DDR 2 Gb NAND Flash (512M x 8 ) Ethrernet MAC/PHY Expansion Connectors (3) EBIU ATAPI Conn 24 MHz Oscillator USB SD Conn CANs KEYPAD (2) CAN Transceiver (2) RJ11 UARTs Rotory SPIs SPORTs EPPIs TWIs SPI IDC Conn (2) IDC Conn PPI IDC Conn IDC Conn PBs (4) LEDs (6) +7.5V Connector 16 Mb SPI Flash Power Regulation ADM3202 RS-232 TX/RX (2) IDC Conn RS-232 Female AC97 Touch Screen VGA LCD AD1980 Or AD1981B CODEC Figure 2-1. System Architecture This EZ-KIT Lite is designed to test the ADSP-BF548 processor capabilities. The processor has an I/O voltage of 3.3V. The core voltage of the processor is controlled by the internal voltage regulator. 2-2 ADSP-BF548 EZ-KIT Lite Evaluation System Manual ADSP-BF548 EZ-KIT Lite Hardware Reference The core voltage and clock rate can be set on the fly by the processor. The input clock is 25 MHz. A 32.768 kHz crystal supplies the real-time clock (RTC) inputs of the processor. The default boot mode for the processor is burst flash boot. See “Boot Mode Select Switch (SW1)” on page 2-15 for information on how to change the default boot mode. Programmable Flags The processor has 153 general-purpose input/output (GPIO) signals spread across ten ports (PA, PB, PC, PD, PE, PF, PG, PH, PI, and PJ). The pins are multi-functional and depend on the ADSP-BF548 processor setup. The following tables show how the programmable flag pins are used on the EZ-KIT Lite. PA programmable flag pins in Table 2-1 PF programmable flag pins in Table 2-6 PB programmable flag pins in Table 2-2 PG programmable flag pins in Table 2-7 PC programmable flag pins in Table 2-3 PH programmable flag pins in Table 2-8 PD programmable flag pins in Table 2-4 PI programmable flag pins in Table 2-9 PE programmable flag pins in Table 2-5 PJ programmable flag pins in Table 2-10 Table 2-1. PA Port Programmable Flag Connections Processor Pin Other Processor Function EZ-KIT Lite Function PA0 TFS2 Expansion interface, SPORT2 connector PA1 DT2SEC/TMR4 Expansion interface, SPORT2 connector PA2 DT2PRI Expansion interface, SPORT2 connector PA3 TSCLK2 Expansion interface, SPORT2 connector PA4 RFS2 Expansion interface, SPORT2 connector PA5 DR2SEC/TMR5 Expansion interface, SPORT2 connector PA6 DR2PRI Expansion interface, SPORT2 connector PA7 RSCLK2/TACLK0 Expansion interface, SPORT2 connector ADSP-BF548 EZ-KIT Lite Evaluation System Manual 2-3 Programmable Flags Table 2-1. PA Port Programmable Flag Connections (Cont’d) Processor Pin Other Processor Function EZ-KIT Lite Function PA8 TFS3/TACLK1 Expansion interface, SPORT3 connector PA9 DT3SEC/TMR6 Expansion interface, SPORT3 connector PA10 DT3PRI/TACLK2 Expansion interface, SPORT3 connector PA11 TSCLK3/TACLK3 Expansion interface, SPORT3 connector PA12 RFS3/TACLK4 Expansion interface, SPORT3 connector PA13 DR3SEC/TMR7/TACLK5 Expansion interface, SPORT3 connector PA14 DR3PRI/TACLK6 Expansion interface, SPORT3 connector PA15 RSCLK3/TACLK7 and TACI7 Expansion interface, SPORT3 connector Table 2-2. PB Port Programmable Flag Connections 2-4 Processor Pin Other Processor Function EZ-KIT Lite Function PB0 SCL1 Expansion interface, TWI connector PB1 SDA1 Expansion interface, TWI connector PB2 UART3RTS Default: PPI1CLK Mux select via SW14.3. Expansion interface PB3 UART3CTS Default: audio codec reset via SW16.1. Expansion interface PB4 UART2TX Default: LCD data available via SW14.1. Expansion interface PB5 UART2RX/TACI2 Default: LCD IRQ via SW14.2. Expansion interface PB6 UART3TX Expansion interface, UART3 connector PB7 UART3RX/TACI3 Expansion interface, UART3 connector PB8 SPI2SS/TMR0 Default: PB1 via SW5.1. Expansion interface, timers connector, SPORT2–3 connectors PB9 SPI2SEL1/TMR1 Default: PB2 via SW5.2. Expansion interface, timers connector, UART3 connector, SPORT2–3 connectors ADSP-BF548 EZ-KIT Lite Evaluation System Manual ADSP-BF548 EZ-KIT Lite Hardware Reference Table 2-2. PB Port Programmable Flag Connections (Cont’d) Processor Pin Other Processor Function EZ-KIT Lite Function PB10 SPI2SEL2/TMR2 Default: PB3 via SW5.3. Expansion interface, timers connector, UART3 connector, SPORT2–3 connectors PB11 SPI2SEL3/BOOTWAIT Default: PB4 via SW5.4. Expansion interface, host interface connector. NOR RESET via SW16.4. PB12 SPI2SCK Expansion interface PB13 SPI2MOSI Expansion interface PB14 SPIMISO Expansion interface Table 2-3. PC Port Programmable Flag Connections Processor Pin Other Processor Function EZ-KIT Lite Function PC0 TFS0 Default: CAN0 via SW6.3 SPI connector, TWI connector, SPORT2–3 connectors PC1 DT0SEC/MMCLK Not used PC2 DT0PRI Audio codec data pin PC3 TSCLK0 Audio codec clock pin PC4 RFS0 Audio codec sync pin PC5 DR0SEC/MBCLK Default: CAN1 via SW15.3 SPI connector, TWI connector, SPORT2–3 connectors PC6 DR0PRI Audio codec data pin PC7 RSCLK0 Audio codec clock pin PC8 SD_D0 SD memory data pin PC9 SD_D1 SD memory data pin PC10 SD_D2 SD memory data pin PC11 SD_D3 SD memory data pin ADSP-BF548 EZ-KIT Lite Evaluation System Manual 2-5 Programmable Flags Table 2-3. PC Port Programmable Flag Connections (Cont’d) Processor Pin Other Processor Function EZ-KIT Lite Function PC12 SD_CLK SD memory clock pin PC13 SD_CMD SD memory command pin Table 2-4. PD Port Programmable Flag Connections 2-6 Processor Pin Other Processor Function EZ-KIT Lite Function PD0 PPI1_D0/HOST_D8/ TFS1/PPI0_D18 Default: LCD module via SW17.3. Host interface connector, expansion interface, PPI1 connector PD1 PPI1_D1/HOST_D9/ DT1SEC/PPI0_D19 Default: LCD module via SW17.3. Host interface connector, expansion interface, PPI1 connector PD2 PPI1_D2/HOST_D10/ DT1PRI /PPI0_D20 Default: LCD module via SW17.3. Host interface connector, expansion interface, PPI1 connector PD3 PPI1_D3/HOST_D11/ TSCLK1/PPI0_D21 Default: LCD module via SW17.3. Host interface connector, expansion interface, PPI1 connector PD4 PPI1_D4/HOST_D12/ RFS1/PPI0_D22 Default: LCD module via SW17.3. Host interface connector, expansion interface, PPI1 connector PD5 PPI1_D5/HOST_D13/ DR1SEC/PPI0_D23 Default: LCD module via SW17.3. Host interface connector, expansion interface, PPI1 connector PD6 PPI1_D6/HOST_D14/ DR1PRI Host interface connector, expansion interface, PPI1 connector PD7 PPI1_D7/HOST_D15/ RSCLK1 Host interface connector, expansion interface, PPI1 connector PD8 PPI1_D8/HOST_D0/ PPI2_D0/KEY_ROW0 Default: keypad via SW2.8. Host interface connector, expansion interface, PPI1 connector ADSP-BF548 EZ-KIT Lite Evaluation System Manual ADSP-BF548 EZ-KIT Lite Hardware Reference Table 2-4. PD Port Programmable Flag Connections (Cont’d) Processor Pin Other Processor Function EZ-KIT Lite Function PD9 PPI1_D9/HOST_D1/ PPI2_D1/KEY_ROW1 Default: keypad via SW2.7. Host interface connector, expansion interface, PPI1 connector PD10 PPI1_D10/HOST_D2/ PPI2_D2/KEY_ROW2 Default: keypad via SW2.6. Host interface connector, expansion interface, PPI1 connector PD11 PPI1_D11/HOST_D3/ PPI2_D3/KEY_ROW3 Default: keypad via SW2.5. Host interface connector, expansion interface, PPI1 connector PD12 PPI1_D12/HOST_D4/ PPI2_D4/KEY_COL0 Default: keypad via SW2.4. Host interface connector, expansion interface, PPI1 connector PD13 PPI1_D13/HOST_D5/ PPI2_D5/KEY_COL1 Default: keypad via SW2.3. Host interface connector, expansion interface, PPI1 connector PD14 PPI1_D14/HOST_D6/ PPI2_D6/KEY_COL2 Default: keypad via SW2.2. Host interface connector, expansion interface, PPI1 connector PD15 PPI1_D15/HOST_D7/ PPI2_D7/KEY_COL3 Default: keypad via SW2.1. Host interface connector, expansion interface, PPI1 connector Table 2-5. PE Port Programmable Flag Connections Processor Pin Other Processor Function EZ-KIT Lite Function PE0 SPI0SCK/KEY_COL7 SPI memory, LCD touchscreen controller, expansion interface PE1 SPI0MISO/KEY_ROW6 SPI memory, LCD touchscreen controller, expansion interface PE2 SPI0MOSI/KEY_COL6 SPI memory, LCD touchscreen controller, expansion interface PE3 SPI0SS/KEY_ROW5 Default: LCD DISP via SW14.4. Expansion interface ADSP-BF548 EZ-KIT Lite Evaluation System Manual 2-7 Programmable Flags Table 2-5. PE Port Programmable Flag Connections (Cont’d) Processor Pin Other Processor Function EZ-KIT Lite Function PE4 SPI0SEL1/KEY_COL5 Default: SPI memory. Expansion interface PE5 SPI0SEL2/KEY_ROW4 Default: LCD touchscreen controller Expansion interface PE6 SPI0SEL3/KEY_COL4 Expansion interface PE7 UART0TX/KEY_ROW7 Default: USB OTG VR1 and U39 enable via SW16.2. Expansion interface PE8 UART0RX/TACI0 Default: Ethernet IRQ via SW16.3. Expansion interface PE9 UART1RTS UART1 serial port via SW7.3 PE10 UART1CTS UART1 serial port via SW7.1 PE11 PPI1_CLK Expansion interface, PPI1 connector PE12 PPI1_FS1 Expansion interface, PPI1 connector PE13 PPI1_FS2 Expansion interface, PPI1 connector PE14 SCL0 Expansion interface, SPORT2–3 connectors, PPI1 connector PE15 SDA0 Expansion interface, SPORT2–3 connectors, PPI1 connector Table 2-6. PF Port Programmable Flag Connections 2-8 Processor Pin Other Processor Function EZ-KIT Lite Function PF0 PPI0_D0 Default: LCD module via SW17. Expansion interface PF1 PPI0_D1 Default: LCD module via SW17. Expansion interface PF2 PPI0_D2 Default: LCD module via SW17. Expansion interface PF3 PPI0_D3 Default: LCD module via SW17. Expansion interface ADSP-BF548 EZ-KIT Lite Evaluation System Manual ADSP-BF548 EZ-KIT Lite Hardware Reference Table 2-6. PF Port Programmable Flag Connections (Cont’d) Processor Pin Other Processor Function EZ-KIT Lite Function PF4 PPI0_D4 Default: LCD module via SW17. Expansion interface PF5 PPI0_D5 Default: LCD module via SW17. Expansion interface PF6 PPI0_D6 Default: LCD module via SW17. Expansion interface PF7 PPI0_D7 Default: LCD module via SW17. Expansion interface PF8 PPI0_D8 Default: LCD module via SW17. Expansion interface PF9 PPI0_D9 Default: LCD module via SW17. Expansion interface PF10 PPI0_D10 Default: LCD module via SW17. Expansion interface PF11 PPI0_D11 Default: LCD module via SW17. Expansion interface PF12 PPI0_D12 Default: LCD module via SW17. Expansion interface PF13 PPI0_D13 Default: LCD module via SW17. Expansion interface PF14 PPI0_D14 Default: LCD module via SW17. Expansion interface PF15 PPI0_D15 Default: LCD module via SW17. Expansion interface Table 2-7. PG Port Programmable Flag Connections Processor Pin Other Processor Function EZ-KIT Lite Function PG0 PPI0_CLK/TMRCLK Default: LCD module via SW17. Expansion interface PG1 PPI0_FS1 Default: LCD module via SW17. Expansion interface ADSP-BF548 EZ-KIT Lite Evaluation System Manual 2-9 Programmable Flags Table 2-7. PG Port Programmable Flag Connections (Cont’d) Processor Pin Other Processor Function EZ-KIT Lite Function PG2 PPI0_FS2 Default: LCD module via SW17. Expansion interface PG3 PPI0_D16 Default: LCD module via SW17. Expansion interface PG4 PPI0_D17 Default: LCD module via SW17. Expansion interface PG5 SPI1SEL1/HOST_CE/ PPI2_FS2/ CZM Default: rotary encoder via SW4.3. Host interface connector SPI connector via JP2 SPORT2 connector via JP2 SPORT3 connector via JP2 PPI1 connector via JP2 PG6 SPI1SEL2/HOST_RD/ PPI2_FS1 Default: LED1. Expansion interface Host interface connector SPI connector via JP2 SPORT2 connector via JP2 SPORT3 connector via JP2 PPI1 connector via JP2 PG7 SPI1SEL3/HOST_WR/ PPI2_CLK Default: LED2. Expansion interface Host interface connector SPI connector via JP2 SPORT2 connector via JP2 SPORT3 connector via JP2 PG8 SPI1SCK Default: LED3. Expansion interface SPI connector via JP2 SPORT2 connector via JP2 SPORT3 connector via JP2 PPI1 connector via JP2 2-10 ADSP-BF548 EZ-KIT Lite Evaluation System Manual ADSP-BF548 EZ-KIT Lite Hardware Reference Table 2-7. PG Port Programmable Flag Connections (Cont’d) Processor Pin Other Processor Function EZ-KIT Lite Function PG9 SPI1MISO Default: LED4. Expansion interface SPI connector via JP2 SPORT2 connector viaJP2 SPORT3 connector via JP2 PPI1 connector via JP2 PG10 SPI1MOSI Default: LED5. Expansion interface SPI connector via JP2, JP7, and JP8 SPORT2 connector via JP2, JP7, and JP8 SPORT3 connector via JP2, JP7, and JP8 PPI1 connector via JP2, JP7, and JP8 PG11 SPI1SS/MTXON Default: LED6. Expansion interface SPI connector via JP2 SPORT2 connector via JP2 SPORT3 connector via JP2 PPI1 connector via JP2 PG12 CAN0TX CAN0 PG13 CAN0RX/TACI4 Default: CAN0 via SW6.4 SPI connector, TWI connector, timers connector, SPORT2–3 connectors, PPI1 connector PG14 CAN1TX CAN1 PG15 CAN1RX/TACI5 Default: CAN1 via SW15.4 SPI connector, TWI connector, timers connector, SPORT2–3 connectors, PPI1 connector ADSP-BF548 EZ-KIT Lite Evaluation System Manual 2-11 Programmable Flags Table 2-8. PH Port Programmable Flag Connections Processor Pin Other Processor Function EZ-KIT Lite Function PH0 UART1_TX/PPI1_FS3 Default: UART1 serial port. Expansion interface, PPI1 connector PH1 UART1_RX/PPI2_FS3/TACI1 Default: UART1 serial port via SW7.2. Expansion interface PH2 ATAPI_RESET/TMR8/ PPI0_FS3 ATAPI reset; expansion interface PH3 HOST_ADDR/TMR9/CUD Default: rotary encoder via SW4.2. Host interface connector PH4 HOST_ACK/TMR10/CDG Default: rotary encoder via SW4.1. Host interface connector PH5 MTX/DMAR0/TACI8 TACLK8 and Not used PH6 MRX/DMAR1/TACI9 TACLK9 and Not used PH7 MRXON/BOOTWAIT/TACI10 and TACLK10 Expansion interface, host interface connector PH8 A4 Address line on burst flash memory, Ethernet controller, expansion interface PH9 A5 Address line on burst flash memory, Ethernet controller, expansion interface PH10 A6 Address line on burst flash memory, Ethernet controller, expansion interface PH11 A7 Address line on burst flash memory, Ethernet controller, expansion interface PH12 A8 Address line on burst flash memory, expansion interface PH13 A9 Address line on burst flash memory, expansion interface 2-12 ADSP-BF548 EZ-KIT Lite Evaluation System Manual ADSP-BF548 EZ-KIT Lite Hardware Reference Table 2-9. PI Port Programmable Flag Connections Processor Pin Other Processor Function EZ-KIT Lite Function PI0 A10 Address line on burst flash memory, expansion interface PI1 A11 Address line on burst flash memory, expansion interface PI2 A12 Address line on burst flash memory, expansion interface PI3 A13 Address line on burst flash memory, expansion interface PI4 A14 Address line on burst flash memory, expansion interface PI5 A15 Address line on burst flash memory, expansion interface PI6 A16 Address line on burst flash memory, expansion interface PI7 A17 Address line on burst flash memory, expansion interface PI8 A18 Address line on burst flash memory, expansion interface PI9 A19 Address line on burst flash memory, expansion interface PI10 A20 Address line on burst flash memory, expansion interface PI11 A21 Address line on burst flash memory, expansion interface PI12 A22 Address line on burst flash memory, expansion interface PI13 A23 Address line on burst flash memory, expansion interface PI14 A24 Address line on burst flash memory, expansion interface PI15 A25/NORCLK Clock for burst flash memory ADSP-BF548 EZ-KIT Lite Evaluation System Manual 2-13 Programmable Flags Table 2-10. PJ Port Programmable Flag Connections Processor Pin Other Processor Function EZ-KIT Lite Function PJ0 ARDY/WAIT WAIT for burst flash memory, expansion interface PJ1 ND_CE Chip enable for NAND PJ2 ND_RB Ready/busy for NAND PJ3 ATAPI_DIORB ATAPI (hard disk drive) interface PJ4 ATAPI_DIOWB ATAPI (hard disk drive) interface PJ5 ATAPI_CS0B ATAPI (hard disk drive) interface PJ6 ATAPI_CS1B ATAPI (hard disk drive) interface PJ7 ATAPI_DMACKB ATAPI (hard disk drive) interface PJ8 ATAPI_DMARQ ATAPI (hard disk drive) interface PJ9 ATAPI_INTRQ ATAPI (hard disk drive) interface PJ10 ATAPI_IORDY ATAPI (hard disk drive) interface PJ11 BR Expansion interface PJ12 BG Expansion interface PJ13 BGH Expansion interface 2-14 ADSP-BF548 EZ-KIT Lite Evaluation System Manual ADSP-BF548 EZ-KIT Lite Hardware Reference Push Button and Switch Settings This section describes operation of the push buttons and switches. The push button and switch locations are shown in Figure 2-2. Figure 2-2. Push Button and Switch Locations Boot Mode Select Switch (SW1) The rotary switch (SW1) determines the boot mode of the processor. Table 2-11 shows the available boot mode settings. By default the ADSP-BF548 processor boots from the on-board burst flash memory. Table 2-11. Boot Mode Select Switch (SW1) SW1 Position Processor Boot Mode 0 Idle—no boot 1 Boot from 16-bit burst flash memory (default) 2 Boot from 16-bit asynchronous FIFO ADSP-BF548 EZ-KIT Lite Evaluation System Manual 2-15 Push Button and Switch Settings Table 2-11. Boot Mode Select Switch (SW1) (Cont’d) SW1 Position Processor Boot Mode 3 Boot from serial SPI memory 4 Boot from SPI host device 5 Boot from serial TWI memory 6 Boot from TWI host 7 Boot from UART host 8–9 Reserved A Boot from double-data rate (DDR) SDRAM B, C, D Reserved E Boot from 16-bit host DMA F Boot from eight-bit host DMA Keypad Enable Switch (SW2) The keypad enable switch (SW2) disconnects the keypad signals from the GPIO pins of the processor. When the switch is OFF, its associated GPIO signals can be used on the PPI1 port, host interface, or expansion interface (see Table 2-12). Table 2-12. Keypad Enable Switch (SW2) EZ-KIT Lite Signal SW2 Switch Position (Default) Processor Signal PPI1D15/HPD7/KPC3 1 (ON) PD15 PPI1D14/HPD6/KPC2 2 (ON) PD14 PPI1D13/HPD5/KPC1 3 (ON) PD13 PPI1D12/HPD4/KPC0 4 (ON) PD12 PPI1D11/HPD3/KPR3 5 (ON) PD11 PPI1D10/HPD2/KPR2 6 (ON) PD10 2-16 ADSP-BF548 EZ-KIT Lite Evaluation System Manual ADSP-BF548 EZ-KIT Lite Hardware Reference Table 2-12. Keypad Enable Switch (SW2) (Cont’d) EZ-KIT Lite Signal SW2 Switch Position (Default) Processor Signal PPI1D9/HPD1/KPR1 7 (ON) PD9 PPI1D8/HPD0/KPR0 8 (ON) PD8 Rotary Encoder with Momentary Switch (SW3) The rotary encoder can be turned clockwise for an up count or counter-clockwise for a down count. The encoder also features a momentary switch that allows you to zero the counter. The rotary encoder can be disabled from the processor by using the rotary encoder enable switch (SW4). See “Rotary Encoder Enable Switch (SW4)” for more information. Rotary Encoder Enable Switch (SW4) The rotary encoder enable switch (SW4) disconnects the rotary encoder signals from the GPIO pins of the processor. When the switch is OFF, its associated GPIO signals can be used on the host interface (see Table 2-13). Table 2-13. Rotary Encoder Enable Switch (SW4) EZ-KIT Lite Signal SW4 Switch Position (Default) Processor Signal HPACK/CNTCUD 1 (ON) PH4 HPA/CNTCDG 2 (ON) PH3 #HPCE/CNTCZM 3 (ON) PG5 N/A 4 (OFF) N/A ADSP-BF548 EZ-KIT Lite Evaluation System Manual 2-17 Push Button and Switch Settings Push Button Enable Switch (SW5) The push button enable switch (SW5) disconnects the associated push button circuit from the GPIO pins of the processor. When SW5 is OFF, the associated GPIO signals can be used on the expansion interface, host interface, or STAMP (0.1” IDC) headers (see Table 2-14). Table 2-14. Push Button Enable Switch (SW5) Push Button EZ-KIT Lite Signal SW5 Switch Position (Default) Processor Signal PB1 (SW13) PUSHBUTTON1 1 (ON) PB8 PB2 (SW12) PUSHBUTTON2 2 (ON) PB9 PB3 (SW11) PUSHBUTTON3 3 (ON) PB10 PB4 (SW10) PUSHBUTTON4/HPWAIT 4 (ON) PB11 CAN0 Enable Switch (SW6) The CAN0 enable switch (SW6) disconnects the CAN0 signals from the GPIO pins of the processor and deactivates the CAN0 transceiver (U21). When SW6 is in the default positions (shown in Table 2-15), the switch connects to CAN0; otherwise, the associated GPIO signal of SW6 can be used as a STAMP GPIO. Table 2-15. CAN0 Enable Switch (SW6) CAN0 Signal EZ-KIT Lite Signal SW6 Switch Position (Default) Processor Signal ENABLE N/A 1 (OFF) N/A STANDBY N/A 2 (OFF) N/A ERROR CAN0_ERR 3 (ON) PC0 RECEIVE DATA CAN0RX 4 (ON) PG13 2-18 ADSP-BF548 EZ-KIT Lite Evaluation System Manual ADSP-BF548 EZ-KIT Lite Hardware Reference UART Enable Switch (SW7) The UART enable switch (SW7) disconnects the UART1 signals from the GPIO pins of the processor. When the switch is OFF, the associated GPIO signal of SW7 can be used elsewhere on the board (see Table 2-16). Table 2-16. UART Enable Switch (SW7) EZ-KIT Lite Signal SW7 Switch Position (Default) Processor Signal UART1CTS 1 (ON) PE10 UART1_RX 2 (ON) PH1 UART1RTS 3 (ON) PE9 N/A 4 (OFF) N/A Audio Loopback Test Switch (SW8) The audio loopback test switch (SW8) connects the inputs signals of the audio interface to the output signals. This allows the EZ-KIT Lite to be placed in a loopback test mode for signal and circuit continuity and functionality (see “Power-On-Self Test” on page 1-33). All positions of the switch should be ON when running POST. In all other cases, the switch should be kept OFF. Table 2-17 shows the default settings for the SW8 switch. Table 2-17. Audio Loopback Test Switch (SW8) EZ-KIT Lite Input Signal SW8 Switch Position (Default) EZ-KIT Lite Output Signal LINEIN_L 1 (OFF) SURROUT_L LINEIN_R 2 (OFF) SURROUT_R LINEIN_L 3 (OFF) CENTER_OUT LINEIN_R 4 (OFF) LFE_OUT MIC_L 5 (OFF) LINEOUT_L MIC_R 6 (OFF) LINEOUT_R ADSP-BF548 EZ-KIT Lite Evaluation System Manual 2-19 Push Button and Switch Settings Reset Push Button (SW9) The reset push button (SW9) resets all of the ICs on the board. One exception is the USB interface chip. The chip is not reset when the push button is pressed after the USB cable has been plugged in and communication with the PC has been initialized correctly. After USB communication has been initialized, the only way to reset the USB chip is by powering down the board. Programmable Flag Push Buttons (SW10–13) Four momentary push buttons (SW10–13) are provided for general-purpose user input. The buttons connect to the PB11–8 programmable flag pins of the processor. The push buttons are active high and, when pressed, send a high (1) to the processor. The push button enable switch (SW5) disconnects the push buttons from the corresponding PB signal (refer to “Push Button Enable Switch (SW5)” on page 2-18 for more information). The programmable flag signals and associated switches are shown in Table 2-18. Table 2-18. Programmable Flag Switches Push Button EZ-KIT Lite Signal Processor Signal PB1 (SW13) PUSHBUTTON1 PB8 PB2 (SW12) PUSHBUTTON2 PB9 PB3 (SW11) PUSHBUTTON3 PB10 PB4 (SW10) PUSHBUTTON4/HPWAIT PB11 2-20 ADSP-BF548 EZ-KIT Lite Evaluation System Manual ADSP-BF548 EZ-KIT Lite Hardware Reference LCD/PPI Configuration Switch (SW14) The LCD/PPI configuration switch (SW14) connects the GPIO pins of the processor to the LCD or PPI configuration pins: • SW14 position 1 connects PB4 to the data available output (DAV) of the touchscreen controller (U9). • position 2 connects PB5 to the pen interrupt output (PENIRQ) of the touchscreen controller (U9). • SW14 • SW14 SW14 position 3 connects PB2 to the PPI1CLK multiplexter (U20). This allows you to connect the PPI1CLK to the clock signal generated on the expansion interface or the on-board 27 MHz oscillator (U19). position 4 connects PE3 to the DISP signal of the LCD via the LCD data connector (P15). When SW14 is OFF, its associated GPIO signals can be used on the expansion interface (see Table 2-19). Table 2-19. LCD/PPI Configuration Switch (SW14) EZ-KIT Lite Signal SW14 Switch Position (Default) Processor Signal LCD_DAV 1 (ON) UART2TX/PB4 LCD_IRQ 2 (ON) UART2RX/PB5 PPI1_SEL 3 (ON) UART3RTS/PB2 LCD_DISP 4 (ON) PE3 ADSP-BF548 EZ-KIT Lite Evaluation System Manual 2-21 Push Button and Switch Settings CAN1 Enable Switch (SW15) The CAN1 enable switch (SW15) disconnects the CAN1 signals from the GPIO pins of the processor and deactivates the CAN1 transceiver (U33). When SW15 is in the default positions (shown in Table 2-20), the switch connects to CAN1. When otherwise, the associated GPIO signal of SW15 can be used as a STAMP GPIO. Table 2-20. CAN1 Enable Switch (SW15) CAN1 Signal EZ-KIT Lite Signal SW15 Switch Position (Default) Processor Signal ENABLE N/A 1 (OFF) N/A STANDBY N/A 2 (OFF) N/A ERROR CAN1_ERR 3 (ON) PC5 RECEIVE DATA CAN1RX 4 (ON) PG15 Peripheral Control Enable (SW16) The peripheral control enable (SW16) connects the GPIO pins of the processor to the enable pins of the audio codec, USB regulator, or Ethernet controller: 2-22 position 1 connects PB3 to the reset pin of the audio codec (U11). This allows the audio codec to be reset via software. • SW16 • position 2 connects PE7 to the 5 volt VBUS USB regulator (VR1) and FET switch (U39). This allows the software to control the enable pins of both the regulator and the FET switch if the VBUS line is powered with 5 volts by some other host device. When in USB OTG host mode, the signal needs to be a logic 1. This will cause the EZ-KIT to supply the 5V to the VBUS line. When in USB OTG device mode, the signal needs to be a logic 0. This will allow the host device to power the VBUS line and allow the Blackfin processor to remain in device mode. SW16 ADSP-BF548 EZ-KIT Lite Evaluation System Manual ADSP-BF548 EZ-KIT Lite Hardware Reference • SW16 • SW16 position 3 connects PE8 to the interrupt signal of the Ethernet controller (U14). position 4 connects PB11 to the reset of burst flash memory. This allows the software to reset the burst flash. In order to use this signal as a reset for burst flash, SW5.4 needs to be set OFF. When the signal is used as a reset for the burst flash, the HOSTWAIT signal and PB4 are not be available. By default the switch is set to OFF and is not used. When the switch is OFF, its associated GPIO signals can be used on the expansion interface (see Table 2-21). Table 2-21. Peripheral Control Enable (SW16) EZ-KIT Lite Signal SW16 Switch Position (Default) Processor Signal AUDIO_RESET 1 (ON) UART3CTS/PB3 USB_VRSEL 2 (ON) PE7 LAN_IRQ 3 (ON) PE8 NOR_RESET 4 (OFF) PB11 (PUSHBUTTON4/HPWAIT) LCD Module Configuration (SW17) The LCD module configuration switch (SW17) is used to set up the LCD module in 24-bit mode, 18-bit mode, or to disconnect the LCD in order to use the processor EPPI signals on other areas of the board. The default setting is for the LCD module to operate in 24-bit mode; the corresponding switch settings are shown in Table 2-22. To operate the LCD module in 18-bit mode, set SW17 as shown in Table 2-23. ADSP-BF548 EZ-KIT Lite Evaluation System Manual 2-23 Push Button and Switch Settings In order to disconnect the LCD module so that PPI1 or PPI0 can be used elsewhere on the board, follow the settings in Table 2-24. When the switch is OFF, its associated PPI1 and PPI0 signals can be used on the expansion interface, host interface, or STAMP PPI1 header. Table 2-22. LCD Module Configuration in 24-bit Mode (SW17) SW17 Switch Position (Default) Processor Signal EZ-KIT Lite Signal 1 (ON) PPI0CLK PPI0FS1 PPI0FS2 LCD_PPI0CLK LCD_PPI0FS1 LCD_PPI0FS2 2 (OFF) PPI0D[0–17] LCD_R[2–7] LCD_G[2–7] LCD_B[2–7] 3 (ON) PPI0D[0–17] PPI1D[0–5]/HPD[8–13] LCD_R[0–7] LCD_G[0–7] LCD_B[0–7] 4 (OFF) N/A N/A Table 2-23. LCD Module Configuration in 18-bit Mode (SW17) SW17 Switch Position Processor Signal EZ-KIT Lite Signal 1 (ON) PPI0CLK PPI0FS1 PPI0FS2 LCD_PPI0CLK LCD_PPI0FS1 LCD_PPI0FS2 2 (ON) PPI0D[0–17] LCD_R[2–7] LCD_G[2–7] LCD_B[2–7] 3 (OFF) PPI0D[0–17] PPI1D[0–5]/HPD[8–13] LCD_R[0–7] LCD_G[0–7] LCD_B[0–7] 4 (OFF) N/A N/A 2-24 ADSP-BF548 EZ-KIT Lite Evaluation System Manual ADSP-BF548 EZ-KIT Lite Hardware Reference Table 2-24. LCD Module Configuration Disconnected (SW17) SW17 Switch Position Processor Signal EZ-KIT Lite Signal 1 (OFF) PPI0CLK PPI0FS1 PPI0FS2 LCD_PPI0CLK LCD_PPI0FS1 LCD_PPI0FS2 2 (OFF) PPI0D[0–17] LCD_R[2–7] LCD_G[2–7] LCD_B[2–7] 3 (OFF) PPI0D[0–17] PPI1D[0–5]/HPD[8–13] LCD_R[0–7] LCD_G[0–7] LCD_B[0–7] 4 (OFF) N/A N/A Jumpers This section describes functionality of the configuration jumpers. Figure 2-3 shows the jumper locations. Figure 2-3. Configuration Jumper Locations ADSP-BF548 EZ-KIT Lite Evaluation System Manual 2-25 Jumpers UART1 Loopback Jumper (JP1) The UART1 loopback jumper (JP1) is used to place the UART1 port of the processor in a loopback condition. The jumper connects the UART1_TX line of the processor to the UART1_RX signal of the processor. The jumper is required only when the power-on-self-test (POST) is used to test the serial port interface. The jumper setting is shown in Table 2-25. Table 2-25. UART1 Loopback Jumper (JP1) JP1 Setting Mode OFF Normal operation. UART1_TX to UART1_RX is disconnected (default) ON Loopback operation. Connects UART1_TX to UART1_RX SPI1 Enable Jumper (JP2) The SPI1 enable jumper (JP2) activates a buffer and enables the SPI1 port of the processor to be connected to the STAMP headers. The default for these signals is the buffer being disabled, and the SPI1 port not connecting to the STAMP headers. Be aware that using the SPI1 port and its associated signals will disable the user LEDs (LED1–6) because the port and LEDs share the same pins on the processor. The jumper setting is shown in Table 2-26. Table 2-26. SPI1 Enable Jumper (JP2) JP2 Setting Mode OFF SPI1 port deactivated (default) ON SPI1 2-26 port activated ADSP-BF548 EZ-KIT Lite Evaluation System Manual ADSP-BF548 EZ-KIT Lite Hardware Reference Ethernet Speed Select Jumper (JP3) The Ethernet speed select jumper (JP3) selects the speed of the LAN9218 Ethernet controller. No jumper is required by default. The default setting operates the LAN9218 (U14) in 100 Mbps mode and enables auto negotiation. When JP3 is populated, the controller operates in 10 Mbps mode with auto negotiation disabled. The jumper setting is shown in Table 2-27. Table 2-27. Ethernet Speed Select Jumper (JP3) JP3 Setting Mode OFF LAN9218 in 100 Mbps mode; auto negotiation ON (default) ON LAN9218 in 10 Mbps mode; auto negotiation OFF VDDINT Power Jumper (JP4) The VDDINT power jumper (JP4) is used to measure the core voltage and current supplied to the processor core. By default JP4 is ON, and the power flows through the two-pin IDC header. To measure power, remove the jumper and measure the voltage across the 0.05 ohm resistor. Once the voltage is measured, the power can be calculated. For more information, refer to “Power Measurements” on page 1-33. The jumper setting is shown in Table 2-28. Table 2-28. VDDINT Power Jumper (JP4) JP4 Setting Mode ON No power measurement (default) OFF For power measurement ADSP-BF548 EZ-KIT Lite Evaluation System Manual 2-27 Jumpers VDDEXT Power Jumper (JP5) The VDDEXT power jumper (JP5) is used to measure the processor’s I/O voltage and current. By default JP5 is ON, and the power flows through the two-pin IDC header. To measure power, remove the jumper and measure the voltage across the 0.05 ohm resistor. Once the voltage is measured, the power can be calculated. For more information, refer to “Power Measurements” on page 1-33. The jumper setting is shown in Table 2-29. Table 2-29. VDDINT Power Jumper (JP5) JP5 Setting Mode ON No power measurement (default) OFF For power measurement VDDDDR Power Jumper (JP6) The VDDDDR power jumper (JP6) is used to measure the voltage and current supplied to the DDR interface of the processor. By default JP6 is ON, and the power flows through the two-pin IDC header. To measure power, remove the jumper and measure the voltage across the 0.05 ohm resistor. Once the voltage is measured, the power can be calculated. For more information, refer to “Power Measurements” on page 1-33. The jumper setting is shown in Table 2-30. Table 2-30. VDDDDR Power Jumper (JP6) JP6 Setting Mode ON No power measurement (default) OFF For power measurement 2-28 ADSP-BF548 EZ-KIT Lite Evaluation System Manual ADSP-BF548 EZ-KIT Lite Hardware Reference MOSI1 Out Jumper (JP7) The MOSI out jumper (JP7) connects the PG10/MOSI1 pin of the processor to the STAMP headers. To flow data from the processor to the STAMP headers, connect the jumper. To flow data from the STAMP headers to the processor, do not populate the header but the JP8 jumper. Be aware that using the SPI1 port and its associated signals will disable the user LEDs (LED1–6) because the port and LEDs share the same pins on the processor. The jumper setting is shown in Table 2-31. Table 2-31. MOSI1 Out Jumper (JP7) JP7 Setting Mode OFF No connection between the MOSI1 of the processor to the STAMP headers (default) ON MOSI1 of the processor transmitting data to the STAMP headers MOSI1 In Jumper (JP8) The MOSI in jumper (JP8) connect the PG10/MOSI1 pin of the processor to the STAMP headers. To flow data to the processor from the STAMP headers, connect the jumper. To flow data to the STAMP headers from the processor, do not populate the header but the JP7 jumper. Be aware that using the SPI1 port and its associated signals disable the user LEDs (LED1–6) because the port and LEDs share the same pins on the processor. The jumper setting is shown in Table 2-32. Table 2-32. MOSI1 In Jumper (JP8) JP8 Setting Mode OFF No connection between the MOSI1 of the processor to the STAMP headers (default) ON MOSI1 of the processor receiving data from the STAMP headers ADSP-BF548 EZ-KIT Lite Evaluation System Manual 2-29 Jumpers USB OTG Power Jumper (JP11) The USB on-the-go (OTG) power jumper (JP11) connects the supply voltage for the USB OTG interface to the supply voltage of the USB interface of the processor. JP11 should always be populated. The jumper setting is shown in Table 2-33. Table 2-33. USB OTG Power Jumper (JP11) USB Power for JP11 Pins 1 and 3 JP11 Pins 2 and 4 ADSP-BF548 processor ON ON PPI1FS3 Pull-down Jumper (JP12) The PPI1FS3 pull-down jumper (JP12) connects the PPI1FS3 signal of the processor to GND via a pull-down resistor. The jumper should be used when the processor pin is being used for EPPI, and the PPIIFS3 pin is not used. The pull-down assures that the PPI1FS3 signal is not floating and is used for certain modes of the EPPI interface, in which the signal needs to be low. Be aware that installing this jumper while using the serial port (J6) will cause data communication errors on the UART1. By default JP12 is not populated. The jumper setting is shown in Table 2-34. Table 2-34. PPI1FS3 Pull-down Jumper (JP12) JP12 Setting Mode OFF No pull-down resistor to GND on PPIFS3/UART1_TX; Using the serial port J6 (default) ON Pull-down resistor connected to GND on PPIFS3/UART1_TX; Not using the serial port J6 2-30 ADSP-BF548 EZ-KIT Lite Evaluation System Manual ADSP-BF548 EZ-KIT Lite Hardware Reference LEDs This section describes the on-board LEDs. Figure 2-4 shows the LED locations. Figure 2-4. LED Locations User LEDs (LED1–6) Six LEDs connect to six general-purpose I/O pins of the processor (see Table 2-35). The LEDs are active high and are lit by writing a 1 to the correct PG signal. Table 2-35. User LEDs LED Reference Designator Processor Programmable Flag Pin LED1 PG6 LED2 PG7 LED3 PG8 ADSP-BF548 EZ-KIT Lite Evaluation System Manual 2-31 LEDs Table 2-35. User LEDs (Cont’d) LED Reference Designator Processor Programmable Flag Pin LED4 PG9 LED5 PG10 LED6 PG11 Power LED (LED7) When LED7 is lit (green), it indicates that power is being properly supplied to the board. Reset LED (LED8) When LED8 is lit, it indicates that the master reset of all the major ICs is active. The reset LED is controlled by the Analog Devices ADM708 supervisory reset circuit. You can assert the reset push button (SW9) to assert the master reset and to activate LED8. For more information, see “Reset Push Button (SW9)” on page 2-20. Ethernet Link/Activity LED (LED9) When LED9 is lit solid, it indicates that the SMSC LAN9218 (U14) chip detects a valid link. When transmit or receive activity is sensed, LED9 flashes as an activity indicator. For more information on the LED, refer to the LAN9218 data sheet provided by the product manufacturer. 2-32 ADSP-BF548 EZ-KIT Lite Evaluation System Manual ADSP-BF548 EZ-KIT Lite Hardware Reference Connectors This section describes connector functionality and provides information about mating connectors. The connector locations are shown in Figure 2-5. Figure 2-5. Connector Locations ADSP-BF548 EZ-KIT Lite Evaluation System Manual 2-33 Connectors Expansion Interface Connectors (J1–3) Three board-to-board connector footprints provide signals for most of the processor’s peripheral interfaces. The connectors are located at the bottom of the board. For more information, see “Expansion Interface” on page 1-32. For availability and pricing of the J1–3 connectors, contact Samtec. Part Description Manufacturer Part Number 90-position 0.05” spacing, SMT SAMTEC SFC-145-T2-F-D-A Mating Connector 90-position 0.05” spacing (through hole) SAMTEC TFM-145-x1 series 90-position 0.05” spacing (surface mount) SAMTEC TFM-145-x2 series 90-position 0.05” spacing (low cost) SAMTEC TFC-145 series Ethernet Connector (J4) Part Description Manufacturer Part Number RJ-45 Ethernet jack STEWART SS-6488-NF Mating Cable (shipped with EZ-KIT Lite) Cat 5E patch cable RANDOM PC10/100T-007 Cat 5E crossover cable RANDOM PC10/100TC-007 Mating Connector (shipped with EZ-KIT Lite) RJ-45 loopback connector 2-34 RANDOM RAN830 ADSP-BF548 EZ-KIT Lite Evaluation System Manual ADSP-BF548 EZ-KIT Lite Hardware Reference SD Memory Card Connector (J5) Part Description Manufacturer Part Number SD 9-pin connector ITT CANON CCM05-5777LFT T50 Mating Memory Card (shipped with EZ-KIT Lite) 256 MB SanDISK SDSDB-256-A10 RS-232 Connector (J6) Part Description Manufacturer Part Number DB9, female, right angle mount TYCO 5747844-4 Mating Cable 2m female-to-female cable DIGI-KEY AE1020-ND Power Connector (J7) The power connector provides all of the power necessary to operate the EZ-KIT Lite board. Part Description Manufacturer Part Number 2.5 mm power jack SWITCHCRAFT RAPC712X Mating Power Supply (shipped with EZ-KIT Lite) 7.5VDC@4A power supply CUI INC ADSP-BF548 EZ-KIT Lite Evaluation System Manual DTS075400UDC-P6P-DB 2-35 Connectors Dual Audio Connectors (J8 and J9) Part Description Manufacturer Part Number 3.5 mm dual stereo jack SWITCHCRAFT 35RAPC7JS Mating Cable (shipped with EZ-KIT Lite) 3.5mm male/male 6’ cable RANDOM 10A3-01106 Mating Headphone (shipped with EZ-KIT Lite) 3.5 mm stereo headphones KOSS 151225 UR5 Audio Connector (J10) Part Description Manufacturer Part Number 3.5 mm stereo jack SWITCHCRAFT RAPC712X Mating Cable (shipped with EZ-KIT Lite) 3.5mm male/male 6’ cable RANDOM 10A3-01106 Mating Headphone (shipped with EZ-KIT Lite) 3.5 mm stereo headphones KOSS 151225 UR5 CAN Connectors (J11 and J12) Part Description Manufacturer Part Number RJ11 4-pin modular jack TYCO 5558872-1 Mating Cable 4-conductor modular jack cable L-COM TSP3044 Mating Loopback Cable (shipped with EZ-KIT Lite) 4-conductor modular jack cable 2-36 RANDOM RAN290 ADSP-BF548 EZ-KIT Lite Evaluation System Manual ADSP-BF548 EZ-KIT Lite Hardware Reference Battery Holder (J13) Part Description Manufacturer Part Number 24 mm battery holder KEYSTONE 1025-7 Mating Battery (shipped with EZ-KIT Lite) 3V 1000MAH 24 mm LI-COIN PANASONIC CR2477 ATAPI Connector (J14) Part Description Manufacturer Part Number ATAPI 44-pin 22 x 2 mm SAMTEC ASP-130199-02 Mating Hard Drive (shipped with EZ-KIT Lite) 5V ATAPI hard disk drive TOSHIBA MK4032GAX Keypad Connector (P1) Part Description Manufacturer Part Number IDC header female SAMTEC SSW-109-01-TM-S Mating Keypad (shipped with EZ-KIT Lite) 4 x 4 keypad ACT COMPONENTS ADSP-BF548 EZ-KIT Lite Evaluation System Manual ACT-07-30008-000-R 2-37 Connectors Host Interface Connector (P3) The pinout of the P3 connector can be found in “ADSP-BF548 EZ-KIT Lite Schematic” on page B-1. Part Description Manufacturer Part Number IDC header SAMTEC TSW-116-26-T-D Mating Connector IDC socket SAMTEC TSW-116-01-T-D USB OTG Connector (P4) The pinout of the P4 connector can be found in “ADSP-BF548 EZ-KIT Lite Schematic” on page B-1. Part Description Manufacturer Part Number USB 5-pin mini AB MOLEX 56579-0576 Mating Cables (shipped with EZ-KIT Lite) 5-in-1 USB 2.0 cable JO-DAN INTERNAT GXQU-06 LCD Backlight Connector (P5) Part Description Manufacturer Part Number FPC 4-pin 0.5 mm KYOCERA ELCO 046298004000883+ Mating LCD Display Module (shipped with EZ-KIT Lite) 4” TFT LCD with touchscreen 2-38 SHARP LQ043T1DG01 ADSP-BF548 EZ-KIT Lite Evaluation System Manual ADSP-BF548 EZ-KIT Lite Hardware Reference SPORT2 Connector (P6) The pinout of the P6 connector can be found in “ADSP-BF548 EZ-KIT Lite Schematic” on page B-1. Part Description Manufacturer Part Number IDC header FCI 68737-434HLF Mating Connector IDC socket DIGI-KEY S4217-ND SPORT3 Connector (P7) The pinout of the P7 connector can be found in “ADSP-BF548 EZ-KIT Lite Schematic” on page B-1. Part Description Manufacturer Part Number IDC header FCI 68737-434HLF Mating Connector IDC socket DIGI-KEY S4217-ND PPI1 Connector (P8) The pinout of the P8 connector can be found in “ADSP-BF548 EZ-KIT Lite Schematic” on page B-1. Part Description Manufacturer Part Number IDC header FCI 68737-440HLF Mating Connector IDC socket DIGI-KEY ADSP-BF548 EZ-KIT Lite Evaluation System Manual S4220-ND 2-39 Connectors SPI Connector (P9) The pinout of the P9 connector can be found in “ADSP-BF548 EZ-KIT Lite Schematic” on page B-1. Part Description Manufacturer Part Number IDC header FCI 68737-420HLF Mating Connector IDC socket DIGI-KEY S4210-ND Two-Wire Interface Connector (P10) The pinout of the P10 connector can be found in “ADSP-BF548 EZ-KIT Lite Schematic” on page B-1. Part Description Manufacturer Part Number IDC header FCI 68737-420HLF Mating Connector IDC socket DIGI-KEY S4210-ND TIMERS Connector (P11) The pinout of the P11 connector can be found in “ADSP-BF548 EZ-KIT Lite Schematic” on page B-1. Part Description Manufacturer Part Number IDC header FCI 68737-410HLF Mating Connector IDC socket 2-40 DIGI-KEY S4205-ND ADSP-BF548 EZ-KIT Lite Evaluation System Manual ADSP-BF548 EZ-KIT Lite Hardware Reference UART3 Connector (P12) The pinout of the P12 connector can be found in “ADSP-BF548 EZ-KIT Lite Schematic” on page B-1. Part Description Manufacturer Part Number IDC header FCI 68737-410HLF Mating Connector IDC socket DIGI-KEY S4205-ND LCD Touchscreen Connector (P14) Part Description Manufacturer Part Number FPC 4-pin 1mm JST 04FMS-1.0SP-TF(LF)(SN ) Mating LCD Display Module (shipped with EZ-KIT Lite) 4” TFT LCD with touchscreen SHARP LQ043T1DG01 LCD Data Connector (P15) Part Description Manufacturer Part Number FPC 40-pin 0.5mm HIROSE FH12-40S-0.5SH(55) Mating LCD Display Module (shipped with EZ-KIT Lite) 4” TFT LCD with touchscreen SHARP ADSP-BF548 EZ-KIT Lite Evaluation System Manual LQ043T1DG01 2-41 Connectors USB Debug Agent Connector (ZJ1) The USB debug agent connector is the connecting point for the JTAG USB debug agent interface. The JTAG header (ZP4) should not be used whenever ZJ1 and its mating cable are used to communicate to the processor via CCES or VisualDSP++. JTAG Connector (ZP4) The JTAG header is the connecting point for a JTAG in-circuit emulator pod. When an emulator connects to the JTAG header, the USB debug interface is disabled. Pin 3 is missing to provide keying. Pin 3 in the mating connector should have a plug. When using an emulator with the EZ-KIT Lite board, follow the connection instructions provided with the emulator. 2-42 ADSP-BF548 EZ-KIT Lite Evaluation System Manual A ADSP-BF548 EZ-KIT LITE BILL OF MATERIALS The bill of materials corresponds to “ADSP-BF548 EZ-KIT Lite Schematic” on page B-1. Ref. Qty. Description Reference Designator Manufacturer 1 2 74LVC14A SOIC14 U10,U30 TI 74LVC14AD 2 1 IDT74FCT3244 APY SSOP20 U29 IDT IDT74FCT3244APYG 3 1 24.576MHZ OSC005 Y1 EPSON MA-505 24.5760M-C3:ROHS 4 1 25MHZ OSC005 Y3 EPSON MA-505 25.0000 MHZ 5 1 32.768KHZ OSC008 Y2 EPSON MC-156-32.7680KAA0:ROHS 6 1 25MHZ OSC003 U7 EPSON SG-8002CA MP 7 2 SN74LVC1G08 SOT23-5 U25,U31 TI SN74LVC1G08DBVR 8 2 TJA1041 SOIC14 U21,U33 PHILIPS TJA1041T 9 1 FDS9431A SOIC8 U28 FAIRCHILD FDS9431A 10 1 NAND02 TSOP48 U3 ST MICRO NAND02GW3B2CN6E 11 1 27MHZ OSC003 U19 EPSON SG-8002CA-MP ADSP-BF548 EZ-KIT Lite Evaluation System Manual Part Number A-1 A-2 Ref. Qty. Description Reference Designator Manufacturer Part Number 12 2 FDS9926A SOIC8 U22-23 MOUSER 512-FDS9926A 13 1 SI4411DY SO-8 U16 VISHAY Si4411DY-T1-E3 14 1 HX1188 ICS007 U15 DIGI-KEY 553-1340-ND 15 1 LAN9218 TQFP100 U14 SMSC LAN9218-MT 16 1 24MHZ OSC003 U13 EPSON SG-8002CA-MP 17 1 MT46V32M16 TSOP66 U1 MICRON MT46V32M16P-5B:F 18 1 BF548 PC28F128P33 “U5” U5 INTEL PC28F128P33T85 19 1 SN74LVC1G02 SOT23-5 U35 DIGI-KEY 296-11597-1-ND 20 2 SN74CB3Q162 11 TSSOP56 U37-38 DIGI-KEY 296-17629-1-ND 21 1 SN74CB3Q324 5 TSSOP20 U36 DIGI-KEY 296-19130-1-ND 22 1 MIC2025-1 SOIC8 U39 DIGI-KEY 576-1057-ND 23 1 93LC46A SOIC8 U12 MICROCHIP 93LC46A-E/SN 24 1 BF548 M25P16 “U6” U6 ST MICRO M25P16-VMW6G 25 1 74CBTLV3244 TSSOP20 U26 IDT IDT74CBTLV3244PGG 26 2 SN74CB3T1621 0 TSSOP48 U4,U24 DIGI-KEY 296-19147-1-ND 27 1 ADM708SARZ SOIC8 U27 ANALOG DEVICES ADM708SARZ ADSP-BF548 EZ-KIT Lite Evaluation System Manual ADSP-BF548 EZ-KIT Lite Bill Of Materials Ref. Qty. Description Reference Designator Manufacturer Part Number 28 3 ADP3336ARMZ MSOP8 VR1-2,VR5 ANALOG DEVICES ADP3336ARMZ-REEL7 29 1 ADG752BRTZ SOT23-6 U20 ANALOG DEVICES ADG752BRTZ-REEL 30 1 ADM3202ARN Z SOIC16 U32 ANALOG DEVICES ADM3202ARNZ 31 1 ADSP-BF548 MBGA400 U2 ANALOG DEVICES ADSP-BF548BBCZ-5X 32 1 ADP1864AUJZ SOT23-6 VR3 ANALOG DEVICES ADP1864AUJZ-R7 33 1 ADP1823 LFCSP32 VR7 ANALOG DEVICES ADP1823ACPZ-R7 34 1 AD7877 LFCSP32 U9 ANALOG DEVICES AD7877ACPZ-500RL7 35 1 AD1980 LQFP48 U11 ANALOG DEVICES AD1980JSTZ 36 1 ADP1611 MSOP8 VR8 ANALOG DEVICES ADP1611ARMZ-R7 37 1 ADP1715 MSOP8 VR4 ANALOG DEVICES ADP1715ARMZ-R7 38 1 PWR 2.5MM_JACK CON005 J7 SWITCHCRAFT RAPC712X 39 3 .05 45X2 CON019 J1-3 SAMTEC SFC-145-T2-F-D-A 40 1 DIP8 SWT016 SW2 C&K TDA08H0SB1 41 1 DIP6 SWT017 SW8 CTS 218-6LPST 42 8 DIP4 SWT018 SW4-7,SW14-17 ITT TDA04HOSB1 43 1 DB9 9PIN DB9F J6 TYCO 5747844-4 ADSP-BF548 EZ-KIT Lite Evaluation System Manual A-3 A-4 Ref. Qty. Description Reference Designator Manufacturer Part Number 44 2 RJ11 4PIN CON039 J11-12 TYCO 5558872-1 45 7 IDC 2X1 IDC2X1 JP2-8 FCI 90726-402HLF 46 2 IDC 2X1 IDC2X1 JP1,JP12 FCI 90726-402HLF 47 2 IDC 5X2 IDC5X2 P11-12 FCI 68737-410HLF 48 2 IDC 10X2 IDC10X2 P9-10 BURG-FCI 54102-T08-10LF 49 2 IDC 17X2 IDC17X2 P6-7 BURG-FCI 54102-T08-17LF 50 1 IDC 20X2 IDC20X2 P8 BURG-FCI 54102-T08-20LF 51 1 IDC 2X2 IDC2X2 JP11 FCI 68737-404HLF 52 1 3.5MM STEREO_JACK CON001 J10 DIGI-KEY CP1-3525NG-ND 53 1 5A RESETABLE FUS005 F1 MOUSER 650-RGEF500 54 1 ROTARY SWT023 SW1 DIGI-KEY 563-1047-ND 55 1 ROTARY_ENC ODER SWT022 SW3 CTS 290UAB0R201B2 56 2 3.5MM DUAL_STERE O CON050 J8-9 SWITCHCRAFT 35RAPC7JS 57 1 SD_CONN 9PIN CON051 J5 DIGI-KEY 401-1954-ND 58 1 IDC 16x2 IDC16x2 P3 SAMTEC TSW-116-26-T-D ADSP-BF548 EZ-KIT Lite Evaluation System Manual ADSP-BF548 EZ-KIT Lite Bill Of Materials Ref. Qty. Description Reference Designator Manufacturer Part Number 59 1 USB_MINI-AB 5PIN CON052 P4 MOLEX 56579-0576 60 1 BATT_HOLDE R 24MM CON054 J13 KEYSTONE 1025-7 61 1 RJ45 8PIN CON_RJ45_12 P J4 DIGI-KEY 380-1022-ND 62 1 ATAPI44 44PIN 22x2_2MM J14 SAMTEC ASP-130199-02 63 5 MOMENTARY SWT024 SW9-13 PANASONIC EVQ-Q2K03W 64 1 FPC 40PIN CON057 P15 HIROSE FH12-40S-0.5SH(55) 65 1 FPC 4PIN CON060 P5 KYOCERA ELCO 046298004000883+ 66 1 FPC 4PIN CON061 P14 JST 04FMS-1.0SP-TF(LF)(SN) 67 1 IDC 9X1 IDC9X1 P1 SAMTEC SSW-109-01-TM-S 68 1 0 1/4W 5% 1206 R76 KOA 0.0ECTRk7372BTTED 69 7 YELLOW LED001 LED1-6,LED9 PANASONIC LN1461C 70 3 22PF 50V 5% 0805 C115-116,C225 AVX 08055A220JAT 71 4 0.1UF 50V 10% 0805 C30-32,C266 AVX 08055C104KAT 72 1 1M 1/10W 5% 0805 R78 VISHAY CRCW08051M00JNEA 73 7 100 1/10W 5% 0805 R34-36,R100-101, R103,R138 VISHAY CRCW0805100RJNEA ADSP-BF548 EZ-KIT Lite Evaluation System Manual A-5 A-6 Ref. Qty. Description Reference Designator Manufacturer Part Number 74 11 600 100MHZ 200MA 0603 FER1-10,FER20 DIGI-KEY 490-1014-2-ND 75 5 600 100MHZ 500MA 1206 FER11-12,FER15-17 STEWARD HZ1206B601R-10 76 7 1UF 16V 10% 0805 C129,C139,C203205,C278-279 KEMET C0805C105K4RAC TU 77 2 30PF 100V 5% 1206 C143-144 AVX 12061A300JAT2A 78 1 10UH 20% IND001 L1 TDK 445-2014-1-ND 79 4 0 1/10W 5% 0805 R147,R216,R227, R259 VISHAY CRCW08050000Z0EA 80 1 190 100MHZ 5A FER002 FER19 MURATA DLW5BSN191SQ2 81 2 1A ZHCS1000 SOT23-312 D5,D21 ZETEX ZHCS1000TA pb-free 82 6 22 125MW 5% RNS001 RN11-16 CTS 744C083220JP 83 4 1UF 10V 10% 0805 C210,C220-222 AVX 0805ZC105KAT2A 84 20 10UF 6.3V 10% 0805 C9,C26,C49,C60, C67,C74,C84,C122123,C149,C152, C167,C206,C208, C232-233,C235-237, C255 AVX 08056D106KAT2A 85 5 4.7UF 6.3V 10% 0805 C138,C140,C198, C202,C209 AVX 08056D475KAT2A ADSP-BF548 EZ-KIT Lite Evaluation System Manual ADSP-BF548 EZ-KIT Lite Bill Of Materials Ref. Qty. Description Reference Designator Manufacturer Part Number 86 38 0.1UF 10V 10% 0402 C1-2,C25,C27,C96, C109,C114,C119121,C124-125,C132, C134,C142,C153166,C175,C177-179, C240,C256,C275277 AVX 0402ZD104KAT2A 87 104 0.01UF 16V 10% 0402 C3-8,C10-19,C2324,C33-48,C50-59, C61-66,C68-73,C7583,C85-92,C112113,C130-131,C136137,C141,C148, C150-151,C170-171, C180,C184-186, C188,C192,C195197,C211,C229-230, C243-244,C249-250, C257-259 AVX 0402YC103KAT2A 88 64 10K 1/16W 5% 0402 R8-13,R16-19,R26, R29,R55-56,R60, R77,R95,R108-111, R120-123,R131-133, R148,R158,R161163,R166,R168, R171,R173,R178, R182,R187,R198, R200-203,R206, R209,R213-214, R222-225,R229-230, R248-249,R254, R257,R273-275, R282,R284 VISHAY CRCW040210K0FKED 89 9 4.7K 1/16W 5% 0402 R43,R45-49,R65, R143,R212 VISHAY CRCW04024K70JNED ADSP-BF548 EZ-KIT Lite Evaluation System Manual A-7 A-8 Ref. Qty. Description Reference Designator Manufacturer Part Number 90 32 0 1/16W 5% 0402 R20,R30,R57-59, R61,R146,R149, R172,R174-177, R205,R207,R210211,R215,R232-243, R278-279 PANASONIC ERJ-2GE0R00X 91 4 1.2K 1/16W 5% 0402 R139-140,R276-277 PANASONIC ERJ-2GEJ122X 92 7 22 1/16W 5% 0402 R151-154,R169-170, R283 PANASONIC ERJ-2GEJ220X 93 20 33 1/16W 5% 0402 R7,R14,R21,R27-28, R66,R244-247,R250253,R255,R268-272 VISHAY CRCW040233R0JNEA 94 2 18PF 50V 5% 0805 C28-29 AVX 08055A180JAT2A 95 6 100UF 10V 10% C CT1-3,CT5,CT8-9 AVX TPSC107K010R0075 96 2 64.9K 1/10W 1% 0805 R69,R165 VISHAY CRCW080564K9FKEA 97 2 210.0K 1/4W 1% 0805 R68,R164 VISHAY CRCW0805210KFKEA 98 1 0.022UF 50V 5% 0805 C145 AVX 08055C223JAT2A 99 10 49.9 1/10W 1% 0805 R83-92 DIGI-KEY 311-49.9CRCT-ND 100 6 0.1UF 16V 10%0603 C189,C260,C264265,C272,C274 AVX 0603YC104KAT2A 101 9 1UF 16V 10% 0603 C94,C103-104,C118, C187,C215-216, C241-242 PANASONIC ECJ-1VB1C105K 102 1 4.7UF 25V 20% 0805 C102 AVX 0805ZD475KAT2A ADSP-BF548 EZ-KIT Lite Evaluation System Manual ADSP-BF548 EZ-KIT Lite Bill Of Materials Ref. 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Description Reference Designator Manufacturer Part Number 103 1 68PF 50V 5% 0603 C200 AVX 06035A680JAT2A 104 11 470PF 50V 5% 0603 C93,C97-101,C105106,C110-111,C199 AVX 06033A471JAT2A 105 1 220UF 6.3V 20% D2E CT4 SANYO 10TPE220ML 106 3 10K 1/10W 5% 0603 R99,R263-264 VISHAY CRCW060310K0JNEA 107 1 10M 1/10W 5% 0603 R15 VISHAY CRCW060310M0FNEA 108 3 100K 1/10W 5% 0603 R188-189,R261 VISHAY CRCW0603100KJNEA 109 9 330 1/10W 5% 0603 R119,R124-130, R141 VISHAY CRCW0603330RJNEA 110 1 1M 1/10W 5% 0603 R67 VISHAY CRCW06031M00FNEA 111 2 0 1/10W 5% 0603 R73,R156 PHYCOMP 232270296001L 112 8 10 1/10W 5% 0603 R102,R104,R134137,R218,R220 VISHAY CRCW060310R0JNEA 113 2 75.0K 1/16W 1% 0603 R71,R179 VISHAY CRCW060375K0FKEA 114 2 1K 1/10W 5% 0603 R37,R42 DIGI-KEY 311-1.0KGRTR-ND 115 3 4700PF 16V 10% 0603 C168,C218,C226 DIGI-KEY 311-1083-2-ND 116 4 100PF 50V 5% 0603 C169,C172, C227-228 AVX 06035A101JAT2A 117 1 12.4K 1/10W 1% 0603 R80 DIGI-KEY 311-12.4KHRTR-ND 118 4 62.0 1/10W 1% 0603 R105-106,R219, R221 DIGI-KEY 311-62.0HRTR-ND ADSP-BF548 EZ-KIT Lite Evaluation System Manual A-9 Ref. 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Description Reference Designator Manufacturer Part Number 119 1 680PF 50V 5% 0603 C231 PANASONIC ECJ-1VC1H681J 120 2 75.0 1/10W 1% 0603 R93-94 DALE CRCW060375R0FKEA 121 2 270PF 50V 5% 0603 C95,C117 DIGI-KEY 311-1185-2-ND 122 2 1UF 6.3V 20% 0402 C107-108 PANASONIC ECJ-0EB0J105M 123 3 100 1/16W 5% 0402 R1,R50-51 DIGI-KEY 311-100JRTR-ND 124 1 390PF 25V 5% 0603 C261 AVX 06033A391FAT2A 125 1 24.9K 1/10W 1% 0603 R155 DIGI-KEY 311-24.9KHTR-ND 126 6 1.05K 1/16W 1% 0603 R74-75,R81,R96-98 PANASONIC ERJ-3EKF1051V 127 4 10UF 10V 10% 0805 C135,C193,C271, C273 PANASONIC ECJ-2FB1A106K 128 1 20.0K 1/16W 1% 0603 R266 PANASONIC ERJ-3EKF2002V 129 4 0.05 1/2W 1% 1206 R157,R192-194 SEI CSF 1/2 0.05 1%R 130 3 10UF 16V 10% 1210 C201,C234,C238 AVX 1210YD106KAT2A 131 1 GREEN LED001 LED7 PANASONIC LN1361CTR 132 1 RED LED001 LED8 PANASONIC LN1261CTR 133 2 1000PF 50V 5% 1206 C190-191 AVX 12065A102JAT2A 134 1 255.0K 1/10W 1% 0603 R160 VISHAY CRCW06032553FK A-10 ADSP-BF548 EZ-KIT Lite Evaluation System Manual ADSP-BF548 EZ-KIT Lite Bill Of Materials Ref. Qty. Description Reference Designator Manufacturer Part Number 135 1 80.6K 1/10W 1% 0603 R159 DIGI-KEY 311-80.6KHRCT-ND 136 1 200MA BAT54A SOT23D D12 MOUSER 512-BAT54A 137 2 200MA BAT54 SOT23D D10-11 MOUSER 512-BAT54 138 1 8.2UH 20% IND012 L4 COILCRAFT MSS6132-822ML 139 1 10UH 20% IND012 L3 COILCRAFT MSS6132-103ML 140 2 1.1K 1/16W 1% 0402 R191,R208 PANASONIC ERJ-2RKF1101X 141 1 18K 1/16W 5% 0402 R183 DIGI-KEY 311-18KJRCT-ND 142 1 820 1/16W 5% 0402 R184 DIGI-KEY 311-820JRCT-ND 143 1 12.0K 1/16W 1% 0402 R79 DIGI-KEY 311-12.0KLRCT-ND 144 1 430 1/16W 1% 0402 R180 DIGI-KEY 311-430LRCT-ND 145 1 1200PF 50V 10% 0402 C219 DIGI-KEY 490-1304-1-ND 146 1 82PF 50V 5% 0402 C217 DIGI-KEY 490-1290-1-ND 147 2 22000PF 25V 10% 0402 C223,C239 DIGI-KEY 490-3252-1-ND 148 1 1500PF 50V 10% 0402 C224 DIGI-KEY 490-3245-1-ND 149 3 5A MBRS540T3G SMC D4,D13,D15 ON SEMI MBRS540T3G ADSP-BF548 EZ-KIT Lite Evaluation System Manual A-11 Ref. Qty. Description Reference Designator Manufacturer Part Number 150 3 15KV PGB1010603 0603 D1,D8-9 LITTLEFUSE PGB1010603MR 151 1 VARISTOR V5.5MLA 30A 0603 R142 LITTLEFUSE V5.5MLA0603 152 1 THERM 0.5A 0.4 1206 R72 LITTLEFUSE 1206L050-C 153 19 33 125MW 5% RNS001 RN1-10,RN17-25 CTS 744C083330JP 154 1 20MA MA3X717E DIO005 D16 PANASONIC MA3X717E 155 2 100MA MA27D27 DIO006 D2,D7 PANASONIC MA27D27 156 1 2A CZRF52C2V2 DIO007 D3 DIGI-KEY 641-1052-1-ND 157 1 2.5UH 30% IND013 L2 COILCRAFT MSS1038-252NLB 158 4 47.0K 1/16W 1% 0402 R38-41 ROHM MCR01MZPF4702 159 2 3.01K 1/16W 1% 0402 R52-53 ROHM MCR01MZPF3011 160 1 5.6K 1/16W 5% 0402 R25 PANASONIC ERJ-2GEJ562X 161 5 1.0K 1/16W 1% 0402 R2-3,R31-33 PANASONIC ERJ-2RKF1001X 162 2 1000PF 2000V 10% 1206 C146-147 AVX 1206GC102KAT1A 163 3 82 1/16W 5% 0402 R4-6 ROHM MCR01MZPJ820 A-12 ADSP-BF548 EZ-KIT Lite Evaluation System Manual ADSP-BF548 EZ-KIT Lite Bill Of Materials Ref. Qty. Description Reference Designator Manufacturer Part Number 164 1 1UF 50V 10% 0603 C267 DIGI-KEY 587-1257-1-ND 165 1 154.0K 1/16W 1% 0402 R70 DIGI-KEY 541-154KLCT-ND 166 1 10.0 1/10W 1% 0603 R82 DIGI-KEY 311-10.0HRTR-ND 167 3 10.0K 1/16W 1% 0402 R181,R185,R265 DIGI-KEY 541-10.0KLCT-ND 168 1 60.4 1/8W 1% 0805 R262 ROHM MCR10EZPF60R4 169 1 15uH 20% IND015 L5 COILCRAFT MSS4020-153ML 170 3 .5A B0540W SOD-123 D17-19 DIODES INC B0540W-7-F 171 1 .5A BZT52C33S SOD-323 D20 DIODES INC BZT52C33S-7-F 172 4 2.2UF 25V 10% 0805 C263,C268-270 DIGI-KEY 490-3331-1-ND 173 1 1.0 1/16W 1% 0402 R260 DIGI-KEY 541-1.00LCT-ND 174 1 34.0K 1/10W 1% 0603 R186 DIGI-KEY 541-34.0KHCT-ND ADSP-BF548 EZ-KIT Lite Evaluation System Manual A-13 A-14 ADSP-BF548 EZ-KIT Lite Evaluation System Manual A B C D 1 1 2 2 ADSP-BF548 EZ-KIT LITE SCHEMATIC 3 3 ANALOG DEVICES 4 Board No. C Date A B C Nashua, NH 03063 4 PH: 1-800-ANALOGD ADSP-BF548 EZ-KIT LITE TITLE Title Size 20 Cotton Road Rev A0206-2006 1.4C Sheet 9-12-2008_17:29 D 1 of 17 A B C D RN1 DDR_A[0:12] DDR_A0 DDR_A1 DDR_A2 DDR_A3 1 R1A 2 R2A 3 R3A 4 R4A R1B R2B R3B R4B 8 DDR_A0_R 7 DDR_A1_R 6 DDR_A2_R 5 DDR_A3_R 8 DDR_A4_R 7 DDR_A5_R 6 DDR_A6_R 5 DDR_A7_R DDR_A[0:12]_R 2.5V 33 RNS001 DDR_A5 DDR_A6 DDR_A7 DDR_A8 U2 DDR_A[0:12] DDR_A0 G19 E20 DDRD1 DDR_A2 DDRA1 G17 DDRD0 DDR_A1 DDRA0 DDR_A3 G18 DDR_A4 G16 DDR_A5 F19 DDRA4 DDRD4 DDRA5 DDRD5 C20 DDRD3 DDR_A7 DDRA3 D20 DDRD2 DDR_A6 DDRA2 DDRA6 E19 DDR_A10 B20 DDR_A11 F17 DDRD8 DDR_A9 DDRA8 F18 DDRD7 DDR_A12 DDRA9 DDRD10 DDRA11 DDRD11 D19 DDRA12 2 M19 DDR_D1 L19 DDR_D2 DDR_A11 L20 DDR_D3 L17 DDR_D4 K16 DDR_D5 DDR_D6 DDRCS0 K17 DDR_D7 DDRBA0 K19 DDR_D8 J20 DDR_D9 K18 DDR_D10 H20 DDR_D11 DDRBA1 DDRBA0 DDRBA1 J19 DDRCK1 J18 DDR_D14 J16 DDR_D15 DDR_D2 DDR_D3 D16 E16 DDRQM0 C18 DDRWE DDRCK1 DDRQM1 G20 DDRCAS D18 DDRCK2 DDRRAS DDRQS0 DDRCS1 DDRQS1 DDRCS0 DDRCKE DDR_D0 DDR_D13 J17 DDRQM1 DDRCK2 DDR_D[0:15] DDR_D1 DDRD15 DDRCK1 DDR_A[0:12]_R DDR_A0_R 29 DDR_A1_R 30 DDR_A2_R 31 33 RNS001 DDR_A3_R 32 RN3 DDR_A4_R 35 R3B R4B 1 R1A 2 R2A 3 R3A 4 R4A R1B R2B R3B R4B 8 DDR_A8_R DDR_A5_R 36 7 DDR_A9_R DDR_A6_R 37 6 DDR_A12_R DDR_A7_R 38 5 DDR_A11_R DDR_A8_R 39 DDR_A9_R 40 DDR_A10_R 28 1 R1A 2 R2A 3 R3A 4 R4A DDR_A11_R 41 DDR_A12_R 42 R1B R2B R3B R4B 8 DDRCS0_R 7 5 DDRBA1_R DDRBA0_R DDR_A10_R E18 DDR_D4 DDRCAS E17 DDR_D5 DDRRAS F20 DDR_D6 DDRQS0 DDR_D7 B19 H18 23 R4B 7 DDR_D1_R 6 DDR_D2_R 5 DDR_D3_R DDR_D[0:15]_R 22 DDRCAS_R 21 DDRWE_R 44 DDRCKE_R 20 DDRQM0_R 47 DDRQM1_R 45 1 R1A 2 R2A 3 R3A 4 R4A R1B R2B R3B R4B 8 DDR_D4_R 7 DDR_D5_R 6 DDR_D6_R 5 DDR_D7_R R1 100 0402 46 49 DDRCK1 DDR_D8 DDRCKE DDR_D9 ADSP-BF548 MBGA400 DDR_D10 DDR_D11 DDR_D13 DDR_D14 DDR_D15 4 DDR_D1_R 5 DDR_D2_R 7 DDR_D3_R 8 DDR_D4_R 10 DDR_D5_R 11 DDR_D6_R 13 DDR_D7_R 54 DDR_D8_R 56 DDR_D9_R 57 DDR_D10_R 59 DDR_D11_R 60 DDR_D12_R 62 DDR_D13_R 63 DDR_D14_R 65 DDR_D15_R DQ2 A3 DQ3 A4 DQ4 A5 DQ5 A6 DQ6 A7 DQ7 A8 DQ8 A9 DQ9 A10/AP DQ10 A11 DQ11 A12 DQ12 BA0 DQ14 BA1 DQ15 51 UDQS 16 LDQS CS RAS DDR_D[0:15]_R DDRQS1_R DDRQS0_R 2 CAS 19 DNU1 50 DNU2 WE CKE LDM 14 NC1 17 NC2 25 NC3 43 NC4 53 NC5 UDM CK CK1 VREF 2.5V 1 R1A 2 R2A 3 R3A 4 R4A R1B R2B R3B R4B 8 DDR_D8_R 7 DDR_D9_R 6 DDR_D10_R 5 DDR_D11_R 64 MB DDR (32M x 16) R2 1.0K 0402 C1 0.1UF 0402 RN8 DDR_D12 DDR_D0_R A2 MT46V32M16 TSOP66 33 RNS001 3 2 DQ0 DQ1 DDRCK1 RN7 DDRCS0 B18 R3B DDR_D0_R 33 RNS001 DDRQS1 C19 24 RN6 DDRWE F16 R2B 8 33 RNS001 DDRQM0 27 DDRBA1_R DDRCS0_R R1B A1 1 DQ13 26 DDRRAS_R 1 R1A 2 R2A 3 R3A 4 R4A A0 DDRBA0_R 6 33 RNS001 DDR_D12 H19 DDRCK1 U1 RN5 DDRD14 H16 DDRBA1 DDR_A10 DDRD12 H17 R2B 33 RNS001 K20 DDRD13 DDRBA0 R1B RN4 DDRD9 DDRA10 DDR_A9 DDR_D[0:15] DDR_D0 DDR_A12 DDRD6 DDRA7 DDR_A8 L18 1 R1A 2 R2A 3 R3A 4 R4A 6 12GNDQ1 52GNDQ2 58GNDQ3 64GNDQ4 34GNDQ5 48GND1 66GND2 GND3 DDR_A4 1 3 VDDQ19 VDDQ215 VDDQ355 VDDQ461 VDDQ5 1 VDD118 VDD233 VDD3 RN2 DDR_VREF 1 R1A 2 R2A 3 R3A 4 R4A R1B R2B R3B R4B 8 DDR_D12_R 7 DDR_D13_R 6 DDR_D14_R 5 DDR_D15_R 3 R3 1.0K 0402 C2 0.1UF 0402 33 RNS001 RN10 2.5V DDRQM0 DDRWE DDRCAS DDRRAS 1 R1A 2 R2A 3 R3A 4 R4A R1B R2B R3B R4B 8 7 6 5 DDRQM0_R DDRWE_R DDRCAS_R DDRRAS_R 33 RNS001 C9 10UF 0805 C4 0.01UF 0402 C11 0.01UF 0402 C7 0.01UF 0402 C6 0.01UF 0402 C8 0.01UF 0402 C5 0.01UF 0402 C10 0.01UF 0402 C3 0.01UF 0402 RN9 DDRCKE DDRQM1 U1 1 R1A 2 R2A 3 R3A 4 R4A R1B R2B R3B R4B 8 DDRCKE_R 7 6 DDRQM1_R 5 ANALOG DEVICES 33 RNS001 4 R28 33 0402 DDRQS0 R27 33 0402 DDRQS1 Size DDRQS1_R A B Board No. C Date C Nashua, NH 03063 4 PH: 1-800-ANALOGD ADSP-BF548 EZ-KIT LITE DDR INTERFACE Title DDRQS0_R 20 Cotton Road Rev A0206-2006 1.4C Sheet 9-12-2008_16:43 D 2 of 17 A B A5 C4 A6 C7 A7 C5 A8 D7 A9 A3 PH8/A4 D11 PI3/A13 A5 A15 B6 A16 A6 D12 PI4/A14 D13 PI5/A15 D14 PI6/A16 A17 B7 A18 A7 D7 D15 U5 A[1:24] PI8/A18 C15 D9 A17 D10 D14 D11 D15 D12 E15 D13 E14 D14 D17 D15 C8 A20 B8 A21 A8 C16 ABE1/NDALE PI9/A19 C17 ABE0/NDCLE ABE1/NDALE ABE0/NDCLE PI10/A20 PI11/A21 A22 A9 A23 C9 D10 AMS3 PI12/A22 B10 AMS2 PI13/A23 D9 AMS1 D8 PI14/A24 A10 AMS0 D12 AWE PI15/A25/NORCLK M16 PJ2/NANDRB# T20 PJ3/ATAPIDIOR# N17 PJ4/ATAPIDIOW# U20 PJ5/ATAPICS0# P18 PJ6/ATAPICS1# N16 PJ7/ATAPIDMACK# R19 A13 A5 B7 A20 C7 AOE ARE AWE R20 0 0402 CLKOUT R13 10K 0402 R200 10K 0402 NORWAIT A21 C8 A22 A8 A23 G1 A24 H8 B4 AMS0 NANDCE F8 ARE NANDRB U25 1 NOR_RESET G8 AWE 4 ATAPIDIOR D4 2 RESET C6 SN74LVC1G08 SOT23-5 ATAPIDIOW ATAPICS0 F6 AOE A4 ATAPICS1 ATAPIDMACK E6 NORCLK D1 A4 D2 A5 D3 A6 D4 A7 D5 A8 D6 A9 D7 A10 D8 A11 D9 A12 D10 A13 D11 A14 D12 A15 D13 A16 D14 A17 ATAPIIORDY 3.3V 3.3V D1 G3 D2 E4 D3 E5 D4 G5 D5 G6 D6 H7 D7 E1 D8 E3 D9 F3 D10 F4 D11 F5 D12 H5 D13 G7 D14 E7 D15 SW14: LCD/PPI Configuration Switch POS. A19 A20 WAIT F7 LCD_DAV (U9) ON J3.6 (Expansion Interface) SW14.2 UART2RX (U2) LCD_IRQ (U9) ON J3.5 (Expansion Interface) SW14.3 UART3RTS (U2) PPI1_SEL (U20) ON J3.32 (Expansion Interface) SW14.4 PE3 (U2) LCD_DISP (P15) ON J2.11 (Expansion Interface) 2 NORWAIT A22 NC1 A23 NC2 NC7 NC3 NC4 CE NC5 OE NC6 E8 B8 F1 G2 H1 3.3V B6 WE RST WP ADV R201 10K 0402 VPEN CLK UART2RX ABE0/NDCLE NANDRB NAND02 TSOP48 D0 R10 10K 0402 D1 R8 10K 0402 C19 0.01UF 0402 5 PPI1_SEL LCD_DISP 3.3V C13 0.01UF 0402 U6 D4 D5 SPI0MOSI D6 SPI0SCK 5 SI 6 SCK 1 CS 3 WP 7 HOLD R205 0 0402 D7 SPI0SEL1 3.3V 8 VCC 2 SO SPI0MISO GND 4 R12 10K 0402 C14 0.01UF 0402 ANALOG DEVICES C137 0.01UF 0402 16 Mb SPI FLASH U6 Date B Board No. C U25 C 20 Cotton Road Nashua, NH 03063 4 PH: 1-800-ANALOGD ADSP-BF548 EZ-KIT LITE EBIU Title Size U3 3 D3 M25P16 SO8W C12 0.01UF 0402 R203 10K 0402 D2 U5 A 4 LCD_IRQ R11 10K 0402 NAND C18 0.01UF 0402 6 D[0:7] 29 D0 30 D1 31 D2 32 D3 41 D4 42 D5 43 D6 44 D7 3.3V C17 0.01UF 0402 3 LCD_DAV R9 10K 0402 9 CE 8 OE 18 WE 17 AL 16 CL 19 WP 7 R/~B 3.3V C16 0.01UF 0402 7 SW14: LCD/PPI Configuration Switch BGH/PJ13 64MB DDR 32MB BURST FLASH ETHERNET NOT USED NOT USED 8 2 DIP4 SWT018 3.3V BG/PJ12 1 4 3.3V R65 4.7K 0402 R202 10K 0402 SW14 UART2TX PE3 DEVICE ALTERNATE FUNCTION / OFF MODE UART2TX (U2) UART3RTS BR/PJ11 DEFAULT SW14.1 3.3V ABE1/NDALE C15 0.01UF 0402 TO ATAPIPDIAG Memory Map 4 FROM A21 PC28F128P33 EBGA64 ATAPIINTRQ D15 E2 A18 ATAPIDMARQ ARE DDR Bank 0 ASYNC Memory Bank 0 ASYNC Memory Bank 1 ASYNC Memory Bank 2 ASYNC Memory Bank 3 C4 A19 AWE 0x01FF FFFF 0x21FF FFFF 0x2400 007F 0x27FF FFFF 0x2FFF FFFF D3 A12 A7 3.3V NANDCE 0x0000 0000 0x2000 0000 0x2400 0000 0x2800 0000 0x2C00 0000 A11 A18 AMS0 U3 BANK B3 C3 D8 R173 10K 0402 END A9 A10 D7 ADSP-BF548 MBGA400 START A3 A17 N19 PJ13/BGH# A8 A16 P20 PJ12/BG# C2 AMS1 M17 PJ11/BR# A2 A7 D0 A3 3 P19 ATAPIPDIAG A6 A2 D0 2 T19 PJ10/ATAPIIORDY D2 D[0:15] F2 1 P17 PJ9/ATAPIINTRQ D1 A5 A1 1 ON PJ8/ATAPIDMARQ# A4 AMS2 NORCLK N18 PJ1/NANDCE# 3 B9 R20 PJ0/AMCARDY/NORWAIT C1 B5 L16 CLKOUT A3 C5 12 VCC137 VCC2 B12 ARE B1 A15 13 36GND1 GND2 C10 AOE A1 A2 A14 AMS3 3.3V 2 A1 D8 PI7/A17 A19 A24 D10 PI2/A12 A14 B17 D9 PI1/A11 B5 D6 D8 PI0/A10 A13 A16 C14 PH13/A9 A4 D5 D7 C6 A12 D4 B16 D6 PH12/A8 B4 A15 D5 PH11/A7 A11 D3 D4 PH10/A6 A3 D2 B15 D3 PH9/A5 A10 B13 D2 GNDQ1 GNDQ2 D5 D5 D6 G4 B3 A4 D1 D1 32 MB BURST FLASH (16M x 16) VCCQ1 VCCQ2 VCCQ3 A2 A3 C13 D0 D H2 H6 A2 A1 D0 GND1 GND2 A2 3.3V D[0:15] D13 B2 H4 B2 VCC1 VCC2 1 A1 A6 H3 U2 A[1:24] C Rev A0206-2006 1.4C Sheet 9-12-2008_16:43 D 3 of 17 A B C D 3.3V 3.3V U2 A11 A12 CLKIN PB0/SCL1 XTAL PB1/SDA1 PB2/UART3RTS C141 0.01UF 0402 A14 R230 10K 0402 R15 10M 0603 U7 1 1 RTXI PB3/UART3CTS RTXO PB4/UART2TX R14 33 0402 4 VDD PB5/UART2RX/TMRACI2 PB6/UART3TX 3 OE OUT Y2 GND 25MHZ 2 OSC003 U7 B14 PB7/UART3RX/TMRACI3 1 4 TERM1 TERM2 2 3 NC1 NC2 C28 18PF 0805 PB8/SPI2SS/TMR0 PB9/SPI2SEL1/TMR1 32.768KHZ OSC008 PB10/SPI2SEL2/TMR2 C29 18PF 0805 PB11/SPI2SEL3/TMR3/HPWAIT PB12/SPI2SCK PB13/SPI2MOSI TFS2 DT2SEC DT2PRI RTC TSCLK2 RFS2 DR2SEC DR2PRI RSCLK2 TFS3 DT3SEC DT3PRI TSCLK3 2 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V RFS3 DR3SEC DR3PRI RSCLK3 U12 V12 W12 Y12 W11 V11 Y11 U11 U10 Y10 Y9 V10 Y8 W10 Y7 W9 PB14/SPI2MISO R171 10K 0402 R139 1.2K 0402 R140 1.2K 0402 R277 1.2K 0402 R276 1.2K 0402 LED3 LED4 LED5 BR/PJ11 LED6 NMI CAN0TX SCL0 CAN0RX SDA0 CAN1TX SCL1 CAN1RX V16 Y19 Y18 U15 P16 R18 Y13 W13 PA1/DT2SEC/TMR4 PC0/TFS0 PA2/DT2PRI PC1/DT0SEC PA3/TSCLK2 PC2/DT0PRI PA4/RFS2 PC3/TSCLK0 PA5/DR2SEC/TMR5 PC4/RFS0 PA6/DR2PRI PC5/DR0SEC PA7/RSCLK2/TMRCLK0 PC6/DR0PRI PA8/TFS3/TMRCLK1 PC7/RSCLK0 PA9/DT3SEC/TMR6 PC8/SDDO PA10/DT3PRI/TMRCLK2 PC9/SDD1 PA11/TSCLK3/TMRCLK3 PC10/SDD2 PA12/RFS3/TMRCLK4 PC11/SDD3 PA13/DR3SEC/TMR7/TMRCLK5 PA14/DR3PRI/TMRCLK6 PC12/SDCLK PC13/SDCMD PG8/SCK1 PE1/SPI0MISO/KEY_ROW6 PG9/MISO1 PE2/SPI0MOSI/KEY_COL6 PG10/MOSI1 PE3/#SPI0SS/KEY_ROW5 PG11/SPI1SS/MTXON# PE4/SPI0SEL1/KEY_COL5 PG12/CAN0TX PE5/SPI0SEL2/KEY_ROW4 PG13/CAN0RX/TMRACI4 PE6/SPI0SEL3/KEY_COL4 PG14/CAN1TX PE7/UART0TX/KEY_ROW7 PG15/CAN1RX/TMRACI5 PE8/UART0RX/TMRACI0 PE9/UART1RTS TMS SW1: Boot Mode Select Switch POSITION Idle-no boot 1 Boot from 16-bit flash memory 3 Boot from serial SPI memory Boot from SPI host device 5 Boot from serial TWI memory 6 Boot from TWI host 7 Boot from UART host 8 Reserved 9 Reserved A Boot from DDR SDRAM B Reserved C Reserved D Reserved E Boot from16-bit Host DMA F Boot from 8-bit Host DMA TDI C SW1 45 23 6 1 7 0 8 F 9 E A DCB V4 V5 TRST PE10/UART1CTS TMS PE14/SCL0 EMU PE15/SDA0 W1 2 W2 4 W3 8 W4 V7 UART3RX W8 PUSHBUTTON1 V8 PUSHBUTTON2 U7 PUSHBUTTON3 W7 PUSHBUTTON4/HPWAIT Y6 SPI2SCK V9 SPI2MOSI Y5 SPI2MISO H2 CAN0_ERR J3 PC1 J2 DT0PRI H1 TSCLK0 G2 RFS0 G1 CAN1_ERR J5 DR0PRI H3 RSCLK0 Y14 SD_D0 V13 SD_D1 U13 SD_D2 W14 Y15 SD_CLK W15 R16 10K 0402 R17 10K 0402 R18 10K 0402 R19 10K 0402 RESET C11 C12 R243 0 0402 SD_CMD SPI0SCK V19 T17 R244 33 0402 SPI0MISO U18 SPI0MOSI V14 R245 33 0402 PE3 Y16 SPI0SEL1 W20 W19 R17 R246 33 0402 PE7 SPI0SEL2 V20 PE8 U19 R255 33 0402 UART1RTS T18 UART1CTS SPI0SEL3 U16 SCL0 W17 SDA0 SW16: Peripheral Control Enable Switch TDO TDI PH5/DMAR0/TMRACI8/TMRCLK8 PH6/DMAR1/TMRACI9/TMRCLK9 C3 UART3CTS/PB3 D6 PH6 PE7 H4 BOOTWAIT PE8 BMODE0 HOSTWAIT BMODE1 8 2 7 3 6 4 5 AUDIO_RESET USB_VRSEL 3 LAN_IRQ NOR_RESET DIP4 SWT018 BMODE2 BMODE3 R21 33 0402 NMI RESET CLKBUF D11 SW16: Peripheral Control Enable Switch CLKBUF POS. FROM TO DEFAULT ALTERNATE FUNCTION / OFF MODE ADSP-BF548 MBGA400 SW16.1 UART3CTS/PB3 (U2) AUDIO_RESET (U11) ON J3.33 (Expansion Interface) SW16.2 PE7 (U2) USB_VRSEL (U39, VR1) ON J3.37 (Expansion Interface) SW16.3 PE8 (U2) LAN_IRQ (U14) ON J3.38 (Expansion Interface) SW16.4 HOSTWAIT (U2) NOR_RESET (U25) OFF P3.12 (HOST Interface) ANALOG DEVICES 4 Size Board No. C Date B C 20 Cotton Road Nashua, NH 03063 4 PH: 1-800-ANALOGD ADSP-BF548 EZ-KIT LITE CONTROL Title A SW16 1 PH5 SWT023 ROTARY NMI 2 SD_D3 TCK PH7/TMRACI10/TMRCLK10 1 1 UART3TX 4 4 TDO UART2RX W6 3 Boot from 16-bit asynchronous FIFO 3.3V DEFAULT UART2TX Y3 2 2 TCK V3 UART3CTS/PB3 Y4 ON 0 R5 UART3RTS U6 1 3 EMU BOOT MODE T5 U5 SDA1 T6 PA15/RSCLK3/TMRACI7/TMRCLK7 SDA1 TRST SCL1 Y2 PA0/TFS2 PE0/SPI0SCK/KEY_COL7 R209 10K 0402 W5 Rev A0206-2006 1.4C Sheet 9-12-2008_16:43 D 4 of 17 A B C D 3.3V U2 R4 PPI1D7/HPD15 T2 PPI1D6/HPD14 R3 PPI1D5/HPD13 T1 PPI1D4/HPD12 R2 PPI1D3/HPD11 R1 PPI1D2/HPD10 P4 PPI1D1/HPD9 P3 PPI1D0/HPD8 1 U3 PPI1D15/HPD7/KPC3 U4 PPI1D14/HPD6/KPC2 V2 PPI1D13/HPD5/KPC1 T4 PPI1D12/HPD4/KPC0 V1 PPI1D11/HPD3/KPR3 T3 PPI1D10/HPD2/KPR2 U2 PPI1D9/HPD1/KPR1 U1 PPI1D8/HPD0/KPR0 Y17 PF2/PPI0D2 PD4/PPI1D4/HPD12/RFS1/PPI0D22 PF3/PPI0D3 PD3/PPI1D3/HPD11/TSCLK1/PPI0D21 PF4/PPI0D4 PD2/PPI1D2/HPD10/DT1PRI/PPI0D20 PF5/PPI0D5 PD1/PPI1D1/HPD9/DT1SEC/PPI0D19 PF6/PPI0D6 PD0/PPI1D0/HPD8/TFS1/PPI0D18 PF7/PPI0D7 PD15/PPI1D15/HPD7/PPI2D7/KPC3 PD14/PPI1D14/HPD6/PPI2D6/KPC2 PD13/PPI1D13/HPD5/PPI2D5/KPC1 PD12/PPI1D12/HPD4/PPI2D4/KPC0 PD11/PPI1D11/HPD3/PPI2D3/KPR3 PF8/PPI0D8 PF9/PPI0D9 PF10/PPI0D10 PF11/PPI0D11 PF12/PPI0D12 PD10/PPI1D10/HPD2/PPI2D2/KPR2 PF13/PPI0D13 PD9/PPI1D9/HPD1/PPI2D1/KPR1 PF14/PPI0D14 PD8/PPI1D8/HPD0/PPI2D0/KPR0 PF15/PPI0D15 PG3/PPI0D16 PG6/SPI1SEL2/#HPRD/PPI2FS1 PG4/PPI0D17 K2 PPI0D3 L2 PPI0D4 L1 PPI0D6 K4 PPI0D7 L3 PG2/PPI0FS2 PE11/PPI1CLK HPACK/CNTCUD (U2) SW3.1 ON P3.10 (HOST Interface) SW4.2 HPA/CNTCDG (U2) SW3.3 ON P3.8 (HOST Interface) SW4.3 HPCE/CNTCZM (U2) SW3.4 ON P3.6 (HOST Interface) SW4.4 N/A N/A OFF N/A R33 1.0K 0402 R35 100 0805 U10 4 5 74LVC14A SOIC14 6 74LVC14A SOIC14 1 3.3V PPI0D10 M3 U10 3 PPI0D9 M2 PPI0D11 M4 ROTARY ENCODER PPI0D12 N4 PPI0D13 N1 SW3 PPI0D14 N2 N3 P1 K5 SW4.1 C30 0.1UF 0805 NOTE FOR 0.1 REV BF548 AND GREATER: PPI0FS3 FUNCTION MOVED TO PH1 (DSP PIN U14) PPI0D16 PPI2FS3 FUNCTION MOVED TO PH2 (DSP PIN V17) PPI0D17 B SW1 PLEASE REFER TO THE BF548 DATASHEET FOR MORE DETAILS PPI0CLK SW2 COMMON ROTARY_ENCODER SWT022 JP12: PPI1FS3 PULL-DOWN JUMPER JUMPER PPI0FS1 L5 A PPI0D15 PG7/SPI1SEL3/#HPWR/PPI2CLK PG1/PPI0FS1 ALTERNATE FUNCTION / OFF MODE PPI0D8 M1 PH4/HPACK/TMR10/CNTCUD DEFAULT PPI0D5 L4 J4 TO PPI0D2 K1 PG5/SPI1SEL1/#HPCE/PPI2FS2/CNTCZM PG0/PPI0CLK/TMRCLK PH3/HPA/TMR9/CNTCDG FROM R32 1.0K 0402 1 3 4 R34 100 0805 5 1 2 SW4 1 U10 2 9 74LVC14A SOIC14 8 74LVC14A SOIC14 Connect PPI1FS3 to GND. Not using serial port J6 OFF Using serial port J6. 7 3 6 4 5 HPACK/CNTCUD HPA/CNTCDG #HPCE/CNTCZM DIP4 SWT018 3.3V ON 8 2 C31 0.1UF 0805 MODE PPI0FS2 P2 U10 4 U17 HPACK/CNTCUD PD5/PPI1D5/HPD13/DR1SEC/PPI0D23 POS. PPI0D1 3 V18 HPA/CNTCDG PF1/PPI0D1 SW4: Rotary Encoder Enable Switch PPI0D0 J1 2 V15 #HPCE/CNTCZM PD6/PPI1D6/HPD14/DR1PRI K3 1 W16 LED2 PF0/PPI0D0 ON LED1 PD7/PPI1D7/HPD15/RSCLK1 SW4: Rotary Encoder Enable Switch 3.3V PPI1CLK JP3 DEFAULT JUMPER SETTING = OFF (NOT INSTALLED) PE12/PPI1FS1 PE13/PPI1FS2 2 PH0/UART1_TX/PPI1FS3 M5 PPI1FS1 P5 PPI1FS2 R31 1.0K 0402 R272 33 0402 W18 U10 PH1/UART1_RX/PPI2FS3/TMRACI1 PH2/ATAPIRESET/TMR8/PPI0FS3 U14 UART1_RX V17 2 R36 100 0805 PPI1FS3/UART1_TX C33 0.01UF 0402 U10 11 ADSP-BF548 MBGA400 10 74LVC14A SOIC14 PPI0FS3/ATAPIRESET U10 13 12 74LVC14A SOIC14 C32 0.1UF 0805 R225 10K 0402 NOTE: DEFAULT JUMPER SETTING = DNP JP12 1 2 IDC2X1 R268 33 0402 PPI0CLK RN17 PPI0D0 PPI0D1 PPI0D2 PPI0D3 R1A 2 R2A 3 R3A 4 R4A R1B R2B R3B R4B PPI1FS1 PPI1FS1_R PPI0D2_R 5 R271 33 0402 PPI0D3_R 33 RNS001 3 PPI1CLK_R PPI0D1_R 6 PPI1FS2 PPI1FS2_R RN18 R3A 4 R4A R2B R3B R4B 8 PPI0D4_R 7 6 5 PPI1D7/HPD15 PPI0D5_R PPI1D6/HPD14 PPI0D6_R PPI1D5/HPD13 PPI0D7_R PPI1D4/HPD12 1 R1A 2 R2A 3 R3A 4 R4A PPI0D12 PPI0D13 PPI0D14 PPI0D15 3 R3A 4 R4A PPI0D17 PPI0FS1 PPI0FS2 R2B R3B R4B 8 7 6 5 PPI0D8_R PPI1D3/HPD11 PPI0D9_R PPI1D2/HPD10 PPI0D10_R PPI1D1/HPD9 PPI0D11_R PPI1D0/HPD8 1 R1A 2 R2A 3 R3A 4 R4A RN20 RN23 2 R2A 3 R3A 4 R4A R1B R2B R3B R4B 8 7 6 PPI0D12_R PPI1D15/HPD7/KPC3 PPI0D13_R PPI1D14/HPD6/KPC2 PPI0D14_R 5 PPI0D15_R PPI1D13/HPD5/KPC1 PPI1D12/HPD4/KPC0 1 R1A 2 R2A 3 R3A 4 R4A 33 RNS001 33 RNS001 RN25 RN24 4 PPI0D16 R1B 33 RNS001 R1A 1 R1A 2 R2A 3 R3A 4 R4A DSP (U2) P1.2 ON Expansion Interface, HOST Interface, PPI1 SW2.3 DSP (U2) P1.3 ON Expansion Interface, HOST Interface, PPI1 SW2.4 DSP (U2) P1.4 ON Expansion Interface, HOST Interface, PPI1 SW2.5 DSP (U2) P1.5 ON Expansion Interface, HOST Interface, PPI1 SW2.6 DSP (U2) P1.6 ON Expansion Interface, HOST Interface, PPI1 R2B R3B R4B 8 7 SW2.7 DSP (U2) P1.7 ON Expansion Interface, HOST Interface, PPI1 R148 10K 0402 6 5 PPI1D6/HPD14_R R1B R2B R3B R4B 8 7 6 5 33 RNS001 PPI0D16_R PPI1D11/HPD3/KPR3 PPI0D17_R PPI1D10/HPD2/KPR2 PPI0FS1_R PPI1D9/HPD1/KPR1 PPI0FS2_R PPI1D8/HPD0/KPR0 1 R1A 2 R2A 3 R3A 4 R4A PPI1D14/HPD6/KPC2_R SW2.8 DSP (U2) P1.8 ON Expansion Interface, HOST Interface, PPI1 PPI1D12/HPD4/KPC0_R PPI1D4/HPD12_R HOST PORT PPI1D11/HPD3/KPR3_R 3.3V PPI1D10/HPD2/KPR2_R PPI1D9/HPD1/KPR1_R R1B R2B R3B R4B 8 7 6 5 PPI1D3/HPD11_R PPI1D7/HPD15_R PPI1D2/HPD10_R PPI1D6/HPD14_R PPI1D1/HPD9_R PPI1D5/HPD13_R PPI1D0/HPD8_R PPI1D4/HPD12_R PPI1D3/HPD11_R PPI1D2/HPD10_R PPI1D1/HPD9_R R1B R2B R3B R4B 8 7 6 5 PPI1D15/HPD7/KPC3_R PPI1D0/HPD8_R PPI1D14/HPD6/KPC2_R PPI1D15/HPD7/KPC3_R PPI1D13/HPD5/KPC1_R PPI1D14/HPD6/KPC2_R PPI1D12/HPD4/KPC0_R PPI1D13/HPD5/KPC1_R PPI1D12/HPD4KPC0_R PPI1D11/HPD3/KPR3_R PPI1D10/HPD2/KPR2_R R1B R2B R3B R4B 8 7 6 5 PPI1D11/HPD3/KPR3_R PPI1D9/HPD1/KPR1_R PPI1D10/HPD2/KPR2_R PPI1D8/HPD0/KPR0_R PPI1D9/HPD1/KPR1_R P3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 PPI1D8/HPD0/KPR0_R LED1 R163 10K 0402 SW2 1 16 P1 1 2 15 2 3 14 3 4 13 4 5 12 5 6 11 6 7 10 7 8 9 8 3 9 IDC9X1 R214 10K 0402 #HPCE/CNTCZM HPA/CNTCDG SW2: Keypad Enable Switch R259 0 0805 HPACK/CNTCUD HOSTWAIT R150 0 0402 DNP ANALOG DEVICES BOOTWAIT R149 0 0402 PUSHBUTTON4/HPWAIT Title IDC16X2 PPI1D8/HPD0/KPR0_R Size Date C 20 Cotton Road Nashua, NH 03063 4 PH: 1-800-ANALOGD ADSP-BF548 EZ-KIT LITE PPI, KEYPAD, THUMBWHEEL INTERFACE Board No. C B R161 10K 0402 DIP8 SWT016 LED2 33 RNS001 A PPI1D15/HPD7/KPC3_R PPI1D13/HPD5/KPC1_R PPI1D5/HPD13_R R158 10K 0402 KEYPAD PPI1D7/HPD15_R RN22 33 RNS001 1 SW2.2 8 PPI0D11 R2A Expansion Interface, HOST Interface, PPI1 7 PPI0D10 2 ON 6 PPI0D9 R1A R1B 33 RNS001 RN19 1 P1.1 5 33 RNS001 PPI0D8 DSP (U2) ON 3 SW2.1 RN21 R1B 3.3V ALTERNATE FUNCTION / OFF MODE 4 PPI0D7 R2A DEFAULT 3 PPI0D6 R1A 2 TO 2 PPI0D5 1 FROM 1 PPI0D4 POS. R270 33 0402 PPI0D0_R 7 3.3V R269 33 0402 PPI1CLK 8 3.3V SW2: Keypad Enable Switch R224 10K 0402 PPI0CLK_R 1 3.3V Rev A0206-2006 1.4C Sheet 9-12-2008_16:43 D 5 of 17 A B C D VDDEXT VDDEXT U2 E9 VDDEXT1 E10 VDDEXT2 E11 VDDEXT3 E12 VDDEXT4 F8 VDDEXT5 F13 1 2 VDDINT VDDEXT6 G5 VDDEXT7 G6 VDDEXT8 G7 VDDEXT9 G14 VDDEXT10 H5 VDDEXT11 H6 VDDEXT12 K6 VDDEXT13 M15 VDDEXT14 N5 VDDEXT15 N15 VDDEXT16 P15 VDDEXT17 R6 VDDEXT18 R7 VDDEXT19 R8 VDDEXT20 R15 VDDEXT21 T7 VDDEXT22 T8 VDDEXT23 T9 VDDEXT24 T10 VDDEXT25 T11 VDDEXT26 T12 VDDEXT27 T13 VDDEXT28 T14 VDDEXT29 T15 VDDEXT30 T16 VDDEXT31 F15 VDDEXT32 E5 VDDEXT33 F7 VDDEXT34 F9 VDDINT1 G8 VDDINT2 G12 VDDINT3 G13 VDDINT4 J6 VDDINT5 J13 VDDINT6 L6 VDDINT7 L15 VDDINT8 P6 VDDINT9 P7 VDDINT10 P14 VDDINT11 R10 VDDINT12 R11 VDDINT13 R12 VDDINT14 U9 VDDINT15 3 VDDDDR VDDEXT F10 VDDDDR1 F11 VDDDDR2 D16 MA3X717E DIO005 F12 VDDDDR3 G15 VDDDDR4 H13 VDDDDR5 H14 VDDDDR6 H15 VDDDDR7 J14 VDDDDR8 J15 VDDDDR9 K14 VDDDDR10 K15 VDDDDR11 J13 2 1 C192 0.01UF 0402 CON054 BATTHOLDER DDR_VREF E13 VDDRTC M20 DDR_VREF VROUT R260 1.0 0402 M18 TP18 EXT_WAKE VDDINT A18 VROUT0 FER18 600 0603 A19 VROUT1 E8 VDDMP 4 C259 0.01UF 0402 C248 10UF 0805 C247 0.01UF 0402 A1 GND1 A13 GND2 A20 GND3 B11 GND4 D1 GND5 E3 GND6 F3 GND7 F14 GND8 G9 GND9 G10 GND10 G11 GND11 H7 GND12 H8 GND13 H9 GND14 H10 GND15 H11 GND16 H12 GND17 J7 GND18 J8 GND19 J9 GND20 J10 GND21 J11 GND22 J12 GND23 K7 GND24 K8 GND25 K9 GND26 K10 GND27 K11 GND28 K12 GND29 K13 GND30 L7 GND31 L8 GND32 L9 GND33 L10 GND34 L11 GND35 L12 GND36 L13 GND37 L14 GND38 M6 GND39 M7 GND40 M8 GND41 M9 GND42 M10 GND43 M11 GND44 M12 GND45 M13 GND46 M14 GND47 N6 GND48 N7 GND49 N8 GND50 N9 GND51 N10 GND52 N11 GND53 N12 GND54 N13 GND55 N14 GND56 P8 GND57 P9 GND58 P10 GND59 P11 GND60 P12 GND61 P13 GND62 R9 GND63 R13 GND64 R14 GND65 U8 GND66 Y1 GND67 Y20 GND68 R16 GND69 V6 GND70 D4 GND71 F6 GND72 E7 GNDMP N20 DDR_VSSR C206 10UF 0805 C86 0.01UF 0402 C91 0.01UF 0402 C90 0.01UF 0402 C92 0.01UF 0402 A C88 0.01UF 0402 C87 0.01UF 0402 C39 0.01UF 0402 C38 0.01UF 0402 C40 0.01UF 0402 1 VDDEXT C49 10UF 0805 C48 0.01UF 0402 C44 0.01UF 0402 C45 0.01UF 0402 C43 0.01UF 0402 C46 0.01UF 0402 C47 0.01UF 0402 C42 0.01UF 0402 C50 0.01UF 0402 C41 0.01UF 0402 C51 0.01UF 0402 C60 10UF 0805 C59 0.01UF 0402 C55 0.01UF 0402 C56 0.01UF 0402 C54 0.01UF 0402 C57 0.01UF 0402 C58 0.01UF 0402 C53 0.01UF 0402 C61 0.01UF 0402 C52 0.01UF 0402 C62 0.01UF 0402 VDDEXT 2 VDDINT C208 10UF 0805 C63 0.01UF 0402 C34 0.01UF 0402 C23 0.01UF 0402 C36 0.01UF 0402 C24 0.01UF 0402 C35 0.01UF 0402 C37 0.01UF 0402 C72 0.01UF 0402 C65 0.01UF 0402 C69 0.01UF 0402 C70 0.01UF 0402 C68 0.01UF 0402 C71 0.01UF 0402 C66 0.01UF 0402 C79 0.01UF 0402 C73 0.01UF 0402 C76 0.01UF 0402 C77 0.01UF 0402 C75 0.01UF 0402 C78 0.01UF 0402 C64 0.01UF 0402 VDDINT C67 10UF 0805 3 VDDDDR C74 10UF 0805 VDDDDR ANALOG DEVICES C84 10UF 0805 C80 0.01UF 0402 C85 0.01UF 0402 C82 0.01UF 0402 C81 0.01UF 0402 ADSP-BF548 MBGA400 PLACE AS CLOSE TO U2.M20 AS POSSIBLE C89 0.01UF 0402 C83 0.01UF 0402 Board No. C Date B C Nashua, NH 03063 4 PH: 1-800-ANALOGD ADSP-BF548 EZ-KIT LITE DSP POWER Title Size VDDMP ON BF548 DESIGNS CAN BE CONNECTED DIRECTLY TO VDDINT 20 Cotton Road Rev A0206-2006 1.4C Sheet 9-12-2008_16:43 D 6 of 17 A B C D CENTER/LFE OUT Audio Loopback Test Switch (Default = ALL OFF) For Test Purposes Only MIC IN SW8 1 1 LINEIN_L 2 11 3 10 4 9 5 8 6 7 2 LINEIN_R 12 ON LINE/HP OUT 3 4 1 LINE IN 5 MIC_L 6 MIC_R SURROUT_L SURROUT_R CENTER_OUT 1 LFE_OUT LINEOUT_L LINEOUT_R DIP6 SWT017 SURROUND L/R OUT LABEL "LINE/HP OUT" CT1 100UF C J10 1 FER1 600 0603 5 LINEOUT_L 4 CT2 100UF C FER2 600 0603 3 JS1 LINEOUT_R 2 CON001 VREFOUT R52 3.01K 0402 FER10 600 0603 R53 3.01K 0402 R37 1K 0603 FOR AD1980 USE (DEFAULT): R50 100 0402 R42 1K 0603 C93 470PF 0603 FRONT CHANNELS C97 470PF 0603 POPULATE R58 & R59 WITH 0 OHMS C127 & C128 SHOULD BE UNPOPULATED C109 0.1UF 0402 FOR AD1981B USE: MIC_L R58 & R59 SHOULD BE UNPOPULATED C127 & C128 SHOULD BE POPULATED WITH 270PF FER9 600 0603 2 R51 100 0402 AGND C114 0.1UF 0402 R58 0 0402 C111 470PF 0603 C110 470PF 0603 AGND AGND AGND 2 MIC_R LABEL "MIC" AGND C94 1UF 0603 FER3 600 0603 CENTER_OUT C112 0.01UF 0402 J8 C113 0.01UF 0402 R59 0 0402 2 C102 4.7UF 0805 FER4 600 0603 LFE_OUT 3 AGND AGND 1 4 AGND AGND FER7 600 0603 R47 4.7K 0402 C107 1UF 0402 FER8 600 0603 R48 4.7K 0402 C108 1UF 0402 C127 270PF 0603 DNP LINEIN_L R38 47.0K 0402 C128 270PF 0603 DNP R39 47.0K 0402 C98 470PF 0603 C99 470PF 0603 LABEL"CENTER/LFE" 7 8 5 TP7 LINEIN_R TP6 6 C106 470PF 0603 CON050 TP5 C105 470PF 0603 R49 4.7K 0402 SURR/HP_OUT_L 20 22 TP4 AGND MIC2 14 AUX_L 15 AUX_R LINE_IN_L AGND 24 LINE_IN_R AD1980 RESET 6 BIT_CLK RSCLK0 10 RFS0 C126 47PF 0402 DNP SYNC DR0PRI TP8 R172 0 0402 AC '97 CODEC R56 10K 0402 2 XTL_IN 3 XTL_OUT R41 47.0K 0402 AVDD1 AVDD2 AVDD3 16 AVDD4 EAPD JS1 DVSS1 NC1 Y1 24.576MHZ OSC005 42 NC2 45 ID0 A5V 3.3V 46 ID1 C115 22PF 0805 C116 22PF 0805 C120 0.1UF 0402 C117 270PF 0603 C96 0.1UF 0402 C101 470PF 0603 R54 1K 0603 DNP AGND 43 AGND 34 AGND AGND 4 7 26 AVSS1 40 AVSS2 44 AVSS3 33 AVSS4 W1 COPPER ANALOG DEVICES AGND AGND LOCATE UNDER CODEC. C119 0.1UF 0402 USE 80 MIL WIDE TRACE Board No. C AGND Date C 20 Cotton Road Nashua, NH 03063 4 PH: 1-800-ANALOGD ADSP-BF548 EZ-KIT LITE AC '97 AUDIO Title Size AGND B AGND 38 BRIDGING AGND AND GND U11 AGND 25 1A R44 1K 0603 DNP LABEL"SURROUND" C118 1UF 0603 AD1980 LQFP48 R43 4.7K 0402 4 C95 270PF 0603 9 DVSS2 A C100 470PF 0603 A5V AGND 47 12 3 CON050 DVDD2 R60 10K 0402 5 6 R40 47.0K 0402 1 JS0 U11 8 VREFOUT DVDD1 17 C121 0.1UF 0402 FER6 600 0603 AGND SDATA_OUT 48 4 7 C104 1UF 0603 TP1 3.3V SPDIF_OUT JS1 C122 10UF 0805 1 SURROUT_L 5 DT0PRI R45 4.7K 0402 C124 0.1UF 0402 3 SDATA_IN CODEC_CLKIN C125 0.1UF 0402 AGND 8 R55 10K 0402 C123 10UF 0805 AGND FER5 600 0603 29 AFILT1 30 AFILT2 11 AUDIO_RESET AGND C103 1UF 0603 28 VREFOUT 27 VREF TSCLK0 R61 0 0402 AGND SURROUT_R PHONE_IN AGND AGND 13 23 R57 0 0402 AGND 41 SURR/HP_OUT_R 31 CENTER_OUT 32 LFE_OUT 35 LINE_OUT_L 36 LINE_OUT_R 37 MONO_OUT CD_GND_REF MIC1 TP3 3 39 CD_L 19 21 TP2 AGND 18 CD_R R46 4.7K 0402 LABEL "LINE IN" AGND J9 2 U11 Rev A0206-2006 1.4C Sheet 9-12-2008_16:43 D 7 of 17 A B 3.3V 5V C 3.3V D 5V RN13 15 D[0:15] 1 46 D1 45 D2 44 D3 43 D4 42 D5 40 D6 39 D7 38 37 36 D8 35 D9 34 D10 33 D11 31 D12 30 D13 29 D14 28 D15 27 26 25 1B1 U24_VCC1 U24 VCC1 U4 D0 R227 0 0805 1A1 1B2 1A2 1B3 1A3 1B4 1A4 1B5 1A5 1B6 1A6 1B7 1A7 1B8 1A8 1B9 1A9 1B10 1A10 2B1 2A1 2B2 2A2 2B3 2A3 2B4 2A4 2B5 2A5 2B6 2A6 2B7 2A7 2B8 2A8 2B9 2A9 2B10 2A10 2 3 4 5 ATAPI_D0 A1 ATAPI_D1 A2 ATAPI_D2 A3 ATAPI_D3 6 9 10 45 44 43 ATAPIPDIAG ATAPI_D4 7 46 42 ATAPIDMARQ ATAPI_D5 ATAPIDIOW ATAPI_D6 ATAPIDIOR ATAPI_D7 40 39 38 ATAPIDMACK 11 37 12 36 13 ATAPI_D8 14 ATAPI_D9 16 18 19 20 35 ATAPICS0 34 ATAPICS1 ATAPI_D10 ATAPIIORDY ATAPI_D11 ATAPIINTRQ ATAPI_D12 PPI0FS3/ATAPIRESET 33 31 30 29 ATAPI_D13 21 28 ATAPI_D14 22 27 ATAPI_D15 23 26 24 25 R228 0 0805 DNP 1B1 1 R1A 2 R2A 3 R3A 4 R4A ATAPI_D7 ATAPI_D6 ATAPI_D5 15 U4_VCC1 ATAPI_D4 VCC1 R216 0 0805 R226 0 0805 DNP 1A1 1B2 1A2 1B3 1A3 1B4 1A4 1B5 1A5 1B6 1A6 1B7 1A7 1B8 1A8 1B9 1A9 1B10 1A10 2B1 2A1 2B2 2A2 2B3 2A3 2B4 2A4 2B5 2A5 2B6 2A6 2B7 2A7 2B8 2A8 2B9 2A9 2B10 2A10 2 ATAPI_A1 3 ATAPI_D2 ATAPI_ATAPIDMARQ 7 9 10 1 R1A 2 R2A 3 R3A 4 R4A ATAPI_D3 ATAPI_ATAPIPDIAG 6 ATAPI_ATAPIDIOW ATAPI_D1 ATAPI_ATAPIDIOR ATAPI_D0 ATAPI_ATAPIDMACK 11 22 RNS001 12 RN11 1 R1A 2 R2A 3 R3A 4 R4A ATAPI_D15 13 ATAPI_ATAPICS0 ATAPI_D14 14 ATAPI_ATAPICS1 ATAPI_D13 16 ATAPI_ATAPIIORDY ATAPI_D12 18 SN74CB3T16210 TSSOP48 48 1OE 47 2OE SN74CB3T16210 TSSOP48 GND1 GND2 GND3 GND4 1 NC1 19 ATAPI_RESET R3B R4B ATAPI_D3_R 7 ATAPI_D2_R 6 1 ATAPI_D1_R 5 R7 33 0402 ATAPI_D0_R J14 1 ATAPI_RESET R1B R2B R3B R4B 8 7 6 5 ATAPI_D6_R R25 5.6K 0402 ATAPI_D13_R 7 ATAPI_D5_R 9 ATAPI_D4_R 5V 11 ATAPI_D3_R ATAPI_D12_R 13 22 ATAPI_D11 23 ATAPI_D10 24 ATAPI_D9 1 R1A 2 R2A 3 R3A 4 R4A 15 ATAPI_D1_R R1B R2B R3B R4B 8 7 6 5 R143 4.7K 0402 ATAPI_D11_R ATAPI_D10_R 17 R4 ATAPI_D0_R 82 0402 19 21 ATAPI_D8_R 23 ATAPI_ATAPIDIOW_R R5 82 0402 ATAPI_D9_R 25 ATAPI_ATAPIDIOR_R 27 ATAPI_ATAPIIORDY 1 22 RNS001 R6 ATAPI_ATAPIDMACK_R 82 0402 RN15 1 R1A 2 R2A 3 R3A 4 R4A ATAPI_ATAPIDMACK ATAPI_ATAPIDIOR JP11: USB OTG POWER JUMPER JUMPER 29 31 ATAPI_ATAPIINTRQ R1B R2B R3B R4B 8 7 6 5 33 ATAPI_A2_R ATAPI_ATAPICS1_R 35 ATAPI_A1_R ATAPI_ATAPICS0_R R26 10K 0402 ATAPI_ATAPIDMACK_R 37 ATAPI_ATAPICS0_R 39 ATAPI_ATAPIDIOR_R 41 22 RNS001 SETTING 43 RN16 2 PINS 1 & 3 ON PINS 2 & 4 R168 10K 0402 1 R1A 2 R2A 3 R3A 4 R4A ATAPI_ATAPIDIOW SN74LVC1G02 SOT23-5 R198 10K 0402 ATAPI_A3 ATAPI_A2 ON ATAPI_A1 3.3V R1B R2B R3B R4B 8 DD6 DD9 DD5 DD10 DD4 DD12 DD2 DD13 DD1 DD14 DD0 DD15 GND2 ATAPI_D13_R 16 ATAPI_D14_R 18 ATAPI_D15_R 20 22 24 DIOW GND4 DIOR GND5 IORDY CSEL 26 5V 28 30 DMACK GND6 32 NU 34 PDIAG DA0 DA2 CS0 CS1 ATAPI_ATAPIPDIAG 36 ATAPI_A3_R 38 ATAPI_ATAPICS1_R 2 40 DASP GND7 5V_L 5V_M GND8 RSV 42 44 ATAPI_A2_R 5 ATAPI_A1_R 5V ATAPI 5V_USB 3.6V R144 0 0402 DNP ATAPI_D12_R 14 ATAPI_A3_R 6 22 RNS001 D7 MA27D27 DIO006 ATAPI_D11_R 12 DMARQ GND3 DA1 ATAPI_D10_R 10 KEY3 INTRQ ATAPI_D9_R 8 DD11 DD3 ATAPI_D8_R 6 ATAPI_ATAPIDIOW_R 7 JP11 DEFAULT JUMPER SETTING = ON (INSTALLED) D3 CZRF52C2V2 DIO007 4 DD8 ATAPI44 22X2_2MM 4 ATAPICS1 2 GND1 DD7 5 ATAPI_D15_R ATAPI_D14_R RESET 3 ATAPI_D7_R ATAPI_ATAPIDMARQ RN12 R166 10K 0402 U35 R2B 8 21 ATAPI_ATAPICS0 1 R1B 20 2 ATAPICS0 ATAPI_D4_R 22 RNS001 ATAPI_ATAPICS1 R167 0 0402 DNP ATAPI_D5_R 5 ATAPI_D2_R 8 17 32 41 2OE GND1 GND2 GND3 GND4 47 NC1 8 17 32 41 1OE R4B ATAPI_D6_R 6 ATAPI_ATAPIINTRQ ATAPI_D8 48 R3B ATAPI_D7_R 7 RN14 ATAPI_A3 5 R2B 8 22 RNS001 ATAPI_A2 4 R1B 5V 3.3V D2 MA27D27 DIO006 JP11 1 2 3 4 5V_USB IDC2X2 R64 0 0402 DNP R146 0 0402 3.3V C134 0.1UF 0402 CLKBUF C135 10UF 0805 D6 ZHCS1000 SOT23-312 DNP 3 3 R63 0 0402 DNP F1 USBXI GND 24MHZ 2 OSC003 F2 D3 B1 U13 R62 10K 0402 DNP C129 1UF 0805 USBXO R145 0 0402 DNP F5 U2 3 USBVDDB 4 VDD G4 R66 33 0402 OUT C131 0.01UF 0402 U35 USBVDDA U13 C256 0.1UF 0402 C198 4.7UF 0805 3.3V 3.3V C255 10UF 0805 C243 0.01UF 0402 USBVBUS USBID USBRSET USBDM USBVREF ADSP-BF548 MBGA400 USBDP R72 THERM 1206 U4_VCC1 3.3V J14 5V U24_VCC1 3.3V 5V D2 G3 P4 1 VBUS 2 D3 D+ 4 ID 5 GND 6 SHELL CON052 E2 E1 C130 0.01UF 0402 C195 0.01UF 0402 C196 0.01UF 0402 C197 0.01UF 0402 C244 0.01UF 0402 C249 0.01UF 0402 C250 0.01UF 0402 U4 U24 R142 VARISTOR D9 D8 D1 PGB1010603 0603 PGB1010603 0603 PGB1010603 0603 ANALOG DEVICES 0603 4 FER11 600 1206 R67 1M 0603 C136 0.01UF 0402 Title Size A B C Nashua, NH 03063 4 PH: 1-800-ANALOGD ADSP-BF548 EZ-KIT LITE ATAPI HARD DRIVE, USB OTG Board No. C Date 20 Cotton Road Rev A0206-2006 1.4C Sheet 9-12-2008_16:43 D 8 of 17 A B 3.3V C 3.3V A3V D A3V A3V VDD_LAN_CORE_1_8V VDD_LAN_PLL_1_8V A2 17 A3 16 A4 15 A5 14 A6 13 A7 12 A1 A2 A3 2 20 VDD1 28 VDD2 35 VDD3 42 VDD4 48 VDD5 55 VDD6 61 VDD7 97 VDD8 18 81 AVDD1 85 AVDD2 89 AVDD3 1 A1 VREG A[1:7] 8 VDD_REF U14 7 VDD_PLL 3 VDD_CORE1 65 VDD_CORE2 R98 1.05K 0603 R83 49.9 0805 R84 49.9 0805 R85 49.9 0805 R86 49.9 0805 R82 10.0 0603 U15 1 TPI+ 2 79 TPO+ 78 TPO83 TPI+ 82 TPI- A4 A5 A6 A7 2 D0 64 D1 63 D2 62 D3 59 D4 58 D5 57 D6 56 D7 53 D8 52 D9 51 D10 50 D11 49 D12 46 D13 45 D14 44 D15 43 40 39 38 37 36 33 32 31 30 3.3V 29 26 25 24 23 R75 1.05K 0603 R74 1.05K 0603 22 21 95 RESET 92 ARE 3 93 AWE 94 AMS1 3 7 D0 D1 87 D3 EXRES1 D4 TPO- RD+ TPOCT RDCT TPO+ HX1188 ICS007 RD- 2 14 3 1 11 5 10 6 9 7 8 CON_RJ45_12P R93 75.0 0603 LINK/ACTIVITY R80 12.4K 0603 D5 D6 69 EECLK/GPO4 67 EEDIO/GPO3 68 EECS D7 D8 D9 R94 75.0 0603 LED9 YELLOW LED001 EEP_CLK EEP_DIO EEP_CS C147 1000PF 1206 R141 330 0603 D10 R87 49.9 0805 R88 49.9 0805 R91 49.9 0805 R90 49.9 0805 D11 D12 TP9 98 GPIO0/LED1 99 GPIO1/LED2 100 GPIO2/LED3 D13 D14 R89 49.9 0805 JP3: ETHERNET SPEED SELECT JUMPER R92 49.9 0805 SHGND2 TP10 D15 JUMPER MODE ON 10Mbps; Auto-Negotiation OFF 2 71 TESTMODE D16 D17 74 D18 SPEED_SEL SPEED_SEL D20 JP3 1 C146 1000PF 1206 2 OFF 76 FIFO_SEL 75 PD1 D19 100Mbps; Auto-Negotiation IDC2X1 JP3 DEFAULT JUMPER SETTING = OFF (NOT INSTALLED) D21 D22 R282 10K 0402 D23 D24 R96 1.05K 0603 R97 1.05K 0603 SHGND2 84 NC2 D25 90 NC3 D26 91 NC4 D27 D28 5 XTAL2 6 XTAL1 D29 D30 3.3V 3.3V D31 R78 1M 0805 RESET 9 ATEST RD Y3 WR OSC005 CS R77 10K 0402 3.3V 3 10 C144 30PF 1206 R79 12.0K 0402 AGND4 AGND3 25MHZ EEP_CS C143 30PF 1206 EEP_CLK EEP_DIO R81 1.05K 0603 88 AGND2 86 AGND1 80 77 GND8 GND7 96 GND6 60 GND5 54 GND4 47 41 GND3 34 GND2 GND1 27 19 GND_CORE2 GND_CORE1 66 LAN9218 TQFP100 1 PME VSS_PLL IRQ 4 LAN_PME TD- 15 C145 0.022UF 0805 D2 VSS_REF 70 TPI- 1 3.3V 11 72 TDCT 16 4 6 RBIAS LAN_IRQ TD+ TPICT 8 D[0:15] J4 73 AMDIX_EN R95 10K 0402 U12 1 CS 2 SK MicroWire 3 Serial EEPROM DI 4 DO 93LC46A SOIC8 6 PE C153 0.1UF 0402 7 PRE U14 R76 0 1206 FOR VDD_CORE. PLACE CLOSE TO PINS 3 and 65. 3.3V A3V FER12 600 1206 FOR VDD_PLL. PLACE CLOSE TO PIN 7. 3.3V A3V SHGND2 VDD_LAN_CORE_1_8V 4 C149 10UF 0805 C148 0.01UF 0402 VDD_LAN_PLL_1_8V C150 0.01UF 0402 C152 10UF 0805 C151 0.01UF 0402 C142 0.1UF 0402 C154 0.1UF 0402 C155 0.1UF 0402 C156 0.1UF 0402 C157 0.1UF 0402 C158 0.1UF 0402 C159 0.1UF 0402 C160 0.1UF 0402 C161 0.1UF 0402 C162 0.1UF 0402 C167 10UF 0805 C163 0.1UF 0402 C164 0.1UF 0402 C165 0.1UF 0402 ANALOG DEVICES C166 0.1UF 0402 U14 U14 U14 Date A B Board No. C U14 C Nashua, NH 03063 4 PH: 1-800-ANALOGD ADSP-BF548 EZ-KIT LITE ETHERNET Title Size 20 Cotton Road Rev A0206-2006 1.4C Sheet 9-12-2008_16:43 D 9 of 17 A B C D 3.3V 5V 1 R109 10K 0402 U21 1 ON SW6 1 2 7 3 6 4 5 2 3 CAN0_ERR 4 CAN0RX 8 6 EN 14 STB 8 ERR 5 VIO 3 VDD 10 VBAT R108 10K 0402 3.3V POS. FROM DEFAULT SW6.1 ENABLE GND OFF SW6.2 ~STB GND OFF SW6.3 CAN0_ERR U2 - PC0 ON STAMP_GPIO1 SW6.4 CAN0RX U2 - PG13 ON STAMP_GPIO0 1 1 13 3 11 4 CANH SPLIT LABEL "CAN 0" 12 GND CON039 C168 4700PF 0603 2 TJA1041 SOIC14 ALTERNATE FUNCTION R107 10K 0603 DNP J11 R102 10 0603 2 CANL SW6: CAN Enable Switch TO R105 62.0 0603 9 WAKE CAN0TX SW6: CAN0 Enable Switch 7 INH 1 TXD 4 RXD DIP4 SWT018 C172 100PF 0603 R106 62.0 0603 R104 10 0603 C169 100PF 0603 3.3V 5V CAN 0 C170 0.01UF 0402 2 C171 0.01UF 0402 2 U21 3.3V 5V 7 14 3 6 8 4 5 2 3 CAN1_ERR SW15: CAN1 Enable Switch FROM TO DEFAULT ALTERNATE FUNCTION ENABLE GND OFF SW15.2 ~STB GND OFF SW15.3 CAN1_ERR U2 - PC5 ON SW15.4 CAN1RX U2 - PG15 ON 10 3 R217 10K 0603 DNP J12 1 2 TXD 13 3 11 4 CANH 4 RXD SPLIT CAN1TX CANL SW15: CAN Enable Switch SW15.1 R220 10 0603 ERR TJA1041 SOIC14 3 12 CON039 GND POS. R221 62.0 0603 9 WAKE 1 DIP4 SWT018 7 INH STB C228 100PF 0603 C226 4700PF 0603 2 3 4 CAN1RX EN VBAT 2 ON 6 1 8 VDD U33 SW15 1 5 R222 10K 0402 VIO R223 10K 0402 3.3V R219 62.0 0603 R218 10 0603 LABEL "CAN 1" STAMP_GPIO3 C227 100PF 0603 STAMP_GPIO2 3.3V 5V CAN 1 C230 0.01UF 0402 C229 0.01UF 0402 ANALOG DEVICES U33 4 Board No. C Date A B C Nashua, NH 03063 4 PH: 1-800-ANALOGD ADSP-BF548 EZ-KIT LITE CAN Title Size 20 Cotton Road Rev A0206-2006 1.4C Sheet 9-12-2008_16:43 D 10 of 17 A B C D 3.3V 3.3V R110 10K 0402 1 R111 10K 0402 1 C178 0.1UF 0402 U32 C179 0.1UF 0402 1 C1+ 3 C1- J6 2 1 V+ SW7: UART Enable Switch POS. FROM TO DEFAULT 4 C2+ 5 C2- C177 0.1UF 0402 ALTERNATE FUNCTION / OFF MODE 6 6 V- 2 7 SW7.1 UART1CTS (U2) U32 ON N/A U32 ON J3.47 (Expansion Interface) SW7.3 UART1RTS (U2) U32 ON N/A UART1CTS OFF 7 12 3 6 UART1RTS 4 5 4 UART1CTS 2 3 UART1RTS 10 2 UART1_RX SW7.4 8 ON UART1_RX (U2) SW7 1 1 SW7.2 11 PPI1FS3/UART1_TX LOOPBACK OF CTS TO RTS T1IN T1OUT T2IN T2OUT 14 3 7 8 13 R1OUT R1IN 9 8 R2OUT R2IN ADM3202ARNZ SOIC16 4 9 5 C175 0.1UF 0402 DIP4 SWT018 DB9F 3.3V R99 10K 0603 SW7: UART Enable Switch JP1 1 SERIAL PORT 2 IDC2X1 (UART 1) 2 2 C180 0.01UF 0402 JP1: UART1 LOOPBACK JUMPER JUMPER U32 3V 5V LOOPBACK OPERATION OFF NORMAL OPERATION JP1 DEFAULT JUMPER SETTING = OFF (NOT INSTALLED) CODEC_CLKIN SD MEMORY CONNECTOR MMCLK MTX BOOTWAIT MRXONB MRX 3 3.3V SD_D0 R152 22 0402 MXVR 3.3V 3 SD_D1 R153 22 0402 SD_D2 8 R154 22 0402 THE MXVR PORT IS ONLY AVAILABLE ON THE BF549 9 1 SD_D3 5 R169 22 0402 SOME OF THESE PINS STILL NEED TO BE CONNECTED ON THE BF548 PLEASE REFER TO BF548 DATASHEETS FOR MOST ACCURATE INFO J5 7 SD_CLK DAT0 4 PH5 R151 22 0402 VDD LED6 DAT1 DAT2 C132 0.1UF 0402 CD/DAT3 CLK 2 CMD CON051 GND1 GND2 LED6 GND PC1 PH6 5V ON 3 6 CODEC_CLKIN 3.3V MODE R170 22 0402 SD_CMD J5 ANALOG DEVICES 4 Title Size A B C Nashua, NH 03063 4 PH: 1-800-ANALOGD ADSP-BF548 EZ-KIT LITE MXVR PORT, UART, SD CONN Board No. C Date 20 Cotton Road Rev A0206-2006 1.4C Sheet 9-12-2008_16:43 D 11 of 17 A B C D SW17.1 SW17.2 SW17.3 SW17.4 MODE ALTERNATE FUNCTION U38 2 1A1 3 1A2 4 1A3 5 1A4 6 1A5 7 1A6 9 1A7 10 1A8 11 1A9 12 1A10 13 1A11 14 1A12 3.3V 3.3V OFF OFF OFF N/A LCD DISABLED PPI0, PPI1, & HOST SIGNALS CAN BE USED ON EXPANSION INTERFACE, PPI1, HOST INERFACE PPI0D0_R ON ON OFF N/A LCD IN 18-BIT MODE ON OFF ON N/A * LCD IN 24-BIT MODE PPI1, & HOST SIGNALS CAN BE USED ON EXPANSION INTERFACE, PPI1, HOST INERFACE PPI0D1_R U9 PPI0D2_R P14 13 1 2 11 3 4 Y+ Y- DCLK 3.3V 23 LCD_DAV DAV NC3 17 R210 LCD_IRQ 0 0402 PENIRQ NC4 NC5 6 AUX1/GPIO1 5 AUX2/GPIO2 4 AUX3/GPIO3 21 GPIO4 NC6 NC7 ALERT STOPACQ 30 8 PPI0D7_R 9 16 U36 ARNG BAT1 BAT2 31 2 A1 3 A2 4 A3 5 A4 6 A5 7 A6 8 A7 9 A8 PPI0CLK_R 25 32 PPI0FS1_R R30 0 0402 22 20 PPI0FS2_R LCD_PPI0FS1 3 2 VREF R29 10K 0402 18 LCD_PPI0CLK 17 LCD_R3 LCD_R4 LCD_R5 16 B3 LCD_PPI0FS1 15 14 B5 PPI0D10_R PPI0D11_R B4 LCD_PPI0FS2 13 B6 12 B7 11 B8 PPI0D12_R PPI0D13_R PPI0D14_R AGND PPI0D15_R DGND 19 OE AD7877 LFCSP32 PPI0D16_R GND SN74CB3Q3245 TSSOP20 3.3V PPI0D17_R 55 2OE 2 SN74CB3Q16211 TSSOP56 LCD_R7 LCD_G1 LCD_G2 41 2B1 40 2B2 39 2B3 37 2B4 36 2B5 35 2B6 34 2B7 33 2B8 32 2B9 31 2B10 30 2B11 29 2B12 R274 10K 0402 LCD_Y- PPI0D1_R PPI0D2_R PPI0D4_R ON 1 7 3 6 4 5 3 C254 0.1UF 0402 DNP 8 2 2 4 C253 0.1UF 0402 DNP R273 10K 0402 PPI0D3_R SW17 1 C252 0.1UF 0402 DNP PPI0D5_R PPI0D6_R PPI0D7_R PPI0D8_R DIP4 SWT018 PPI0D9_R PPI0D10_R SW17: LCD Module Configuration Switch LCD_G7 LCD_R0 LCD_B0 LCD_R1 LCD_B1 LCD_R2 LCD_B2 LCD_R3 LCD_B3 LCD_R4 LCD_B4 LCD_R5 LCD_B5 LCD_R6 LCD_B6 LCD_R7 LCD_B7 LCD_G0 PPI0D11_R C267 1UF 0603 C260 0.1UF 0603 4 GND D20 BZT52C33S SOD-323 C266 0.1UF 0805 5 PPI1D2/HPD10_R P5 1 2 3 4 CON060 PPI1D3/HPD11_R PPI1D4/HPD12_R PPI1D5/HPD13_R BACKLIGHT 55 2OE R263 10K 0603 SN74CB3Q16211 TSSOP56 2 FB 15 LCD_R0 LCD_B0 LCD_R1 LCD_B1 LCD_R2 LCD_B2 LCD_R3 LCD_B3 LCD_R4 LCD_B4 LCD_R5 LCD_B5 LCD_R6 LCD_B6 LCD_R7 LCD_B7 2 16 17 18 19 20 21 22 23 24 25 26 27 28 29 LCD_G1 LCD_PPI0CLK LCD_G2 LCD_DISP LCD_G3 LCD_PPI0FS1 30 31 32 33 35 LCD_G4 36 LCD_G5 3 37 LCD_G6 38 LCD_G7 39 LCD_B0 40 LCD_B1 CON057 LCD_B2 LCD_B3 LCD_B4 LCD_B5 LCD_B6 LCD_B7 3.3V R262 60.4 0805 1 COMP R261 100K 0603 C262 0.1UF 0603 DNP C265 0.1UF 0603 C269 2.2UF 0805 C276 0.1UF 0402 C277 0.1UF 0402 C261 390PF 0603 ANALOG DEVICES C275 0.1UF 0402 Board No. C Date B C 20 Cotton Road Nashua, NH 03063 4 PH: 1-800-ANALOGD ADSP-BF548 EZ-KIT LITE LCD Title Size A 14 8 SS ADP1611 MSOP8 4 13 GND4 PPI1D1/HPD9_R GND3 C270 2.2UF 0805 R264 10K 0603 VR8 SD 12 49 SOD-123 B0540W D19 D17 B0540W SOD-123 3 11 LCD_G0 41 2B1 40 2B2 39 2B3 37 2B4 36 2B5 35 2B6 34 2B7 33 2B8 32 2B9 31 2B10 30 2B11 29 2B12 GND2 PPI1D0/HPD8_R TP24 RT 10 LCD_G7 38 PPI0D16_R PPI0D17_R L5 15UH IND015 7 PPI0D14_R PPI0D15_R UNREG_IN SW1 9 LCD_G3 54 1B1 53 1B2 52 1B3 51 1B4 50 1B5 48 1B6 47 1B7 46 1B8 45 1B9 44 1B10 43 1B11 42 1B12 19 D18 B0540W SOD-123 C268 2.2UF 0805 IN 8 34 GND1 TP25 6 7 LCD_PPI0FS2 8 PPI0D13_R 3 5V 6 LCD_G4 15 2A1 16 2A2 18 2A3 20 2A4 21 2A5 22 2A6 23 2A7 24 2A8 25 2A9 26 2A10 27 2A11 28 2A12 PPI0D12_R C264 0.1UF 0603 5 LCD_G2 56 1OE C263 2.2UF 0805 4 LCD_G6 LCD_G1 17 VCC 2 1A1 3 1A2 4 1A3 5 1A4 6 1A5 7 1A6 9 1A7 10 1A8 11 1A9 12 1A10 13 1A11 14 1A12 PPI0D0_R R275 10K 0402 C251 0.1UF 0402 DNP 3 LCD_G5 LCD_G6 U37 LCD_Y+ 2 LCD_G4 LCD_G5 U9 LCD_X- WQVGA LCD_G3 C26 10UF 0805 LCD_MISO LCD_X+ 1 LCD_G0 3.3V C27 0.1UF 0402 SPI0MISO FER20 600 0603 LCD_R6 P15 1 15 2A1 16 2A2 18 2A3 20 2A4 21 2A5 22 2A6 23 2A7 24 2A8 25 2A9 26 2A10 27 2A11 28 2A12 PPI0D8_R PPI0D9_R B2 15 R247 33 0402 3.3V 56 1OE B1 14 C25 0.1UF 0402 5V LCD_R2 VCC 24 AOUT 29 LCD_R1 GND4 NC2 GND3 DOUT PPI0D6_R LCD_R0 49 27 LCD_MISO 1 GND2 NC1 38 DIN 20 19 SPI0MOSI R211 0 0402 X+ 26 SPI0SCK VDDINT 12 54 1B1 53 1B2 52 1B3 51 1B4 50 1B5 48 1B6 47 1B7 46 1B8 45 1B9 44 1B10 43 1B11 42 1B12 19 CS PPI0D5_R 10 3.3V CON061 X- 18 SPI0SEL2 PPI0D3_R PPI0D4_R * DENOTES DEFAULT CONFIGURATION 10 1 PPI0, PPI1, & HOST SIGNALS ALL USED FOR LCD GND1 7 VCC 28 VDRIVE 8 R206 10K 0402 17 VCC SW17: LCD Module Configuration Switch Rev A0206-2006 1.4C Sheet 9-12-2008_16:43 D 12 of 17 A B C D 3.3V SW5: Push Button Enable Switch POS. FROM TO DEFAULT ALTERNATE FUNCTION / OFF MODE PUSHBUTTON1 R120 10K 0402 LABEL "PB1" PB1 (SW13) ON (U2 - GPIO: PB8) R100 100 0805 R134 10 0603 U30 3 1 EXPANSION INTERFACE (J2.7 & J2.26) SW5.1 SW13 MOMENTARY SWT024 TIMERS (P11.6), SPORT2 (P6.28), SPORT3 (P7.28) PUSHBUTTON2 EXPANSION INTERFACE (J2.23), UART3 (P12.3) SW5.2 PB2 (SW12) ON (U2 - GPIO: PB9) TIMERS (P11.8), SPORT2 (P6.30), SPORT3 (P7.30) 4 PUSHBUTTON3 74LVC14A SOIC14 EXPANSION INTERFACE (J3.31), UART3 (P12.5) SW5.3 PB3 (SW11) ON (U2 - GPIO: PB10) C222 1UF 0805 1 TIMERS (P11.10), SPORT2 (P6.32), SPORT3 (P7.32) U29 PUSHBUTTON4/HPWAIT HOST INTERFACE (P3.12), NOR_RESET (SW16.4) SW5.4 PB4 (SW10) ON (U2 -GPIO: PB11) EXPANSION INTERFACE (J1.85) LED1 LED2 LED3 LED4 LED5 R121 10K 0402 LABEL "PB2" LED6 R101 100 0805 R135 10 0603 U30 5 SW12 MOMENTARY SWT024 2 1A1 4 1A2 6 1A3 8 1A4 18 1Y1 16 1Y2 14 1Y3 12 1Y4 11 2A1 13 2A2 15 2A3 17 2A4 9 2Y1 7 2Y2 5 2Y3 3 2Y4 3.3V 6 1 OE1 19 OE2 74LVC14A SOIC14 C221 1UF 0805 LED6 YELLOW LED001 LED5 YELLOW LED001 LED4 YELLOW LED001 LED3 YELLOW LED001 LED2 YELLOW LED001 POWER LED7 GREEN LED001 LED1 YELLOW LED001 IDT74FCT3244APY SSOP20 SW5 1 ON 1 3 6 4 5 2 7 3 4 LABEL "PB3" PUSHBUTTON1 PUSHBUTTON2 R119 330 0603 PUSHBUTTON3 PUSHBUTTON4/HPWAIT R124 330 0603 R125 330 0603 R126 330 0603 R127 330 0603 R128 330 0603 R129 330 0603 3.3V DIP4 SWT018 R122 10K 0402 2 8 2 2 SW5: Push Button Enable Switch R103 100 0805 R136 10 0603 U30 9 SW11 MOMENTARY SWT024 8 C211 0.01UF 0402 74LVC14A SOIC14 C220 1UF 0805 U29 LABEL "PB4" R123 10K 0402 3.3V R138 100 0805 R137 10 0603 U30 1 SW10 MOMENTARY SWT024 2 74LVC14A SOIC14 RESET LED8 RED LED001 C210 1UF 0805 R131 10K 0402 3 R130 330 0603 R132 10K 0402 3.3V 1 MR PFI 1 U31 4 R133 10K 0402 U30 SW9 MOMENTARY SWT024 RESET RESET 8 7 RESET 5 PFO ADM708SARZ SOIC8 2 R162 10K 0402 3 U27 4 DA_SOFT_RESET R182 10K 0402 SN74LVC1G08 SOT23-5 U30 13 12 11 74LVC14A SOIC14 10 3.3V 3.3V 74LVC14A SOIC14 3.3V C185 0.01UF 0402 C184 0.01UF 0402 ANALOG DEVICES C186 0.01UF 0402 4 U31 Title U27 Size Date A B C Nashua, NH 03063 4 PH: 1-800-ANALOGD ADSP-BF548 EZ-KIT LITE PUSH BUTTONS, LEDS AND BOOT MODE Board No. C U30 20 Cotton Road Rev A0206-2006 1.4C Sheet 9-12-2008_16:43 D 13 of 17 A B C D 3.3V EXPANSION INTERFACE (TYPE B) R254 10K 0402 5V 3.3V 5V U20 3.3V U19 1 R253 33 0402 4 VDD 1 OE 3 EXPANSION_PPI_CLK 1 3 OUT GND 27MHZ 2 OSC003 1 4 PPI1_SEL 3.3V 3.3V ADG752BRTZ SOT23-6 D[0:15] A[1:24] A1 6 8 7 A2 A5 10 9 A4 SPI2MISO A9 11 14 A11 13 16 A13 15 18 A15 17 20 19 24 23 A18 PPI0FS2_R A20 28 27 A22 30 29 A24 DT3SEC 32 31 DT3PRI 34 33 TFS3 38 D1 BOOTWAIT PUSHBUTTON1 36 40 35 TSCLK3 37 DT2SEC 39 D0 DT2PRI D3 42 41 D2 TFS2 D5 44 43 D4 TSCLK2 D7 46 45 D6 D9 48 47 D8 D11 50 D13 49 52 D15 51 54 53 PPI0D2_R LED2 LED4 LED6 R73 0 0603 PPI0D5_R PPI0D7_R PPI0D9_R D10 PPI0D11_R D12 PPI0D13_R D14 PPI0D15_R 56 55 58 57 SPI0SEL3 60 59 SCL0 62 61 64 63 66 65 ABE1/NDALE 68 67 ABE0/NDCLE 70 69 AOE 72 PPI0D0_R 6 5 71 74 73 76 75 78 77 80 79 82 81 84 83 86 85 88 87 90 89 8 7 10 9 12 11 14 13 16 15 18 17 20 19 22 21 24 23 26 25 28 27 30 29 32 31 34 33 36 35 38 37 40 39 42 41 44 43 46 45 48 47 50 49 52 51 54 53 56 55 58 57 60 59 62 61 64 63 66 65 A14 A19 2 PPI0D17_R A12 A16 A23 3 SPI2SCK UART2TX PUSHBUTTON1 UART3TX SPI0SCK PE3 PPI0CLK_R PPI0D1_R PPI0D3_R LED1 LED3 LED5 PUSHBUTTON4/HPWAIT AWE 68 67 70 69 72 74 PPI1D2/HPD10_R PPI1D4/HPD12_R PPI1D6/HPD14_R A10 21 25 SPI0MISO A8 22 26 SPI0MOSI A6 A17 A21 4 PPI1D0/HPD8_R J3 2 1 4 3 6 5 PPI1D1/HPD9_R 5 A3 12 1 3 SPI2MOSI A7 J2 2 PPI1D8/HPD0/KPR0_R NMI PPI1D10/HPD2/KPR2_R PPI1D12/HPD4KPC0_R PPI1D14/HPD6/KPC2_R PUSHBUTTON2 PPI0FS1_R DR3SEC RESET DR3PRI RFS3 UART3RTS RSCLK3 SPI0SEL1 DR2SEC SPI0SEL3 DR2PRI RFS2 PE8 PPI1FS2_R RSCLK2 PPI0D4_R PPI0D6_R PPI1FS3/UART1_TX PPI0D8_R PPI0D10_R PPI0D12_R PPI0D14_R PPI0D16_R SDA0 AMS3 AMS2 AMS1 AMS0 8 7 10 9 12 11 14 13 16 15 18 17 20 19 22 21 24 23 26 25 28 27 30 29 32 31 34 33 36 35 38 37 40 39 42 41 44 43 46 45 48 47 50 49 52 51 54 53 56 55 58 57 60 59 62 61 64 63 66 65 68 67 70 69 71 72 71 73 74 73 NORWAIT ARE 76 75 78 77 78 77 79 80 81 82 84 83 86 85 86 85 88 87 88 87 89 CON019 PPI1D5/HPD13_R PPI1D7/HPD15_R PPI1D9/HPD1/KPR1_R PPI1D11/HPD3/KPR3_R U19 U20 PPI1D13/HPD5/KPC1_R PPI1D15/HPD7/KPC3_R EXPANSION_PPI_CLK 2 CLKOUT PUSHBUTTON3 UART3CTS/PB3 SPI0SEL2 PE7 All USB interface circuitry is considered proprietary and has been omitted from this schematic. PPI1FS1_R PPI0FS3/ATAPIRESET When designing your JTAG interface please refer to the Engineer to Engineer Note EE-68 which can be found at http://www.analog.com UART1_RX 3.3V 3.3V R212 4.7K 0402 3.3V R250 33 0402 DSP JTAG HEADER R215 0 0402 TMS TCK ZP4 1 81 83 90 PPI1D3/HPD11_R SDA1 90 TMS 2 TCK 4 5 6 7 8 BR/PJ11 BG/PJ12 TRST DA_EMULATOR_SELECT 3 R251 33 0402 DA_EMULATOR_EMU TRST DA_EMULATOR_TMS TDI TDI DA_EMULATOR_TCK 9 10 11 12 13 14 R252 33 0402 TDO DA_EMULATOR_TRST EMU DA_EMULATOR_TDI 79 84 CON019 UART3RX 3 75 82 C188 0.01UF 0402 3V 76 80 C258 0.01UF 0402 UART2RX TDO DA_EMULATOR_TDO DA_GP0 IDC7X2 EMU DA_GP1 RESET RESET DA_GP2 BGH/PJ13 89 SCL1 DA_SOFT_RESET DA_SOFT_RESET R283 22 0402 CON019 R213 10K 0402 DA_GP3 SHGND 4 1 R249 10K 0402 GND J1 2 3 PPI1CLK_R 6 DEBUG_AGENT C187 1UF 0603 SHGND ANALOG DEVICES 4 Title Size A B C Nashua, NH 03063 4 PH: 1-800-ANALOGD ADSP-BF548 EZ-KIT LITE EXPANSION INTERFACE & JTAG Board No. C Date 20 Cotton Road Rev A0206-2006 1.4C Sheet 9-24-2008_15:47 D 14 of 17 A B 5V C D 3.3V 5V 3.3V UNREG_IN UNREG_IN SPORT 2 P6 2 TSCLK2 DR2PRI 1 3 6 5 8 7 10 DR2SEC DT2SEC DT2PRI RSCLK2 STAMP_MOSI1 SDA0 SCL0 14 13 DT3SEC 16 15 DT3PRI 18 17 24 23 26 25 PUSHBUTTON3 RSCLK3 STAMP_MOSI1 STAMP_SPI1SEL1 STAMP_MISO1 STAMP_SPI1SEL2 STAMP_SCK1 STAMP_SPI1SEL3 SDA0 STAMP_GPIO0 SCL0 27 STAMP_GPIO1 PUSHBUTTON1 29 32 31 34 33 4 3 8 7 10 9 12 STAMP_SPI1SS 21 30 PUSHBUTTON2 TFS2 19 28 PUSHBUTTON1 DR3SEC 11 1 5 DR3PRI STAMP_GPIO2 PUSHBUTTON2 STAMP_GPIO3 PUSHBUTTON3 CAN0RX R232 0 0402 STAMP_GPIO0 LED6 P7 2 6 TSCLK3 RFS2 12 22 STAMP_SCK1 RESET 9 20 STAMP_MISO1 SPORT 3 1 4 R236 0 0402 R237 0 0402 RESET 14 13 16 15 18 17 20 19 22 21 24 23 26 25 28 27 30 29 32 31 34 33 CAN0_ERR STAMP_GPIO1 2 STAMP_SPI1SS TFS3 STAMP_SPI1SEL1 1A2 6 LED1 3.3V CAN1RX STAMP_GPIO2 1A3 8 LED2 1A4 11 STAMP_MISO1 R239 0 0402 STAMP_SPI1SS 4 #HPCE/CNTCZM R238 0 0402 LED5 CAN1_ERR STAMP_GPIO3 R248 10K 0402 STAMP_SPI1SEL2 STAMP_SPI1SEL3 JP2 1 STAMP_GPIO0 LED3 2A4 STAMP_SPI1SEL2 STAMP_SPI1SEL3 R240 0 0402 LED4 R241 0 0402 JP7 OE1 JP2 DEFAULT JUMPER SETTING = NOT INSTALLED 1 R235 0 0402 1 2 IDC2X1 STAMP_GPIO2 2A3 17 STAMP_MOSI1 19 STAMP_GPIO1 2A2 15 R234 0 0402 9 2Y1 7 2Y2 5 2Y3 3 2Y4 2A1 13 STAMP_SPI1SEL1 18 1Y1 16 1Y2 14 1Y3 12 1Y4 1A1 RFS3 11 R233 0 0402 U26 1 2 OE2 STAMP_MOSI1 IDC2X1 74CBTLV3244 TSSOP20 R242 0 0402 STAMP_GPIO3 STAMP_SCK1 IDC17X2 3.3V IDC17X2 JP2: SPI1 ENABLE JUMPER JP8 1 JUMPER 2 LED5 MODE IDC2X1 UNREG_IN 5V 3.3V ON SPI1 CONNECTOR ACTIVATED OFF SPI1 CONNECTOR DEACTIVATED C257 0.01UF 0402 JP2 DEFAULT JUMPER SETTING = OFF (NOT INSTALLED) 2 2 PPI P8 2 1 UNREG_IN 4 3 6 5 8 7 10 9 UNREG_IN 3.3V PPI1CLK_R PPI1D0/HPD8_R PPI1D2/HPD10_R PPI1D4/HPD12_R PPI1D6/HPD14_R PPI1D8/HPD0/KPR0_R PPI1D10/HPD2/KPR2_R PPI1D12/HPD4KPC0_R PPI1D14/HPD6/KPC2_R STAMP_GPIO0 STAMP_SPI1SEL1 RESET 11 14 13 16 15 18 17 20 19 22 21 24 23 26 25 28 27 30 STAMP_MOSI1 STAMP_MISO1 STAMP_SCK1 3 12 SDA0 SCL0 29 32 31 34 33 36 35 38 37 40 39 5V 3.3V SPI TWI PPI1D1/HPD9_R P10 2 1 PPI1D3/HPD11_R 4 3 PPI1D5/HPD13_R 6 SDA1 PPI1D7/HPD15_R PPI1D9/HPD1/KPR1_R STAMP_GPIO0 PPI1D11/HPD3/KPR3_R STAMP_GPIO2 PPI1D13/HPD5/KPC1_R PPI1D15/HPD7/KPC3_R STAMP_MISO1 5 8 7 10 9 SCL1 STAMP_SCK1 RESET STAMP_SPI1SS STAMP_GPIO1 12 11 14 13 16 U26 5V STAMP_SPI1SEL2 STAMP_GPIO3 STAMP_GPIO0 STAMP_GPIO2 15 STAMP_SPI1SEL2 18 17 STAMP_SPI1SS 20 19 P9 2 1 4 3 6 5 8 7 10 9 12 11 14 13 16 15 18 17 20 JP7: MOSI1 OUT JUMPER STAMP_MOSI1 JUMPER STAMP_SPI1SEL1 ON MOSI1 OF U2 TRANSMITTING TO STAMP CONNECTORS OFF NO CONNECTION BETWEEN MOSI1 OF U2 TO STAMP CONNECTORS STAMP_SPI1SEL3 STAMP_GPIO1 JP7 DEFAULT JUMPER SETTING = OFF (NOT INSTALLED) STAMP_GPIO3 19 IDC10X2 PPI1FS3/UART1_TX MODE RESET JP8: MOSI1 IN JUMPER IDC10X2 PPI1FS1_R JUMPER MODE PPI1FS2_R 3 ON MOSI1 OF U2 RECEIVING FROM STAMP CONNECTORS OFF NO CONNECTION BETWEEN MOSI1 OF U2 TO STAMP CONNECTORS IDC20X2 JP8 DEFAULT JUMPER SETTING = OFF (NOT INSTALLED) 3.3V 5V 5V 3.3V UART 3 TIMERS P11 2 4 6 PUSHBUTTON1 8 PUSHBUTTON2 4 10 PUSHBUTTON3 1 3 5 STAMP_GPIO0 STAMP_GPIO1 UART3TX STAMP_GPIO2 P12 2 1 4 3 6 5 8 7 10 9 PUSHBUTTON2 PUSHBUTTON3 ANALOG DEVICES 7 9 UART3RX IDC5X2 IDC5X2 NOTE: PUSHBUTTONS AND TIMERS [2:0] SHARE THE SAME NET NAMES Board No. C Date A B C Nashua, NH 03063 4 PH: 1-800-ANALOGD ADSP-BF548 EZ-KIT LITE STAMP CONNECTORS Title Size 20 Cotton Road Rev A0206-2006 1.4C Sheet 9-24-2008_15:47 D 15 of 17 A B F1 5A FUS005 C D15 MBRS540T3G 5A SMC FER19 190 FER002 4 3 1 2 D LABEL "VDDINT" VROUT UNREG_IN JP4 1 J7 JP4: VDDINT POWER JUMPER 1 D4 MBRS540T3G 5A SMC C191 1000PF 1206 2 MODE ON NO POWER MEASUREMENT OFF FOR POWER MEASUREMENT 1 U28 L1 10UH IND001 1 5 2 6 3 7 4 8 R192 0.05 1206 VDDINT D5 ZHCS1000 SOT23-312 JP4 DEFAULT JUMPER SETTING = ON (INSTALLED) C190 1000PF 1206 2 IDC2X1 R207 0 0402 JUMPER 3 7_5V_POWER CON005 TP15 3.3V CT5 100UF C 1 LABEL "GND" FDS9431A SOIC8 FER15 600 1206 CT3 100UF C C193 10UF 0805 TP11 C189 0.1UF 0603 FER16 600 1206 SHGND SHGND VDDINT JP10 1 3.3V R267 0.05 1206 DNP VR4 1 EN 4 IN 2 ADJ 5 GND1 C272 0.1UF 0603 3 OUT 2 2 C271 10UF 0805 2 IDC2X1 DNP 6 GND2 R265 10.0K 0402 7 GND3 LABEL "GND" 8 TP26 GND4 C273 10UF 0805 ADP1715 MSOP8 C274 0.1UF 0603 R266 20.0K 0603 UNREG_IN C201 10UF 1210 C133 10UF 0805 DNP JP5: VDDEXT POWER JUMPER JUMPER MODE ON NO POWER MEASUREMENT OFF FOR POWER MEASUREMENT UNREG_IN A5V VR5 7 TP17 1 IN1 3 PGND FER17 600 1206 R155 24.9K 0603 OUT1 8 2 IN2 OUT2 R157 0.05 1206 VR3 5 IN 1 COMP 3 SD 5 FB GND 4 ADP3336ARMZ MSOP8 CS R164 210.0K 0805 C209 4.7UF 0805 C199 470PF 0603 C204 1UF 0805 C200 68PF 0603 3 FB 4 6 PGATE GND 2 R159 80.6K 0603 R156 0 0603 ADP1864AUJZ SOT23-6 C205 1UF 0805 1 5 2 6 3 7 4 8 L2 2.5UH IND013 2 3 D13 MBRS540T3G SMC VDDEXT R194 0.05 1206 CT4 220UF D2E CT6 2.2UF B DNP C202 4.7UF 0805 LABEL "GND" W2 COPPER R160 255.0K 0603 AGND JP5 1 JP5 DEFAULT JUMPER SETTING = ON (INSTALLED) SI4411DY SO-8 R165 64.9K 0805 3.3V IDC2X1 OUT3 6 R204 0.05 1206 DNP U16 TP12 4A PGND PGND PGND ANALOG DEVICES 4 Board No. C Date A B C Nashua, NH 03063 4 PH: 1-800-ANALOGD ADSP-BF548 EZ-KIT LITE POWER PAGE 1 Title Size 20 Cotton Road Rev A0206-2006 1.4C Sheet 9-12-2008_16:43 D 16 of 17 A B C D VDDDDR SW1 SW2 C242 1UF 0603 D10 BAT54 SOT23D 2.5V R208 1.1K 0402 R191 1.1K 0402 20 CSL1 23 DH1 BST1 21 1 SW1 R175 0 0402 22 DH1 18 DL1 DL1 1 FB1 32 COMP1 R183 18K 0402 R189 100K 0603 C231 680PF 0603 C224 1500PF 0402 C225 22PF 0805 24 POK1 VREG 31 TRK1 25 UNREG_IN EN1 27 R190 0 0402 DNP R185 10.0K 0402 JP6 UNREG_IN 1 U22 IDC2X1 D12 BAT54A SOT23D LDOSD 28 IN R176 0 0402 14 CSL2 11 BST2 13 SW2 12 DH2 16 DL2 7 COMP2 6 FB2 5 UV2 DH1 4 5 D1A 6 D1B 3 S1 2 7 D2A 8 D2B 1 S2 G1 DH2 R177 0 0402 2 2.5V VR7 R174 0 0402 R184 820 0402 D11 BAT54 SOT23D VREG VREG R186 34.0K 0603 C215 1UF 0603 C234 10UF 1210 DL2 DL1 G2 5V SW1 L3 10UH IND012 R193 0.05 1206 C235 10UF 0805 C236 10UF 0805 C237 10UF 0805 1 CT9 100UF C LABEL "GND" TP23 FDS9926A SOIC8 R188 100K 0603 10 POK2 26 EN2 8 TRK2 3 FREQ 29 VREG 17 PV R178 10K 0402 JP6: VDDDDR POWER JUMPER R179 75.0K 0603 R187 10K 0402 EN2 C217 82PF 0402 VREG R180 430 0402 AGND2 C218 4700PF 0603 C219 1200PF 0402 JUMPER MODE ON NO POWER MEASUREMENT OFF FOR POWER MEASUREMENT JP6 DEFAULT JUMPER SETTING = ON (INSTALLED) 30 EN2 C240 0.1UF 0402 EN2 C239 22000PF 0402 SS1 4 GND 33 NC 2 SYNC DGND2 9 SS2 19 PGND1 15 PGND2 C216 1UF 0603 C223 22000PF 0402 UNREG_IN R181 10.0K 0402 C241 1UF 0603 U23 ADP1823 LFCSP32 C238 10UF 1210 4 G1 5 D1A 6 D1B 3 S1 2 G2 7 D2A 8 D2B 1 S2 DGND2 W3 COPPER 2 DH2 5V DGND2 AGND2 DGND2 DL2 3A SW2 L4 8.2UH IND012 R147 0 0805 C233 10UF 0805 C232 10UF 0805 CT8 100UF C 2 FDS9926A SOIC8 AGND2 W4 COPPER AGND2 1A LABEL "GND" DGND2 TP16 TP22 TP21 TP14 TP13 5V 3.6V 3 R258 0 0402 DNP VR2 7 IN1 8 IN2 R257 10K 0402 6 SD USB_VRSEL R256 0 0402 DNP 5V_USB D22 ZHCS1000 SOT23-312 DNP R278 0 0402 R199 0 0402 DNP R280 0 0805 USB_VRSEL DNP IN1 8 IN2 OUT1 OUT2 OUT3 6 USB_VRSEL SD R229 10K 0402 U39 7 IN1 1 2 3 MH8 MH9 MH10 MH3 MH2 MH1 MH11 MH12 MH13 MH14 R71 75.0K 0603 6 OUT1 8 OUT2 R68 210.0K 0805 C203 1UF 0805 C138 4.7UF 0805 C279 1UF 0805 R281 1K 0603 DNP 2 FLG GND 3 MIC2025-1 SOIC8 C278 1UF 0805 ANALOG DEVICES Size Board No. C Date B C 20 Cotton Road Nashua, NH 03063 4 PH: 1-800-ANALOGD ADSP-BF548 EZ-KIT LITE POWER PAGE 2 Title A MH4 C140 4.7UF 0805 C139 1UF 0805 R69 64.9K 0805 4 MH6 1 EN 5 FB GND 4 ADP3336ARMZ MSOP8 R70 154.0K 0402 5V_USB VR1 7 3 MH5 R279 0 0402 UNREG_IN D21 ZHCS1000 SOT23-312 1 OUT1 2 OUT2 3 OUT3 5 FB GND 4 ADP3336ARMZ MSOP8 Rev A0206-2006 1.4C Sheet 9-12-2008_16:43 D 17 of 17 A B C D FOR BF549 DESIGNS USING MXVR ALL COMPONENTS ON THIS PAGE ARE POPULATED EXCEPT: R195,R196,R284,TP19,TP20 5V NOTE: THIS CIRCUIT FOR B549 DESIGNS ONLY. UNPOPULATED FOR BF548 VERSION. 1 1 DNP = DO NOT POPULATE C183 10UF 0805 DNP R118 10K 0402 DNP R117 10K 0402 DNP U18 3 2 1 FER13 600 0603 DNP FER14 600 0603 DNP C174 10UF 0805 DNP C182 10UF 0805 DNP C176 0.1UF 0402 DNP 5 TXVCC RXVCC 2 3 U17 E2 C2 B2 B1 C1 E1 4 R197 0 0402 DNP 5 6 LED6 XN04114 R196 10K 0402 DNP ICS008 DNP R112 33.0K 0402 DNP C181 0.1UF 0402 DNP R114 0 0402 DNP TXD CONTROL C173 0.1UF 0402 DNP R22 27 0402 DNP 1 R195 0 0402 DNP MTX R116 33.0K 0402 DNP MMCLK TXGND RXGND Default is DNP. (DNP=Do Not Populate) 7 8 MRXONB R113 0 0402 DNP MRX 2 6 HSDL2300 RXD CODEC_CLKIN This allows CODEC to be run based on MOST Frequency. 4 R115 0 0402 DNP STATUS 2 DNP NOTE: MTX and MRX need to be kept as short as possible and should be shielded. They should also not be routed side by side. U2 MFS 3 MXO MXI MLFM MLFP E6 C1 TP19 3 TP20 C2 F4 BF549 DESIGN NOTE: C20 AND C21 SHOULD BE PPS TYPE, 2% TOLERANCE. E4 R23 SHOULD BE 1% TOLERANCE. C20 330PF 0603 DNP R23 330.0 0402 DNP ADSP-BF548 MBGA400 C21 0.047UF 1206 DNP THE LOOP FILTER CIRCUIT SHOULD BE PHYSICALLY CLOSE TO MLF_P AND MLF_M AND SHOULD BE SHIELDED USING GNDMP. 3.3V NOTE: THIS CIRCUIT FOR B549 DESIGNS ONLY. UNPOPULATED FOR BF548 VERSION. 3.3V R231 10K 0402 DNP C22 0.01UF 0402 DNP U8 4 VDD 1 OE 4 R24 33 0402 DNP OUT R284 0 0402 NOTE: PULL-DOWN ON MXI NEEDED WHEN NOT USING MXVR. (BF548) PULL-DOWN SHOULD BE UNPOPULATED FOR MXVR USE. (BF549) 3 ANALOG DEVICES GND 24.576MHZ 2 OSC003 DNP U8 NOTE: THIS CIRCUIT FOR B549 DESIGNS ONLY. Size C Nashua, NH 03063 Board No. B C Rev A0206-2006 Date A 4 PH: 1-800-ANALOGD ADSP-BF548 EZ-KIT LITE MXVR Title UNPOPULATED FOR BF548 VERSION. 20 Cotton Road 1.4C Sheet D 1 of 1 I INDEX A B AD1980 audio codec See also audio interface data pin (PC2), 2-5 reset switch (SW16.1), 2-4, 2-22 AD7877 touchscreen controller, See touchscreen ADM3202 bit, 1-28 advanced technology attachment packet interface, See ATAPI AMS0 memory select pin, 1-17 AMS1 memory select pin, 1-24 analog audio interface, See audio interface architecture, of this EZ-KIT Lite, 2-2 ASYNC (asynchronous memory control) external memory banks 0-3, 1-14 ATA/ATAPI-6 controller, 1-26 ATAPI interface, 1-26, 2-14 connector (J14), 2-37 hard disk drive, 1-26 reset signal (PH2), 2-12 audio interface, xiv, 1-25 connector (J10), 1-25, 2-36 dual connectors (J8-9), 1-25, 2-36 loopback test switch (SW8), 2-19 battery holder (J13), 2-36 bill of materials, A-1 board design database, 1-33 board schematic (ADSP-BF548), B-1 boot modes, 2-15 mode select switch (SW1), 1-18, 1-19, 2-15 burst flash memory, xiii, 1-17, 2-12, 2-13, 2-14, 2-23 C CAN interface, 1-28 CAN0 signals, 2-18 CAN1 signals, 2-22 SW15 (CAN1) enable switch, 2-22 SW6 (CAN0) enable switch, 2-18 transceiver devices, 1-28 CAN0_ERR signal, 1-28, 2-18 CAN0RX signal, 2-18 CAN1_ERR signal, 1-28, 2-22 CAN1RX signal, 2-22 CCLK register, 1-17 CLK pin, 1-19 clock in (CLK IN) signal, 2-3 code security, 1-12 configuration, of this EZ-KIT Lite, 1-4 ADSP-BF548 EZ-KIT Lite Evaluation System Manual I-1 Index connectors diagram of locations, 2-33 J10 (audio), 1-25, 2-36 J13 (battery), 2-36 J1-3 (expansion), 1-32, 2-34 J14 (ATAPI), 2-37 J4 (Ethernet), 1-25, 2-34 J5 (SD card), 1-19, 2-35 J6 (RS-232), 2-35 J7 (power), 2-35 J8-9 (dual audio), 1-25, 2-36 P10 (TWI), 2-40 P11 (timers), 2-40 P12 (UART3), 1-28, 2-4, 2-41 P14 (LCD touchscreen), 2-41 P15 (LCD data), 2-21, 2-41 P1 (keypad), 1-23, 2-37 P3 (host interface), 1-23, 1-24, 2-5, 2-6, 2-10, 2-38 P4 (USB OTG), 1-27, 2-38 P5 (LCD backlight), 2-38 P6 (SPORT2), 2-3, 2-4, 2-8, 2-10, 2-39 P7 (SPORT3), 2-4, 2-8, 2-10, 2-39 P8 (PPI1), 2-6, 2-8, 2-12, 2-39 P9 (SPI), 2-40 PJ11 (AD7877 data), 2-14 PJ12 (AD7877 interrupt), 2-14 ZJ1 (USB), 2-42 ZP4 (JTAG), 1-31, 2-42 contents, of this EZ-KIT Lite package, 1-3 core clock signal (CCLK), 1-15 voltage, 2-2 D data available output (DAV) signal, 1-23, 2-21 DDRCS0 signal, 1-15 I-2 DDR registers, 1-16 default configuration, of this EZ-KIT Lite, 1-4 DIP switch (SW5), 1-31, 2-4, 2-5, 2-18, 2-20, 2-23 double data rate (DDR) interface, xiii, 1-15 E EBIU_AMGCTL register, 1-17 EBIU_DDRCTL0-2 registers, 1-16 enhanced parallel peripheral interface (EPPI), See PPI0, PPI1 ERR signals, 1-28 Ethernet interface, xiv, 1-24 cables, 1-3 connector (J4), 1-25, 2-34 controller (U14), 1-24, 2-12, 2-23 enable switch (SW16.3), 1-24, 2-23 LED (LED9), 2-32 PHY portion, 1-25 serial ROM (U12), 1-24 speed select jumper (JP3), 2-27 evaluation license CCES, 1-11 VisualDSP++, 1-11 example programs, 1-34 expansion interface, 1-18, 1-20, 1-23, 1-32, 2-3, 2-4, 2-7, 2-12, 2-13, 2-14, 2-34 external memory, 1-13, 1-14 F features, of this EZ-KIT Lite, xiii FET switches, 1-26, 1-27, 2-22 flag pins, See programmable flags by name (PAx to PJx) flash memory, See burst flash memory ADSP-BF548 EZ-KIT Lite Evaluation System Manual Index G K general-purpose IO pins, 1-31, 2-16, 2-17, 2-18, 2-19, 2-21, 2-22, 2-31 keypad interface connections, 1-23 connector (P1), 2-37 enable switch (SW2), 1-23, 2-6, 2-16 H host interface, 1-29 host interface connector (P3), 1-23, 1-24, 2-5, 2-6, 2-10, 2-38 I IDC header (P3), 1-29 installation, of this EZ-KIT Lite, 1-4 CCES, 1-5 VisualDSP++, 1-9 interrupt output (PENIRQ) signal, 2-21 IO voltage, 2-2 J JTAG interface, 1-31 connector (ZP4), 1-31, 2-42 jumpers diagram of locations, 2-25 JP11 (USB OTG power), 2-30 JP12 (PPIFS3), 1-28, 2-30 JP1 (UART1 loopback), 1-28, 2-26 JP2 (SPI enable), 2-26 JP3 (Ethernet speed select), 2-27 JP4 (VDDINT power), 1-33, 2-27 JP5 (VDDEXT power), 1-33, 2-28 JP6 (VDDDDR power), 1-33, 2-28 JP7 (MOSI1 out), 2-29 JP8 (MOSI1 in), 2-29 L LCD module See also touchscreen interface, xiii, 1-21 backlight connector (P5), 2-38 config switch (SW17), 1-22, 2-6, 2-8, 2-9 data connector (P15), 2-21, 2-41 PPI config switch (SW14), 1-22, 2-4, 2-7, 2-21 touchscreen connector (P14), 2-41 LEDs diagram of locations, 2-31 LED1-6 (PG6-11), 1-31, 1-34, 2-10, 2-29, 2-31 LED7 (power), 2-32 LED8 (reset), 2-32 LED9 (Ethernet), 2-32 ZLED3 (USB monitor), 1-9 Lockbox secure technology, 1-12 M MAC address, 1-24 Media Instruction Set Computing (MISC), xi memory map, of this EZ-KIT Lite, 1-13 Micro Signal Architecture (MSA), xi MOSI1 in jumper (JP8), 2-29 out jumper (JP7), 2-29 ADSP-BF548 EZ-KIT Lite Evaluation System Manual I-3 Index N NAND chip enable signal, 2-14 flash memory interface, xiii, 1-18 NOR RESER (SW16.4), 2-5 notation conventions, xxi O oscillator, 1-20, 2-21 oscilloscope, 1-33 OTG interface, 1-27 P PA0-15 signals, 2-3 package contents, 1-3 PB0-7 signals, 2-4 PB11 signal, 2-4, 2-18, 2-20, 2-23 PB12-14 signals, 2-4 PB1-4 (SW13-10) push buttons, 1-23, 2-18, 2-20 PB8-10signals, 2-4, 2-18, 2-20 PC0-13 signals, 2-5 PD0-7 signals, 2-6 PD8-15 signals, 2-6, 2-16 PE0-6 signals, 2-7 PE11-15 signals, 2-7 PE7 signal, 1-27, 2-7 PE8 signal, 1-24, 2-7 PE9-10 signals, 2-7, 2-19 pen interrupt (PENIRQ) signal, 1-23 peripheral control enable (SW16), 2-22 PF0-15 signals, 2-8 PG0-4 signals, 2-9 PG10/MOSI1 signal, 2-9, 2-29 PG11-15 signals, 2-9 PG5 signal, 2-9, 2-17 PG6-11 (IO) signals, 1-31, 2-9, 2-31 I-4 PH0 signal, 2-12 PH1 signal, 2-12, 2-19 PH2 signal, 2-12 PH3-4 signals, 2-12, 2-17 PH5-13 signals, 2-12 PI0-15 signals, 2-13 PJ0-13 signals, 2-14 PLL_CTL register, 1-17 PLL_DIV register, 1-17 POST (power-on-self test) program, 1-17, 1-19, 1-28, 1-33, 2-26 power connector (J7), 2-35 LED (LED7), 2-32 measurements, 1-33 supply, 1-3 PPI0 interface config for LCD module, 1-20, 1-21 PPI0FS1 signal, 1-23 PPI1 interface connections, 1-20 connector (P8), 2-6, 2-8, 2-12, 2-39 connector via JP2, 2-10 PPI1CLK multiplexter, 2-21 PPI1FS3 pull-down jumper (JP12), 1-28, 2-30 PPI1_SEL signal, 1-20 product information, xix programmable flags (PCs) PC0 (CAN0_ERR), 1-28 PC5 (CAN1_ERR), 1-28 programmable flags (PFs), See PAx, PBx, PCx, PDx, PEx, PFx, PGx, PHx, PIx, PJx push buttons See also switches by name (SWx) SW13-10, 1-23, 2-18, 2-20 ADSP-BF548 EZ-KIT Lite Evaluation System Manual Index R real-time clock (RTC), 1-30, 2-3 Reduced Instruction Set Computing (RISC), xi related documents, xx reset AD1980 codec (SW16.3), 2-4, 2-22 LEDs (LED8), 2-32 push button (SW9), 2-19, 2-20 rotary enable switch (SW4), 1-24, 2-12 rotary encoder interface, 1-24 enable switch (SW4), 2-10, 2-17 switch (SW3), 1-24, 2-17 RS-232 connector (J6), 2-35 RTC interface, 1-30 S schematic, of ADSP-BF548 EZ-KIT Lite, B-1 SD memory card connector (J5), 1-19, 2-35 clock pin (SD_CLK), 2-6 data pins (SD_Dx), 2-5 SDRAM controller, 1-15 memory map, 1-14 secure digital (SD) interface, See SD memory serial flash memory, 1-18, 2-7 serial peripheral interconnect (SPI) ports, See SPI SPI connector (P9), 2-5, 2-40 connector via JP2, 2-10 flash memory, xiii, 1-18, 2-7 SPI0 interface connections, 1-22 SPI0SEL1 signal, 1-19 SPI0SEL2 signal, 1-19, 1-23 SPI0SEL3 flag pin, 1-19 SPI1 interface, enable jumper (JP2), 2-26 SPORT2 connector (P6), 2-3, 2-4, 2-5, 2-8, 2-10, 2-39 SPORT3 connector (P7), 2-4, 2-5, 2-8, 2-10, 2-39 SRAM memory, 1-13 See also internal memory STAMP connectors, 1-20, 1-28, 2-18, 2-26 startup, of this EZ-KIT Lite CCES, 1-5 VisualDSP++, 1-9 STOPACQ signal, 1-23 SW14 (LCD/PPI config) switch, 1-20, 1-22, 2-4, 2-7, 2-21 SW15 (CAN1 enable) switch, 1-29, 2-22 SW16.1 (audio codec reset) switch, 2-4, 2-22 SW16.2 (USB OTG enable) switch, 1-27, 2-8, 2-22 SW16.3 (Ethernet enable) switch, 1-24, 2-23 SW16.4 (NOR RESET) switch, 2-5, 2-23 SW16 (peripheral Ctrl enable) switch, 2-22 SW17 (LCD config) switch, 1-22, 2-6, 2-8, 2-9 SW1 (boot mode select) switch, 1-18, 1-19, 2-15 SW2 (keypad enable) switch, 1-23, 2-6, 2-16 SW3 (rotary) switch, 1-24, 2-17 SW4 (rotary enable) switch, 1-24, 2-10, 2-12, 2-17 SW5 (push button enable) DIP switch, 1-31, 2-4, 2-5, 2-18, 2-20, 2-23 SW6 (CAN0 enable) switch, 1-28, 2-18 ADSP-BF548 EZ-KIT Lite Evaluation System Manual I-5 Index SW7 (UART enable) switch, 1-28, 2-8, 2-12, 2-19 SW8 (audio loopback test) switch, 2-19 SW9 (reset) push button, 2-19, 2-20 switches See also switches by name (SWx) diagram of locations, 2-15 synchronous dynamic random access memory, See SDRAM system architecture, of this EZ-KIT Lite, 2-2 clock (SCLK), 1-15 universal asynchronous receiver transmitter, See UART USB debug agent connector (ZJ1), 2-42 enable (SW16.2) switch, 1-27, 2-8, 2-22 interface, 2-42 OTG interface connector (P4), 1-27, 2-38 power jumper (JP11), 2-30 regulator (VR1), 2-22 voltage regulators, 1-27 V T technical support, xvii thumbwheel control, xiv timers connector (P11), 2-40 touchscreen interface, 1-22 AD7877 controller, 1-18, 1-22, 2-7, 2-21 connector (P14), 2-41 data connector (PJ11), 2-14 interrupt (PJ12), 2-14 TWI connector (P10), 2-4, 2-5, 2-40 VDDDDR pin, 1-33 power jumper (JP6), 1-33, 2-28 VDDEXT pin, 1-33 power jumper (JP5), 1-33, 2-28 VDDINT pin, 1-33 power jumper (JP4), 1-33, 2-27 very-long instruction word (VLIW), xi voltage planes, 1-32 VR1 (USB voltage) regulator, 1-27 U W UART1 interface connections, 2-12 enable switch (SW7.2), 2-12 installing JP12, 2-30 loopback jumper (JP1), 1-28, 2-26 UART1_RX signal, 2-26 UART1_TX signal, 2-26 UART3 interface connector (P12), 1-28, 2-4, 2-41 UART enable switch (SW7), 1-28, 2-8, 2-19 watchdog timer, 1-30 I-6 ADSP-BF548 EZ-KIT Lite Evaluation System Manual