ADSP-BF533 EZ-KIT Lite® Evaluation System Manual Revision 1.3, April 2004 Part Number 82-000730-01 Analog Devices, Inc. One Technology Way Norwood, Mass. 02062-9106 a Copyright Information © 2004 Analog Devices, Inc., ALL RIGHTS RESERVED. This document may not be reproduced in any form without prior, express written consent from Analog Devices, Inc. Printed in the USA. Limited Warranty The EZ-KIT Lite evaluation system is warranted against defects in materials and workmanship for a period of one year from the date of purchase from Analog Devices or from an authorized dealer. Disclaimer Analog Devices, Inc. reserves the right to change this product without prior notice. Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use; nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under the patent rights of Analog Devices, Inc. Trademark and Service Mark Notice The Analog Devices logo, VisualDSP++, VisualDSP++ logo, Blackfin, CROSSCORE logo, and EZ-KIT Lite are registered trademarks of Analog Devices, Inc. All other brand and product names are trademarks or service marks of their respective owners. Regulatory Compliance The ADSP-BF533 EZ-KIT Lite evaluation system has been certified to comply with the essential requirements of the European EMC directive 89/336/EEC (inclusive 93/68/EEC) and, therefore, carries the “CE” mark. The ADSP-BF533 EZ-KIT Lite evaluation system had been appended to the Technical Construction File referenced “DSPTOOLS1” dated December 21, 1997 and was awarded CE Certification by an appointed European Competent Body as listed below. Technical Certificate No: Z600ANA1.011 Issued by: Technology International (Europe) Limited 41 Shrivenham Hundred Business Park Shrivenham, Swindon, SN6 8TZ, UK The EZ-KIT Lite evaluation system contains ESD (electrostatic discharge) sensitive devices. Electrostatic charges readily accumulate on the human body and equipment and can discharge without detection. Permanent damage may occur on devices subjected to high-energy discharges. Proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Store unused EZ-KIT Lite boards in the protective shipping package. CONTENTS iv ADSP-BF533 EZ-KIT Lite Evaluation System Manual CONTENTS PREFACE Purpose of This Manual ................................................................. xiv Intended Audience ......................................................................... xiv Manual Contents ............................................................................ xv What’s New in This Manual ........................................................... xvi Technical or Customer Support ...................................................... xvi Supported Processors ..................................................................... xvii Product Information ..................................................................... xvii MyAnalog.com ........................................................................ xvii DSP Product Information ....................................................... xviii Related Documents ................................................................ xviii Online Documentation ............................................................. xx Printed Manuals ........................................................................ xx VisualDSP++ Documentation Set .......................................... xx Hardware Manuals ............................................................... xxi Data Sheets .......................................................................... xxi Contacting DSP Publications .................................................... xxi Notation Conventions ................................................................... xxii ADSP-BF533 EZ-KIT Lite Evaluation System Manual v CONTENTS GETTING STARTED Contents of EZ-KIT Lite Package ................................................. 1-1 PC Configuration ......................................................................... 1-3 Installation Tasks .......................................................................... 1-3 Installing VisualDSP++ and EZ-KIT Lite Software .................. 1-4 Installing and Registering VisualDSP++ License ....................... 1-5 Setting Up EZ-KIT Lite Hardware .......................................... 1-5 Installing EZ-KIT Lite USB Driver ......................................... 1-7 Windows 98 USB Driver .................................................... 1-8 Windows 2000 USB Driver .............................................. 1-12 Windows XP USB Driver ................................................. 1-13 Verifying Driver Installation .................................................. 1-15 Starting VisualDSP++ ........................................................... 1-16 USING EZ-KIT LITE EZ-KIT Lite License Restrictions .................................................. 2-2 Memory Map ............................................................................... 2-2 Using SDRAM Interface ............................................................... 2-4 Using Flash Memory ..................................................................... 2-5 Flash Memory Map ................................................................. 2-6 Flash General-Purpose IO ....................................................... 2-7 Configuring Flash Memory ..................................................... 2-9 Using LEDs and Push Buttons .................................................... 2-10 Using Audio ............................................................................... 2-11 vi ADSP-BF533 EZ-KIT Lite Evaluation System Manual CONTENTS Using Video ................................................................................ 2-12 Example Programs ...................................................................... 2-13 Using Background Telemetry Channel ......................................... 2-13 Using EZ-KIT Lite VisualDSP++ Interface .................................. 2-13 Trace Window ....................................................................... 2-14 Enabling Trace Buffer ........................................................ 2-14 Reading Trace Buffer Data ................................................ 2-15 Performance Monitor ............................................................ 2-15 Boot Load ............................................................................. 2-16 Target Options ...................................................................... 2-17 Reset Options ................................................................... 2-17 On Emulator Exit ............................................................. 2-17 Other Options .................................................................. 2-18 Restricted Software Breakpoints ............................................. 2-19 EZ-KIT LITE HARDWARE REFERENCE System Architecture ...................................................................... 3-2 External Bus Interface Unit ...................................................... 3-3 SPORT0 Audio Interface ......................................................... 3-4 SPI Interface ........................................................................... 3-4 Programmable Flags ................................................................. 3-4 PPI Interface ........................................................................... 3-5 Video Output Mode ........................................................... 3-7 Video Input Mode .............................................................. 3-7 UART Port .............................................................................. 3-8 ADSP-BF533 EZ-KIT Lite Evaluation System Manual vii CONTENTS Expansion Interface ................................................................. 3-8 JTAG Emulation Port ............................................................. 3-9 Jumper and DIP Switch Settings ................................................... 3-9 Boot Mode Select Jumpers (JP2–1) ........................................ 3-10 Core Voltage Source Select Jumper (JP3) ............................... 3-10 Test DIP Switches (SW2–1) .................................................. 3-11 Video Configuration Switch (SW3) ....................................... 3-11 Push Button Enable Switch (SW9) ........................................ 3-12 LEDs and Push Buttons .............................................................. 3-13 Programmable Flag Push Buttons (SW7–4) ............................ 3-13 Reset Push Button (SW8) ...................................................... 3-14 Power LED (LED1) .............................................................. 3-14 Reset LEDs (LED3–2) .......................................................... 3-14 User LEDs (LED9–4) ........................................................... 3-15 USB Monitor LED (LED11) ................................................. 3-15 Connectors ................................................................................. 3-16 Expansion Interface (J3–1) .................................................... 3-16 Audio (J5–4) ......................................................................... 3-17 Video (J8) ............................................................................. 3-17 Power (J9) ............................................................................ 3-17 FlashLINK (P1) .................................................................... 3-18 RS232 (P2) ........................................................................... 3-19 SPORT0 (P3) ....................................................................... 3-19 JTAG (P4) ............................................................................ 3-20 viii ADSP-BF533 EZ-KIT Lite Evaluation System Manual CONTENTS BILL OF MATERIALS INDEX ADSP-BF533 EZ-KIT Lite Evaluation System Manual ix CONTENTS x ADSP-BF533 EZ-KIT Lite Evaluation System Manual PREFACE Thank you for purchasing the ADSP-BF533 EZ-KIT Lite®, Analog Devices (ADI) evaluation system for Blackfin® embedded media processors. The Blackfin processors are embedded processors that support a Media Instruction Set Computing (MISC) architecture. This architecture is the natural merging of RISC, media functions, and digital signal processing (DSP) characteristics towards delivering signal processing performance in a microprocessor-like environment. The evaluation board is designed to be used in conjunction with the VisualDSP++® development environment to test the capabilities of the ADSP-BF533 Blackfin processors. The VisualDSP++ development environment gives you the ability to perform advanced application code development and debug, such as: • Create, compile, assemble, and link application programs written in C++, C and ADSP-BF533 assembly • Load, run, step, halt, and set breakpoints in application program • Read and write data and program memory • Read and write core and peripheral registers • Plot memory Access to the ADSP-BF533 processor from a personal computer (PC) is achieved through a USB port or an optional JTAG emulator. The USB interface gives unrestricted access to the ADSP-BF533 processor and the ADSP-BF533 EZ-KIT Lite Evaluation System Manual xi evaluation board peripherals. Analog Devices JTAG emulators offer faster communication between the host PC and target hardware. Analog Devices carries a wide range of in-circuit emulation products. To learn more about Analog Devices emulators and DSP development tools, go to http://www.analog.com/dsp/tools/. ADSP-BF533 EZ-KIT Lite provides example programs to demonstrate the capabilities of the evaluation board. VisualDSP++ license provided with this EZ-KIT Lite evaluaL The tion system limits the size of a user program to 20 KB of internal memory. The board features: • Analog Devices ADSP-BF533 processor D D D Performance to 756 MHz 160-pin Mini-BGA package 27 MHz CLKIN oscillator • Synchronous Dynamic Read Access Memory (SDRAM) D MT48LC16M16 –32 MB (16M x 16-bits) • Flash Memory D 2 MB (512K x 16 x 2chips) • Analog Audio Interface D D D xii AD1836 – Analog Devices 96 kHz audio codec 4 input RCA phono jacks (2 channels) 6 output RCA phono jacks (3 channels) ADSP-BF533 EZ-KIT Lite Evaluation System Manual Preface • Analog Video Interface D D ADV7183 video decoder w/ 3 input RCA phono jacks ADV7171 video encoder w/ 3 output RCA phono jacks • Universal Asynchronous Receiver/Transmitter (UART) D D ADM3202 RS-232 line driver/receiver DB9 male connector • LEDs D 10 LEDs: 1 power (green), 1 board reset (red), 1 USB (red), 6 general purpose (amber), and 1 USB monitor (amber) • Push Buttons D 5 push buttons with debounce logic: 1 reset, 4 programmable flags • Expansion Interface D PPI, SPI, EBIU, Timers2-0, UART, programmable flags, SPORT0, SPORT1 • Other Features D JTAG ICE 14-pin header The EZ-KIT Lite board has two Flash memories with a total of 2 MB of memory. The Flash memories can be used to store user-specific boot code, allowing the board to run as a stand-alone unit. For more information, see “Using Flash Memory” on page 2-5. The board also has 32 MB of SDRAM, which can be used by the user at runtime. ADSP-BF533 EZ-KIT Lite Evaluation System Manual xiii Purpose of This Manual is interfaced with the AD1836 audio codec, allowing you to create audio signal processing applications. SPORT0 is also attached to an off-board connector to allow communication with other serial devices. For information about SPORT0, see “SPORT0 Audio Interface” on page 3-4. SPORT0 The Parallel Peripheral Interface (PPI) of the DSP is connected to both a video encoder and video decoder, allowing you to create video signal processing applications. The UART of the DSP is connected to an RS232 Line Driver and a DB9 male connector, allowing you to interface with a PC or other serial device. Additionally, the EZ-KIT Lite board provides access to most of the processor’s peripheral ports. Access is provided in the form of a three-connector expansion interface. For information about the expansion interface, see “Expansion Interface” on page 3-8. Purpose of This Manual The ADSP-BF533 EZ-KIT Lite Evaluation System Manual provides instructions for using the hardware and installing the software on your PC. This manual provides guidelines for running your own code on the ADSP-BF533 EZ-KIT Lite. The manual also describes the operation and configuration of the evaluation board’s components. Finally, a schematic and a bill of materials are provided as a reference for future ADSP-BF533 board designs. Intended Audience This manual is a user’s guide and reference to the ADSP-BF533 EZ-KIT Lite evaluation system. Programmers who are familiar with the Analog Devices Blackfin processor architecture, operation, and programming are the primary audience for this manual. xiv ADSP-BF533 EZ-KIT Lite Evaluation System Manual Preface Programmers who are unfamiliar with Analog Devices Blackfin processors can use this manual in conjunction with the ADSP-BF533 Processor Hardware Reference and the Blackfin Processor Instruction Set Reference, which describe the processor architecture and instruction set. Programmers who are unfamiliar with VisualDSP++ should refer to the VisualDSP++ online Help and the VisualDSP++ user’s or getting started guides. For the locations of these documents, refer to “Related Documents”. Manual Contents The manual consists of: • Chapter 1, “Getting Started” on page 1-1 Provides software and hardware installation procedures, PC system requirements, and basic board information. • Chapter 2, “Getting Started” on page 1-1 Provides information on the EZ-KIT Lite from a programmer’s perspective and provides an easy-to-access memory map. • Chapter 3, “EZ-KIT Lite Hardware Reference” on page 3-1 Provides information on the hardware aspects of the evaluation system. • Appendix A, “Bill Of Materials” on page A-1 Provides a list of components used to manufacture the EZ-KIT Lite board. ADSP-BF533 EZ-KIT Lite Evaluation System Manual xv What’s New in This Manual • Appendix B, “Schematics” on page B-1 Provides the resources to allow EZ-KIT Lite board-level debugging or to use as a reference design. This appendix is not part of the online Help. The online Help viewers should go the PDF version of the ADSP-BF533 EZ-KIT Lite Evaluation System Manual located in the Docs\EZ-KIT Lite Manuals folder on the installation CD to see the schematics. What’s New in This Manual This revision of the ADSP-BF533 EZ-KIT Lite Evaluation System Manual provides the updated schematics and information on the boot mode and core voltage source selection jumpers. Technical or Customer Support You can reach DSP Tools Support in the following ways. • Visit the DSP Development Tools website at www.analog.com/technology/dsp/developmentTools/index.html • Email questions to [email protected] • Phone questions to 1-800-ANALOGD • Contact your ADI local sales office or authorized distributor xvi ADSP-BF533 EZ-KIT Lite Evaluation System Manual Preface • Send questions by mail to Analog Devices, Inc. One Technology Way P.O. Box 9106 Norwood, MA 02062-9106 USA Supported Processors The ADSP-BF533 EZ-KIT Lite evaluation system supports ADSP-BF533 Blackfin Analog Devices embedded processors. Product Information You can obtain product information from the Analog Devices website, from the product CD-ROM, or from the printed publications (manuals). Analog Devices is online at www.analog.com. Our website provides information about a broad range of products—analog integrated circuits, amplifiers, converters, and digital signal processors. MyAnalog.com MyAnalog.com is a free feature of the Analog Devices website that allows customization of a webpage to display only the latest information on products you are interested in. You can also choose to receive weekly email notification containing updates to the webpages that meet your interests. MyAnalog.com provides access to books, application notes, data sheets, code examples, and more. ADSP-BF533 EZ-KIT Lite Evaluation System Manual xvii Product Information Registration: Visit www.myanalog.com to sign up. Click Register to use MyAnalog.com. Registration takes about five minutes and serves as means for you to select the information you want to receive. If you are already a registered user, just log on. Your user name is your email address. DSP Product Information For information on digital signal processors, visit our website at www.analog.com/dsp, which provides access to technical publications, data sheets, application notes, product overviews, and product announcements. You may also obtain additional information about Analog Devices and its products in any of the following ways. • Email questions or requests for information to [email protected] • Fax questions or requests for information to 1-781-461-3010 (North America) or +49 (0) 89 76903-157 (Europe) Related Documents For information on product related development software, see the following publications. Table 1. Related DSP Publications xviii Title Description ADSP-BF533 Embedded Processor Datasheet General functional description, pinout, and timing. ADSP-BF533 EZ-KIT Lite Evaluation System Manual Preface Table 1. Related DSP Publications (Cont’d) Title Description ADSP-BF533 Blackfin Processor Hardware Reference Description of internal processor architecture and all register functions. Blackfin Processor Instruction Set Reference Description of all allowed processor assembly instructions. Table 2. Related VisualDSP++ Publications Title Description VisualDSP++ 3.5 User’s Guide for 16-Bit Proces- Detailed description of VisualDSP++ 3.5 feasors tures and usage. VisualDSP++ 3.5 Assembler and Preprocessor Manual for Blackfin Processors Description of the assembler function and commands for Blackfin processors. VisualDSP++ 3.5 C/C++ Complier and Library Manual for Blackfin Processors Description of the complier function and commands for Blackfin processors VisualDSP++ 3.5 Linker & Utilities Manual for 16-Bit Processors Description of the linker function and commands for 16-bit processors. VisualDSP++ 3.5 Loader Manual for 16-Bit Processors Description of the loader/splitter function and commands for 16-bit processors. The listed documents can be found through online Help or in the Docs folder of your VisualDSP++ installation. Most documents are available in printed form. you plan to use the EZ-KIT Lite board in conjunction with a L IfJTAG emulator, refer to the documentation that accompanies the emulator. ADSP-BF533 EZ-KIT Lite Evaluation System Manual xix Product Information Online Documentation Your software installation kit includes online Help as part of the Windows® interface. These help files provide information about VisualDSP++ and the ADSP-BF533 EZ-KIT Lite evaluation system. To view VisualDSP++ Help, click on the Help menu item or go to the Windows task bar and select Start –>Programs –>Analog Devices–>VisualDSP for 16-bit Processors –>VisualDSP++ Documentation. To view ADSP-BF533 EZ-KIT Lite Help, which now is a part of the VisualDSP++ Help system, go the Contents tab of the Help window and select Manuals –>Hardware Tools –>EZ-KIT Lite. Evaluation Systems. For more documentation, please go to http://www.analog.com/technology/dsp/library.html. Printed Manuals For general questions regarding literature ordering, call the Literature Center at 1-800-ANALOGD (1-800-262-5643) and follow the prompts. VisualDSP++ Documentation Set Printed copies of VisualDSP++ manuals may be purchased through Analog Devices Customer Service at 1-781-329-4700; ask for a Customer Service representative. The manuals can be purchased only as a kit. For additional information, call 1-603-883-2430. If you do not have an account with Analog Devices, you will be referred to Analog Devices distributors. To get information on our distributors, log onto www.analog.com/salesdir/continent.asp. xx ADSP-BF533 EZ-KIT Lite Evaluation System Manual Preface Hardware Manuals Printed copies of hardware reference and instruction set reference manuals can be ordered through the Literature Center or downloaded from the Analog Devices website. The phone number is 1-800-ANALOGD (1-800-262-5643). The manuals can be ordered by a title or by product number located on the back cover of each manual. Data Sheets All data sheets can be downloaded from the Analog Devices website. As a general rule, printed copies of data sheets with a letter suffix (L, M, N, S) can be obtained from the Literature Center at 1-800-ANALOGD (1-800-262-5643) or downloaded from the website. Data sheets without the suffix can be downloaded from the website only—no hard copies are available. You can ask for the data sheet by part name or by product number. If you want to have a data sheet faxed to you, the phone number for that service is 1-800-446-6212. Follow the prompts and a list of data sheet code numbers will be faxed to you. Call the Literature Center first to find out if requested data sheets are available. Contacting DSP Publications Please send your comments and recommendations on how to improve our manuals and online Help. You can contact us at [email protected]. ADSP-BF533 EZ-KIT Lite Evaluation System Manual xxi Notation Conventions Notation Conventions The following table identifies and describes text conventions used in this manual. conventions, which apply only to specific chapters, may L Additional appear throughout this document. Example Description Close command (File menu) or OK Text in bold style indicates the location of an item within the VisualDSP++ environment’s and boards’ menu system and user interface items. {this | that} Alternative required items in syntax descriptions appear within curly brackets separated by vertical bars; read the example as this or that. [this | that] Optional items in syntax descriptions appear within brackets and separated by vertical bars; read the example as an optional this or that. [this,…] Optional item lists in syntax descriptions appear within brackets delimited by commas and terminated with an ellipsis; read the example as an optional comma-separated list of this. PF9-0 Registers, connectors, pins, commands, directives, keywords, code examples, and feature names are in text with letter gothic font. filename Non-keyword placeholders appear in text with italic style format. [ xxii Note: A note providing information of special interest or identifying a related topic. In the online version of this book, the word Note appears instead of this symbol. Caution: A caution providing information about critical design or programming issues that influence operation of a product. In the online version of this book, the word Caution appears instead of this symbol. ADSP-BF533 EZ-KIT Lite Evaluation System Manual 1 GETTING STARTED This chapter provides the information you need to begin using ADSP-BF533 EZ-KIT Lite evaluation system. For correct operation, install the software and hardware in the order presented in “Installation Tasks” on page 1-3. The chapter includes the following sections. • “Contents of EZ-KIT Lite Package” on page 1-1 Provides a list of the components shipped with this EZ-KIT Lite evaluation system. • “PC Configuration” on page 1-3 Describes the minimum requirements for the PC to work with the EZ-KIT Lite evaluation system. • “Installation Tasks” on page 1-3 Describes the step-by-step procedures for setting up the hardware and software. Contents of EZ-KIT Lite Package Your ADSP-BF533 EZ-KIT Lite evaluation system package contains the following items. • ADSP-BF533 EZ-KIT Lite board • EZ-KIT Lite Quick Start Guide ADSP-BF533 EZ-KIT Lite Evaluation System Manual 1-1 Contents of EZ-KIT Lite Package • VisualDSP++ 3.5 Installation Quick Reference Card • CD containing: D VisualDSP++ for 16-Bit Processors with a limited license D ADSP-BF533 EZ-KIT Lite debug software D USB driver files D Example programs D ADSP-BF533 EZ-KIT Lite Evaluation System Manual • Universal 7.5V DC power supply • USB 2.0 type cable • Registration card (please fill out and return) If any item is missing, contact the vendor where you purchased your EZ-KIT Lite or contact Analog Devices, Inc. The EZ-KIT Lite evaluation system contains ESD (electrostatic discharge) sensitive devices. Electrostatic charges readily accumulate on the human body and equipment and can discharge without detection. Permanent damage may occur on devices subjected to high-energy discharges. Proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Store unused EZ-KIT Lite boards in the protective shipping package. 1-2 ADSP-BF533 EZ-KIT Lite Evaluation System Manual Getting Started PC Configuration For correct operation of the VisualDSP++ software and the EZ-KIT Lite, your computer must have the minimum configuration: Windows 98, Windows 2000, Windows XP Intel (or comparable) 333 MHz processor VGA Monitor and color video card 2-button mouse 200 MB free on hard drive 128 MB RAM Full-speed USB port CD-ROM Drive [ EZ-KIT Lite does not run under Windows 95 or Windows NT. Installation Tasks The following task list is provided for the safe and effective use of the ADSP-BF533 EZ-KIT Lite. Follow these instructions in the presented order to ensure correct operation of your software and hardware. 1. VisualDSP++ and EZ-KIT Lite software installation 2. VisualDSP++ license installation and registration 3. EZ-KIT Lite hardware setup 4. EZ-KIT Lite USB driver installation 5. USB driver installation verification 6. VisualDSP++ startup ADSP-BF533 EZ-KIT Lite Evaluation System Manual 1-3 Installation Tasks Installing VisualDSP++ and EZ-KIT Lite Software This EZ-KIT Lite comes with the latest version of VisualDSP++ 3.5 for 16-bit processors. VisualDSP++ installation includes EZ-KIT Lite installations. To install VisualDSP++ and EZ-KIT Lite software: 1. Insert the VisualDSP++ installation CD into the CD-ROM drive. 2. If Autoplay is enabled on your PC, you see the Install Shield Wizard Welcome screen. Otherwise, choose Run from the Start menu, and enter D:\ADI_Setup.exe in the Open field, where D is the name of your local CD-ROM drive. 3. Follow the on-screen instructions to continue installing the software. 4. At the Custom Setup screen, select your EZ-KIT Lite from the list of available systems and choose the installation directory. Click an icon in the Feature Description field to see the selected system’s description. When you have finished, click Next. 5. At the Ready to Install screen, click Back to change your install options, click Install to install the software, or click Cancel to exit the install. 6. When the EZ-KIT Lite installs, the Wizard Completed screen appears. Click Finish. 1-4 ADSP-BF533 EZ-KIT Lite Evaluation System Manual Getting Started Installing and Registering VisualDSP++ License VisualDSP++ and EZ-KIT Lites are licensed products. You may run only one copy of the software for each license purchased. Once a new copy of the VisualDSP++ or EZ-KIT Lite software is installed on your PC, you must install, register, and validate your licence. The VisualDSP++ 3.5 Installation Quick Reference Card included in your package will guide you through the licence installation and registration process (refer to Tasks 1, 2, and 3). Setting Up EZ-KIT Lite Hardware The EZ-KIT Lite evaluation system contains ESD (electrostatic discharge) sensitive devices. Electrostatic charges readily accumulate on the human body and equipment and can discharge without detection. Permanent damage may occur on devices subjected to high-energy discharges. Proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Store unused EZ-KIT Lite boards in the protective shipping package. The ADSP-BF533 EZ-KIT Lite board is designed to run outside your personal computer as a stand-alone unit. You do not have to open your computer case. To connect the EZ-KIT Lite board: 1. Remove the EZ-KIT Lite board from the package. Be careful when handling the board to avoid the discharge of static electricity, which may damage some components. 2. Figure 1-1 shows the default jumper settings, DIP switch, connector locations, and LEDs used in installation. Confirm that your board is set up in the default configuration before continuing. ADSP-BF533 EZ-KIT Lite Evaluation System Manual 1-5 Installation Tasks Figure 1-1. EZ-KIT Lite Hardware Setup 3. Plug the provided power supply into J9 on the EZ-KIT Lite board. Visually verify that the green power LED (LED1) is on. Also verify that the two red reset LEDs (LED2 and LED3) go on for a moment and then go off. 4. Connect one end of the USB cable to an available full speed USB port on your PC and the other end to J10 on the ADSP-BF533 EZ-KIT Lite board. 1-6 ADSP-BF533 EZ-KIT Lite Evaluation System Manual Getting Started Installing EZ-KIT Lite USB Driver The EZ-KIT Lite evaluation system installed on the following platforms requires one full-speed USB port. • “Windows 98 USB Driver” on page 1-8 describes the installation on Windows 98. • “Windows 2000 USB Driver” on page 1-12 describes the installation on Windows 2000. • “Windows XP USB Driver” on page 1-13 describes the installation on Windows XP. The USB driver used by the debug agent is not Microsoft certified because it is intended for a development or laboratory environment, not a commercial environment. ADSP-BF533 EZ-KIT Lite Evaluation System Manual 1-7 Installation Tasks Windows 98 USB Driver Before using the ADSP-BF533 EZ-KIT Lite for the first time, the Windows 98 USB driver must first be installed. To install the USB driver: 1. Insert the CD into the CD-ROM drive. The connection of the device to the USB port activates the Windows 98 Add New Hardware Wizard, as shown in Figure 1-2. Figure 1-2. Windows 98 – Add New Hardware Wizard 2. Click Next. 1-8 ADSP-BF533 EZ-KIT Lite Evaluation System Manual Getting Started 3. Select Search for the best driver for your device, as shown in Figure 1-3. Figure 1-3. Windows 98 – Searching for Driver 4. Click Next. 5. Select CD-ROM drive, as shown in Figure 1-4. Figure 1-4. Windows 98 – Searching for CD-ROM ADSP-BF533 EZ-KIT Lite Evaluation System Manual 1-9 Installation Tasks 6. Click Next. Windows 98 locates the WmUSBEz.inf file on the installation CD, as shown in Figure 1-5. Figure 1-5. Windows 98 – Locating Driver 7. Click Next. The Coping Files dialog box appears (Figure 1-6). Figure 1-6. Windows 98 – Searching for .SYS File 1-10 ADSP-BF533 EZ-KIT Lite Evaluation System Manual Getting Started 8. Click Browse. The Open dialog box, shown in Figure 1-7, appears on the screen. Figure 1-7. Windows 98 – Opening .SYS File 9. In Drives, select your CD-ROM drive. 10. Click OK. The Copying Files dialog box (Figure 1-8) appears. Figure 1-8. Windows 98 – Copying .SYS File 11. Click OK. ADSP-BF533 EZ-KIT Lite Evaluation System Manual 1-11 Installation Tasks The driver installation is now complete, as shown in Figure 1-9. Figure 1-9. Windows 98 – Completing Software Installation 12. Click Finish to exit the wizard. Verify the installation by following the instructions in “Verifying Driver Installation” on page 1-15. Windows 2000 USB Driver VisualDSP++ 3.5 installation software pre-installs the necessary drivers for the selected EZ-KIT Lite. The install also upgrades an older driver if such is detected in the system. to running the VisualDSP++ 3.5 installer, ensure there are no [ Prior other Hardware Wizard windows running in the background. If there are any wizard windows running, close them before starting the installer. 1-12 ADSP-BF533 EZ-KIT Lite Evaluation System Manual Getting Started To install the USB driver: 1. If VisualDSP++ 3.5 is already installed on your system, go to step 2. Otherwise, run VisualDSP++ 3.5 installation. Refer to the VisualDSP++ 3.5 Installation Quick Reference Card for a detailed installation description. When installing VisualDSP++ 3.5 on Windows 2000, make sure the appropriate EZ-KIT Lite component is selected for the installation. 2. Connect the EZ-KIT Lite device to your PC’s USB port. Windows 2000 automatically detects an EZ-KIT device and automatically installs the appropriate driver for the selected device (see step 1). 3. Verify the installation by following the instructions in “Verifying Driver Installation” on page 1-15. Windows XP USB Driver VisualDSP++ 3.5 installation software pre-installs the necessary drivers for the selected EZ-KIT Lite. The install also upgrades an older driver if such is detected in the system. to running the VisualDSP++ 3.5 installer, ensure there are no [ Prior other Hardware Wizard windows running in the background. If there are any wizard windows running, close them before starting the installer. To install the USB driver: 1. If VisualDSP++ 3.5 is already installed on your system, go to step 2. Otherwise, run VisualDSP++ 3.5 installation. Refer to the VisualDSP++ 3.5 Installation Quick Reference Card for a detailed installation description. When installing VisualDSP++ 3.5 on Windows XP, make sure the appropriate EZ-KIT Lite component is selected for the installation. ADSP-BF533 EZ-KIT Lite Evaluation System Manual 1-13 Installation Tasks 2. Connect the EZ-KIT Lite device to your PC’s USB port. By connecting the device to the USB port you activate the Windows XP Found New Hardware Wizard, shown in Figure 1-10. Figure 1-10. Windows XP – Found New Hardware Wizard 1-14 ADSP-BF533 EZ-KIT Lite Evaluation System Manual Getting Started 3. Select Install the software automatically (Recommended) and click Next. When Windows XP completes the driver installation for the selected device (see step 1), a window shown in Figure 1-11 appears on the screen. Figure 1-11. Windows XP – Completing Driver Installation 4. Verify the installation by following the instructions in “Verifying Driver Installation”. Verifying Driver Installation Before using the EZ-KIT Lite evaluation system, verify that the USB driver software is installed properly: 1. Ensure that the USB cable is connected to the evaluation board and the PC. 2. Verify that the yellow USB monitor LED (LED11) is lit. This signifies that the board is communicating properly with the host PC and is ready to run VisualDSP++. ADSP-BF533 EZ-KIT Lite Evaluation System Manual 1-15 Installation Tasks 3. Verify that the USB driver software is installed properly. Open Windows Device Manager and verify that ADSP-BF533 EZ-KIT Lite shows under ADI Development Tools with no exclamation point, as in Figure 1-12. Figure 1-12. Device Manager Window Lite on Windows 98, disconnect the USB [ Ifcableusingfroman theEZ-KIT board before booting the PC. When Windows 98 is booted and you are logged on, re-connect the USB cable to the board. The operation should continue normally from this point. Starting VisualDSP++ To set up a session in VisualDSP++: 1. Verify that the yellow USB monitor LED (LED11, located near the USB connector) is lit. This signifies that the board is communicating properly with the host PC and is ready to run VisualDSP++. 2. Hold down the Control (CTRL) key. 1-16 ADSP-BF533 EZ-KIT Lite Evaluation System Manual Getting Started 3. Select the Start button on the Windows taskbar, then choose Programs, Analog Devices, VisualDSP++ 3.5 for 16-bit Processors, VisualDSP++ Environment. If you are running VisualDSP++ for the first time, go to step 4. If you already have existing sessions, the Session List dialog box appears on the screen. 4. Click New Session. 5. The New Session dialog box, shown in Figure 1-13, appears on the screen. Figure 1-13. New Session Dialog Box 6. In Debug Target, choose EZ-KIT Lite (ADSP-BFxxx). 7. In Processor, choose the appropriate processor, ADSP-BF533. 8. Type a new target name in Session Name or accept the default name. 9. Click OK to return to the Session List. Highlight the new session and click Activate. ADSP-BF533 EZ-KIT Lite Evaluation System Manual 1-17 Installation Tasks 1-18 ADSP-BF533 EZ-KIT Lite Evaluation System Manual 2 USING EZ-KIT LITE This chapter provides specific information to assist you with developing programs for the ADSP-BF533 EZ-KIT Lite evaluation system. The information appears in the following sections. • “EZ-KIT Lite License Restrictions” on page 2-2 Describes the restrictions of the VisualDSP++ license shipped with the EZ-KIT Lite. • “Memory Map” on page 2-2 Defines the ADSP-BF533 EZ-KIT Lite board’s memory map. • “Using SDRAM Interface” on page 2-4· Defines the register values to configure the on-board SDRAM. • “Using Flash Memory” on page 2-5 Describes the on-board Flash memory. • “Example Programs” on page 2-13 Provides information about the example programs included in the ADSP-BF533 EZ-KIT Lite evaluation system. • “Using Background Telemetry Channel” on page 2-13 Highlights the advantages of the Background Telemetry Channel feature of VisualDSP++. • “Using EZ-KIT Lite VisualDSP++ Interface” on page 2-13 ADSP-BF533 EZ-KIT Lite Evaluation System Manual 2-1 EZ-KIT Lite License Restrictions Describes the trace, performance monitoring, boot loading, context switching, and target options facilities of the EZ-KIT Lite system. For more detailed information about programming the ADSP-BF533 Blackfin processor, see the documents referred to as “Related Documents”. EZ-KIT Lite License Restrictions The license shipped with the EZ-KIT Lite imposes the following restrictions. • The size of a user program is limited to 20 KB of the ADSP-BF533 processor’s internal memory space. • No connections to simulator or emulator sessions are allowed. • The EZ-KIT Lite hardware must be connected and powered up in order to use VisualDSP++ with a kit license. Memory Map The ADSP-BF533 processor has internal SRAM that can be used for instruction or data storage. The configuration of internal SRAM is detailed in the ADSP-BF533 Processor Hardware Reference. The ADSP-BF533 EZ-KIT Lite board includes two types of external memory, SDRAM and Flash memory. The size of the SDRAM is 32 Mbytes (16M x 16-bit). The processor’s memory select pin ~SMS0 is configured for the SDRAM. 2-2 ADSP-BF533 EZ-KIT Lite Evaluation System Manual Using EZ-KIT Lite The Flash memory is implemented with two Dual-Bank Flash Memory devices. These devices include primary and secondary Flash memory as well as internal SRAM and registers. Primary Flash memory totals 2 Mbytes mapped into two separate asynchronous memory banks, 1 Mbyte each. Secondary Flash memory, along with SRAM and registers, occupies the third bank of asynchronous memory space. The processor’s ~AMS0, ~AMS1, and ~AMS2 memory select pins are used for that purpose. Table 2-1. EZ-KIT Lite Evaluation Board Memory Map Start Address External Memory End Address Content 0x0000 0000 0x07FF FFFF SDRAM Bank 0 (SDRAM). See “Using SDRAM Interface” on page 2-4. 0x2000 0000 0x2000 FFFF ASYNC Memory Bank 0 (Primary Flash A). See “Using Flash Memory” on page 2-5. 0x2010 0000 0x201F FFFF ASYNC Memory Bank 1 (Primary Flash B). See “Using Flash Memory” on page 2-5. 0x2020 0000 0x202F FFFF ASYNC Memory Bank 2 (Flash A and B Secondary Memory, SRAM and Internal Registers). See “Using Flash Memory” on page 2-5. All other locations Internal Memory Not used 0xFF80 0000 0xFF80 3FFF Data Bank A SRAM 16 KB 0xFF80 4000 0xFF80 7FFF Data Bank A SRAM/CACHE 16 KB 0xFF90 0000 0xFF90 3FFF Data Bank B SRAM 16 KB 0xFF90 4000 0xFF90 7FFF Data Bank B SRAM/CACHE 16 KB 0xFFA0 0000 0xFFA0 FFFF Instruction SRAM 64 KB 0xFFA1 0000 0xFFA1 3FFF Instruction SRAM /CACHE 16 KB 0xFFB0 0000 0xFFBO 0FFF Scratch Pad SRAM 4 KB 0xFFC0 0000 0xFFDF FFFF System MMRs 2 MB 0xFFE0 0000 0xFFFF FFFF Core MMRs 2 MB All other locations Reserved ADSP-BF533 EZ-KIT Lite Evaluation System Manual 2-3 Using SDRAM Interface Using SDRAM Interface The three SDRAM control registers must be initialized in order to use the MT48LC4M16ATG-75 16M x 16 bits (32 MB) SDRAM memory. When you are in a VisualDSP++ EZ-KIT Lite session (that is, using the USB debug interface and not using an emulator), the SDRAM registers are configured automatically through the debugger. The values in Table 2-2 are used whenever Bank 0 is accessed through the debugger (for example, when viewing memory windows or loading a program). The numbers were derived for maximum flexibility and work for a system clock frequency between 54 MHz and 133 MHz. Table 2-2. EZ-KIT Lite Session SDRAM Default Settings1 Register Value Function EBIU_SDGCTL 0x0091998D Calculated with SCLK = 133 MHz 16-bit data path External buffering timing disabled tWR = 2 SCLK cycles tRCD = 3 SCLK cycles tRP = 3 SCLK cycles tRAS = 6 SCLK cycles pre-fetch disabled CAS latency = 3 SCLK cycles SCLK1 disabled EBIU_SDBCTL 0x00000013 Bank 0 enabled Bank 0 size = 32 MB Bank 0 column address width = 9 bits EBIU_SDRRC 0x000001A0 Calculated with SCLK = 54 MHz RDIV = 416 clock cycles 1 54 MHz <= SCLK <= 133 MHz. The EBIU_SDGCTL register can only be re-written within the user code by first placing the chip in self refresh (see the ADSP-BF533 Blackfin Processor Hardware Reference). Clearing the appropriate checkbox on the Target 2-4 ADSP-BF533 EZ-KIT Lite Evaluation System Manual Using EZ-KIT Lite Options dialog box, which is accessible through the Settings pull-down menu, disables automatic and allows manual configuration. For more information, see “Target Options” on page 2-17. Automatic configuration of SDRAM is not optimized for any SCLK frequency. Table 2-3 shows the optimized configuration for the SDRAM registers using a 118.8 MHz, 126 MHz, and 133 MHz SCLK. The frequency of 118.8 MHz is the maximum SCLK frequency when using a 594 MHz core frequency, the maximum frequency for the EZ-KIT Lite when using the internal voltage regulator. Only the EBIU_SDRRC register needs to be modified in the user code to achieve maximum performance. Table 2-3. SDRAM Optimum Settings Register SCLK = 133 MHz (Processor MAX) SCLK = 126 MHz (CCLK = 756 MHz) SCLK = 118.8 MHz (CCLK = 594 MHz) EBIU_SDGCTL 0x0091 998D 0x0091 998D 0x0091 998D EBIU_SDBCTL 0x0000 0013 0x0000 0013 0x0000 0013 EBIU_SDRRC 0x0000 0406 0x0000 03CF 0x0000 0397 An example program is included in the EZ-KIT installation directory to demonstrate how to set up the SDRAM interface. Using Flash Memory The following sections describe how to use the memory and general-purpose IO pins, as well as how to configure the Flash memory device. The ADSP-BF533 EZ-KIT Lite board employs two PSD4256G6V Flash/General-Purpose IO devices from STMicroelectronics. These devices not only have Flash memory but also extra IO pins, which are memory mapped. ADSP-BF533 EZ-KIT Lite Evaluation System Manual 2-5 Using Flash Memory Example code is provided in the EZ-KIT installation directory to demonstrate how to program the Flash memory as well as to demonstrate the functionality of the general-purpose IO pins. Flash Memory Map Each device includes the following memory segments: • 1M byte of primary Flash memory • 64K bytes of secondary Flash memory • 32 Kbytes of internal SRAM • 256 Bytes of configuration registers (IO control) Access to each segment can be 8-bit or 16-bit. The processor’s ~AMS0, ~AMS1, and ~AMS2 memory select pin are used for that purpose. Asynchronous memory Bank 0 is always enabled after a hard reset, while Banks 1 and 2 need to be enabled by software. Table 2-4 provides an example on asynchronous memory configuration registers. Table 2-4. Asynchronous Memory Control Registers Settings Example Register Value Function EBIU_AMBCTL0 0x7BB07BB0 Timing control for Banks 1 and 0 0x7BB0 Timing control for Bank 2 (Bank 3 is not used) 0xF Enable all banks EBIU_AMBCTL1 EBIU_AMGCTL bits 15-0 bits 3-0 Each Flash chip is initially configured with the memory sectors mapped into the processor’s address space as shown in Table 2-5. 2-6 ADSP-BF533 EZ-KIT Lite Evaluation System Manual Using EZ-KIT Lite Table 2-5. Flash Memory Map Start Address End Address Content 0x2000 0000 0x200F FFFF Flash A Primary (1MB) 0x2010 0000 0x201F FFFF Flash B Primary (1MB) 0x2020 0000 0x2020 FFFF Flash A Secondary (64KB) 0x2024 0000 0x2024 7FFF Flash A SRAM (32KB) 0x2027 0000 0x2027 00FF Flash A Registers (256 Bytes) 0x2028 0000 0x2028 FFFF Flash B Secondary (64KB) 0x202C 0000 0x202C 7FFF Flash B SRAM (32KB) 0x202E 0000 0x202E 00FF Flash B Registers (256 Bytes) All other locations Reserved Flash General-Purpose IO This section describes general-purpose IO signals that are controlled by means of setting appropriate registers of the Flash A or Flash B. These registers are mapped into the processor’s address space, as shown in Table 2-5 on page 2-7. Flash device IO pins are arranged as 8-bit ports labeled A through G. There is a set of 8-bit registers associated with each port. These registers are: Direction, Data In, and Data Out. Note that the Direction and Data Out registers are cleared to all zeros at power-up or hardware reset. The Direction register controls IO pins direction. When a bit is 0, a corresponding pin functions as an input. When a bit is 1, a corresponding pin is an output. This is a 8-bit read-write register. The Data In register allows reading the status of port’s pins. This is a 8-bit read-only register. ADSP-BF533 EZ-KIT Lite Evaluation System Manual 2-7 Using Flash Memory The Data Out register allows clearing an output pin to 0 or setting it to 1. This is a 8-bit read-write register. The ADSP-BF533 EZ-KIT Lite board employs only Flash A and Flash B ports A and B. Table 2-6 and Table 2-7 provide configuration register addresses for Flash A and Flash B, respectively (only ports A and B are listed). The following bits connect to the Expansion Board connector: • Flash A port B bits 7 and 6 • Flash B port A bits 7–0 and port B bits 7–0 Table 2-6. Flash A Configuration Registers for port A, B Register Name (Read-only) Data In Data Out Direction (Read-Write) (Read-Write) Port A Address Port B Address 0x2027 0000 0x2027 0001 0x2027 0004 0x2027 0005 0x2027 0006 0x2027 0007 Table 2-7. Flash B Configuration Registers for port A, B Register Name Data In (Read-only) Data Out Direction (Read-Write) (Read-Write) Port A Address Port B Address 0x202E 0000 0x202E 0001 0x202E 0004 0x202E 0005 0x202E 0006 0x202E 0007 Table 2-8 and Table 2-9 depict the IO assignments. Table 2-8. Flash A Port A Controls 2-8 Bit # User IO Bit Value 7 Not defined Any 6 Not defined Any 5 PPI Clock Select bit 1 00 = Local OSC (27 MHz) ADSP-BF533 EZ-KIT Lite Evaluation System Manual Using EZ-KIT Lite Table 2-8. Flash A Port A Controls (Cont’d) Bit # User IO Bit Value 4 PPI Clock Select bit 0 01= Video Decoder Pixel Clock 1X = Expansion Board PPI Clock 3 Video Decoder Reset 0= Reset ON; 1= Reset OFF 2 Video Encoder Reset 0= Reset ON; 1= Reset OFF 1 Reserved Any 0 Codec Reset 0= Reset ON; 1= Reset OFF Table 2-9. Flash A Port B Controls Bit # User IO Bit Value 7 Not used Any 6 Not used Any 5 LED9 0= LED OFF; 1= LED ON 4 LED8 0= LED OFF; 1= LED ON 3 LED7 0= LED OFF; 1= LED ON 2 LED6 0= LED OFF; 1= LED ON 1 LED5 0= LED OFF; 1= LED ON 0 LED4 0= LED OFF; 1= LED ON Configuring Flash Memory The Flash memory is completely configurable. To modify the default setup of each flash, you must use PSDsoft Express™ software. After the project has been modified, the Flash memory must be re-programmed using FlashLINK™. The default project file is provided in \…\VisualDSP 32-Bit Processors\Blackfin\EZ-KITs\ADSP-BF533\PSDConfigFiles directory. Analog Devices does not provide any support for setting up the ADSP-BF533 EZ-KIT Lite Evaluation System Manual 2-9 Using LEDs and Push Buttons PSD4256G6V with PSDsoft Express or programming it using FlashLINK. Email STMicroelectronics at [email protected] for technical assistance. The PSD4256G6Vcan be re-programmed using the FlashLINK JTAG programming cable available from STMicoreclectronics (www.st.com/psd) for approximately $59. FlashLINK plugs into any PC parallel port. The PSDsoft Express development software is required to modify the DSM2150 configuration and to operate the FlashLINK cable. PSDsoft Express can be downloaded at no charge from www.st.com/psd. Using LEDs and Push Buttons The EZ-KIT Lite provides four push buttons and six LEDs for general-purpose IO. The six LEDs, labeled LED4 through LED9, are accessed via some of the general-purpose IO pins of Flash memory interface. For information on how to program the pins, see “Flash General-Purpose IO” on page 2-7. The four general-purpose push button are labeled SW4 through SW7. A status of each individual button can be read through programmable flag (PF) inputs, PF8 through PF11. A PF reads “1” when a corresponding switch is being pressed-on. When the switch is released, the PF reads “0”. A connection between the push button and PF input is established through the SW9 DIP switch. See “Push Button Enable Switch (SW9)” on page 3-12 for details. An example program is included in the EZ-KIT installation directory to demonstrate the functionality of the LEDs and push buttons. 2-10 ADSP-BF533 EZ-KIT Lite Evaluation System Manual Using EZ-KIT Lite Using Audio The AD1836 audio codec provides three channels of stereo audio output and two channels of multichannel 96 kHz input. The SPORT0 interface of the processor is linked with the stereo audio data input and output pins of the AD1836 codec. The processor is capable of transferring data to the audio codec in time-division multiplexed (TDM) or I2S mode. The I2S mode allows the codec to operate with a 96 kHz sample rate but only allows you to use two channels of output. TDM mode can operate at a maximum of 48 kHz sample rate but allows for simultaneous use of all input and output channels. When using I2S mode, the TSCLK0 and RSCLK0 pins, as well as the TFS0 and RFS0 pins of the processor, must be tied together external to the processor. This is accomplished with the SW9 DIP switch (see “Push Button Enable Switch (SW9)” on page 3-12 for more information). The AD1836 audio codec’s internal configuration registers are configured using the processor’s SPI port. The processor’s PF4 programmable flag pin is used as the select for this device. For information on how to configure the multichannel codec, go to www.analog.com/UploadedFiles/Datasheets/344740003AD1836_prc.pdf. The reset for the AD1836 codec comes from the general-purpose IO pin PA0 of Flash A. For information on how to use the pin, see “Flash General-Purpose IO” on page 2-7. Example programs are included in the EZ-KIT installation directory to demonstrate the AD1836 codec operation. ADSP-BF533 EZ-KIT Lite Evaluation System Manual 2-11 Using Video Using Video The board supports video input and output applications. The ADV7171 video encoder provides up to three output channels of analog video, while the ADV7183 video decoder provides up to three input channels of analog video. Both the encoder and the decoder connect to the Parallel Peripheral Interface (PPI) of the ADSP-BF533 processor. For additional information on the video interface hardware, refer to “PPI Interface” on page 3-5. For the video interface to be operational, the following basic steps must be performed. 1. Configure the SW3 DIP switch as required by the application. Refer to “Video Configuration Switch (SW3)” on page 3-11 for details. 2. Remove reset to the video device. Refer to “Flash General-Purpose IO” on page 2-7 for details. 3. If using the decoder: D D Enable device by driving programmable flag output PF2 to “0”. Select PPI clock (see Table 2-8 on page 2-8). 4. Program internal registers of the video device in use. Both video encoder and decoder use a 2-wire serial interface to access internal registers. A programmable flag PF0 functions as a serial clock (SCL), and PF1 functions as a serial data (SDAT). 5. Program the ADSP-BF533 processor’s PPI interface (configuration registers, DMA, etc.). Example programs are included in the EZ-KIT installation directory to demonstrate the capabilities of the video interface. 2-12 ADSP-BF533 EZ-KIT Lite Evaluation System Manual Using EZ-KIT Lite Example Programs Example programs are provided with the ADSP-BF533 EZ-KIT Lite to demonstrate various capabilities of the evaluation board. These programs are installed with the EZ-KIT Lite software and can be found in \…\VisualDSP 16-bit Processors\Blackfin\EZ-KITs\ADSP-BF533\Examples. Please refer to the readme file provided with each example for more information. Using Background Telemetry Channel The ADSP-BF533 USB debug agent supports the Background Telemetry Channel (BTC), which facilitates data exchange between VisualDSP++ and the processor without interrupting DSP execution. The BTC allows the user to view a variable as it is updated or changed, all while the processor continues to execute. For increased performance of the BTC, including faster reading and writing, please check out our latest line of DSP emulators at www.analog.com/Analog_Root/productPage/productHome/0,2121,EMULATORS,00.html. For more information about the Background Telemetry Channel, see the VisualDSP++ 3.5 User’s Guide for 16-Bit Processors or online Help. Using EZ-KIT Lite VisualDSP++ Interface This section provides information on the following parts of the VisualDSP++ graphical user interface: • “Trace Window” on page 2-14 • “Performance Monitor” on page 2-15 • “Boot Load” on page 2-16 ADSP-BF533 EZ-KIT Lite Evaluation System Manual 2-13 Using EZ-KIT Lite VisualDSP++ Interface • “Target Options” on page 2-17 • “Restricted Software Breakpoints” on page 2-19 Trace Window Choosing the Trace command from the View–>Debug Windows menu opens the Trace window (Figure 2-1). Figure 2-1. Trace Window The trace buffer stores a history of the last 16 changes in program flow taken by the program sequencer. View the history to recreate the program sequencer’s most recent path. The trace buffer does not track changes in flow caused by zero-overhead loops or while in the reset service routine. use the trace buffer, ensure your program leaves the reset service L Toroutine. Enabling Trace Buffer To view trace history in the Trace window, first, enable the trace buffer (choose Enable Trace from the Tools–>Trace menu). On each halt, the Trace window is updated with the changes that occurred since the last halt. Reading the trace buffer destroys the trace buffer’s contents and discards the information previously stored before the last run. 2-14 ADSP-BF533 EZ-KIT Lite Evaluation System Manual Using EZ-KIT Lite Reading Trace Buffer Data The first column between the square brackets (in blue) indicates the line number in the Trace window. The second column between square brackets, which comes in vertical pairs, shows the trace number. For each discontinuity, the first (top position) is the source trace, and the second (bottom position) is the destination trace. The third column in between square brackets shows the addresses of the instructions. Each address is followed by the assembly instruction. The trace grows upward. In Figure 2-1 on page 2-14, trace 0 occurred before trace 1, which occurred before trace 2, and so on. Performance Monitor Choosing Performance Monitor from the Settings menu opens the Performance Monitor Control dialog box shown in Figure 2-2. A description of the dialog box appears in Table 2-10 on page 2-16. Figure 2-2. Performance Monitor Dialog Box ADSP-BF533 EZ-KIT Lite Evaluation System Manual 2-15 Using EZ-KIT Lite VisualDSP++ Interface The performance monitor is a 32-bit counter that allows you to track occurrences of events within the core and use these to analyze system behavior. When the counter reaches zero, it causes an exception or emulation event, as specified by the Type option. Table 2-10. Performance Monitor Options Option Description Enable Enables performance monitoring. Mode Determines the mode of operation for tracking events: Disabled disables the monitor. User tracks while in user mode. Supervisor tracks while in supervisor mode. Both tracks while in both user mode and supervisor mode. Type Determines the type of event occurring on a match: Exception causes an exception to occur. You can install a handler to detect and handle this exception. Emulation halts the DSP. Event Specifies the tracked event. Refer to your processor’s Hardware Reference for details. Events include stalls, cache hits or misses, loop iterations, branches, interrupts, loads, stores, DMA accesses, and more. Count Specifies the count. When the 32-bit counter reaches zero, an exception or emulation event occurs. For example, to halt on the third occurrence of an event, load the count with 0xFFFFFFFE and set Type to Emulation. The counter counts up and wraps around, causing the processor to halt as desired. Boot Load Choosing Boot Load from the Settings menu runs the processor and performs a hard reset on the board. This command saves you from having to shut down VisualDSP++, reset the EZ-KIT Lite board, and bring up VisualDSP++ again when you want to perform a hard reset. Use this feature when loading debug boot code from an external part or when you want to put the device into a known state. 2-16 ADSP-BF533 EZ-KIT Lite Evaluation System Manual Using EZ-KIT Lite Target Options Choosing Target Options from the Settings menu opens the Target Options dialog box (Figure 2-3). Use target options to control certain aspects of the processor on the ADSP-BF533 EZ-KIT Lite evaluation system. Figure 2-3. Target Options Dialog Box Reset Options Reset options control how the processor behaves when a reset occurs. The reset options are described in Table 2-11. Table 2-11. Reset Options Option Description Core reset Resets the core when the debugger executes a reset. System reset Resets the peripherals when the debugger executes a reset. On Emulator Exit This target option controls processor behavior when VisualDSP++ relinquishes DSP control (for example, when exiting VisualDSP++). The option is described in Table 2-12. ADSP-BF533 EZ-KIT Lite Evaluation System Manual 2-17 Using EZ-KIT Lite VisualDSP++ Interface Table 2-12. On Emulator Exit Target Options Option Description On Emulator Exit Determines the state the DSP is left in when the emulator relinquishes control of the DSP: Reset DSP and Run causes the DSP to reset and begin execution from its reset vector location. Run from current PC causes the DSP to begin running from its current location. Stall the DSP resets the DSP and then writes a JUMP 0 to the first location in internal memory so the DSP is stuck in a tight loop after exiting. Other Options Table 2-13 describes other available target options. Table 2-13. Miscellaneous Target Options Option Description Reset before loading executable Resets registers before loading a DSP executable. Clear this option when DSP registers must not change to their reset values when a file load occurs. Verify all writes to target memory Validates all memory writes to the DSP. After each write, a read is performed and the values are checked for a matching condition. Enable this option during initial program development to locate and fix initial build problems (such as attempting to load data into non-existent memory). Clear this option to increase performance while loading executable files, since VisualDSP++ does not perform the extra reads that are required to verify each write. 2-18 ADSP-BF533 EZ-KIT Lite Evaluation System Manual Using EZ-KIT Lite Table 2-13. Miscellaneous Target Options (Cont’d) Option Description Reset cycle counters on run Resets the cycle count registers to zero before a Run command is issued. Select this option to count the number of cycles executed between breakpoints in a program. Auto configure SDRAM bank 0 VisualDSP++ will auto-configure the necessary registers to communicate with the SDRAM Bank 0 memory included on the EZ-KIT Lite evaluation board. Select this option to cause VisualDSP++ to configure Bank 0 when it is accessed through VisualDSP++ (for example, when viewing memory windows or loading a program). Clear this option if you want to manually configure memory. Restricted Software Breakpoints The EZ-KIT Lite development system restricts breakpoint placement when certain conditions are met. That is, under some conditions, breakpoints cannot be placed effectively. Such conditions depend on bus architecture, pipeline depth, and ordering of the EZ-KIT Lite and its target processor. ADSP-BF533 EZ-KIT Lite Evaluation System Manual 2-19 Using EZ-KIT Lite VisualDSP++ Interface 2-20 ADSP-BF533 EZ-KIT Lite Evaluation System Manual 3 EZ-KIT LITE HARDWARE REFERENCE This chapter describes the hardware design of the ADSP-BF533 EZ-KIT Lite board. The following topics are covered. • “System Architecture” on page 3-2 Describes the configuration of the ADSP-BF533 EZ-KIT Lite board and explains how the board components interface with the processor. • “Jumper and DIP Switch Settings” on page 3-9 Shows the location and describes the function of the configuration jumpers and DIP switches. • “LEDs and Push Buttons” on page 3-13 Shows the location and describes the function of the LEDs and push buttons. • “Connectors” on page 3-16 Shows the location and gives the part number for all of the connectors on the board. Also, the manufacturer and part number information is given for the mating parts. ADSP-BF533 EZ-KIT Lite Evaluation System Manual 3-1 System Architecture System Architecture This section describes the processor’s configuration on the EZ-KIT Lite board. 32 MB SDRAM 2 MB Flash (16M x 16-bit) 32.768 KHz Oscillator EBUI JTAG Port JTAG Header LEDs (6) (1M x 8-bit x 2-chips) RTC ADSP-BF533 Processor Expansion Connectors (3) 27 MHz Oscillator UART SPORT1 SPI SPORT0 PPI/PFs PBs (4) SPORT0 +7.5V Connector A5V 3.3V Power Regulation ADM3202 RS-232 TX/RX RS-232 Male AD1836 Codec Stereo In Phono Jacks (4) Stereo Out Phono Jacks (6) ADV7183 Video Decoder ADV7171 Video Encoder Video In Phono Jacks (3) Video Out Phono Jacks (3) Figure 3-1. System Architecture The EZ-KIT Lite has been designed to demonstrate the capabilities of the ADSP-BF533 Blackfin processor. The processor has IO voltage of 3.3V. The c ore voltage of the processor can be supplied from either the internal voltage regulator or a fixed 1.4V external regulator. If the processor is operating at speeds greater than 600 MHz, it is necessary to use the 1.4V regulator. For more information about setting the source of the core voltage, see “Core Voltage Source Select Jumper (JP3)” on page 3-10. 3-2 ADSP-BF533 EZ-KIT Lite Evaluation System Manual EZ-KIT Lite Hardware Reference The core voltage and the core clock rate can be set on the fly by the processor. The input clock is 27 MHz. A 32.768 kHz crystal supplies the Real Time Clock (RTC) inputs of the processor. The default mode for the processor is Flash boot. See “Boot Mode Select Jumpers (JP2–1)” on page 3-10 for information about changing the default boot mode. External Bus Interface Unit The External Bus Interface Unit (EBIU) connects an external memory to the ADSP-BF533 device. It includes a 16-bit wide data bus, an address bus, and a control bus. Both 16-bit and 8-bit access are supported. On the EZ-KIT Lite, the EBI unit connects to SDRAM and Flash memory. 32 Mbytes (16M x 16 bits) of SDRAM connect to the synchronous memory select 0 pin (~SMS0). Refer to “Using SDRAM Interface” on page 2-4 for information about configuring the SDRAM. Note that SDRAM clock is the processor’s Clock Out (CLK OUT), which frequency should not exceed 133 MHz. Two Flash memory devices are connected to the asynchronous memory select signals, ~AMS2 through ~AMS0. The devices provide total of 2 Mbytes of primary Flash memory, 128 Kbytes of secondary Flash memory, and 64 Kbytes of SRAM. The processor can use this memory for both booting and storing information during normal operation. Refer to “Using Flash Memory” on page 2-5 for details. All of the address, data, and control signals are available externally via the extender connectors P3–1. The pinout of these connectors can be found in Appendix B, “Schematics” on page B-1. ADSP-BF533 EZ-KIT Lite Evaluation System Manual 3-3 System Architecture SPORT0 Audio Interface The SPORT0 interface is connected to the AD1836 audio codec, the SPORT connector (P3), and the expansion interface. The AD1836 codec uses both the primary and secondary data transmit and receive pins to input and output data from the audio input and outputs. The pinout of the SPORT connector and the expansion interface connectors can be found in Appendix B, “Schematics” on page B-1. SPI Interface The processor’s Serial Peripheral Interconnect (SPI) interface is connected to the AD1836 audio codec and the expansion interface. The SPI connection to the AD1836 is used to access the control registers of the device. The PF4 flag of the processor is used as the devices select for the SPI port. Programmable Flags The processor has 15 programmable flag pins (PFs). The pins have multiple functions, depending on the setup of the processor. Table 3-1 shows how the programmable flag pins are used on the EZ-KIT Lite. Table 3-1. Programmable Flag Connections DSP PF Pin EZ-KIT Function PF0 Serial clock for programming ADV7171 and ADV7183 PF1 Serial data for programming ADV7171 and ADV7183 PF2 ADV7183 ~OE PF3 PF4 3-4 Other DSP Function FS3 ADV7183 Field Pin. See “Video Configuration Switch (SW3)” on page 3-11. AD1836 SPI Select ADSP-BF533 EZ-KIT Lite Evaluation System Manual EZ-KIT Lite Hardware Reference Table 3-1. Programmable Flag Connections (Cont’d) DSP PF Pin Other DSP Function EZ-KIT Function PF5 PF6 PF7 PF8 Push button (SW4). See “Using LEDs and Push Buttons” on page 2-10 and “Push Button Enable Switch (SW9)” on page 3-12 for information on how to disable the push button. PF9 Push button (SW5). See “Using LEDs and Push Buttons” on page 2-10 and “Push Button Enable Switch (SW9)” on page 3-12 for information on how to disable the push button. PF10 Push button (SW6). See “Using LEDs and Push Buttons” on page 2-10 and “Push Button Enable Switch (SW9)” on page 3-12 for information on how to disable the push button. PF11 Push button (SW7). See “Using LEDs and Push Buttons” on page 2-10 and “Push Button Enable Switch (SW9)” on page 3-12 for information on how to disable the push button. PF12 PPI7 ADV7171 and ADV7183 Data (MSB) PF13 PPI6 ADV7171 and ADV7183 Data PF14 PPI5 ADV7171 and ADV7183 Data PF15 PPI4 ADV7171 and ADV7183 Data PPI Interface The Parallel Peripheral Interface (PPI) of the ADSP-BF533 processor is a half-duplex, bi-directional port that can accommodate up to 16 bits of data. The interface has a dedicated input clock (27 MHz), three multiplexed frame sync signals, and four bits of dedicated data. The remaining data bits come from re-configured programmable flag pins. For informa- ADSP-BF533 EZ-KIT Lite Evaluation System Manual 3-5 System Architecture tion about the pins, which multiplexed with the PPI, see “Programmable Flags” on page 3-4. For information about the ADSP-BF533 processor PPI interface, refer to the ADSP-BF533 Blackfin Processor Hardware Reference. Table 3-2 describes the PPI pins and their use on the EZ-KIT Lite board. Table 3-2. PPI Connections DSP PPI Pin Other DSP Function EZ-KIT Function PPI7 PF12 ADV7171 and ADV7183 Data (MSB) PPI6 PF13 ADV7171 and ADV7183 Data PPI5 PF14 ADV7171 and ADV7183 Data PPI4 PF15 ADV7171 and ADV7183 Data PPI3 ADV7171 and ADV7183 Data PPI2 ADV7171 and ADV7183 Data PPI1 ADV7171 and ADV7183 Data PPI0 ADV7171 and ADV7183 Data PF3 FS3 ADV7183 Field Pin. For more information, see “Video Configuration Switch (SW3)” on page 3-11. TMR1 PPI_HSYNC ADV7171 and ADV7183 HSYNC. For more information, see “Video Configuration Switch (SW3)” on page 3-11. TMR2 PPI_FSYNC ADV7171 and ADV7183 VSYNC. For more information, see “Video Configuration Switch (SW3)” on page 3-11. PPI_CLK Input from either the ADV7183 output clock or the same 27 MHz oscillator driving the processor. For more information, see “Using Video” on page 2-12. The ADSP-BF533 EZ-KIT Lite board employs 8-bit PPI interface for video output and video input. 3-6 ADSP-BF533 EZ-KIT Lite Evaluation System Manual EZ-KIT Lite Hardware Reference Video Output Mode In the video output mode, the PPI interface is configured as output and connects to the on-board video encoder device, ADV7171. The ADV7171 encoder device generates three analog video channels on DAC B, DAC C, and DAC D outputs. The PPI data connects to P7–0 of the encoder’s pixel inputs. The encoder’s PPI input clock runs at 27 MHz, and it is in phase with CLK IN of the ADSP-BF533 processor. The encoder’s synchronization signals, HSYNC and VSYNC, can be configured as inputs or outputs. Video Blanking control signal is at level “1”. The HSYNC and VSYNC signals can be connected to the ADSP-BF533 processor’s multiplexed sync pins and to the on-board video decoder, ADV7183, via the SW3 switch, as described in “Video Configuration Switch (SW3)” on page 3-11. Video Input Mode In the video input mode, the PPI interface is configured as input and connects to the on-board video decoder device, ADV7183. The ADV7183 decoder receives three analog video channels on AIN1, AIN4, and AIN5 input. The decoder’s pixel data outputs P15–8 drive the PPI data (PPI3–0 and PF15–12). The decoder’s 27 MHz pixel clock output can be selected to drive PPI clock, as shown in Table 2-8 on page 2-8. Synchronization outputs of the decoder, HS/HACTIVE, VS/VACTIVE, and FIELD can connected to the ADSP-BF533 processor’s multiplexed sync pins and to the on-board video encoder, ADV7171, via the SW3 DIP switch, as described in “Video Configuration Switch (SW3)” on page 3-11. ADSP-BF533 EZ-KIT Lite Evaluation System Manual 3-7 System Architecture UART Port The processor’ Universal Asynchronous Receiver/Transmitter (UART) port is connected to the ADM3202 RS232 line driver as well as to the expansion interface. The RS232 line driver is connected to the DB9 male connector, allowing you to interface with a PC or other serial device. Expansion Interface The expansion interface consists of the three 90-pin connectors. Table 3-3 on page 3-8 shows the interfaces each connector provides. For the exact pinout of these connectors, refer to Appendix B, “Schematics” on page B-1. The mechanical dimensions of the connectors can be obtained from Technical or Customer Support. Table 3-3. Connector Interfaces Connector Interfaces J1 5V, G ND, Address, Data, PPI J2 3.3V, GND, SPI, NMI, TMR2–0, SPORT0, SPORT1, PF15–0, EBUI control signals J3 5V, 3.3V, GND, UART, Flash IO, Reset, Video control signals Limits to the current and to the interface speed must be taken into consideration when you use the expansion interface. The maximum current limit is dependent on the capabilities of the regulator used. Additional circuitry can also add extra loading to signals, decreasing their maximum effective speed. Devices does not support and is not responsible for the [ Analog effects of additional circuitry. 3-8 ADSP-BF533 EZ-KIT Lite Evaluation System Manual EZ-KIT Lite Hardware Reference JTAG Emulation Port The JTAG emulation port allows an emulator to access the processor’s internal and external memory through a 6-pin interface. The JTAG emulation port of the processor is also connected to the USB debugging interface. When an emulator is connected to the board at P4, the USB debugging interface is disabled. See “JTAG (P4)” on page 3-20 for more information about the JTAG connector. To learn more about available emulators, contact Analog Devices (see “Product Information”). Jumper and DIP Switch Settings This section describes the operation of the jumpers and DIP switches. The jumpers and DIP switch locations are shown in Figure 3-2. Figure 3-2. Jumper and DIP Switch Locations ADSP-BF533 EZ-KIT Lite Evaluation System Manual 3-9 Jumper and DIP Switch Settings Boot Mode Select Jumpers (JP2–1) The JP1 and JP2 jumpers determine the boot mode of the processor. Table 3-4 shows the available boot mode settings. By default, the processor boots from the on-board Flash memory. Table 3-4. Boot Mode Settings JP1 (BMODE1) JP2 (BMODE0) Boot Mode Installed Installed 16-Bit External Memory Installed 1 Not installed Flash Memory Not installed Installed Reserved Not installed Not installed SPI EEPROM 1 Default settings Core Voltage Source Select Jumper (JP3) The core voltage of the processor can be derived from either the processor’s internal voltage regulator or from a fixed 1.4V external regulator. It is necessary to use the 1.4V external regulator when the processor runs at speeds greater than 600 MHz. Table 3-5 summarizes the functionality of the Core Voltage Source Select Jumper, JP3. Table 3-5. Core Voltage Source Settings Position Core Voltage Source 1 and 2 Processor Internal Voltage Regulator 2 and 3 1.4V External Regulator 3-10 ADSP-BF533 EZ-KIT Lite Evaluation System Manual EZ-KIT Lite Hardware Reference Test DIP Switches (SW2–1) Two DIP switches (SW1 and SW2) are located on the bottom of the board. The switches are used only for testing and should always be in the “OFF” position. Video Configuration Switch (SW3) The video configuration switch (SW3) controls how some video signals from the ADV7183 video decoder and ADV7171 video encoder are routed to the processor’s PPI. The switch also determines if the PF2 pin controls the OE of the ADV7183 video decoder outputs. Table 3-6 shows which processor’s signals are connected to the encoder and decoder when in the “ON” position. Table 3-6. Video Configuration Switch (SW3) Switch Position (Default) Processor Signal Video Signal 1 (OFF) TMR1 (HSYNC) HSYNC 2 (OFF) TMR1 (HSYNC) HS (ADV7183) 3 (OFF) TMR2 (VSYNC) VS (ADV7183) 4 (OFF) TMR2 (VSYNC) VSYNC (ADV7171) 5 (OFF) PF3 (FIELD) FIELD (ADV7183) 6 (ON) PF2 ~OE (ADV7171) (ADV7183) Positions 1 thorough 5 of SW3 determine how and if the VSYNC, HSYNC, and control signals are routed to the processors PPI. In standard configuration of the encoder and decoder, this is not necessary because the processor is capable of reading the embedded control information, which is in the data stream. FIELD ADSP-BF533 EZ-KIT Lite Evaluation System Manual 3-11 Jumper and DIP Switch Settings Position 6 of SW3 determines whether PF2 is connected to the ~OE signal of the ADV7183. When the switch “OFF”, PF2 can be used for other operations, and the decoder output enable is held “HIGH” with a pull-up resistor. Push Button Enable Switch (SW9) The push button enable switch (SW9) positions 1 through 4 allow the user to disconnect the drivers associated with the push buttons from the PF pins of the processor. Positions 5 and 6 are used to connect the transmit and receive the frame syncs and clocks of SPORT0. This is important when the AD1836 video decoder and the processor are communicating in I2S mode. Table 3-7 shows which PF is driven when the switch is in the “ON” position. Table 3-7. Push Button Enable Switch (SW9) Switch Position Default Setting Pin # Signal (Side 1) Pin # Signal (Side 2) 1 ON 1 SW4 12 PF8 2 ON 2 SW5 11 PF9 3 ON 3 SW6 10 PF10 4 ON 4 SW7 9 PF11 5 OFF 5 TFS0 8 RFS0 6 OFF 6 RSCLK0 7 TSCLK0 3-12 ADSP-BF533 EZ-KIT Lite Evaluation System Manual EZ-KIT Lite Hardware Reference LEDs and Push Buttons This section describes the functionality of the LEDs and push buttons. Figure 3-3 shows the locations of the LEDs and push buttons. Figure 3-3. LED and Push Button Locations Programmable Flag Push Buttons (SW7–4) Four push buttons, SW7–4, are provided for general-purpose user input. The buttons connect to the processor’s programmable flag pins PF11–8. The push buttons are active “HIGH” and, when pressed, send a High (1) to the processor. Refer to “Using LEDs and Push Buttons” on page 2-10 for more information on how to use the PFs when programming the processor. The push button enable switch (SW9) is capable of disconnecting the ADSP-BF533 EZ-KIT Lite Evaluation System Manual 3-13 LEDs and Push Buttons push buttons from the PF (refer to “Push Button Enable Switch (SW9)” on page 3-12 for more information). The programmable flag signals and their corresponding switches are shown in Table 3-8. Table 3-8. Programmable Flag Switches DSP Programmable Flag Pin Push Button Reference Designator PF8 SW4 PF9 SW5 PF10 SW6 PF11 SW7 Reset Push Button (SW8) The RESET push button resets all of the ICs on the board. One exception is the USB interface chip (U34). The chip is not being reset when the push button is pressed after the USB cable has been plugged in and communication has been correctly initialized with the PC. After USB communication has been initialized, the only way to reset the USB is by powering down the board. Power LED (LED1) When LED1 is lit (green), it indicates that power is being properly supplied to the board. Reset LEDs (LED3–2) When LED2 is lit, it indicates that the master reset of all the major ICs is active. When LED3 is lit, the USB interface chip (U34) is being reset. The USB chips only reset on power-up, or if USB communication has not been initialized. 3-14 ADSP-BF533 EZ-KIT Lite Evaluation System Manual EZ-KIT Lite Hardware Reference User LEDs (LED9–4) Six LEDs are connected to six of the Flash memory (U5) general-purpose IO pins. The LEDs are active “HIGH” and are lit by writing a “1” to the correct memory address in the Flash memory. Refer to “Using LEDs and Push Buttons” on page 2-10 for more information about how to use the flash when programming the LEDs. Table 3-9. User LEDs LED Reference Designator Flash Port Name LED4 PB0 LED5 PB1 LED6 PB2 LED7 PB3 LED8 PB4 LED9 PB5 USB Monitor LED (LED11) The USB Monitor LED (LED11) indicates that USB communication has been initialized successfully and you may connect to the processor using a VisualDSP++ EZ-KIT Lite session. This should take approximately 15 seconds. If the LED does not light, try cycling power on the board and/or reinstalling the USB driver (see “Installing EZ-KIT Lite USB Driver” on page 1-7). ADSP-BF533 EZ-KIT Lite Evaluation System Manual 3-15 Connectors Connectors This section describes the connector functionality and provides information about mating connectors. The locations of the connectors are shown in Figure 3-4 on page 3-16. Figure 3-4. Connector Locations Expansion Interface (J3–1) Three board-to-board connector footprints provide signals for most of the processor’s peripheral interfaces. The connectors are located at the bottom of the board. For more information about the expansion interface, see on page 3-8. For the availability and pricing of the J1, J2, and J3 connectors, contact Samtec. 3-16 ADSP-BF533 EZ-KIT Lite Evaluation System Manual EZ-KIT Lite Hardware Reference Part Description Manufacturer Part Number 90 Position 0.05" Spacing, SMT (J1, J2, J3) Samtec SFC-145-T2-F-D-A Mating Connector 90 Position 0.05” Spacing (Through Hole) Samtec TFM-145-x1 Series 90 Position 0.05” Spacing (Surface Mount) Samtec TFM-145-x2 Series 90 Position 0.05” Spacing (Low Cost) Samtec TFC-145 Series Part Description Manufacturer Part Number 2x2 RCA Jacks (J5) SWITCHCRAFT PJRAS2X2S01 3x2 RCA Jacks (J4) SWITCHCRAFT PJRAS3X2S01 Audio (J5–4) Mating Connector Two channel RCA interconnect cable Monster Cable BI100-1M Video (J8) Part Description Manufacturer Part Number 3x2 RCA Jacks (J4) SWITCHCRAFT PJRAS3X2S01 Power (J9) The power connector provides all of the power necessary to operate the EZ-KIT Lite board. The power connector supplies DC power to the board. The following table shows the power connector pinout. ADSP-BF533 EZ-KIT Lite Evaluation System Manual 3-17 Connectors Part Description Manufacturer Part Number 2.5 mm Power Jack (J9) SWITCHCRAFT RAPC712 Digi-Key SC1152-ND Mating Power Supply (shipped with EZ-KIT Lite) 7.5V Power Supply GlobTek TR9CC2000LCP-Y The power connector supplies DC power to the EZ-KIT Lite board. Table 3-10 shows the power supply specifications. Table 3-10. Power Supply Specification Terminal Connection Center pin +7.5 VDC@2amps Outer Ring GND FlashLINK (P1) The FlashLINK connector allows you to configure and program the STMicroelectronics DSM2150 flash/PLD chip. See “Configuring Flash Memory” on page 2-9 for more information about the FlashLINK connector. Part Description Manufacturer Part Number Right-angle 7X2 Shrouded 0.1 spacing (J10) TYCO 2-767004-2 Mating Assembly FlashLINK JTAG Programmer 3-18 ST Micro FL-101B ADSP-BF533 EZ-KIT Lite Evaluation System Manual EZ-KIT Lite Hardware Reference RS232 (P2) The RS232-compatible connector is described in Table 3-11. Table 3-11. RS232 Connector Part Description Manufacturer Part Number DB9, Male, Right Angle (P2) Digi-Key A2096-ND Mating Assembly 2m Female to female cable Digi-Key AE1016-ND SPORT0 (P3) The SPORT0 connector is linked to a 20-pin connector. The connector’s pinout can be found in “Schematics” on page B-1. For pricing and availability on these connectors, contact AMP. Part Description Manufacturer Part Number 20 position AMPMODU system 50 receptacle (P3) AMP 104069-1 Mating Connectors 20 position ribbon cable connector AMP 111196-4 20 position AMPMODU system 20 connector AMP 2-487937-0 20 position AMPMODU system 20 connector (w/o lock) AMP 2-487938-0 Flexible film contacts (20 per connector) AMP 487547-1 ADSP-BF533 EZ-KIT Lite Evaluation System Manual 3-19 Connectors JTAG (P4) The JTAG header is the connecting point for a JTAG in-circuit emulator pod. When an emulator is connected to the JTAG header, the USB debug interface is disabled. 3 is missing to provide keying. Pin 3 in the mating connector L Pin should have a plug. using an emulator with the EZ-KIT Lite board, follow the L When connection instructions provided with the emulator. 3-20 ADSP-BF533 EZ-KIT Lite Evaluation System Manual Part Number Manufacturer Reference Design Description Quantity Reference A BILL OF MATERIALS 1 2 74LVC14A SOIC14 U10,U41 HEX-INVER-SCHMITT-TR IGGER TI 74LVC14AD 2 1 IDT74FCT3244APY SSOP20 3.3V-OCTAL-BUFFER IDT IDT74FCT3244APY 3 1 IDT74FCT3807AQ U4 QSOP20 3.3V 1-10 CLOCK DRIVER IDT IDT74FCT3807AQ 4 1 CY7C64603-128 PQFP128 U34 USB-TX/RX MICROCONTROLLER CYPRESS CY7C64603-128NC 5 1 MMBT4401 SOT-23 Q1 NPN TRANSISTOR 200MA FAIRCHILD MMBT4401 6 1 74LVC00AD SOIC14 U9 PHILIPS 74LVC00AD 7 1 CY7C1019BV33-15VC SOJ32 128K X 8 SRAM U39 CYPRESS CY7C1019BV33-12VC 8 1 SN74AHC1G02 SOT23-5 SINGLE-2 INPUT-NOR U44 TI SN74AHC1G02DBVR 9 1 SN74LV164A SOIC14 8-BIT-PARALLEL-SERIAL U35 TI SN74LV164AD U31 ADSP-BF533 EZ-KIT Lite Evaluation System Manual A-1 Part Number Manufacturer Reference Design Description Quantity Reference A-2 10 1 CY7C4201V-15AC TQFP3264-BYTE-FIFO U43 CYPRESS CY7C4201V-15AC 11 1 12.0MHZ THR OSC006 CRYSTAL Y1 DIG01 300-6027-ND 12 1 SN74AHC1G00 SOT23-5 SINGLE-2-INPUT-NAND U42 TI SN74AHC1G00DBVR 13 1 12.288MHZ SMT OSC003 U11 DIG01 SG-8002CA-PCC-ND 14 1 SN74LVC1G125 SOT23-5 SINGLE-3STATE-BUFFER U7 TI SN74LVC1G125DBVR 15 1 NDS8434A SO-8 P-MOSFET U32 FAIRCHILD NDS8434A SEMI 16 1 MT48LC16M16A2TG-75 TSOP54 256MB-SDRAM U8 MICRON MT48LC16M16A2TG-75 17 1 27MHZ SMT OSC003 U3 EPSON SG-8002CA MP 18 1 32.768KHZ SMT OSC008 U2 EPSON MC-156 32.768KA-A2 19 2 PSD4256G6V-10UI TSOP54 U5–6 1MB-FLASH/GPIO ST MICRO PSD4256G6V-10UI 20 1 IDT2305-1DC SOIC8 U46 1 TO 5 ZERO DELAY CLK BUF INTEICS9112AM-16 GRATED SYS 21 1 SN74LVC1G32 SOT23-5 SINGLE-2 INPUT OR GATE U21 TI 22 1 BF533 24LC00-SN "U33" SEE 1000127 U33 ANALOG DEVICES 23 2 1000pF 50V 5% 1206 CERM C96–97 AVX SN74LVC1G32DBVR 12065A102JAT2A ADSP-BF533 EZ-KIT Lite Evaluation System Manual Part Number Manufacturer Reference Design Description Quantity Reference Bill Of Materials 24 6 2200pF 50V 5% 1206 NPO C12,C17,C22, C27,C32,C37 AVX 12065A222JAT050 25 1 ADM708SAR SOIC8 VOLTAGE-SUPERVISOR U29 ANALOG DEVICES ADM708SAR 26 1 ADP3338AKC-33 SOT-223 VR1 3.3V-1.0AMP REGULATOR ANALOG DEVICES ADP3338AKC-3.3 27 1 ADP3339AKC-5 SOT-223 5V-1.5A REGULATOR VR5 ANALOG DEVICES ADP3339AKC-5-REEL 28 2 ADP3339AKC-33 SOT-223 3.3V 1.5A REGULATOR VR3–4 ANALOG DEVICES ADP3339AKC-3.3-RL 29 1 ADP3336ARM MSOP8 ADJ 500MA REGULATOR VR6 ANALOG DEVICES ADP3336ARM-REEL 30 1 ADV7171KSU TQFP44 VID-ENCODER U27 ANALOG DEVICES ADV7171KSU 31 1 10MA AD1580BRT SOT23D 1.2V-SHUNT-REF D1 ANALOG DEVICES AD1580BRT 32 2 ADG752BRT SOT23-6 CMOS-SPDT-SWITCH U25–26 ANALOG DEVICES ADG752BRT 33 3 AD8061ART SOT23-5 300MHZ-AMP U22–24 ANALOG DEVICES AD8061ART-REEL 34 1 ADM3202ARN SOIC16 RS232-TXRX U30 ANALOG DEVICES ADM3202ARN 35 1 ADV7183KST LQFP80 VID-DECODER U28 ANALOG DEVICES ADV7183KST 36 8 AD8606AR SOIC8 OPAMP U12–13,U15–20 ANALOG DEVICES 37 1 ADSP-BF533SKBC MINIBGA160 U1 AD8606AR ANALOG DEVICES ADSP-BF533 EZ-KIT Lite Evaluation System Manual A-3 Part Number AD1836AAS MQFP52 MULTI-CHANNEL-96KHZ-CODEC U14 ANALOG DEVICES AD1836AAS 39 5 RUBBER FEET BLACK MH1–5 MOUSER 517-SJ-5018BK 40 1 PWR 2.5MM_JACK CON005 RA J9 SWITCHCRAFT SC1152-ND12 41 1 USB 4PIN CON009 USB J10 MILL-MAX 897-30-004-90-000000 42 1 RCA 2X2 CON013 J5 SWITCHCRAFT PJRAS2X2S01 43 1 .05 10X2 CON014 RA P3 AMP 104069-1 44 5 SPST-MOMENTARY SWT013 6MM SW4-8 PANASONIC EVQ-PAD04M 45 1 IDC 7X2 IDC7X2SRDRA RIGHT ANGLE SHROUDED P1 MOLEX 70247-1401 46 3 0.05 45X2 CON019 SMT SOCKET J1–3 SAMTEC SFC-145-T2-F-D-A 47 4 DIP6 SWT017 SW1–3,SW9 DIG01 CKN1364-ND 48 2 RCA 3X2 CON024 RA J4,J8 SWITCHCRAFT PJRAS3X2S01 49 14 0.00 1/8W 5% 1206 A-4 Manufacturer Reference Design Description Quantity Reference 38 1 R27–30,R148, YAGEO R157–158,R167, R174–175, R177–178, R182,R193 0.0ECT-ND ADSP-BF533 EZ-KIT Lite Evaluation System Manual 50 7 AMBER-SMT LED001 GULL-WING Part Number Manufacturer Reference Design Description Quantity Reference Bill Of Materials LED4–9, LED11 PANASONIC LN1461C-TR 51 12 330pF 50V 5% 805 NPO C13,C18,C23, C28,C33,C38 52 42 0.01uF 100V 10% 805 CERM C4,C85,C87, AVX C108,C112–113, C123–124, C126–128, C136,C146–147, C149–155, C159–161 08051C103KAT2A 53 8 C129–130, C137–142 AVX 08053C224FAT 54 73 0.1uF 50V 10% 805 CERM C6,C8,C71–72, AVX C75–81,C84, C86,C88–95, C98–101,C105, C109–111, C114–122,C125, C131 08055C104KAT 55 8 0.001uF 50V 5% 805 NPO C7,C9–11, AVX C49–50,C52–53 08055A102JAT2A 56 8 10uF 16V 10% C TANT CT13, CT21–27 SPRAGUE 293D106X9016C2T 57 45 10K 100MW 5% 805 R1, R4, R10, R12–13,R15–16 CR21-103J-T 58 9 33 100MW 5% 805 R5–6, R8–9,R31, AVX R144,R179,R183 CR21-330JTR 59 2 4.7K 100MW 5% 805 R17,R220 AVX CR21-4701F-T 60 1 1M 100MW 5% 805 R202 AVX CR21-1004F-T 61 1 1.5K 100MW 5% 805 R203 AVX CR21-1501F-T 0.22uF 25V 10% 805 CERM AVX AVX ADSP-BF533 EZ-KIT Lite Evaluation System Manual 08055A331JAT A-5 Part Number 1.2K 1/8W 5% 1206 R129 DALE CRCW1206-122JRT1 63 6 49.9K 1/8W 1% 1206 R38,R45,R54, R62,R70,R78 AVX CR32-4992F-T 64 2 2.21K 1/8W 1% 1206 R212–213 AVX CR32-2211F-T 65 1 2000pF 50V 5% 1206 CERM C83 AVX 12065A202JAT2A 66 12 100pF 100V 5% 1206 NPO C15,C20,C25, C30,C35,C40, AVX 12061A101JAT2A 67 5 10uF 16V 10% B TANT CT1–2,CT14–16 AVX TAJB106K016R 68 4 100 100MW 5% 805 R149,R152, R154–155 AVX CR21-101J-T 69 6 220pf 50V 10% 1206 NPO C16,C21,C26, C31,C36,C41 AVX 12061A221JAT2A 70 4 600 100MHZ 200MA 603 0.50 BEAD FER14–17 MURATA BLM11A601SPT 71 3 2A S2A_RECT DO-214AA SILICON RECTIFIER D2–4 GENERALSEMI S2A 72 12 600 100MHZ 500MA 1206 0.70 BEAD FER1–5, FER9–11, FER18–19, FER18–19, FER21–22 DIGI-KEY 240-1019-1-ND 73 4 237 1/8W 1% 1206 R93,R95,R97, R99 AVX CR32-2370F-T 74 4 750K 1/8W 1% 1206 R86,R90,R94, R96 DALE/VISH CRCW12067503FRT1 AY 75 16 5.76K 1/8W 1% 1206 A-6 Manufacturer Reference Design Description Quantity Reference 62 1 R82–85,R87–89, PHYCOMP R91–92,R98 9C12063A5761FKHFT ADSP-BF533 EZ-KIT Lite Evaluation System Manual Part Number Manufacturer Reference Design Description Quantity Reference Bill Of Materials 76 6 11.0K 1/8W 1% 1206 R34,R48,R50, R58,R66,R74 DALE CRCW12061102FRT1 77 8 120PF 50V 5% 1206 NPO C42–45,C55, C57–59 PHILLIPS 1206CG121J9B200 78 1 68PF 50V 5% 1206 C82 PHILLIPS 1206CG680J9B200 79 1 1UF 16V 10% 805 X7R C5 MURATA GRM40X7R105K016AL 80 12 75 1/8W 5% 1206 R113–114, R116–117, R120–121 PHILIPS 9C12063A75R0JLHFT 81 2 30PF 100V 5% 1206 C206–207 AVX 12061A300JAT2A 82 1 68UF 6.3V 20% D TANT CT28 PANASONIC ECS-TOJD686R 83 6 680PF 50V 1% 805 NPO C14,C19,C24, C29,C34,C39 AVX 08055A681FAT2A 84 3 10UF 25V +80-20% 1210 Y5V C198–200 MURATA GRM235Y.5V106Z025 85 6 2.74K 1/8W 1% 1206 R41,R47,R57, R65,R73,R81 PANASONIC ERJ-8ENF2741V 86 12 5.49K 1/8W 1% 1206 R35,R40,R42, R49,R51,R56, R59 PANASONIC ERJ-8ENF5491V 87 6 3.32K 1/8W 1% 1206 R36,R43,R52, R60,R68,R76 DALE 88 6 1.65K 1/8W 1% 1206 R37,R44,R53, R61,R69,R77 PANASONIC ERJ-8ENF1651V 89 10 10UF 16V 20% CAP002 ELEC CT3–12 DIG01 PCE3062TR-ND 90 1 R184 PHILIPS 9C08052A5362FKRT/R 53.6K 1/10W 1% 805 ADSP-BF533 EZ-KIT Lite Evaluation System Manual CRCW12063321FRT1 A-7 Part Number Manufacturer Reference Design Description Quantity Reference A-8 91 1 10UH 47 +/-20 IND001 L12 DIG01 445-1202-2-ND 92 2 10K 50MW 5% BGA36 RN1–2 CTS RT130B7 93 15 0.00 100MW 5% 805 R3,R22,R24–25, VISHAY R111,R132, R135–136,R141, R186–189, R210,R222 CRCW0805 0.0 RT1 94 1 190 100MHZ 5A FER002 FER23 MURATA DLW5BSN191SQ2 95 1 3.32K 100MW 1% 805 C188 DIG01 P3.32KCCTR-ND 96 3 22 1/10W 5% 805 R14, R180–181 VISHAY/DAL CRCW0805220JRT1 E 97 6 0.68UH 0.72 10% 805 L4–9 MURATA LQG21NR68K10T1 98 1 1A ZHCS1000 SOT23D SCHOTTKY D5 ZETEX ZHCS1000 99 1 5.6K 1/10W 5% 805 R140 VISHAY CRCW0805562JRT1 100 3 2.2UH 0.63 10% 805 L1–3 MURATA LQG21N2R2K10 101 3 1UF 10V 10% 805 C60–61,C104 AVX 0805ZC105KAT2A 102 2 18PF 50VDC 5% 805 CERM C1, C3 PANASONIC ECJ-2VC1H180J 103 1 10M 1/8W 5% 805 R20 AVX CR21-106J-T 104 1 DB9 9PIN DB9M RIGHT ANGLE MALE P2 3M 787203-2 105 7 1K 1/8W 5% 1206 R115,R118–119, AVX R125–126,R131 106 3 100K 1/8W 5% 1206 R112,R130,R176 CR1206-1003 FRT1 107 2 22 1/8W 5% 1206 R200,R207 DALE CR32-102J-T CRCW1206220JRT1 ADSP-BF533 EZ-KIT Lite Evaluation System Manual Part Number Manufacturer Reference Design Description Quantity Reference Bill Of Materials 108 9 270 1/8W 5% 1206 R146–147, AVX R160–162, R164–165,R168, R195 CR32-271J-T 109 1 680 1/8W 5% 1206 R163 AVX CR32-681J-T 110 1 150 1/8W 1% 1206 R122 PANASONIC ERJ-8ENF1500V 111 2 RED-SMT LED001 GULL-WING LED2–3 PANASONIC LN1261C 112 1 GREEN-SMT LED001 GULL-WING LED1 PANASONIC LN1361C 113 6 604 1/8W 1% 1206 R39,R46,R55, R63,R71,R79 PANASONIC ERJ-8ENF6040V 114 4 1uF 25V 20% A TANT -55+125 CT17–20 PANASONIC ECS-T1EY105R 115 2 ADG774A QSOP16 QUICKSWITCH-257 U37–38 ANALOG DEVICES ADG774ABRQ 116 1 IDC 7X2 IDC7X2 HEADER P4 BERG 54102-T08-07 117 1 2.5A RESETABLE FUS001 F1 RAYCHEM CORP. SMD250-2 ADSP-BF533 EZ-KIT Lite Evaluation System Manual A-9 A-10 ADSP-BF533 EZ-KIT Lite Evaluation System Manual A B C D 1 1 2 2 ADSP-BF533 EZ-KIT Lite 3 3 DNP = Do Not Populate ANALOG DEVICES 4 Approvals Date Title 20 Cotton Road Nashua, NH 03063 4 PH: 1-800-ANALOGD ADSP-BF533 EZ-KIT LITE - TITLE Drawn Checked Engineering A B C Size Board No. C Date Rev A0167-2001 1.6 Sheet 3-24-2003_13:34 D 1 of 13 A 3.3V B 3.3V C D R5 33 805 ADV7183_27MHZ_CLK U4 R225 10K 805 3 O1 5 O2 7 O3 9 O4 11 O5 12 O6 14 O7 16 O8 18 O9 19 O10 R1 10K 805 1 R179 33 805 U3 1 OE 1 OUT IN 3 27MHZ OSC003 R6 33 805 ADV7171_27MHZ_CLK 3.3V R7 33 805 DNP R8 33 805 PPI_27MHZ_CLK 1 CLK_OUT R9 33 805 REF DSP_CLK IDT74FCT3807AQ QSOP20 Not populated in standard EZ-KIT Configuration. Can be used to provide DSP clock frequency other than that of the Video Interface. 6 R19 DNP 805 4 EXT_DSP_CLK VDD GND 8 CLKOUT 3 CLK1 2 CLK2 5 CLK3 7 CLK4 RTC RTXI CLK_OUT_EXP1 R181 22 805 R109 22 805 IDT2305-1DC SOIC8 1 RTXO R20 10M 805 CLK_OUT_EXP2 R224 33 805 U36 1 OE R180 22 805 U46 U2 1 4 2 3 NC2 TERM1 TERM2 DNP 3 OUT NC1 DNP 30.0000MHZ OSC003 DNP C1 18PF 805 U1 D[0:15] 2 3.3V R12 10K 805 A1 J14 A2 K14 A3 L14 A1 A2 M9 D0 N9 D1 P9 D2 M8 D3 N8 D4 P8 D5 M7 D6 N7 D7 P7 D8 M6 D9 N6 D10 P6 D11 M5 D12 N5 D13 P5 D14 D0 D1 L13 A7 K12 A8 L12 D3 A6 A4 J13 K13 D2 A5 A3 A4 A5 A6 A7 A8 A9 M12 A10 M13 A11 M14 A12 N14 A13 N13 A14 N12 A15 M11 A9 A10 A11 A12 D4 D5 D6 D7 D8 D9 D10 D11 A13 D12 A14 D13 A15 A16 N11 A17 P13 A18 P12 A19 A16 D14 P4 D15 RFS0 DR0PRI DR0SEC TSCLK0 TFS0 DT0PRI DT0SEC A18 P11 A19 E14 AMS0 F14 AMS1 E13 ARDY G12 AMS3 DSCLK1 RFS1 DR1PRI DR1SEC TSCLK1 TFS1 D15 DT1PRI AMS1 RX AMS2 TX ARE ARE SRAS AWE SCAS H14 AWE MOSI D13 C14 D12 SWE H13 ~ABE0/SDQM0 SCKE ~ABE1/SDQM1 CLKOUT H12 ~ABE0/SDQM0 ~ABE1/SDQM1 B13 SA10 D14 BR BR SRAS MISO SCAS SCK SWE SMS C13 SCKE TMR0 CLK_OUT SA10 N10 BGH TMR1 TMR2 RTXI A12 CLKIN J2 DR0SEC J1 TSCLK0 H3 TFS0 H1 DT0PRI H2 DT0SEC G1 G2 RSCLK1 RFS1 G3 DR1PRI F3 DR1SEC F1 TSCLK1 E1 TFS1 F2 DT1PRI L3 RX K3 TX RESET R13 10K 805 RESET VROUT2 B12 PF3 B1 PF4 B2 PF5 B3 PF6 B4 PF7 A2 PF8 A3 PF9 PF4 PF5 PF6 PF7 2 SJ2 SHORTING JUMPER DEFAULT=JP1=INSTALLED SJ3 PF9 A4 PF10 A5 PF11 B5 PF12 B6 PF13 A6 PF14 C6 PF15 SHORTING JUMPER DEFAULT=JP2=NOT INSTALLED PF10 PF11 PF12 Boot Mode Select Jumpers (JP1, JP2) DEFAULT = Flash Boot PF13 PF14 3.3V PF15 C8 PP0 B8 PP1 A7 PP2 B7 PP3 PP0 PP[0:3] PP1 DSP_CLK RTXO JP1 (BMODE1) JP2 (BMODE0) INSTALLED INSTALLED 16-BIT External Memory Boot Mode INSTALLED NOT INSTALLED Flash NOT INSTALLED INSTALLED Reserved NOT INSTALLED NOT INSTALLED SPI EEPROM PP2 R16 10K 805 PP3 MOSI E2 MISO R15 10K 805 R18 10K 805 3.3V C9 PPI_CLK PPI_CLK D1 SCK L2 TMR0 M1 TMR1 K2 TMR2 A9 RTXI TCK N3 TDO M3 TDI N2 TMS N1 TRST M2 EMU 3 TDO TDI TMS R2 10K 805 TRST R10 10K 805 EMU A8 RTXO N4 BMODE0 P3 BMODE1 NMI A13 C3 PF3 D3 A11 VROUT1 PF2 PF2 * XTALO C10 PF1 C2 DT1SEC B10 NMI C1 PF1 PF[0:15] E3 SMS BG BGH DR0PRI PF0 P2 P10 BG RFS0 D2 PF0 TCK R14 22 805 B14 E12 J3 K1 AMS3 AOE G14 RSCLK0 AMS0 G13 AOE L1 PF8 DT1SEC F13 ARDY RSCLK0 A17 AMS2 3 C3 18PF 805 U1 A[1:19] R4 10K 805 32.768KHZ OSC008 BMODE0 BMODE1 VROUT C2 0.1UF 805 DNP JP1 R17 4.7K 805 ADSP-BF533-750 MINIBGA160 R3 0.00 805 DNP JP2 1 R11 0.00 805 DNP 1 2 2 IDC2X1 2X1 ADSP-BF533-750 MINIBGA160 IDC2X1 2X1 DNP = Do Not Populate ANALOG DEVICES 4 Approvals Date Title 20 Cotton Road Nashua, NH 03063 4 PH: 1-800-ANALOGD ADSP-BF533 EZ-KIT LITE - DSP Drawn Checked Engineering A B C Size Board No. C Date Rev A0167-2001 1.6 Sheet 3-2-2004_15:06 D 2 of 12 A B C D 3.3V FlashLINK JTAG HEADER 3.3V R26 10K 805 P1 1 FLASH_TDI FLASH_TMS 2 3 4 5 6 7 8 R22 0.00 805 FLASH_TDI FLASH_TSTAT U9 FLASH_RESET_C 1 1 U7 2 9 FLASH_TCK_IN SN74LVC1G125 SOT23-5 10 11 74LVC00AD SOIC14 12 13 1 2 FLASH_RESET 2 RESET FLASH_TDI_A PD0_A FLASH_TDI_B 74LVC14A SOIC14 PD1_A PD2_A 14 FLASH_TERR 7X2 IDC7X2SRDRA FLASH_TDO DNP R21 0.00 805 R25 0.00 805 PE7_A FLASH_TSTAT FLASH_TDO C125 0.1UF 805 RN1 DNP R23 0.00 805 U10 3 4 FLASH_TCK 1 3.3V FLASH_TDO_A PE6_A FLASH_TDI_A R24 0.00 805 C5 1UF 805 FLASH_TDO_B PB7_A PB6_A LED6 LED5 LED4 LED2 LED3 LED[6:1] FLASH A (1MB) 512K x 16 2 LED1 B2 COM1 A1 R1 A2 R2 A3 R3 B1 R4 B3 R5 C1 R6 C2 R7 C3 R8 E2 COM2 D1 R9 D2 R10 D3 R11 E1 R12 E3 R13 F1 R14 F2 R15 F3 R16 10K BGA36 L2 RN2 COM4 K1 B2 K2 A1 R32 R31 PB4_B K3 R30 R28 M1 R27 M2 R26 FLASH_TMS PB3_B PC5_A PB7_B PC4_A M3 R25 FLASH_TERR R24 R22 R21 H3 R20 J1 R19 J2 R18 J3 R17 R8 PE7_B ADV7183_RESET PD1_B ADV7171_RESET PA7_B AD1898_RESET PA6_B AD1836_RESET R9 D2 PB0_B PPICLK_AD7183_SELECT COM2 D1 PD0_B PA7_A H1 R7 C3 E2 PPICLK_ONBOARD_SELECT G3 R6 C2 PA6_A G2 R23 R5 C1 PE6_B G1 R4 B3 PB2_B H2 R3 B1 PB1_B COM3 R2 A3 PB6_B L3 R1 A2 PB5_B L1 R29 COM1 R10 D3 R11 E1 R12 E3 R13 F1 R14 F2 PA5_B R15 F3 R16 10K BGA36 FLASH B (1MB) 512K x 16 1 L2 COM4 K1 R32 K2 R31 K3 R30 L1 R29 L3 R28 M1 R27 M2 R26 M3 R25 H2 COM3 G1 R24 G2 R23 G3 R22 H1 R21 H3 R20 J1 R19 J2 R18 J3 R17 PC5_B PA0_B PD2_B PC4_B FLASH_TDO FLASH_RESET_C FLASH_TCK_IN PA4_B PA3_B PA2_B PA1_B 2 SDRAM 256Mb (32MB - 16M x 16) D[0:15] A[1:19] U5 3 ~ABE0/SDQM0 AD0 A1 3 4 AD1 A2 5 A3 6 AD2 AD3 A4 7 A5 10 A6 11 A7 12 A8 13 A9 14 A10 15 A11 16 A12 17 A13 18 A14 19 A15 20 U6 PF0 PF1 PF2 PF3 AD4 PF4 AD5 PF5 AD6 PF6 AD7 PF7 41 A17 42 A18 43 A19 44 45 PC4_A 46 PC5_A 47 AMS0 48 AMS2 AD9 PG0 AD10 PG1 AD11 PG2 AD12 PG3 AD13 PG4 AD14 PG5 AD15 PG6 59 60 AOE 40 ~ABE1/SDQM1 PC1 PA0 PC2 PA1 PC3 PA2 PC4 PA3 PC5 PA4 PC6 PA5 PC7 PA6 CNTL1/~RD CNTL2 PB1 FLASH_TMS 72 FLASH_TCK 73 FLASH_TDI_A 74 FLASH_TDO_A 75 FLASH_TSTAT 4 76 FLASH_TERR 77 PE6_A 78 PE7_A PE0/TMS PB3 PE1/TCK PB4 PE2/TDI PB5 PE3/TDO PB6 PE4/TSTAT PB7 PD0 PD1 PD2 39 FLASH_RESET RESET PSD4256G6V-10UI TQFP80 PD3 AD1 D2 A2 5 34 D3 A3 6 AD2 AD3 35 D4 A4 7 36 D5 A5 10 37 D6 A6 11 38 D7 AD4 AD5 AD6 A7 12 A8 13 AD7 D8 A9 14 22 D9 A10 15 23 D10 A11 16 AD9 AD10 AD11 24 D11 A12 17 25 D12 A13 18 AD12 AD13 26 D13 A14 19 27 D14 A15 20 28 D15 51 55 56 57 58 LED1 62 LED2 63 LED3 64 LED4 65 LED5 66 LED6 68 79 80 1 2 A17 42 D1 PF1 33 D2 34 D3 PF2 PF3 35 D4 36 D5 37 D6 PF4 PF5 PF6 38 PF7 21 D8 22 D9 23 D10 PG0 PG1 PG2 24 D11 25 D12 PG3 PG4 26 D13 27 D14 28 D15 PG5 PG6 ADV7183_RESET PC4_B PPICLK_AD7183_SELECT PC5_B PPICLK_ONBOARD_SELECT AMS1 PA6_A AMS2 PC1 43 PC2 44 PC3 45 PC4 46 PC5 47 PC6 48 PC7 LED[6:1] AOE ~ABE1/SDQM1 FLASH_TMS FLASH_TCK FLASH_TDI_B PB6_A FLASH_TDO_B PB7_A FLASH_TSTAT PD0_A PE6_B PD1_A PE7_B R228 0.00 805 PD2_A AWE CNTL1/~RD 40 CNTL2 71 PE0/TMS 72 PE1/TCK 73 PE2/TDI 74 PE3/TDO 75 25 A4 26 A5 29 A6 30 A7 31 A8 32 A9 33 A10 34 A0 A1 DQ10 A11 DQ11 A12_NC DQ12 DQ13 BA0 DQ14 BA1 DQ15 16 SWE WE 17 SCAS CAS PA1_B 18 SRAS D5 11 D6 13 D7 42 D8 44 D9 45 D10 47 D11 48 D12 50 D13 51 D14 53 D15 DQ9 A10 PA0_B 10 DQ8 A9 21 D4 DQ7 A8 A19 8 DQ6 A7 20 D3 DQ5 A6 A18 D2 7 DQ4 A5 36 5 DQ3 A4 A13 D1 DQ2 A3 35 D0 4 DQ1 A2 A12 2 DQ0 22 RAS 3 19 CS 37 CKE 38 CLK SMS SCKE CLK_OUT PA2_B PA3_B 15 ~ABE0/SDQM0 DQML PA4_B 39 ~ABE1/SDQM1 DQMH PA5_B PA6_B MT48LC16M16A2TG-75 TSOP54 PA7_B PE4/TSTAT 61 PB0 62 PB1 63 PB2 64 PB3 65 PB4 66 PB5 67 PB6 68 PB7 PB0_B PB1_B PB2_B PB3_B PB4_B DNP = Do Not Populate PB5_B ANALOG DEVICES PB6_B PB7_B 76 PE5/~TERR 77 PE6 78 PE7 39 RESET PSD4256G6V-10UI TQFP80 B A3 SA10 79 PD0 80 PD1 PD3 2 20 Cotton Road Nashua, NH 03063 4 PH: 1-800-ANALOGD PD0_B PD1_B Approvals Date Title PD2_B AWE ADSP-BF533 EZ-KIT LITE - MEMORY Drawn Checked Engineering A 24 CNTL0/~WR 60 PD2 R231 0.00 805 23 A2 59 1 FLASH_B_RESET FLASH_RESET 51 PA0 52 PA1 53 PA2 54 PA3 55 PA4 56 PA5 57 PA6 58 PA7 A1 D7 PC0 PA7_A 61 67 AD15 41 A19 ADV7171_RESET 54 AD14 A16 A18 AD1898_RESET 53 D0 32 PG7 AD1836_RESET 52 31 PF0 AD8 21 FLASH_TERR PE7 4 33 PE5/~TERR PE6 AD0 A1 AWE PB0 3 ~ABE0/SDQM0 CNTL0/~WR PB2 71 D1 PC0 PA7 AWE D0 32 AD8 PG7 A16 31 U8 C Size Board No. C Date Rev A0167-2001 1.6 Sheet 2-13-2004_9:47 D 3 of 13 A B C D ADC2 ADC1 R31 33 805 U11 1 OE 1 DAC1 R32 10K 805 DAC2 DAC3 3.3V OUT LEFT (WHITE) 3 AD1836_CLK RIGHT (RED) 1 12.288MHZ OSC003 OUT (J4) R42 5.49K 1206 IN (J5) R48 11.0K 1206 3.3V C20 100PF 1206 R43 3.32K 1206 OUT1R- C18 330PF 805 6 U13 7 DAC1 RIGHT R33 10K 805 R230 0.00 805 R229 0.00 805 47 48 44 RFS0 43 RSCLK0 OUT1R+ 8 ASDATA1 OUT1L+ 45 AD1836_CLK OUT1L+ 9 ASDATA2 OUT1L- OUT1L- ABCLK OUT1R+ OUT1R+ 30 OUT1R- J4 3X2 CON024 CT3 10UF CAP002 51 SCK 2 MOSI 49 MISO 16 IN1L+ ADC1 LEFT IN1L- 17 18 IN1R+ ADC1 RIGHTIN1R- 19 9 R45 49.9K 1206 C17 2200PF 1206 DAC1 RIGHT 2 MCLK 6 PF4 C21 220PF 1206 AD1836_VREF 31 OUT2L+ 50 R47 2.74K 1206 DAC1 LEFT ALRCLK OUT1R- R106 10K 805 R46 604 1206 DAC1_RIGHT 7 2 R107 10K 805 AD8606AR SOIC8 R44 1.65K 1206 U14 DR0SEC R108 10K 805 C19 680PF 805 R49 5.49K 1206 AUDIO CODEC DR0PRI 5 OUT2L+ 7 CLATCH OUT2L- OUT2L- DAC2 LEFT CCLK AGND 33 CDATA OUT2R+ COUT OUT2R- IN1L+ OUT3L+ OUT2R+ 32 OUT2R- 4 OUT3L+ 5 IN1L- OUT3L- IN1R+ OUT3R+ OUT3L- 35 IN1R- OUT3R+ OUT3R- 34 OUT3R- DAC2 RIGHT DAC3 LEFT R35 5.49K 1206 R34 11.0K 1206 DAC3 RIGHT C15 100PF 1206 R36 3.32K 1206 OUT1L20 21 ADC2 LEFT 22 IN2L1 23 IN2L2 IN2L+/CL2/CL2 DSDATA1 38 IN2L-/CL1/CL1 DSDATA2 NC/IN2L1/IN2L+ DSDATA3 NC/IN2L2/IN2L- DLRCLK IN2R2 ADC2 RIGHT IN2R1 25 3 26 27 3 AD1836_RESET C13 330PF 805 DT0SEC 42 36 DAC1 LEFT TSCLK0 IN2R-/CR1/CR1 FILTD 12 C9 0.001UF 805 C10 0.001UF 805 AD8606AR SOIC8 R37 1.65K 1206 R39 604 1206 OUT1L+ J4 3X2 CON024 CT4 10UF CAP002 IN2R+/CR2/CR2 3 DAC1_LEFT 8 CT1 10UF B PD/RST C6 0.1UF 805 CT2 10UF B C8 0.1UF 805 R41 2.74K 1206 AD1836AAS MQFP52 C7 0.001UF 805 C14 680PF 805 R40 5.49K 1206 13 FILTR U13 3 R30 0.00 1206 NC/IN2R2/IN2RNC/IN2R1/IN2R+ 2 1 TFS0 37 DBCLK 24 DT0PRI 41 C16 220PF 1206 9 AD1836_VREF 3 C11 0.001UF 805 R38 49.9K 1206 C12 2200PF 1206 U12 1 AD1836_VREF AGND 2 AD8606AR SOIC8 R28 0.00 1206 R27 0.00 1206 AGND 5 U12 AGND 7 6 AD8606AR SOIC8 For test only R193 0.00 1206 SW1 ON 11 3 10 4 9 5 8 6 7 3 ADC2_LEFT 4 ADC2_RIGHT 12 2 2 ADC1_RIGHT 1 ADC1_LEFT 4 1 ANALOG DEVICES DAC1_LEFT DAC1_RIGHT 20 Cotton Road Nashua, NH 03063 4 PH: 1-800-ANALOGD DAC2_LEFT Approvals DAC2_RIGHT 5 DAC3_LEFT AGND 6 DAC3_RIGHT SWT017 DIP6 Checked B Date Title ADSP-BF533 EZ-KIT LITE - AUDIO CODEC Drawn Engineering A DNP = Do Not Populate R29 0.00 1206 C Size Board No. C Date Rev A0167-2001 1.6 Sheet 2-11-2004_14:35 D 4 of 13 A B C D 1 1 R67 5.49K 1206 R66 11.0K 1206 C35 100PF 1206 R59 5.49K 1206 R68 3.32K 1206 OUT2R- R58 11.0K 1206 C33 330PF 805 2 C28 330PF 805 3 R72 5.49K 1206 C34 680PF 805 AD8606AR SOIC8 R69 1.65K 1206 R60 3.32K 1206 OUT3R- U16 1 DAC2 RIGHT C30 100PF 1206 6 U15 7 DAC3 RIGHT R71 604 1206 5 J4 3X2 CON024 CT7 10UF CAP002 OUT2R+ DAC2_RIGHT R64 5.49K 1206 4 C29 680PF 805 AD8606AR SOIC8 R61 1.65K 1206 R63 604 1206 OUT3R+ R73 2.74K 1206 C36 220PF 1206 J4 3X2 CON024 CT6 10UF CAP002 6 AD1836_VREF DAC3_RIGHT 1 R70 49.9K 1206 C32 2200PF 1206 R65 2.74K 1206 2 C31 220PF 1206 3 R62 49.9K 1206 C27 2200PF 1206 AD1836_VREF 2 AGND AGND R75 5.49K 1206 R74 11.0K 1206 C40 100PF 1206 R51 5.49K 1206 R76 3.32K 1206 R50 11.0K 1206 OUT2L- R52 3.32K 1206 OUT3L- C38 330PF 805 6 U16 C23 330PF 805 7 3 C25 100PF 1206 DAC2 LEFT 2 U15 5 R80 5.49K 1206 C39 680PF 805 AD8606AR SOIC8 R77 1.65K 1206 R79 604 1206 OUT2L+ 3 J4 3X2 CON024 CT8 10UF CAP002 DAC2_LEFT 5 R81 2.74K 1206 C41 220PF 1206 3 1 DAC3 LEFT R56 5.49K 1206 C24 680PF 805 AD8606AR SOIC8 R53 1.65K 1206 R55 604 1206 OUT3L+ J4 3X2 CON024 CT5 10UF CAP002 DAC3_LEFT 2 6 R78 49.9K 1206 C37 2200PF 1206 AD1836_VREF R57 2.74K 1206 C26 220PF 1206 3 R54 49.9K 1206 C22 2200PF 1206 AD1836_VREF AGND AGND DNP = Do Not Populate ANALOG DEVICES 4 Approvals Date Title 20 Cotton Road Nashua, NH 03063 4 PH: 1-800-ANALOGD ADSP-BF533 EZ-KIT LITE - AUDIO OUT Drawn Checked Engineering A B C Size Board No. C Date Rev A0167-2001 1.6 Sheet 3-24-2003_13:34 D 5 of 13 A 1 J5 2X2 CON013 B CT12 10UF CAP002 FER3 600 1206 2 R91 5.76K 1206 C J5 2X2 CON013 R98 5.76K 1206 ADC1_LEFT C57 120PF 1206 C54 100PF 1206 2 CT10 10UF CAP002 FER1 600 1206 5 3 D R99 237 1206 U19 C45 120PF 1206 C46 100PF 1206 1 1 IN1L- AGND 3 AD8606AR SOIC8 C53 0.001UF 805 R101 5.76K 1206 C51 100PF 1206 R85 5.76K 1206 R84 5.76K 1206 ADC1 LEFT AGND 6 C50 0.001UF 805 R86 750K 1206 R97 237 1206 U19 AD1836_VREF U18 6 7 7 2 ADC2 LEFT C43 120PF 1206 C58 120PF 1206 R96 750K 1206 IN1L+ IN2L1 5 AD1836_VREF 5 IN2L2 3 AD1836_VREF AD8606AR SOIC8 R102 5.76K 1206 U18 2 AGND AGND AD1836_VREF 1 R87 5.76K 1206 ADC2_LEFT 6 AGND R105 5.76K 1206 2 AD8606AR SOIC8 AD8606AR SOIC8 AGND AGND J5 2X2 CON013 CT11 10UF CAP002 FER4 600 1206 1 R100 5.76K 1206 J5 2X2 CON013 R92 5.76K 1206 CT9 10UF CAP002 FER2 600 1206 4 R89 5.76K 1206 R88 5.76K 1206 ADC2_RIGHT ADC1_RIGHT 3 6 C59 120PF 1206 C56 100PF 1206 2 R95 237 1206 U20 AGND 2 1 AGND IN1R- AGND AD8606AR SOIC8 R104 5.76K 1206 C52 0.001UF 805 R103 5.76K 1206 AD8606AR SOIC8 3 R82 5.76K 1206 C48 100PF 1206 R83 5.76K 1206 AGND 6 C49 0.001UF 805 6 U17 7 7 AD1836_VREF R90 750K 1206 R93 237 1206 U20 ADC2 RIGHT C42 120PF 1206 ADC1 RIGHT C55 120PF 1206 R94 750K 1206 IN2R2 3 AD1836_VREF 3 3 U17 AGND 1 AD1836_VREF C44 120PF 1206 C47 100PF 1206 IN1R+ AD1836_VREF 5 IN2R1 5 AD8606AR SOIC8 AD8606AR SOIC8 AGND AGND DNP = Do Not Populate ANALOG DEVICES 4 Approvals Date Title 20 Cotton Road Nashua, NH 03063 4 PH: 1-800-ANALOGD ADSP-BF533 EZ-KIT LITE - AUDIO IN Drawn Checked Engineering A B C Size Board No. C Date Rev A0167-2001 1.6 Sheet 3-24-2003_13:34 D 6 of 13 A B PPICLK_ONBOARD_SELECT PPICLK_AD7183_SELECT 0 0 PPI_27MHZ_CLK (DEFAULT) 0 1 ADV7183_CLKOUT 1 X EXPANSION_CLK C PPCLK DAC B U25 U26 1 DAC D CVSB CVSB Component Video B R G Differential Component Video U V Y C Y R132 0.00 805 3 6 ADV7183_CLKOUT 1 DAC C Composite Video S Video 3 PPI_27MHZ_CLK D 1 PPI_CLK R125 1K 1206 6 4 PPICLK_AD7183_SELECT 1 4 ADG752BRT SOT23-6 A3V ADG752BRT SOT23-6 EXPANSION_PPI_CLK PPICLK_ONBOARD_SELECT U24 5 4 L5 0.68UH 805 L3 2.2UH 805 L4 0.68UH 805 1 3 3V_B VIDEO ENCODER TP4 R128 10K 805 C71 0.1UF 805 C69 330PF 805 C70 330PF 805 R124 75 1206 VIDEO_DAC_B 5 DAC B AD8061ART SOT23-5 2 R123 75 1206 J8 3X2 CON024 R127 75 1206 6 R126 1K 1206 R129 1.2K 1206 C72 0.1UF 805 U27 SW2 7 6 5 PF12 PF[15:12] PP[3:0] 4 PF13 3 PF14 2 PF15 42 PP3 41 PP2 40 PP1 39 PP0 38 44 ADV7171_27MHZ_CLK DAC_C P12 DAC_D 26 A3V 25 P9 VREF P8 RSET P5 FIELD/VSYNC P4 BLANK 3V_B ADV7171_RESET U23 15 3 24 PF1_SDATA 23 R130 PF0_SCLOCK 100K 1206 ADV7171_HSYNC 16 5 8 6 7 ADV7171_VSYNC L6 0.68UH 805 L2 2.2UH 805 L7 0.68UH 805 1 3 P3 1 P2 3V_B P1 R122 150 1206 D1 AD1580 SOT23D R121 75 1206 2 C67 330PF 805 C68 330PF 805 R120 75 1206 VIDEO_DAC_C 2 DAC C AD8061ART SOT23-5 2 3 R118 1K 1206 P0 CLOCK 11 VAA1 1 RESET 20 VAA3 AGND2 ALSB AGND2 30 28 VAA5 R131 1K 1206 SDATA SCLOCK 3 21 GND1 29 GND2 35 37 36 A3V 43 SCRESET/RTC GND3 TTX GND4 TTXREQ GND5 19 10 U22 R112 100K 1206 ADV7171KSU TQFP44 4 L8 0.68UH 805 L1 2.2UH 805 L9 0.68UH 805 1 2 R113 75 1206 C73 330PF 805 C74 330PF 805 J8 3X2 CON024 R116 75 1206 5 3 VIDEO_DAC_D 8 DAC D AD8061ART SOT23-5 9 R115 1K 1206 R114 75 1206 R182 0.00 1206 DNP = Do Not Populate AGND2 ANALOG DEVICES AGND2 R226 0.00 805 4 2 VIDEO_DAC_C J8 3X2 CON024 R117 75 1206 5 17 VAA4 18 9 34 4 HSYNC 4 VIDEO_DAC_B 33 P7 P6 10 VIDEO_DAC_D SWT017 DIP6 COMP VAA2 22 VIDEO_AVIN5 27 P11 P10 3 6 8 DAC_B P13 R119 1K 1206 5 9 P14 VIDEO_AVIN4 31 4 12 DAC_A 11 3 2 P15 12 2 2 13 32 1 AGND2 14 1 VIDEO_AVIN1 ON AGND2 PF1 PF1_SDATA R227 0.00 805 PF0 AGND2 Approvals Date Title PF0_SCLOCK 20 Cotton Road Nashua, NH 03063 4 PH: 1-800-ANALOGD ADSP-BF533 EZ-KIT LITE - VIDEO OUT Drawn Checked Engineering A B C Size Board No. C Date Rev A0167-2001 1.6 Sheet 2-3-2004_11:53 D 7 of 13 A B C D DAC_D DAC_B DAC_C 3.3V (WHITE) OUT 1 R142 10K 805 (RED) IN R143 10K 805 R139 10K 805 R138 10K 805 VIDEO DECODER 1 XTAL1 P15 P14 P13 68 PF0_SCLOCK Composite Video CVBS CVBS SDA P11 SCLK P10 CVBS P9 Differential Component Video Y U S Video Y C V 64 ADV7183_RESET 36 RESET P8 PWRDN P7 P6 J8 3X2 CON024 65 R141 0.00 805 7 AVIN1 C90 0.1UF 805 NC[ISO] P4 VIDEO_AVIN1 42 41 AIN1 P3 AIN7 P2 9 P1 TP7 J8 3X2 CON024 2 44 43 R136 0.00 805 4 AVIN4 P5 C88 0.1UF 805 AIN2 LLC1 TP6 46 45 AIN3 LLC2 AIN9 NC[LLCREF] 6 ELPF 58 J8 3X2 CON024 57 R135 0.00 805 1 AVIN5 C89 0.1UF 805 60 59 AIN10 AIN5 AIN11 3 62 61 CT16 10UF B R137 75 1206 R134 75 1206 HS 51 52 C81 0.1UF 805 AIN12 NC[CLKIN] REFOUT CML SFL[HFF] NC[AEF] NC[DV] 48 49 CT15 10UF B C78 0.1UF 805 C80 0.1UF 805 CAPY1 CAPY2 NC[RD] OE 54 55 CAPC1 NC[GPO3] CAPC2 NC[GPO2] NC[GPO1] C77 0.1UF 805 NC[GPO0] 50 A3V AVDD A5V DNP FER10 600 1206 CT14 10UF B C76 0.1UF 805 5 PP3 6 PP2 7 PP1 8 PP0 PP[3:0] R144 33 805 R183 33 805 U21 1 4 19 ADV7183_CLKOUT 2 SN74LVC1G32 SOT23-5 20 21 22 23 24 PVDD_ADV7183 32 33 27 C82 0.01UF 805 26 25 R140 1.5K 805 2 C83 82NF 805 37 2 ADV7183_HS 1 ADV7183_VS 80 ADV7183_FIELD 69 3.3V ADV7183_VREF 70 ADV7183_HREF 16 11 ADV7171_HSYNC R145 10K 805 12 ADV7183_HS 13 ADV7183_VS 78 ADV7171_VSYNC 77 ADV7183_FIELD 79 SW3 12 11 10 9 8 7 1 2 3 4 5 6 TMR1 TMR2 PF3 PF2 SWT017 DIP6 3 AGND2 PF15 AIN6 NC[AFF] C75 0.1UF 805 R133 75 1206 FIELD NC[VREF] NC[HREF] TP5 76 AIN4 VS VIDEO_AVIN5 PF14 AIN8 AGND2 VIDEO_AVIN4 P0 75 PF[15:12] 1 AVIN5 PF13 2 AVIN4 P12 74 3 67 PF1_SDATA AVIN1 ALSB PF12 4 66 73 5 28 XTAL 6 29 ADV7183_27MHZ_CLK ON AVIN1 AVIN4 AVIN5 U28 DVDD1 DVDD2 C79 0.1UF 805 DVDD3 38 PVDD DVDDIO1 DVDDIO2 39 40 FER12 600 1206 47 53 DNP FER11 600 1206 56 63 17 18 34 1.8V R232 10K 805 3.3V 3 35 FER8 600 1206 30 DVDD_ADV7183 10 DNP FER9 600 1206 72 4 15 AGND1 AGND2 DGND1 AGND3 DGND2 AGND4 DGND3 AGND5 DGND4 NC[AGND6] DGND5 3 9 14 31 71 PVDD_ADV7183 A1.8V ADV7183AKST LQFP80 FER13 600 1206 C84 0.1UF 805 C85 0.01UF 805 C86 0.1UF 805 C87 0.01UF 805 DNP = Do Not Populate ANALOG DEVICES 4 AGND2 Approvals Date Title 20 Cotton Road Nashua, NH 03063 4 PH: 1-800-ANALOGD ADSP-BF533 EZ-KIT LITE - VIDEO IN Drawn Checked Engineering A B C Size Board No. C Date Rev A0167-2001 1.6 Sheet 2-13-2004_12:39 D 8 of 13 A B C D 3.3V 3.3V R150 10K 805 PF8 R149 100 805 3 1 R157 0.00 1206 U10 3.3V SW4 SWT013 SPST-MOMENTARY 4 USB RESET LED3 RED-SMT LED001 74LVC14A SOIC14 CT17 1UF A 3.3V R159 10K 805 4 USB_CONFIGURED RESET LED2 RED-SMT LED001 RESET U9 1 MR 4 PFI 74LVC00AD SOIC14 RESET RESET 8 U31 7 2 1A1 4 1A2 6 1A3 8 1A4 LED1 ADM708SAR SOIC8 RESET LED2 LED3 R155 100 805 R167 0.00 1206 U10 11 LED4 SOFT_RESET 10 SW5 SWT013 SPST-MOMENTARY LED5 74LVC14A SOIC14 LED[6:1] R171 10K 805 U9 9 12 LED6 CT18 1UF A R172 10K 805 U9 U10 8 11 10 5 PFO R151 10K 805 R164 270 1206 USB_RESET 5 U29 SW8 SWT013 SPST-MOMENTARY R170 10K 805 6 R166 10K 805 3.3V 2 1 3.3V 3.3V R165 270 1206 PF9 3.3V 13 12 13 74LVC00AD SOIC14 74LVC00AD SOIC14 74LVC14A SOIC14 18 1Y1 16 1Y2 14 1Y3 12 5V 1Y4 11 2A1 13 2A2 15 2A3 17 2A4 9 2Y1 7 2Y2 5 2Y3 3 2Y4 1 OE1 19 OE2 LED9 AMBER-SMT LED001 LED8 AMBER-SMT LED001 LED7 AMBER-SMT LED001 LED6 AMBER-SMT LED001 LED5 AMBER-SMT LED001 POWER LED1 GREEN-SMT LED001 LED4 AMBER-SMT LED001 2 IDT74FCT3244APY SSOP20 R160 270 1206 3.3V R161 270 1206 R168 270 1206 R162 270 1206 R147 270 1206 R146 270 1206 R163 680 1206 R156 10K 805 PF10 R154 100 805 R148 0.00 1206 U10 9 SW6 SWT013 SPST-MOMENTARY 8 74LVC14A SOIC14 3.3V CT20 1UF A UART C92 0.1UF 805 C94 0.1UF 805 3.3V 11 TX T1IN 10 PF6 T2IN DNP R153 10K 805 U10 6 4 9 5 8 TFS0 RSCLK0 6 6 CT19 1UF A 10 5 74LVC14A SOIC14 3 4 5 SW7 SWT013 SPST-MOMENTARY 11 3 R158 0.00 1206 12 2 2 R152 100 805 ON 1 PF11 SW9 1 7 PF8 12 RX PF9 2 P2 PF11 FER17 600 603 14 T1OUT 1 7 T2OUT FER14 600 603 13 R169 0.00 805 PF10 6 2 7 C93 0.1UF 805 FER16 600 603 3 8 4 PF7 RFS0 3 FER15 600 603 6 V- R1OUT R1IN 9 8 R2OUT R2IN ADM3202ARN SOIC16 R111 0.00 805 2 IDC2X1 2X1 V+ 4 C2+ 5 C2- P5 1 C91 0.1UF 805 1 C1+ 3 C1- 3 R110 0.00 805 U30 9 DNP 5 TSCLK0 SWT017 DIP6 DB9M 9PIN DNP = Do Not Populate SW8 PB Enable Switch Position Function Connects the push buttons to the Programmable Flags of the DSP 1-4 Useful if using the PFs for another purpose. Connects SPORT0 frame sync and clock together external to the DSP 5,6 Required when AD1836 is in I2S mode 4 ANALOG DEVICES Approvals Date Title 20 Cotton Road Nashua, NH 03063 4 PH: 1-800-ANALOGD ADSP-BF533 EZ-KIT IO/RESET/UART Drawn Checked Engineering A B C Size Board No. C Date Rev A0167-2001 1.6 Sheet 2-3-2004_11:18 D 9 of 13 A B C D EXPANSION INTERFACE (TYPE B) 3.3V 5V 3.3V 5V 1 1 All USB interface circuitry is considered proprietary and has been omitted from this schematic. D[0:15] PF[0:15] J1 2 A1 1 4 3 6 5 J2 2 1 4 3 6 A3 8 7 A2 A5 10 9 A4 A7 12 11 A6 MOSI A9 14 13 A8 MISO A11 16 15 8 7 9 12 18 17 A12 A15 20 19 A14 A19 22 21 24 23 26 25 28 30 2 14 13 PA5_B 16 15 PA7_B 17 PA7_A D1 D3 TMR2 27 TMR0 29 DT1SEC 34 33 TFS1 36 35 TSCLK1 DT0SEC 37 40 39 42 41 DT0PRI D0 D2 TFS0 TSCLK0 D5 44 43 D4 D7 46 45 D6 PF14 D9 48 47 50 49 D10 D13 52 51 D12 54 53 56 55 58 PP0 PP2 19 22 21 24 23 PB7_A 26 25 28 27 30 29 32 31 34 33 36 35 38 37 40 39 42 41 44 43 TMR1 RESET DR1SEC RESET DR1PRI ADV7183_HS RFS1 ADV7183_FIELD DSCLK1 ADV7183_HREF DR0SEC 59 62 61 46 45 PF13 PF10 48 47 PF11 PF8 50 49 PF9 PF6 52 51 PF7 64 63 66 65 ~ABE1/SDQM1 PF4 54 53 PF5 PF2 56 55 PF3 PF0 58 57 PF1 60 59 68 67 ~ABE0/SDQM0 70 69 AOE 72 71 74 73 76 75 78 AWE EXPANSION_PPI_CLK 64 63 66 67 70 69 72 PP1 SMS PP3 65 68 79 82 81 ~ABE0/SDQM0 84 83 SRAS 86 85 SA10 90 7 10 9 12 11 14 13 16 15 18 17 20 19 22 21 24 23 26 25 28 27 30 29 32 34 33 36 35 38 SWE RX R173 10K 805 PA0_B PA2_B DSP JTAG HEADER PA4_B PA6_B PA6_A EMULATOR_SELECT PB6_A 31 73 76 75 78 77 80 79 82 81 84 83 86 85 88 87 90 89 2 3 4 5 6 CLK_OUT_EXP1 7 8 EXT_DSP_CLK 9 10 ADV7183_VS 11 12 ADV7183_VREF 13 14 EMULATOR_EMU EMULATOR_TMS 41 RSCLK0 44 43 46 45 48 47 50 49 52 51 54 53 56 55 58 57 2 EMULATOR_TCK EMULATOR_TRST EMULATOR_TDI EMULATOR_TDO IDC7X2 7X2 60 59 AMS3 62 61 AMS2 64 63 AMS1 66 65 AMS0 68 67 ARDY 70 69 72 71 74 73 76 75 SPORT0 R174 0.00 1206 P3 DT0PRI DT0SEC TFS0 71 74 P4 1 37 39 ARE ~ABE1/SDQM1 TSCLK0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 3 RSCLK0 77 80 79 82 81 SCKE 84 83 SCAS 86 85 88 87 90 89 CLK_OUT_EXP2 89 45X2 CON019 8 78 80 87 5 42 77 88 3 6 40 D14 61 4 PF15 PF12 62 1 RFS0 57 60 J3 2 DR0PRI D8 D11 D15 20 NMI A18 DT1PRI 38 PA3_B 11 A16 31 32 PA1_B SCK A10 A13 A17 TX 5 10 18 3 When designing your JTAG interface please refer to the Engineer to Engineer Note EE-68 which can be found at http://www.analog.com 3.3V A[1:19] BR BG RFS0 R175 0.00 1206 DR0SEC DR0PRI CON014 10X2 BGH 45X2 CON019 45X2 CON019 DNP = Do Not Populate ANALOG DEVICES 4 Approvals Date Title 20 Cotton Road Nashua, NH 03063 4 PH: 1-800-ANALOGD ADSP-BF533 EZ-KIT LITE - CONNECTOR Drawn Checked Engineering A B C Size Board No. C Date Rev A0167-2001 1.6 Sheet 2-12-2004_15:37 D 10 of 13 A B C 5V F1 2.5A FUS001 1 FER23 CHOKE_COIL 4 3 1 2 D2 2A DO-214AA UNREG_IN 3 INPUT 2 UNREG_IN GND 1 ADP3339AKC-5 SOT-223 1 2 FER18 600 1206 OUTPUT J9 D3 2A DO-214AA C97 1000PF 1206 A5V R177 0.00 1206 VR5 D R176 100K 1206 CT22 10UF C 3V_B R178 0.00 1206 VR1 C98 0.1UF 805 CT23 10UF C C175 0.1UF 805 3 INPUT FER19 600 1206 2 OUTPUT GND 1 ADP3338AKC-33 SOT-223 3 7.5V_POWER CON005 2.5MM_JACK C104 1UF 805 C96 1000PF 1206 1 A3V CT21 10UF C C143 0.1UF 805 R186 0.00 805 VDDRTC R187 0.00 805 DSP_VDD_EXT SHGND DSP_VDD_EXT R223 3.32K 805 D4 2A DO-214AA DSP_VDD_INT 2 2 TP15 UNREG_IN R188 0.00 805 VR3 3 INPUT OUTPUT U32 2 1 R222 0.00 805 DSP_VDD_INT 5 SJ1 GND 1 ADP3339AKC-33 SOT-223 CT25 10UF C L12 10UH IND001 C100 0.1UF 805 CT24 10UF C VROUT 2 6 3 7 4 8 3 1 NDS8434A SO-8 SHORTING JUMPER DEFAULT=2 & 3 CT28 68UF D D5 ZHCS1000 SOT23D 1A SW10: Core Voltage Source Select DEFAULT: 2 & 3 JP3 1 C105 0.1UF 805 2 Position Function 1 and 2 DSP_VDD_INT = DSP Internal Voltage Regulation 2 and 3 DSP_VDD_INT = 1.4V Fixed 3 IDC3X1 3X1 3.3V R211 0.00 805 UNREG_IN R189 0.00 805 VR4 3 INPUT 3 OUTPUT VR6 7 IN1 8 IN2 R214 10K 805 2 1V4 2 DNP OUT2 3 OUT3 GND 1 ADP3339AKC-33 SOT-223 CT27 10UF C 1 OUT1 6 SD C101 0.1UF 805 CT26 10UF C 5 FB GND 4 ADP3336ARM MSOP8 Note: For boards without a 750MHz processor this jumper will not be populated and the DSP_VDD_INT will be hard-wired with R222 to use the processor internal regulator. R210 0.00 805 C60 1UF 805 R184 64.9K 805 3 3.3V C61 1UF 805 3.3V 1.8V A1.8V CT13 10UF C FER20 1206 VR2 R185 340K 805 7 R192 10K 805 IN1 8 IN2 6 SD 1 OUT1 2 OUT2 3 OUT3 5 FB GND 4 ADP3336ARM MSOP8 C102 1UF 805 R190 76.8K 1206 C103 1UF 805 R191 147K 1206 FER21 600 1206 MH2 MH1 MH3 MH4 DNP = Do Not Populate MH5 TP12 TP14 TP13 TP11 TP8 TP9 ANALOG DEVICES TP10 4 FER22 600 1206 SHGND Approvals Date Title 20 Cotton Road Nashua, NH 03063 4 PH: 1-800-ANALOGD ADSP-BF533 EZ-KIT LITE - POWER Drawn Checked SHGND SHGND A B Engineering C Size Board No. C Date Rev A0167-2001 1.6 Sheet 2-19-2004_13:19 D 11 of 13 A B C D DSP_VDD_EXT DSP_VDD_INT BBBYP RES IN PLACE OF C188 C181 0.01UF 805 C183 0.01UF 805 C184 0.1UF 805 C182 0.1UF 805 C185 0.1UF 805 C180 0.1UF 805 C199 10UF 1210 C200 10UF 1210 C198 10UF 1210 C190 0.01UF 805 C188 0.01UF 805 C187 0.1UF 805 C189 0.1UF 805 C186 0.1UF 805 C191 0.1UF 805 C196 0.01UF 805 C194 0.01UF 805 C193 0.1UF 805 C195 0.1UF 805 C192 0.1UF 805 C197 0.1UF 805 DNP R194 0.00 805 C179 0.1UF 805 1 1 ADSP-21533 U1 3.3V C159 0.01UF 805 3.3V C153 0.01UF 805 C155 0.01UF 805 C154 0.01UF 805 C150 0.01UF 805 IDT74FCT3807 U4 3.3V C149 0.01UF 805 C136 0.01UF 805 C126 0.01UF 805 PSD4265 A U5 3.3V C127 0.01UF 805 3.3V C124 0.01UF 805 PSD4265 B U6 C169 0.01UF 805 C123 0.01UF 805 C174 0.01UF 805 C173 0.01UF 805 SN74LVC1G125 U7 3.3V C166 0.01UF 805 C168 0.01UF 805 C167 0.01UF 805 C201 0.01UF 805 3.3V C208 0.01UF 805 SDRAM U8 74LVC00AD U9 A5V C151 0.01UF 805 74LVC14A U10 A5V C130 0.22UF 805 C138 0.22UF 805 AGND AGND AD8606 U12 AD8606 U13 2 2 3.3V 5V C165 0.01UF 805 A5V C177 0.1UF 805 C99 0.1UF 805 A5V C176 0.1UF 805 C178 0.1UF 805 C129 0.22UF 805 AGND AD1836 U14 A5V A5V C137 0.22UF 805 A5V C139 0.22UF 805 A5V C141 0.22UF 805 A5V C140 0.22UF 805 3.3V C142 0.22UF 805 AGND AGND AGND AGND AGND AGND AD8606 U15 AD8606 U16 AD8606 U17 AD8606 U18 AD8606 U19 AD8606 U20 3V_B 3.3V 3.3V A3V C210 0.1UF 805 C110 0.1UF 805 SN74AHC1G08 U21 3.3V A3V C108 0.01UF 805 C111 0.1UF 805 A3V C112 0.01UF 805 C109 0.1UF 805 AGND2 AGND2 AGND2 AD8061 U22 AD8061 U23 AD8061 U24 3.3V 3.3V C113 0.01UF 805 3.3V C172 0.01UF 805 C171 0.01UF 805 ADG752 U25 ADG752 U26 3.3V DVDD_ADV7183 3 3 C146 0.01UF 805 C147 0.01UF 805 C145 0.1UF 805 ADV7171 U27 C148 0.1UF 805 C144 0.1UF 805 C95 0.1UF 805 C119 0.1UF 805 C132 0.1UF 805 C128 0.01UF 805 C204 0.01UF 805 C156 0.1UF 805 C157 0.1UF 805 C158 0.1UF 805 C152 0.01UF 805 ADM708SAR U29 ADV7183 U28 C163 0.01UF 805 ADM3202 U30 C161 0.01UF 805 IDT74FCT3244APY U31 C209 0.1UF 805 IDT2305 U46 DNP = Do Not Populate ANALOG DEVICES 4 Approvals Date Title 20 Cotton Road Nashua, NH 03063 4 PH: 1-800-ANALOGD ADSP-BF533 EZ-KIT LITE - BYPASS CAPS Drawn Checked Engineering A B C Size Board No. C Date Rev A0167-2001 1.6 Sheet 2-2-2004_19:17 D 12 of 13 I INDEX Symbols ~AMS0, memory select pin, 2-3, 2-6, 3-3 ~AMS1, memory select pin, 2-3, 2-6, 3-3 ~AMS2, memory select pin, 2-3, 2-6, 3-3 ~SMS0, memory select pin, 2-2, 3-3 peripheral ports, -xiv real time clock (RTC), 3-3 ADV7171, video encoder, 2-12, 3-6, 3-7, 3-11 ADV7183, video decoder, 2-12, 3-6, 3-7, 3-11 ASYNC, memory banks 0-3, 2-3 audio applications, -xiv codec, 2-11 A connectors (J4, J5), 3-17 AD1836, 2-11, 3-4, 3-12 interface, see SPORT0 Add New Hardware Wizard, Windows see also AD1836 98, 1-8 ADSP-BF533 processor address space, 2-6 audio interface, see SPORT0 Clock In (CLK IN), 3-7 Clock Out (CLK OUT), 3-3 core voltage, 3-2 External Bus Interface Unit (EBIU), 3-3 input clock, 3-3 internal memory restrictions, 2-2 internal SRAM, 2-2 IO voltage, 3-2 memory map, 2-2 parallel peripheral interface (PPI), 3-5 B background telemetry channel (BTC), 2-13 bill of materials, A-1 boot load, 2-16 mode select (JP1-2), 3-10 breakpoints, restrictions, 2-19 C clock frequency, 2-4, 2-5 codecs, 3-4 configuration registers (IO), 2-6 ADSP-BF533 EZ-KIT Lite Evaluation System Manual I-1 INDEX connecting, EZ-KIT Lite board, 1-5 connectors, 1-5, 3-16 extender connectors (P3-1), 3-3 FlashLINK (P1), 3-18 J1 (expansion interface), 3-8 J10 (USB), 1-6 J2 (expansion interface), 3-8 J3 (expansion interface), 3-8 J4 (audio), 3-17 J5 (audio), 3-17 J8 (video), 3-17 J9 (power), 3-17 P4 (JTAG), 3-9, 3-20 P9 (SPORT0), 3-19 RS232 (P2), 3-19 see also expansion interface contents, EZ-KIT Lite package, 1-1 conventions, manual, -xxii core frequency, 2-5 voltage, 3-10 customer support, -xvi D Device Manager window, 1-16 DIP switches, 3-9 see SW dual bank Flash memory, 2-3 E EBIU_SDBCTL, 2-4 EBIU_SDGCTL, 2-4 EBIU_SDRRC, 2-4 electrostatic discharge, 1-2 I-2 emulation events, 2-16 example programs, 2-13 exceptions, 2-16 expansion board, 2-8 interface, 3-4, 3-8, 3-16 extender connectors (P3-1), 3-3 external bus interface unit (EBIU), 3-3 flash memory, see flash memory regulator, 3-2, 3-10 external memory, 3-9 bank 0 (primary A), 2-3 bank 0 (SDRAM), 2-3 EZ-KIT Lite board architecture, 3-2 features, -xii F features, EZ-KIT Lite board, -xii flag pins, see programmable flags (PFs) flash A, 2-7 configuration registers, 2-8 port A controls, 2-8 port B controls, 2-9 primary, 2-7 registers, 2-7 secondary, 2-7 SRAM, 2-7 flash B, 2-7 configuration registers, 2-8 primary, 2-7 registers, 2-7 secondary, 2-7 ADSP-BF533 EZ-KIT Lite Evaluation System Manual INDEX SRAM, 2-7 flash memory, -xiii, 2-5, 3-3, 3-10 configuring, 2-9 general-purpose IO pins (U5), 3-15 map, 2-6 modifying, PSDsoft Express, 2-9 primary, 2-3, 3-3 programming, FlashLINK, 2-9 reserved, 2-7 secondary, 3-3 flash ports, PB0-5, 3-15 Found New Hardware Wizard Windows 2000, 1-14 frequency, 2-4, 2-5 G general-purpose IO, 2-10, 2-11 graphical user interface (GUI), 2-13 H hard reset, 2-16 Help, online, -xx HSYNC signal, 3-6, 3-7, 3-11 I I2S mode, 2-11 installation, summary, 1-3 installing EZ-KIT Lite USB driver, 1-7 VisualDSP++ and EZ-KIT Lite license, 1-5 VisualDSP++ and EZ-KIT Lite software, 1-4 interfaces SDRAM, 2-4 see graphical user interface (GUI) internal regulator, 3-2 internal memory, 2-3, 3-9 core MMRs, 2-3 data bank A SRAM, 2-3 data bank B SRAM, 2-3 instruction SRAM, 2-3 instruction SRAM/CACHE, 2-3 reserved, 2-3 scratch pad SRAM, 2-3 system MMRs, 2-3 IO configuration registers, 2-6 signals, 2-7 voltage, 3-2 IO port registers, 2-7 Data In, 2-7 Data Out, 2-8 Direction, 2-7 J JTAG connector (P4), 3-20 emulation port, 3-9 programming cable, 2-10 jumpers, 1-5, 3-9 JP1-2 (boot mode select), 3-10 JP3 (core voltage source select), 3-10 L LEDs, 1-5, 2-10, 3-13 LED1, 1-6, 3-14 ADSP-BF533 EZ-KIT Lite Evaluation System Manual I-3 INDEX LED11, 1-15, 1-16, 3-15 LED2-3, 1-6, 3-14 LED4-9, 2-9, 3-15 license restrictions, 2-2 PPI0-7, 3-6 TMR1-2, 3-6 processor memory map, see ADSP-BF533 processor programmable flags (PFs), 3-4, 3-5 PF0, 2-12, 3-4 M PF1, 2-12 memory, 2-4 PF10-11, 3-5, 3-12, 3-14 flash configuration, 2-6 PF12-15, 3-5, 3-6 SDRAM configuration, 2-4 PF2, 2-12, 3-4, 3-11 select pins, see ~AMS0, ~AMS1, PF3, 3-4 ~AMS2, ~SMS0 PF4, 2-11, 3-4 memory map, see ADSP-BF533 PF5-7, 3-5 processor PF8-11, 2-10, 3-5, 3-12, 3-14 PF9, 3-5, 3-12, 3-14 P push buttons, see also push buttons P3, SPORT connector, 3-4 push buttons, 2-10, 3-13 package contents, 1-1 connecting to PF pins, 3-13 Parallel Peripheral Interface (PPI), -xiv, SW4-7 (general input), 3-5, 3-12, 2-12, 3-5 3-14 PC SW8 (reset), 3-14 configuration, 1-3 SW9 (enable), 2-11, 3-12, 3-13 parallel port, 2-10 Performance Monitor Control dialog R box, 2-15 registering, this product, 1-2, 1-5 PFs, see programmable flags regulators, 3-2, 3-10 power reset connector (J9), 3-17 board, 2-16 specifications, 3-18 options, 2-17 supply, 3-18 processor, 3-14 PPI interface, 2-12, 3-7 push button (SW8), 3-14 primary flash memory, 2-6 service routines, 2-14 primary processor pins RFS0, signal, 3-12 PF3, 3-6 RSCLK0 PPI_CLK, 3-6 I-4 ADSP-BF533 EZ-KIT Lite Evaluation System Manual INDEX register, 2-11 signals, 3-12 TMR1-2, primary processor pins, 3-6 trace buffer, 2-14 destination, 2-15 S instruction addresses, 2-15 SCLK, 2-4, 2-5 number, 2-15 SDRAM, -xiii, 2-2, 2-3, 2-4, 2-5, 3-3 source, 2-15 secondary flash memory, 2-6 trace window, 2-14, 2-15 serial TSCLK0 clock (SCL), 2-4, 2-12 register, 2-11 data (SDAT), 2-12 Serial Peripheral Interconnect (SPI), 3-4 signal, 3-12 setting U EZ-KIT Lite hardware, 1-5 target options, 2-17 UART port, 3-8 software breakpoints, 2-19 Universal Asynchronous Receiver SPI port, 2-11 Transmitter (UART), -xiii, -xiv SPORT0, -xiv, 2-11, 3-4, 3-12, 3-19 USB SRAM, 2-3, 2-6, 3-3 cable, 1-2 starting VisualDSP++, 1-16 connector (P7), 3-18, 3-19 SW1-2, test DIP switches, 3-11 driver installation, Windows 2000, SW3, DIP switch, 2-12, 3-7, 3-9, 3-11 1-12 system driver installation, Windows 98, 1-8 architecture, EZ-KIT Lite board, 3-2 driver installation, Windows XP, 1-13 clock, 2-4 interface, 3-9 requirements, PC, 1-3 interface chip (U34), 3-14 monitor LED (LED11), 3-15 user LEDs (LED9-4), 3-15 T see also LEDs target options dialog box, 2-17 V miscellaneous, 2-18 on emulator exit, 2-17 verifying USB driver installation, 1-15 reset, 2-17 video, 2-12 test DIP switches (SW1-2), 3-11 configuration switch (SW3), 3-11 TFS0 signal, 3-12 connector (J8), 3-17 ADSP-BF533 EZ-KIT Lite Evaluation System Manual I-5 INDEX decoder, -xiv encoder, -xiv input mode, 3-7 interface, 2-12 output mode, 3-7 VisualDSP++ documentation, -xx I-6 installation, 1-4 license, 1-5 online Help, -xx requirements, 1-3 starting, 1-16 voltage regulators, 3-2 VSYNC signal, 3-6, 3-7, 3-11 ADSP-BF533 EZ-KIT Lite Evaluation System Manual