Smart Quad Channel Low-Side Switch TLE 5216 G SPT-IC Features • • • • • • Overload protection Short circuit protection Cascadeable serial diagnostic interface Overvoltage protection µC compatible input Electrostatic discharge (ESD) protection P-DSO-20-10 Type ▼ TLE 5216 G Ordering Code Package Q67006-A9206 P-DSO-20-10 ▼ New Type Application • All kinds of resistive and inductive loads (relays, electromagnetic valves) • µC compatible power switch for 12 V applications • Solenoid control switch in automotive and industrial control systems Semiconductor Group 1 1998-06-22 TLE 5216 G General Description Quad channel Low-Side Switch in Smart Power Technology (SPT) with four separate LOW active inputs and four open drain DMOS output stages. The TLE 5216G is protected by embedded protection functions and designed for automotive and industrial applications. Product Summary Parameter Symbol Values Unit Supply voltage VS VDS(AZ)max 6 … 30 V 75 V RON(typ) ID 0.35 Ω 4×2 A Drain source clamping voltage (OUT1 - OUT4) ON resistance Output current Pin Configuration (top view) P-DSO-20-10 GND N.C. IN1 IN2 OUT1 VS OUT2 SEROUT CLK GND 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 GND N.C. IN4 IN3 OUT4 RESET OUT3 SERIN CS GND AEP01617 Figure 1 Semiconductor Group 2 1998-06-22 TLE 5216 G Pin Definitions and Functions Pin No. Symbol Function 3 IN1 Input switch 1; active LOW; internal pull-up 4 IN2 Input switch 2; active LOW; internal pull-up 5 OUT1 Output switch 1; overload and shorted load protected 6 VS Supply voltage 7 OUT2 Output switch 2; overload and shorted load protected 8 SEROUT Data-out of serial diagnostic interface; open drain 9 CLK Clock for serial diagnostic interface 1, 10, 11, 20 GND Ground 12 CS Chip select for serial diagnostic interface; internal pull-up 13 SERIN Data-in of serial diagnostic interface; internal pull-up 14 OUT3 Output switch 3; overload and shorted load protected 15 RESET Reset; active LOW; shuts down all outputs and resets the error flags 16 OUT4 Output switch 4; overload and shorted load protected 17 IN3 Input switch 3; active LOW; internal pull-up 18 IN4 Input switch 4; active LOW; internal pull-up 2, 19 N.C. Not connected Semiconductor Group 3 1998-06-22 TLE 5216 G V BB VS RESET GND TLE 5216 G V Internal Overload OUT1 Open Load IN1 Logic Channel 1 Short to GND Clamp Regulator dv/dt Circuit Current Limit IN2 IN3 OUT2 Logic, Protection- and Power-Circuit of Channel 2-4 (equivalent to Channel 1) OUT3 OUT4 IN4 Logic Channel 1-4 SERIN Serial Diagnostic Interface CS CLK SEROUT AES02013 Figure 2 Block Diagram Semiconductor Group 4 1998-06-22 TLE 5216 G Application Description This IC is specially designed to drive inductive loads up to 2 A nominal current (valves, relays, etc.). Integrated clamp-diodes limit the output voltage when inductive loads are turned off. For the detection of errors at the load there is a serial diagnostic interface, which monitors the following errors for every output separately: – open load in inactive mode – shorted output (shorted to ground) in inactive mode – overload or shorted load in active mode Circuit Description The block diagram shows the four independent power drivers with the referring logic block and the serial diagnostic interface which stores and transfers the diagnostic signals to the external circuit. Each power switch connects a high side load to ground when a LOW signal applies at the inputs. To protect the IC against short circuit and over load each output is provided with a current limitation and a delayed overload shutdown. The slew rate of the switching process is limited internally. The integrated clamp diodes limit the voltage at the output to VDS(AZ), when inductive loads are switched off. The maximum power dissipation, which is given from the static and dynamic thermal resistance, limits the allowable inductive energy. A diode in parallel to every output clamps negative voltage. All outputs, preferably the outputs 1 and 2 and the outputs 3 and 4 may be used in parallel (no addition of max. freewheeling energy). A curve of the output voltage is shown in figure 6. The diagnostic block monitors the voltages across the power switch. If in active mode (LOW level input) there is a higher voltage than VDS(OV) for a time longer than tVDS(OV), the diagnostic block will show an overload in the error register and the affected power switch will be shut off. The switch can only be reactivated if the corresponding input is switched off and then on again. In inactive mode (HIGH level at input) open load or shorted output (shorted load to ground) is detected and signalled to the serial diagnostic interface. If the voltage across the power switch is lower than VDS(OL) for the time tVDS(OL) (min. 50 µs) open load is identified. If the voltage is even lower than VDS(SH) for the time tVDS(SH) (min. 30 µs) "shorted to ground" is detected. An internal voltage divider will pull the output to the voltage VDS if there is an open load. A new error on the same output stage will over-write the old error report. The protocol of the serial diagnostic interface includes independent error reports for each output driver. As soon as an error is latched into the error register the serial data output (SEROUT) of the interface will go LOW (while CS is still HIGH). If the chip select gets a LOW signal Semiconductor Group 5 1998-06-22 TLE 5216 G (CS = L), all error reports can be shifted out serially. The rising edge of the CS will reset all error registers. The function of the serial diagnostic interface is shown in figure 7. The data input (SERIN) allows several TLE 5216 G or other serial diagnostic interfaces to be cascaded. A LOW signal on the reset pin (RESET) or a supply voltage lower than the operating range (4.5 V) will erase the error register and disable all four power switches. Absolute Maximum Ratings Tj = – 40 °C to 150 °C Parameter Symbol Supply voltage VS VIN VSEROUT Tj TStg ID(AZ) ID(AZ) IGND IGND Input voltages IN1 … IN4, SERIN, CLK, CS, RESET Status output voltage Data OUT (SEROUT) Operating temperature range Storage temperature range Output current per channel Ground pin current Tj = 25 °C Tj = 125 °C Tj = 25 °C Tj = 125 °C Values Unit – 2 … 40 V – 0.3 … 7 V – 0.3 … 10 V – 40 … 150 °C – 50 … 150 °C – 3.8 … 3.8 A – 2.95 … 2.95 A – 10 … 10 –8…8 A A Thermal resistance (junction-case static) See diagrams P-DSO-20-10 RthJC 5 K/W Transient thermal impendance tp = 100 µs; square pulse ZthJC tp = 100 µs; triangle pulse ZthJC 0.5 0.2 K/W K/W Note: Maximum ratings are absolute ratings; exceeding only one of these values may cause irreversible damage to the integrated circuit. Semiconductor Group 6 1998-06-22 TLE 5216 G Operating Range Parameter Symbol VS Supply voltage Limit Values min. max. 6 30 Unit V Supply voltage outputs switchable; no diagnostic VS Input LOW voltage Input HIGH voltage Clock input HIGH voltage Inverse current at output VS > 6 V VS > 6 V VS > 6 V VS > 6 V 4.5 V VINL VINH VCLKH ID – 0.3 1 V 2 6 V 2.4 6 V Tj fCLK tCLKH, tCLKL tCSH, tCSL tCSC – 40 150 °C 0 500 kHz – 0.3 A 1) isolated cooling fin Junction temperature Clock frequency Clock pulse width CS pulse width Setup time CS to CLK 1) VS > 6 V VS > 6 V VS > 6 V VS > 6 V 400 ns 2 µs 2 µs If inverse current occurs at output 2 or 3, then provide external pull-up resistor 5.6 kΩ to + 5 V at input DIN. Note: In the operating range the functions given in the circuit description are fulfilled. Semiconductor Group 7 1998-06-22 TLE 5216 G Electrical Characteristics VS = 6 V to 18 V; Tj = – 40 °C to 150 °C (unless otherwise specified) Parameter Symbol Limit Values min. Unit typ. max. 3.5 8 8 15 0.35 0.55 0.4 Ω 0.63 Ω 70 75 Power Supply (VS) Outputs ON IS Outputs OFF IS Supply current mA mA Power Outputs ON state resistance Tj = 25 °C; ID = 2 A; all VDS > 0 V RDS(ON) Tj = 125 °C; ID = 1.5 A; t > 100 µs RDS(ON) Clamping voltage (OUT1 - OUT4) ID = 1 A; 0 < Tj < 125 °C; all VDS > 0 V VDS(AZ) 65 Negative clamping voltage Tj = 25 °C; ID = – 0.3 A VDS(AZ) –1 Current limitation Tj = 0 °C; VDS = VDS (OV) ID(lim) Tj = 25 °C; VDS = VDS (OV) ID(lim) Tj = 125 °C; VDS = VDS (OV) ID(lim) 3.0 2.8 2.25 Leakage current VS = 0 V; VDS = 12 V; all VDS > 0 V IR V – 0.5 V 3.6 3.3 2.6 4.2 A 3.8 A 2.95 A 0.2 0.5 mA Digital Inputs Inputs IN1 … IN4, CS, SERIN Input LOW current Input HIGH current Input hysteresis 0 V < VIN < 2 V IINL – 200 – 100 – 50 µA VIN = 5 V IINH VINHys – 20 0 0.5 0.6 0 V < VINCLK < 5 V IINCLK – 20 2 0.5 0.7 5 µA V Input Clock (CLK) Input current VINCLKHys Input hysteresis Semiconductor Group 8 5 µA V 1998-06-22 TLE 5216 G Electrical Characteristics (cont’d) VS = 6 V to 18 V; Tj = – 40 °C to 150 °C (unless otherwise specified) Parameter Symbol Limit Values Unit min. typ. max. – 25 – 10 –5 0.5 0.6 Input Reset Input current 0 V < VINR < 2 V IINR VINRHys Input hysteresis µA V Input Currents in Case of Inverse Current at Output Σ ID = – 0.3 A; VS = 0 V; 0 V < VIN < 5 V IIN IIN IIN Inputs CLK, SEROUT, CS, SERIN Inputs IN1 … IN4 Input RESET 200 µA 100 µA 25 µA Timings Data valid SEROUT after CLK no 100 % testing tDDA RL = 12 Ω tDON Output OFF delay RL = 12 Ω tDOFF Difference of delays RL = 12 Ω tDON – tDOFF Output slew rate falling CL = 1 nF; 10 V → 2 V Sf Output slew rate rising ID = 1 A; 5 V → 55 V Sr Output ON delay 0 150 400 ns 0 1.4 10 µs 0 2.4 10 µs –3 –1 3 µs – 15 –8 –5 V/µs 10 14 20 V/µs 5 µA 0.5 V Diagnostic Output (SEROUT) Output leakage current Output LOW voltage Semiconductor Group VSEROUT = 5 V ISEROUTH 0 V < ISEROUT < 1.6 mA VSEROUTL 9 0 0 0.2 1998-06-22 TLE 5216 G Electrical Characteristics (cont’d) VS = 6 V to 18 V; Tj = – 40 °C to 150 °C (unless otherwise specified) Parameter Symbol Limit Values Unit min. typ. max. Output ON VDS(OV) 1.5 2 2.5 V VS = 12 V; VBB = 12 V tVDS(OV) 30 80 200 µs 3.3 6.7 3.8 7.7 4.3 8.7 V V Differential open load output resistance outputs OFF RD 5 15 40 kΩ Open load threshold VS = 6.5 V; outputs OFF VDS(OL) VS = 12.5 V VDS(OL) 4.3 9.3 4.7 10.2 5.2 11 V V VS = 12 V tVDS(OL) 50 130 250 µs Shorted to ground threshold VS = 6.5 V; outputs OFF VDS(SH) VS = 12.5 V VDS(SH) 2.4 4.5 2.8 5.4 3.3 6.3 V V VS = 12 V tVDS(SH) 30 80 200 µs Diagnostic Functions Overload threshold Overload delay Open load output voltage VS = 6.5 V; outputs OFF VDS VS = 12.5 V VDS Open load delay Shorted to ground delay Note: The listed characteristics are ensured over the operating range of the integrated circuit. Typical characteristics specify mean values expected over the production spread. If not otherwise specified, typical characteristics apply at TA = 25 °C and the given supply voltage. Semiconductor Group 10 1998-06-22 TLE 5216 G Test Circuits VBB 100 µ F VS = Load VS IN 1 OUT1 IN 2 OUT2 + TLE 5216 G IN 3 OUT3 IN 4 V INH = OUT4 RESET SERIN CS Ι D1 Ι D2 Ι D3 Ι D4 CLK SEROUT GND 5 kΩ VDS (OUT4) VDS (OUT3) VDS (OUT2) VDS (OUT1) + = 5V = V INL AES01437 Figure 3 Test Circuit 1 100 µ F + VS IN 1 OUT1 OUT2 IN 2 12 V = TLE 5216 G IN 3 IN 4 OUT3 OUT4 RESET SERIN CS 12 Ω 3 mH a b CLK SEROUT GND 1 nF + 5V = AES01438 Figure 4 Test Circuit 2 Semiconductor Group 11 1998-06-22 TLE 5216 G ΙS 100 µ F 6 ... 18 V = VS 12 Ω IN 1 OUT1 IN 2 OUT2 TLE 5216 G + IN 3 OUT3 IN 4 OUT4 RESET SERIN CS 12 Ω 12 Ω 12 Ω CLK SEROUT GND a b 5V = + AES01439 Figure 5 Test Circuit 3 Input H L VDS (OUT) VDS (AZ) t VDS (OV) Output Voltage Sr VLoad Sf 50% t DON t VDS (OL) VDS (OL) t VDS (OL) t DOFF t VDS (SH) t VDS (SH) VDS (SH) "Over Load" VDS (OV) VDS (OL) VDS (SH) 0 "Shorted" VDS(AZ) "Open Load" t AED01442 Figure 6 Switching Waveforms with Inductive Loads Semiconductor Group 12 1998-06-22 Semiconductor Group 13 SEROUT SERIN CLK CS No Error Error Error Code: L H L H L H L H <t V L H No Error Power Output Assignment tV tDHOLD D0 Di0 1 D2 2 D3 Di3 Overload, Shorted Load D1 Di1 Di2 tDSET tCSC D4 3 D5 Open Load Di4 D6 Di0 t DDA Shorted Load to Ground 4 D7 tCLKL tCLKH Di1 Di2 Di4 Normal Function Overload, Shorted Load Open Load Shorted to Ground Di3 1/f CLK tCSH tCSL AED01445 HH HL LH LL TLE 5216 G Figure 7 Serial Diagnostic Interface Timing Diagram 1998-06-22 TLE 5216 G Thermal Resistance for P-DSO-20-10 AED01893 10 1 K/W Z th 10 0 5 1 Switch 2 Switches 4 Switches 10 -1 5 10 -2 10 -2 5 10 -1 10 0 5 5 10 1 Pulse width (square) ms 10 2 Note: Thermal resistance is measured at TC = 25 °C and Tjpeak = 45 °C. Multiple switches are equally loaded at the same time. Tj1 0.2 mJ/K PV1 (W) Tj2 0.4 K/W 0.2 mJ/K PV2 (W) Tj3 0.4 K/W 0.2 mJ/K PV3 (W) Tj4 PV4 (W) 0.4 K/W 0.4 K/W 0.2 mJ/K 0.8 K/W 0.6 mJ/K 1.4 K/W 0.8 mJ/K 0.8 K/W 0.6 mJ/K 0.8 mJ/K 2 mJ/K 2.4 K/W 15 K/W 1.4 K/W 0.8 mJ/K 0.8 K/W 0.6 mJ/K 2 mJ/K 1 K/W 1.4 K/W 0.8 K/W 0.6 mJ/K 2.4 K/W 15 K/W 2.4 K/W 2 mJ/K 1 K/W 1.4 K/W 0.8 mJ/K 2.4 K/W 2 mJ/K 100 mJ/K 0.75 K/W TC (K) AES01895 Figure 8 Thermal Equivalent Circuit for P-DSO-20-10 Note: Thermal equivalent circuit is valid at TC = 25 °C and 25 °C < Tj < 45 °C. At TC = 110 °C and 110 °C < Tj < 130 °C, Zth is 15 % higher. For high power transients with Tj max – TC ≤ 100 K add 25 % headroom for thermal non-uniformity. Semiconductor Group 14 1998-06-22 TLE 5216 G Definition of Dynamic Thermal Resistance (triangle Pulse) Maximum Freewheeling Energy for Inductive Loads P AED01447 100 Z th = ( T j max - T j 0 ) /Pmax mJ Freewheeling Energy Pmax 0 Tj 100 µ s t 0 80 f= 10 Hz 70 50 Hz 60 50 100 Hz f= 10 Hz 50 Hz 40 TC =60 C 30 100 Hz T j max 20 10 Tj 0 0 0.0 100 µ s t 0 AED01446 TC =110 C 0.5 1.0 1.5 2.0 A 2.5 Switching Current Maximum Freewheeling Energy for Inductive Loads with Various Switches in Parallel TC = 110 °C, f = 10 Hz AED01448 40 Max. Freewheeling Energy mJ 30 3...4 Switches 20 2 Switches 10 0 1 Switch 0 2 6 4 8 A 10 Switching Current Semiconductor Group 15 1998-06-22 TLE 5216 G Diagnostic Threshold versus Supply Voltage Current Limitation versus Temperature VDS Ι D(lim) VS VDS (SH) 12 V 4 max 3 Error: Open Load VDS 6 A Normal Function VDS (OL) AED01444 5 min Open Load Output Voltage 2 Error: Shorted to Ground 1 VS 18 AED01443 0 -40 0 50 100 C 150 Tj 4 VS *) VS CLK VCC 5.6 k Ω 1-4 OUT GND CLK TLE 5216 G CS 5.6 kΩ SERIN SEROUT IN RESET VCC TLE 5216 G CS SERIN To Loads VS RESET 1-4 To Loads 1-4 OUT A9-13 Control 2.IC A8 Diagnosis Chip select A7 Diagnosis Clock A6 Power On Reset VCC 3.3 k Ω A5 SEROUT GND *) The capacitance depends on the inductance and current load of the supply. IN Microcontroller i.e. SAB 80515 1-4 4 A1-4 Diagnosis Data In Control 1.IC AES01449 Figure 9 Application Circuit Semiconductor Group 16 1998-06-22 TLE 5216 G Package Outlines B 5˚ ±3˚ 0.02 0.25 +0.0 7 - 1.3 1.2 -0.3 11 ±0.15 1) 2.8 3.5 max. 0 +0.15 3.25 ±0.1 P-DSO-20-10 (Plastic Dual Small Outline Package) 15.74 ±0.1 1.27 0.4 Index Marking 0.1 6.3 +0.13 0.25 M 20 11 1 1 x 45˚ 10 A 20x 14.2 ±0.3 Heatsink 0.95 ±0.15 0.25 M B 15.9 ±0.15 1) GPS05791 GPS05791 A 1) Does not include plastic or metal protrusion of 0.15 max. per side Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book “Package Information”. SMD = Surface Mounted Device Semiconductor Group 17 Dimensions in mm 1998-06-22