BSC079N03S G OptiMOS®2 Power-Transistor Product Summary Features • Fast switching MOSFET for SMPS • Optimized technology for notebook DC/DC converters V DS 30 V R DS(on),max 7.9 mΩ ID 40 A 1) • Qualified according to JEDEC for target applications • N-channel • Logic level P-TDSON-8 • Excellent gate charge x R DS(on) product (FOM) • Very low on-resistance R DS(on) • Superior thermal resistance • Avalanche rated • Pb-free plating; RoHS compliant Type Package Ordering Code Marking BSC079N03S G P-TDSON-8 Q67042 S4290 079N03S Maximum ratings, at T j=25 °C, unless otherwise specified Parameter Symbol Conditions Continuous drain current ID Value T C=25 °C 40 T C=100 °C 40 T A=25 °C, R thJA=45 K/W 2) I D,pulse T C=25 °C3) 160 Avalanche energy, single pulse E AS I D=40 A, R GS=25 Ω 120 Reverse diode dv /dt dv /dt I D=40 A, V DS=24 V, di /dt =200 A/µs, T j,max=150 °C 6 Gate source voltage V GS Power dissipation P tot T A=25 °C, R thJA=45 K/W 2) Operating and storage temperature T j, T stg Rev. 1.01 mJ kV/µs ±20 V 60 W 2.8 -55 ... 150 IEC climatic category; DIN IEC 68-1 A 14.6 Pulsed drain current T C=25 °C Unit °C 55/150/56 page 1 2004-12-15 BSC079N03S G Parameter Values Symbol Conditions Unit min. typ. max. - - 2.1 minimal footprint - - 62 6 cm2 cooling area2) - - 45 Thermal characteristics Thermal resistance, junction - case R thJC Thermal resistance, R thJA junction - ambient K/W Electrical characteristics, at T j=25 °C, unless otherwise specified Static characteristics Drain-source breakdown voltage V (BR)DSS V GS=0 V, I D=1 mA 30 - - Gate threshold voltage V GS(th) V DS=V GS, I D=30 µA 1.2 1.6 2 Zero gate voltage drain current I DSS V DS=30 V, V GS=0 V, T j=25 °C - 0.1 1 V DS=30 V, V GS=0 V, T j=125 °C - 10 100 V µA Gate-source leakage current I GSS V GS=20 V, V DS=0 V - 10 100 nA Drain-source on-state resistance R DS(on) V GS=4.5 V, I D=40 A - 9.3 11.6 mΩ V GS=10 V, I D=40 A - 6.6 7.9 - 1 - Ω 31 62 - S Gate resistance RG Transconductance g fs 1) |V DS|>2|I D|R DS(on)max, I D=40 A J-STD20 and JESD22 2) Device on 40 mm x 40 mm x 1.5 mm epoxy PCB FR4 with 6 cm 2 (one layer, 70 µm thick) copper area for drain connection. PCB is vertical in still air. 2) See figure 3 Rev. 1.01 page 2 2004-12-15 BSC079N03S G Parameter Values Symbol Conditions Unit min. typ. max. - 1680 2230 - 600 800 Dynamic characteristics Input capacitance C iss Output capacitance C oss Reverse transfer capacitance Crss - 79 120 Turn-on delay time t d(on) - 5.1 7.7 Rise time tr - 4.2 6.3 Turn-off delay time t d(off) - 21 31 Fall time tf - 3.4 5.1 Gate to source charge Q gs - 5.3 7.0 Gate charge at threshold Q g(th) - 2.7 3.6 Gate to drain charge Q gd - 3.4 5.2 Switching charge Q sw - 6.0 8.6 Gate charge total Qg - 13 17 Gate plateau voltage V plateau - 3.1 - Gate charge total, sync. FET Q g(sync) V DS=0.1 V, V GS=0 to 5 V - 11 15 Output charge Q oss V DD=15 V, V GS=0 V - 13 18 - - 40 - - 160 V GS=0 V, V DS=15 V, f =1 MHz V DD=15 V, V GS=10 V, I D=20 A, R G=2.7 Ω pF ns Gate Charge Characteristics3) V DD=15 V, I D=20 A, V GS=0 to 5 V nC V nC Reverse Diode Diode continous forward current IS Diode pulse current I S,pulse Diode forward voltage V SD V GS=0 V, I F=40 A, T j=25 °C - 0.93 1.2 V Reverse recovery charge Q rr V R=15 V, I F=I S, di F/dt =400 A/µs - - 10 nC 3) T C=25 °C A See figure 16 for gate charge parameter definition Rev. 1.01 page 3 2004-12-15 BSC079N03S G 1 Power dissipation 2 Drain current P tot=f(T C) I D=f(T C); V GS≥10 V 70 50 60 40 50 30 I D [A] P tot [W] 40 30 20 20 10 10 0 0 0 40 80 120 160 0 40 80 T C [°C] 120 T C [°C] 3 Safe operating area 4 Max. transient thermal impedance I D=f(V DS); T C=25 °C; D =0 Z thJC=f(t p) parameter: t p parameter: D =t p/T 1000 limited by on-state resistance 102 I D [A] 10 100 1 1 µs 10 µs 100 0.5 100 µs DC 101 101 Z thJC [K/W] 103 160 10 1 ms 0.2 0.1 0.05 10 ms 0 10 -1 10 0.1 0.02 1 0.01 single pulse 10-1 10-2 0.1 0.1 1 -1 10 Rev. 1.01 10 0 10 100 1 V DS [V] 10 2 10 page 4 0.01 0 0 -6 10 0 -5 10 0 -4 10 0 -3 t p [s] 10 0 -2 10 10-1 2004-12-15 BSC079N03S G 5 Typ. output characteristics 6 Typ. drain-source on resistance I D=f(V DS); T j=25 °C R DS(on)=f(I D); T j=25 °C parameter: V GS parameter: V GS 80 30 2.8 V 4.5 V 10 V 70 4V 3V 3.2 V 3.7 V 3.4 V 25 60 20 3.7 V R DS(on) [mΩ] I D [A] 50 40 3.4 V 30 15 4V 10 4.5 V 3.2 V 20 10 V 5 3V 10 2.8 V 0 0 0 1 2 3 0 10 20 V DS [V] 30 40 50 I D [A] 7 Typ. transfer characteristics 8 Typ. forward transconductance I D=f(V GS); |V DS|>2|I D|R DS(on)max g fs=f(I D); T j=25 °C 80 80 70 70 60 60 50 50 g fs [S] I D [A] parameter: T j 40 30 30 20 20 150 °C 25 °C 10 10 0 0 0 1 2 3 4 5 0 10 20 30 40 50 60 I D [A] V GS [V] Rev. 1.01 40 page 5 2004-12-15 BSC079N03S G 9 Drain-source on-state resistance 10 Typ. gate threshold voltage R DS(on)=f(T j); I D=40 A; V GS=10 V V GS(th)=f(T j); V GS=V DS parameter: I D 2.5 14 12 2 300 µA R DS(on) [mΩ] 10 V GS(th) [V] 98 % 8 typ 6 1.5 30 µA 1 4 0.5 2 0 0 -60 -20 20 60 100 140 180 -60 -20 20 60 100 140 180 T j [°C] T j [°C] 11 Typ. capacitances 12 Forward characteristics of reverse diode C =f(V DS); V GS=0 V; f =1 MHz I F=f(V SD) parameter: T j 104 103 10000 150 °C, 98% Ciss 102 3 25 °C Coss I F [A] C [pF] 10 102 150 °C 1000 25 °C, 98% 101 Crss 100 100 101 10-1 10 0 10 20 30 0.5 1 1.5 2 V SD [V] V DS [V] Rev. 1.01 0 page 6 2004-12-15 BSC079N03S G 13 Avalanche characteristics 14 Typ. gate charge I AS=f(t AV); R GS=25 Ω V GS=f(Q gate); I D=20 A pulsed parameter: T j(start) parameter: V DD 100 12 15 V 10 100 °C 6V 25 °C 125 °C 8 V GS [V] I AV [A] 24 V 10 6 4 2 1 0 1 10 100 1000 0 5 10 15 20 25 Q gate [nC] t AV [µs] 15 Drain-source breakdown voltage 16 Gate charge waveforms V BR(DSS)=f(T j); I D=1 mA 36 V GS 34 Qg 32 V BR(DSS) [V] 30 28 V g s(th) 26 24 Q g (th) 22 Q sw Q gs 20 -60 -20 20 60 100 140 Q gate Q gd 180 T j [°C] Rev. 1.01 page 7 2004-12-15 BSC079N03S G Package Outline P-TDSON-8: Outline Footprint Dimensions in mm Rev. 1.01 page 8 2004-12-15 BSC079N03S G Package Outline P-TDSON-8: Tape Dimensions in mm Rev. 1.01 page 9 2004-12-15 BSC079N03S G Published by Infineon Technologies AG Bereich Kommunikation St.-Martin-Straße 53 D-81541 München © Infineon Technologies AG 1999 All Rights Reserved. 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Infineon Technologies' components may only be used in life-support devices or systems with the expressed written approval of Infineon Technologies if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. Rev. 1.01 page 10 2004-12-15