ISL59481 ® Data Sheet December 22, 2006 Dual, 500MHz Triple, Multiplexing Amplifiers Features • Dual, triple 4:1 multiplexers for RGB The ISL59481 contains two independent unity gain triple 4:1 MUX amplifiers that feature high slew rate and excellent bandwidth for RGB video switching. Each RGB 4:1 MUX contains binary coded, channel select logic inputs (S0, S1), and separate logic inputs for High Impedance output (HIZ) and power-down (EN) modes. The HIZ state presents a high impedance at the output so that both RGB MUX outputs can be wired together to form an 8:1 RGB MUX amplifier or they can be used in R-R, G-G, and B-B pairs to form a 4:1 differential input/output MUX. Separate power-down mode controls (EN1, EN2) are included to turn off unused circuitry in power sensitive applications. With both EN pins pulled high, the ISL59481 enters a standby power mode consuming just 36mW. Ordering Information PART NUMBER (Note) ISL59481IRZ • Externally configurable for various video MUX circuits including - 8:1 RGB MUX - Two separate 4:1 RGB MUX - 4:1 differential RGB video MUX • Internally set gain-of-1 • High impedance outputs (HIZ) • Power-down mode (EN) • ±5V operation • ±870V/µs slew rate • 500MHz bandwidth • Supply current 16mA/CH PART MARKING TAPE & REEL ISL59481 IRZ - ISL59481IRZ-T13 ISL59481 IRZ FN6208.3 13” PACKAGE (Pb-free) PKG. DWG. # 48 Ld Exposed L48.7x7B Pad 7x7 QFN 48 Ld Exposed L48.7x7B Pad 7x7 QFN NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. • Pb-free plus anneal (RoHS compliant) Applications • HDTV/DTV analog inputs • Video projectors • Computer monitors • Set-top boxes • Security video • Broadcast video equipment Related Literature TABLE 1. CHANNEL SELECT LOGIC TABLE ISL59481 S1-1, 2 S0-1, 2 EN1, EN2 HIZ1, 2 OUTPUT1, 2 0 0 0 0 IN0 (A, B, C) 0 1 0 0 IN1 (A, B, C) 1 0 0 0 IN2 (A, B, C) 1 1 0 0 IN3 (A, B, C) X X 1 X Power-down X X 0 1 High Z 1 • Application Note AN1235 “ISL59481EVAL1 Evaluation Board User’s Guide” CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2006. All Rights Reserved. All other trademarks mentioned are the property of their respective owners. ISL59481 Pinout OUTC1 1 37 IN1B1 38 INIC1 39 GND 40 IN2A1 41 IN2B1 42 IN2C1 43 GND 44 IN3A1 45 IN3B1 46 IN3C1 47 S1-1 48 S0-1 ISL59481 (48 LD QFN) TOP VIEW +1 36 IN2A2 0 OUTB1 2 35 GND +1 V1- 3 OUTA1 4 34 IN1C2 0 33 IN1B2 +1 0 V1+ 5 32 IN1A2 THERMAL PAD EN1 6 31 GND HIZ1 7 30 IN0A2 IN0C1 8 29 IN0B2 IN0B1 9 28 IN0C2 IN0A1 10 27 HIZ2 +1 OUTB2 22 OUTC2 21 S0-2 20 S1-2 19 IN3C2 18 IN3B2 17 IN3A2 16 GND 15 CONNECTED TO VPAD MUST BE TIED TO V- IN2C2 14 IN2B2 13 +1 0 +1 26 EN2 25 V2+ OUTA2 24 IN1A1B 12 THERMAL PAD INTERNALLY 0 0 V2- 23 GND 11 Functional Diagram ISL59481 EN0-1 S0-1 EN1-1 S1-1 DECODE1 IN0(A1, B1, C1) IN1(A1, B1, C1) EN2-1 OUT(A1, B1, C1) IN2(A1, B1, C1) IN3(A1, B1, C1) EN3-1 AMPLIFIER1 BIAS HIZ1 EN1 EN0-2 S0-2 EN1-2 S1-2 DECODE2 IN0(A2, B2, C2) IN1(A2, B2, C2) EN2-2 OUT(A2, B2, C2) IN2(A2, B2, C2) IN3(A2, B2, C2) EN3-2 AMPLIFIER2 BIAS HIZ2 EN2 2 FN6208.3 December 22, 2006 ISL59481 Absolute Maximum Ratings (TA = +25°C) Thermal Information Supply Voltage (V+ to V-). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11V Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . V- -0.5V, V+ +0.5V Supply Turn-on Slew Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . 1V/µs Digital and Analog Input Current (Note 1) . . . . . . . . . . . . . . . . 50mA Output Current (Continuous) . . . . . . . . . . . . . . . . . . . . . . . . . . 50mA ESD Rating Human Body Model (Per MIL-STD-883 Method 3015.7). . . .2500V Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .300V Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C Ambient Operating Temperature . . . . . . . . . . . . . . . .-40°C to +85°C Operating Junction Temperature . . . . . . . . . . . . . . .-40°C to +125°C Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. If an input signal is applied before the supplies are powered up, the input current must be limited to these maximum values. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA Electrical Specifications PARAMETER V1+ = V2+ = +5V, V1- = V2- = -5V, GND = 0V, TA = +25°C, Input Video = 1VP-P and RL = 500Ω to GND, CL = 5pF unless otherwise specified. DESCRIPTION CONDITIONS MIN TYP MAX UNIT GENERAL +IS Enabled Enabled Supply Current No load, VIN = 0V, EN1, EN2 Low 75 92 100 mA -IS Enabled Enabled Supply Current No load, VIN = 0V, EN1, EN2 Low -96 -92 -68 mA +IS Disabled Disabled Supply Current No load, VIN = 0V, EN1, EN2 High 5 6.2 8 mA -IS Disabled Disabled Supply Current No load, VIN = 0V, EN1, EN2 High -250 -20 µA VOUT Positive and Negative Output Swing VIN = ±3.5V, RL = 500Ω 3.1 3.4 |V| IOUT Output Current RL = 10Ω to GND 80 135 |mA| VOS Output Offset Voltage VIN = 0V -10 Input Bias Current VIN = 0V -10 ROUT HIZ Output Resistance HIZ = Logic High 1.2 MΩ ROUT Enabled Output Resistance HIZ = Logic Low 0.1 Ω Input Resistance VIN = ±3.5V 10 MΩ Voltage Gain VIN = ±1.5V, RL= 500Ω Output Current in High Impedance state VOUT = 0V Ib RIN ACL or AV IHIZ 0.98 -2 0.99 14 mV +10 µA 1.02 1.2 V/V µA LOGIC VIH Input High Voltage (Logic Inputs) VIL Input Low Voltage (Logic Inputs) IIH Input High Current (Logic Inputs) VH = 5V 215 IIL Input Low Current (Logic Inputs) VL = 0V -10 0.1% Settling Time RL= 500Ω, CL = 1.5pF, Step = 1V Power Supply Rejection Ratio DC, PSRR V+ and V- combined ISO Channel Isolation f = 10MHz, Ch-Ch X-Talk and Off Isolation, CL = 1.5pF dG Differential Gain Error dP BW 2 V 0.8 V 270 320 µA -1 +10 µA AC GENERAL tS PSRR 10 ns 56 dB 75 dB NTC-7, RL = 150, CL = 1.5pF 0.02 % Differential Phase Error NTC-7, RL = 150, CL = 1.5pF 0.02 ° -3dB Bandwidth CL = 1.5pF 500 MHz 3 52 FN6208.3 December 22, 2006 ISL59481 Electrical Specifications PARAMETER FBW V1+ = V2+ = +5V, V1- = V2- = -5V, GND = 0V, TA = +25°C, Input Video = 1VP-P and RL = 500Ω to GND, CL = 5pF unless otherwise specified. (Continued) DESCRIPTION CONDITIONS MIN TYP MAX UNIT 0.1dB Bandwidth CL = 1.5pF 60 MHz 0.1dB Bandwidth CL = 4.7pF 120 MHz Slew Rate 25% to 75%, RL = 150Ω, Input Enabled, CL = 1.5pF ±870 V/µs VIN = 0V CL = 1.5pF 20 mVP-P EN Switching Glitch VIN = 0V CL = 1.5pF 200 mVP-P HIZ Switching Glitch VIN = 0V CL = 1.5pF 200 mVP-P tSW-L-H Channel Switching Time Low to High 1.2V logic threshold to 10% movement of analog output 18 ns tSW-H-L Channel Switching Time High to Low 1.2V logic threshold to 10% movement of analog output 20 ns tr, tf Rise and Fall Time 10% to 90% 1.1 ns tpd Propagation Delay 10% to 10% 0.9 ns SR SWITCHING CHARACTERISTICS VGLITCH Channel-to-Channel Switching Glitch Typical Performance Curves VS = ±5V, RL = 500Ω to GND, TA = +25°C, unless otherwise specified. 5 10 NORMALIZED GAIN (dB) 6 3 CL=11.5pF CL=7.3pF 4 CL=6.2pF 2 0 -2 CL=4.7pF -4 CL=2.2pF -6 -8 CL=1.5pF CL INCLUDES 1.5pF BOARD CAPACITANCE SOURCE POWER=-20dBm 4 CL=16.5pF NORMALIZED GAIN (dB) 8 SOURCE POWER=-20dBm 2 1 0 -1 RL=100Ω -2 RL=150Ω -3 RL=500Ω -4 RL=1kΩ -5 -10 1M 10M 100M FREQUENCY (Hz) 1M 1G 10M 100M FREQUENCY (Hz) 1G FIGURE 2. GAIN vs FREQUENCY vs RL FIGURE 1. GAIN vs FREQUENCY vs CL 100 0.2 SOURCE 0.1 POWER=-20dBm NORMALIZED GAIN (dB) -0.1 -0.2 OUTPUT RESISTANCE (Ω) CL=4.7pF 0.0 ² CL=1.5pF -0.3 -0.4 -0.5 -0.6 10 1 -0.7 -0.8 1M 10M 100M FREQUENCY (Hz) FIGURE 3. 0.1dB GAIN vs FREQUENCY 4 1G 0.1 0.1M 1M 10M FREQUENCY (Hz) 100M 1G FIGURE 4. ROUT vs FREQUENCY FN6208.3 December 22, 2006 ISL59481 Typical Performance Curves VS = ±5V, RL = 500Ω to GND, TA = +25°C, unless otherwise specified. 0.8 (Continued) 0 RL=500Ω CL=1.5pF 0.6 -10 INPUT X TO OUTPUT Y CROSSTALK -20 0.4 -30 -40 (dB) VOUT (V) 0.2 0.0 -50 OFF ISOLATION INPUT X TO OUTPUT X -60 -0.2 -70 -0.4 ² -80 -0.6 -90 -100 0.1M -0.8 TIME (5ns/DIV) 1M 10M 100M 1G FREQUENCY (Hz) FIGURE 5. TRANSIENT RESPONSE FIGURE 6. CROSSTALK AND OFF ISOLATION 20 PSRR (V+) 0 1V/DIV PSRR (dB) -10 -20 VIN = 0V S0, S1 50Ω TERM. 10 PSRR (V-) -30 -40 0 20mV/DIV -50 -60 -70 -80 0.3M 1M 10M 100M 0 VOUT A, B, C 1G 20ns/DIV FREQUENCY (Hz) FIGURE 7. PSRR CHANNELS A, B, C FIGURE 8. CHANNEL TO CHANNEL SWITCHING GLITCH VIN = 0V ENABLE 50Ω TERM. VIN = 1V 0 0 0 VOUT A, B, C 20ns/DIV FIGURE 9. CHANNEL TO CHANNEL TRANSIENT RESPONSE VIN = 1V 5 100mV/DIV 0.5V/DIV VIN = 0V 1V/DIV 1V/DIV S0, S1 50Ω TERM. VOUT A, B, C 0 20ns/DIV FIGURE 10. ENABLE SWITCHING GLITCH VIN = 0V FN6208.3 December 22, 2006 ISL59481 Typical Performance Curves VS = ±5V, RL = 500Ω to GND, TA = +25°C, unless otherwise specified. VIN = 1V ENABLE HIZ 50Ω TERM. VIN = 0V 1V/DIV 1V/DIV 50Ω TERM. 0 0 0 200mv/DIV 1V/DIV (Continued) VOUT A, B, C 0 VOUT A, B, C 20ns/DIV 10ns/DIV FIGURE 11. ENABLE TRANSIENT RESPONSE VIN = 1V FIGURE 12. HIZ SWITCHING GLITCH VIN = 0V JEDEC JESD51-7 HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD - QFN EXPOSED DIEPAD SOLDERED TO PCB PER JESD51-5 HIZ 0 VOUT A, B, C 0 POWER DISSIPATION (W) 1V/DIV 50Ω TERM. 1V/DIV 6 VIN=1V 5 4.34W QFN48 θJA =23°C/W 4 3 2 1 0 0 10ns/DIV FIGURE 13. HIZ TRANSIENT RESPONSE VIN = 1V 6 25 50 75 85 100 125 150 AMBIENT TEMPERATURE (°C) FIGURE 14. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE FN6208.3 December 22, 2006 ISL59481 Pin Description ISL59481 (48 LD QFN) PIN NAME EQUIVALENT CIRCUIT 1 OUTC1 Circuit 3 Output of amplifier C1 Output of amplifier B1 2 OUTB1 Circuit 3 3, 23 V1-, V2- Circuit 4A DESCRIPTION Negative power supply #1 and #2 4 OUTA1 Circuit 3 5, 25 V1+, V2+ Circuit 4A Circuit 2 Device enable (active low) with internal pull-down resistor. A logic High puts device into power-down mode leaving the logic circuitry active. This state is not recommended for logic control where more than one MUX-amp share the same video output line. Circuit 2 Output disable (active high) with internal pull-down resistor. A logic high puts the output in a high impedance state. Use this state when more than one MUX-amp share the same video output line. Circuit 1 Channel 0 input for amplifier C1 6 EN1 26 EN2 7 HIZ1 27 HIZ2 8 IN0C1 Output of amplifier A1 Positive Power Supply #1 and #2 9 IN0B1 Circuit 1 Channel 0 input for amplifier B1 10 IN0A1 Circuit 1 Channel 0 input for amplifier A1 11 GND Circuit 4A 12 IN1A1 Circuit 1 13 IN2B2 Circuit 1 Channel 2 input for amplifier B2 14 IN2C2 Circuit 1 Channel 2 input for amplifier C2 15 GND Circuit 4B 16 IN3A2 Circuit 1 17 IN3B2 Circuit 1 Channel 3 input for amplifier B2 18 IN3C2 Circuit 1 Channel 3 input for amplifier C2 Ground pin for amplifier A1 Channel 1 input for amplifier A1 Ground pin for amplifier C2 Channel 3 input for amplifier A2 19, 47 S1-2, S1-1 Circuit 2 Channel select pin MSB (binary logic code) for amplifiers A2, B2, C2 (S1-2) and A1, B1, C1 (S1-1) 20, 48 S0-2, S0-1 Circuit 2 Channel select pin LSB (binary logic code) for amplifiers A2, B2, C2 (S0-2) and A1, B1, C1 (S0-1) 21 OUTC2 Circuit 2 Output of amplifier C2 22 OUTB2 Circuit 1 Output of amplifier B2 24 OUTA2 Circuit 1 Output of amplifier A2 28 IN0C2 Circuit 1 Channel 0 input for amplifier A2 29 IN0B2 Circuit 1 Channel 0 input for amplifier B2 30 IN0A2 Circuit 1 Channel 0 input for amplifier C2 31 GND Circuit 4B 32 IN1A2 Circuit 1 33 IN1B2 Circuit 1 Channel 1 input for amplifier B2 34 IN1C2 Circuit 1 Channel 1 input for amplifier C2 35 GND Circuit 4B 36 IN2A2 Circuit 1 37 IN1B1 Circuit 1 Channel 1 input for amplifier B1 38 IN1C1 Circuit 1 Channel 1 input for amplifier C1 39 GND Circuit 4A 40 IN2A1 Circuit 1 41 IN2B1 Circuit 1 Channel 2 input for amplifier B1 42 IN2C1 Circuit 1 Channel 2 input for amplifier C1 43 GND Circuit 4A 44 IN3A1 Circuit 1 45 IN3B1 Circuit 1 Channel 3 input for amplifier B1 46 IN3C1 Circuit 1 Channel 3 input for amplifier C1 7 Ground pin for amplifier C2 Channel 1 input for amplifier A2 Ground pin for amplifier B2 Channel 2 input for amplifier A2 Ground pin for amplifier B1 Channel 2 input for amplifier A1 Ground pin for amplifier C1 Channel 3 input for amplifier A1 FN6208.3 December 22, 2006 ISL59481 Pin Equivalent Circuits V+ V+ 21k LOGIC PIN IN 33k + 1.2V - GND V- V- V- CIRCUIT 1 CIRCUIT 2 V1+ V2+ GNDA1 GNDA2 CAPACITIVELY COUPLED ESD CLAMP GNDB1 V+ OUT SUBSTRATE 1 CAPACITIVELY COUPLED ESD CLAMP GNDB2 GNDC1 CIRCUIT 3 SUBSTRATE 2 V1- V2~1MΩ ~1MΩ GNDC2 V1- V2CIRCUIT 4A Application Information AC Test Circuits General ISL59481 VIN CL 5pF 50Ω or 75Ω RL 500Ω FIGURE 15A. TEST CIRCUIT WITH OPTIMAL OUTPUT LOAD TEST EQUIPMENT ISL59481 RS VIN 50Ω or 75Ω CL 5pF THERMAL HEAT SINK PAD CIRCUIT 4B The ISL59481 is ideal as the matrix element of high performance switchers and routers. Key features include high impedance buffered analog inputs and excellent AC performance at output loads down to 150Ω for video cabledriving. The unity-gain current feedback output amplifiers are stable operating into capacitive loads and bandwidth is optimized with a load of 5pF in parallel with a 500Ω. Total output capacitance can be split between the PCB capacitance and an external load capacitor. Ground Connections 475Ω 50Ω or 75Ω 50Ω or 75Ω For the best isolation and crosstalk rejection, all GND pins must connect to the GND plane. Power-up Considerations FIGURE 15B. TEST CIRCUIT FOR MEASURING WITH 50Ω OR 75Ω INPUT TERMINATED EQUIPMENT TEST EQUIPMENT ISL59481 RS VIN 50Ω or 75Ω CL 5pF 50Ω or 75Ω 50Ω or 75Ω FIGURE 15C. BACKLOADED TEST CIRCUIT FOR VIDEO CABLE APPLICATION. BANDWIDTH AND LINEARITY FOR RL LESS THAN 500Ω WILL BE DEGRADED. FIGURE 15. TEST CIRCUITS Figure 15A illustrates the optimum output load for testing AC performance. Figure 15B illustrates the optimum output load when connecting to 50Ω input terminated equipment. 8 The ESD protection circuits use internal diodes from all pins the V+ and V- supplies. In addition, a dV/dT-triggered clamp is connected between the V+ and V- pins, as shown in the Equivalent Circuits 1 through 4 section of the Pin Description table. The dV/dT triggered clamp imposes a maximum supply turn-on slew rate of 1V/µs. Damaging currents can flow for power supply rates-of-rise in excess of 1V/µs, such as during hot plugging. Under these conditions, additional methods should be employed to ensure the rate of rise is not exceeded. Consideration must be given to the order in which power is applied to the V+ and V- pins, as well as analog and logic input pins. Schottky diodes (Motorola MBR0550T or equivalent) connected from V+ to ground and V- to ground (Figure 16) will shunt damaging currents away from the internal V+ and V- ESD diodes in the event that the V+ supply is applied to the device before the V- supply. One Schottky can be used to protect both V+ power supply pins, and a second for the protection of both V- pins. FN6208.3 December 22, 2006 ISL59481 V+ SUPPLY SCHOTTKY PROTECTION LOGIC V+ LOGIC CONTROL S0 POWER GND EXTERNAL CIRCUITS V+ GND V- IN0 V+ V+ V+ SIGNAL OUT V- DE-COUPLING CAPS IN1 VV- V- V- SUPPLY FIGURE 16. SCHOTTKY PROTECTION CIRCUIT If positive voltages are applied to the logic or analog video input pins before V+ is applied, current will flow through the internal ESD diodes to the V+ pin. The presence of large decoupling capacitors and the loading effect of other circuits connected to V+, can result in damaging currents through the ESD diodes and other active circuits within the device. Therefore, adequate current limiting on the digital and analog inputs is needed to prevent damage during the time the voltages on these inputs are more positive than V+. HIZ State Each internal 4:1 triple MUX-amp has a three-state output control pin (HIZ1 and HIZ2). Each has an internal pull-down resistor to set the output to the enabled state with no connection to the HIZ pin. The HIZ state is established within approximately 15ns by placing a logic high (>2V) on the HIZ pin. If the HIZ state is selected, the output is a high impedance 1.4MΩ with approximately 1.5pF in parallel with a 10μA bias current from the output. When more than one MUX shares a common output, the high impedance state loading effect is minimized over the maximum output voltage swing and maintains its high Z even in the presence of high slew rates. The supply current during this state is the same as the active state. EN and Power-down States The EN pin is active low. An internal pull-down resistor ensures the device will be active with no connection to the EN pin. The power-down state is established within approximately 80ns, if a logic high (>2V) is placed on the EN pin. In the power-down state, supply current is reduced significantly by shutting the three amplifiers off. The output presents a high impedance to the output pin, however, there is a risk that the disabled amplifier output can be back-driven at signal voltage levels exceeding ~2VP-P. Under this condition, large incoming slew rates can cause fault currents of tens of mA. Therefore, the parallel connection of multiple outputs is not recommended unless the application can tolerate the limited power-down output impedance. Limiting the Output Current No output short circuit current limit exists on these parts. All applications need to limit the output current to less than 50mA. Adequate thermal heat sinking of the parts is also required. 9 PC Board Layout The AC performance of this circuit depends greatly on the care taken in designing the PC board. The following are recommendations to achieve optimum high frequency performance from your PC board. • The use of low inductance components, such as chip resistors and chip capacitors, is strongly recommended. • Minimize signal trace lengths. Trace inductance and capacitance can easily limit circuit performance. Avoid sharp corners. Use rounded corners when possible. Vias in the signal lines add inductance at high frequency and should be avoided. PCB traces greater than 1" begin to exhibit transmission line characteristics with signal rise/fall times of 1ns or less. High frequency performance may be degraded for traces greater than one inch, unless controlled impedance (50Ω or 75Ω) strip lines or microstrips are used. • Match channel-channel analog I/O trace lengths and layout symmetry. This will minimize propagation delay mismatches. • Maximize use of AC de-coupled PCB layers. All signal I/O lines should be routed over continuous ground planes (i.e. no split planes or PCB gaps under these lines). Avoid vias in the signal I/O lines. • Use proper value and location of termination resistors. Termination resistors should be as close to the device as possible. • When testing, use good quality connectors and cables, matching cable types and keeping cable lengths to a minimum. • A minimum of 2 power supply decoupling capacitors are recommended (1000pF, 0.01µF) as close to the devices as possible. Avoid vias between the cap and the device because vias add unwanted inductance. Larger caps can be farther away. When vias are required in a layout, they should be routed as far away from the device as possible. • The NIC pins are placed on both sides of the input pins. These pins are not internally connected to the die. It is recommended these pins be tied to ground to minimize crosstalk. FN6208.3 December 22, 2006 ISL59481 The QFN Package Requires Additional PCB Layout Rules for the Thermal Pad amp2 in a similar fashion. The individual control for each 4:1 triple MUX enables external connections to configure the device for different MUX applications. The thermal pad is electrically connected to V- supply through the high resistance IC substrate. Its primary function is to provide heat sinking for the IC. However, because of the connection to the V1- and V2- supply pins through the substrate, the thermal pad must be tied to the V- supply to prevent unwanted current flow to the thermal pad. Do not tie this pin to GND as this could result in large back biased currents flowing between GND and the V- pins. Maximum AC performance is achieved if the thermal pad is attached to a dedicated decoupled layer in a multi-layered PC board. In cases where a dedicated layer is not possible, AC performance may be reduced at upper frequencies. 8:1 RGB Video MUX For a triple input RGB 8:1 MUX (Figure 17), the RGB amplifier outputs of MUX-amp1 are parallel-connected to the RGB amplifier outputs of MUX-amp2 to produce the single RGB video output. Input channels CH0 to CH3 are assigned to MUX-amp1, and channels CH4 through CH7 are assigned to MUX-amp2. Channels CH0 through CH3 are selected by setting HIZ1 low, HIZ2 high (enables MUX-amp1 and threestates MUX-amp2), and the appropriate channel select logic to S0-1, S1-1. Reversing the logic inputs of HIZ1, HIZ2 switches from MUX-amp1 to MUX-amp2 enables the selection of channels CH4 through CH7. The channel select inputs are parallel connected (S0-1 to S0-2) and (S1-1 to S1-2) to form two logic controls S0, S1. A single S2 control is split into complimentary logic inputs for HIZ1 and HIZ2 to produce a chip select function for the MSB. The logic control truth table is shown in Figure 17. The thermal pad requirements are proportional to power dissipation and ambient temperature. A dedicated layer eliminates the need for individual thermal pad area. When a dedicated layer is not possible, an isolated thermal pad on another layer should be used. Pad area requirements should be evaluated on a case by case basis. MUX Application Circuits Each of the two 4:1 triple MUX amplifiers have their own binary-coded, TTL compatible channel select logic inputs (S0-1, 2, and S1-1, 2). All three amplifiers are switched simultaneously from their respective inputs with S0-1 S1-1 controlling MUX-amp1, and S0-2, S1-2 controlling MUXamp2. The HIZ control inputs (HIZ1, HIZ2) and device enable control inputs (EN1 and EN2) control MUX-amp1 and MUX- ISL59481 1/3 MUX-AMP1 CH0 CH1 CH2 CH3 IN0A1 IN1A1 IN2A1 CHANNEL SELECT TRUTH TABLE 8:1 VIDEO MUX OUTA1 IN3A1 S0-1 CH0A - CH7A S1-1 CHANNELS B & C NOT SHOWN CONTROL LOGIC OUTA HIZ1 CH4 CH5 IN0A2 CH6 CH7 IN3A2 S1 S2 1/3 MUX-AMP2 IN1A2 IN2A2 S0 CHANNEL SELECT LOGIC INPUTS +1 +1 S0-2 S1-2 OUTA2 S2 S1 S0 OUTA, B, C 0 0 0 CH0A, B, C 0 0 1 CH1A, B, C 0 1 0 CH2A, B, C 0 1 1 CH3A, B, C 1 0 0 CH4A, B, C 1 0 1 CH5A,B,C 1 1 0 CH6A, B, C 1 1 1 CH7A, B, C CONTROL LOGIC HIZ2 FIGURE 17. APPLICATION CIRCUIT FOR 8:1 RGB VIDEO MUX 10 FN6208.3 December 22, 2006 ISL59481 4:1 RGB Differential Video MUX MUX amp shown in Figure 18. Connecting HIZ1 and HIZ2 to +5V disables the 4:1 differential MUX, and enables the connection of additional differential-connected MUX amplifiers to the same outputs, thus allowing input expansion to 8:1 or more. Connecting the channel select pins in parallel (S0-1 to S0-2 and S1-1 to S1-2) converts the 8 individual RGB video inputs into 4 differential RGB input pairs. The amplifier RGB outputs are similarly paired resulting in a fully differential 4:1 RGB ISL59481 1/3 MUX-AMP1 CH0 IN0A1 + - IN1A1 IN2A1 +1 CHANNEL SELECT TRUTH TABLE 4:1 DIFFERENTIAL VIDEO MUX OUTA1 IN3A1 CH0A - CH3A CH1 - S1-1 CHANNELS B & C NOT SHOWN + IN0A2 - CH1 S0 OUTA, B, C 0 0 CH0A, B, C OUTA 0 1 CH1A, B, C - 1 0 CH2A, B, C 1 1 CH3A, B, C + 1/3 MUX-AMP2 IN1A2 IN2A2 CHANNEL SELECT LOGIC INPUTS CONTROL LOGIC HIZ1 CH2 S1 S0-1 + + +1 OUTA2 IN3A2 - S0-2 S0 S1-2 S1 HIZ CONTROL LOGIC HIZ2 FIGURE 18. APPLICATION CIRCUIT FOR 4:1 RGB DIFFERENTIAL VIDEO MUX All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 11 FN6208.3 December 22, 2006 ISL59481 Package Outline Drawing L48.7x7B 48 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 0, 12/06 4X 5.5 7.00 A 44X 0.50 B 37 6 PIN 1 INDEX AREA 6 PIN #1 INDEX AREA 48 1 7.00 36 3.70 12 25 (4X) 0.15 13 24 0.10 M C A B 48X 0 . 40 TOP VIEW 4 0.25 BOTTOM VIEW SEE DETAIL "X" ( 6 . 80 TYP ) ( 0.10 C BASE PLANE 0 . 85 ± 0 . 1 3.70 ) C SEATING PLANE 0.08 C SIDE VIEW ( 44X 0 . 5 ) C 0 . 2 REF 5 ( 48X 0 . 25 ) ( 48X 0 . 60 ) 0 . 00 MIN. 0 . 05 MAX. TYPICAL RECOMMENDED LAND PATTERN DETAIL "X" NOTES: 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. 3. Unless otherwise specified, tolerance : Decimal ± 0.05 4. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 5. Tiebar shown (if present) is a non-functional feature. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 indentifier may be either a mold or mark feature. 12 FN6208.3 December 22, 2006