INFINEON TUA6014XS

Components
for Entertainment Electronics
2 Band TV Tuner
TUA 6012, TUA 6014
Mixer-Oscillator-PLL
Data Sheet 1998-09-01
Edition 1998-09-01
This edition was realized using
the software system FrameMaker
Published by Siemens AG, Bereich
Halbleiter, Marketing-Kommunikation,
Balanstraße 73,
81541 München
© Siemens AG 1998.
All Rights Reserved.
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implemented within components or
assemblies.
The information describes the type of
component and shall not be considered
as assured characteristics.
Terms of delivery and rights to change
design reserved.
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and prices please contact
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Germany or the Siemens Companies and
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(see address list).
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Siemens AG is an approved CECC manufacturer.
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Components used in life-support devices or systems must be expressly
authorized for such purpose!
Critical components1 of the Semiconductor Group of Siemens AG, may only be
used in life-support devices or systems2
with the express written approval of the
Semiconductor Group of Siemens AG.
1 A critical component is a component
used in a life-support device or system
whose failure can reasonably be
expected to cause the failure of that
life-support device or system, or to
affect its safety or effectiveness of that
device or system.
2 Life support devices or systems are
intended (a) to be implanted in the
human body, or (b) to support and/or
maintain and sustain human life. If
they fail, it is reasonable to assume
that the health of the user may be
endangered.
TUA 6012, TUA 6014
Revision History:
Current Version: 1998-09-01
Previous Version:
04.98
Page
Page
(in previous (in current
Version)
Version)
Subjects (major changes since last revision)
Editorial Update
5
Feature list updated
6
Application description modified
12
I2C-Bus Interface description modified
20
Max. value of parameter IPOH changed
24
Test circuit modified
30
Limit values for channel 6 beat and channel A-5 beat added
Data Classification
Maximum Ratings
Maximum ratings are absolute ratings; exceeding only one of these values may cause
irreversible damage to the integrated circuit.
Recommended Operating Conditions
Under this conditions the functions given in the circuit description are fulfilled. Nominal
conditions specify mean values expected over the production spread and are the
proposed values for interface and application. If not stated otherwise, nominal values will
apply at TA=25°C and the nominal supply voltage.
Characteristics
The listed characteristics are ensured over the operating range of the integrated circuit.
Edition 1998-09-01
Published by Siemens AG, Semiconductor Group
Copyright  Siemens AG 1998. All rights reserved.
Terms of delivery and right to change design reserved.
TUA 6012
TUA 6014
Table of Contents
Page
1
1.1
1.2
1.3
1.4
1.5
1.6
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2
2.1
2.2
2.3
2.3.1
2.3.2
2.3.3
2.3.4
2.3.5
2.3.6
2.3.7
2.3.8
Circuit Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Mixer-Oscillator Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PLL Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I2C-Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bit Allocation Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Description of Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
UHF/VHF Bandswitch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Address Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Test Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reference Divider Ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A/D Converter Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I2C-Bus Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11
11
11
12
13
14
14
15
15
15
15
16
3
3.1
3.2
3.3
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AC/DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17
17
18
19
4
4.1
4.2
4.3
Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DC and RF Parameter Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Measurement of Crystal Oscillator Frequency . . . . . . . . . . . . . . . . . . . . . . .
Equivalent I/O-Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
24
24
25
26
5
5.1
5.2
Application Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Application Circuit 1, PAL (evaluation board) . . . . . . . . . . . . . . . . . . . . . . . . 27
Application Circuit 2, NTSC (Evaluation Board) . . . . . . . . . . . . . . . . . . . . . . 28
6
6.1
6.2
6.3
Electrical Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Admittance VHF Mixer Input Y0 = 20 ms (symmetrical and single ended) . .
Input Impedance UHF Mixer Input Z0 = 50 Ω (symmetrical) . . . . . . . . . . . .
Output Admittance IF Output Y0 = 20 ms (symmetrical) . . . . . . . . . . . . . . .
7
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
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29
29
30
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1998-09-01
2 Band TV Tuner
Mixer-Oscillator-PLL
TUA 6012
TUA 6014
BIPOLAR
1
Overview
1.1
Features
General
• Suitable for NTSC and PAL tuners
• Full ESD protection
Mixer/Oscillator
•
•
•
•
P-TSSOP-28-1
High impedance mixer input for VHF
Low impedance mixer input for UHF
4 pin oscillator for VHF
4 pin oscillator for UHF
PLL
• PLL with short lock-in time;
no asynchronous divider stage
• High voltage VCO tuning output
• Fast I2C Bus
• 4 NPN bandswitch buffers
• Internal VHF/UHF switch
• Lock-in flag
• Power-down reset
• Programmable reference divider ratio (64, 80, 128)
• Programmable charge pump current
Type
Ordering Code
Package
TUA 6012XS
Q67006-A5234-A701
P-TSSOP-28-1
TUA 6014XS
Q67036-A1001-A701
P-TSSOP-28-1
TUA 6014-K
Q67036-A1006-A702
P-TSSOP-28-1
TUA 6014-S
Q67036-A1020-A701
P-TSSOP-28-1
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TUA 6012
TUA 6014
1.2
Functional Description
The TUA6012, TUA6014 devices combine a digitally programmable phase locked loop
(PLL), with a mixer-oscillator block including two balanced mixers and oscillators for use
in TV tuners.
The PLL block with four hard-switched chip addresses forms a digitally programmable
phase locked loop. With a 4 MHz quartz crystal, the PLL permits precise setting of the
frequency of the tuner oscillator up to 900 MHz in increments of 50 kHz, 62.5 kHz or
31.25 kHz. The tuning process is controlled by a microprocessor via an I2C Bus. The
device has four output ports, two of them (P0 and P1) can also be used as TTL input
ports. A flag is set when the loop is locked. The input ports and lock flag can be read by
the processor via the I2C Bus.
The mixer-oscillator block includes two balanced mixers (double balanced mixer with
high-impedance input for VHF low, VHF high and low-impedance input for UHF), two
frequency and amplitude-stable balanced oscillators for VHF low, VHF high and UHF, a
low-noise reference voltage source and a band switch.
1.3
Application
The ICs are suitable for PAL and NTSC tuners in TV- and VCR-sets or cable set-top
receivers for analog TV and Digital Video Broadcasting.
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TUA 6012
TUA 6014
1.4
Pin Configuration
MIXU
MIXU
MIXV
MIXV
V VCC
IFout
IFout
GND D
SDA
SCL
CAS
ADC
P3
Q
1
2
3
4
5
6
7
TUA 6012XS
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
OU-B2
OU-C1
OU-C2
OU-B1
OV-B2
OV-C1
OV-C2
OV-B1
GND A
TUNE
CHGPMP
P0/I0
P1/I1
P2
OU-B2
OU-C1
OU-C2
OU-B1
OV-B2
OV-C1
OV-C2
OV-B1
GND A
TUNE
CHGPMP
P0/I0
P1/I1
P2
28
1
27
2
26
3
25
4
24
5
23
6
TUA
6014XS
22
7
TUA 6014-K
21
8
TUA 6014-S
20
9
19
10
18
11
17
12
16
13
15
14
MIXU
MIXU
MIXV
MIXV
V VCC
IFout
IFout
GND D
SDA
SCL
CAS
ADC
P3
Q
UEP10670
UEP10669
Figure 1
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TUA 6012
TUA 6014
1.5
Pin Definitions and Functions
Function
TUA 6012
TUA 6014
Pin No. Symbol
1
28 OU-B2
UHF oscillator amplifier, high-impedance base input,
symmetrical to OU-B1
2
27 OU-C1
UHF oscillator amplifier, high-impedance collector output,
symmetrical to OU-C2
3
26 OU-C2
UHF oscillator amplifier, high-impedance collector output,
symmetrical to OU-C1
4
25 OU-B1
UHF oscillator amplifier, high-impedance base input,
symmetrical to OU-B2
5
24 OV-B2
VHF oscillator amplifier, high-impedance base input,
symmetrical to OV-B1
6
23 OV-C1
VHF oscillator amplifier, high-impedance collector output,
symmetrical to OV-C2
7
22 OV-C2
VHF oscillator amplifier, high-impedance collector output,
symmetrical to OV-C1
8
21 OV-B1
VHF oscillator amplifier, high-impedance base input,
symmetrical to OV-B2
9
20 GNDA
Analog Ground
10
19 TUNE
VCO tuning voltage output
11
18 CHGPMP Charge pump output/loop filter
12
17 P0/I0
Port output/TTL input
13
16 P1/I1
Port output/TTL input
14
15 P2
Port output
15
14 Q
4 MHz low-impedance crystal oscillator input
16
13 P3
Port output
17
12 ADC
ADC input
18
11 CAS
Chip address select
19
10 SCL
Clock input for the I2C Bus
20
9
SDA
Data input/output for the I2C Bus
21
8
GNDD
Digital Ground
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TUA 6012
TUA 6014
Pin Definitions and Functions (cont’d)
1.5
Function
TUA 6012
TUA 6014
Pin No. Symbol
22
7
IFout
Inverse open collector mixer output, high-impedance,
symmetrical to IFout
23
6
IFout
Open collector mixer output, high-impedance,
symmetrical to IFout
24
5
VVCC
Positive supply voltage
25
4
MIXV
VHF low or VHF high mixer input, high-impedance,
symmetrical to MIXV
26
3
MIXV
VHF low or VHF high mixer input, high-impedance,
symmetrical to MIXV
27
2
MIXU
UHF mixer input, low-impedance, symmetrical to MIXU
28
1
MIXU
UHF mixer input, low-impedance, symmetrical to MIXU
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TUA 6012
TUA 6014
1.6
Block Diagram
MIXU MIXU MIXV MIXV V VCC IFout
28 (1) 27 (2) 26 (3) 25 (4) 24 (5) 23 (6)
IFout GND D SDA SCL CAS ADC P3
Q
22 (7) 21 (8) 20 (9) 19 (10) 18 (11) 17 (12) 16 (13) 15 (14)
Ι 2 C-Bus
Interface
Mixer
UHF
ADC
Crystal
Oscillator
Mixer
VHF
Progr.
Divider
Isolation
Amplifier
Isolation
Amplifier
Oscillator
UHF
Oscillator
VHF
Ref.Divider
PhaseDet. &
ChgPmp
Ι/O-Ports
1 (28) 2 (27) 3 (26) 4 (25) 5 (24) 6 (23) 7 (22) 8 (21) 9 (20) 10 (19) 11 (18) 12 (17) 13 (16) 14 (15)
OU-B2 OU-C1 OU-C2 OU-B1 OV-B2 OV-C1 OV-C2 OV-B1 GND A TUNE CHGPMP P0/I0
P1/I1
P2
UEB10671
The pin numbers given in parenthesis refer to the TUA 6012XS.
Figure 2
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TUA 6012
TUA 6014
2
Circuit Description
2.1
Mixer-Oscillator Block
The mixer oscillator section includes two balanced mixers (double balanced mixer), two
balanced oscillators for VHF low and/or VHF high band and UHF, a reference voltage
source and a band switch.
Filters between tuner input and IC separate the TV frequency signals into two bands.
The band switching in the tuner front-end is done by using two, three or four port outputs.
In the selected band the signal passes a tuner input stage with MOSFET amplifier, a
double-tuned bandpass filter and is then fed to the balanced mixer input of the IC which
has in case of VHF low/VHF high a high-impedance input and in case of UHF a lowimpedance input. The VHF low/VHF high input can be used unsymmetrically by
capacitively grounding one of the input pins. The input signal is mixed there with the
signal from the activated on chip oscillator to the IF frequency and is available at the
balanced high-impedance output pair (IFout/IFout).
2.2
PLL Block
The mixer-oscillator signal VCO/VCO is internally DC-coupled as a differential signal at
the programmable divider inputs. The signal subsequently passes through a
programmable divider with ratio N = 256 through 32767 and is then compared in a digital
frequency/phase detector to a reference frequency fref = 4 MHz / reference divider ratio
(fref = 31.25 kHz, 50 kHz or 62.5 kHz). This frequency is derived from a unbalanced, lowimpedance 4 MHz crystal oscillator (pin Q) divided by reference divider ratio
(programmable reference divider ratio = 128, 80 or 64).
The phase detector has two outputs, UP and DOWN that drive two current sources I+
and I- of a charge pump. If the negative edge of the divided VCO signal appears prior to
the negative edge of the reference signal, the I+ current source pulses for the duration
of the phase difference. In the reverse case the I- current source pulses. If the two
signals are in phase, the charge pump output (CHGPMP) goes into the high-impedance
state (PLL is locked). An active low-pass filter integrates the current pulses to generate
the tuning voltage for the VCO (internal amplifier, external pullup resistor at TUNE and
external RC circuitry). The charge pump output is also switched into the high-impedance
state when the control bit T0 = 1. Here it should be noted, however, that the tuning
voltage can alter over a long period in the high-impedance state as a result of selfdischarge in the peripheral circuity. TUNE may be switched off by the control bit OS to
allow external adjustments.
If the VCO is not working the PLL locks to a tuning voltage of 33 V.
By means of control bit 5I the pump current can be switched between two values by
software. This programmability permits alteration of the control response of the PLL in
the locked-in state. In this way different VCO gains can be compensated, for example.
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TUA 6012
TUA 6014
The software-switched ports P0, P1, P2 and P3 are general-purpose open-collector
outputs. The test bit T1 = 1, switches the test signals fref (4 MHz / reference divider ratio)
and Cy (divided input signal) to P0 and P1 respectively. P0, P1 are bidirectional.
The lock detector resets the lock flag FL when the width of the charge pump current
pulses is greater than the period of the crystal oscillator (i.e. 250 ns). Hence, when
FL = 1, the maximum deviation of the input frequency from the programmed frequency
is given by
∆f = ±IP (KVCO / fQ) (C1 + C2) / (C1C2)
where IP is the charge pump current, KVCO the VCO gain, fQ the crystal oscillator
frequency and C1, C2 the capacitances in the loop filter (see ”Application Circuits” on
page 27). As the charge pump pulses at 62.5 kHz (= fref), it takes a maximum of 16 µs
for FL to be reset after the loop has lost lock state.
Once FL has been reset, it is set only if the charge pump pulse width is less than 250 ns
for eight consecutive fref periods. Therefore it takes between 128 and 144 µs for FL to be
set after the loop regains lock.
2.3
I2C-Bus Interface
Data is exchanged between the processor and the PLL via the I2C Bus. The clock is
generated by the processor (input SCL), while pin SDA functions as an input or output
depending on the direction of the data (open collector, external pull-up resistor). Both
inputs have hysteresis and a low-pass characteristic, which enhance the noise immunity
of the I2C Bus.
The data from the processor pass through an I2C-Bus controller. Depending on their
function the data are subsequently stored in registers. If the bus is free, both lines will be
in the marking state (SDA, SCL are HIGH). Each telegram begins with the start condition
and ends with the stop condition. Start condition: SDA goes LOW, while SCL remains
HIGH. Stop condition: SDA goes HIGH while SCL remains HIGH. All further information
transfer takes place during SCL = LOW, and the data is forwarded to the control logic on
the positive clock edge.
The table ”Bit Allocation” (see ”Bit Allocation Read/Write” on page 13) should be referred
to the following description. All telegrams are transmitted byte-by-byte, followed by a
ninth clock pulse, during which the control logic returns the SDA line to LOW
(acknowledge condition). The first byte is comprised of seven address bits. These are
used by the processor to select the PLL from several peripheral components (chip
select). The LSB bit (R/W) determines whether data are written into (R/W = 0) or read
from (R/W = 1) the PLL.
In the data portion of the telegram during a WRITE operation, the MSB bit of the first or
third data byte determines whether a divider ratio or control information is to follow. In
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TUA 6012
TUA 6014
each case the second byte of the same data type has to follow the first byte. If the
address byte indicates a READ operation, the PLL generates an acknowledge and then
shifts out the status byte onto the SDA line. If the processor generates an acknowledge,
a further status byte is output; otherwise the data line is released to allow the processor
to generate a stop condition. The status word consists of two bits from the TTL input
ports, three bits from the A/D converter, the lock flag and the power-on flag.
Four different chip addresses can be set by appropriate DC level at pin CAS
(see ”Address Selection” on page 15).
When the supply voltage is applied, a power-on reset circuit prevents the PLL from
setting the SDA line to LOW, which would block the bus. The power-on reset flag POR
is set at power-on and if VVCC falls below 3.2 V. It will be reset at the end of a READ
operation.
2.3.1 Bit Allocation Read/Write
Byte
MSB Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 LSB Ack
Remarks
Write Data
Address byte
1
1
0
0
0
MA1 MA0 0
A
Progr. divider
byte 1
0
n14
n13
n12
n11
n10
n9
n8
A
Progr. divider
byte 2
n7
n6
n5
n4
n3
n2
n1
n0
A
Control byte 1
1
5I
T1
T0
1
RSA RSB OS
A
Control byte 2
x
x
x
x
P3
P2
A
Address byte
1
1
0
0
0
MA1 MA0 1
A
Status byte
POR FL
x
I1
I0
A2
A
P1
P0
Read Data
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A0
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TUA 6012
TUA 6014
2.3.2 Description of Symbols
Symbol
Description
MA0, MA1
Address selection bits (see ”Address Selection” on page 15)
n14 to n0
Programmable divider bits:
N = 214 * n14 + 213 * n13 + ... + 23 * n3 + 22 * n2 + 21 * n1 + n0
5I
Charge pump current:
Bit = 0 : Charge pump current = 50 µA
Bit = 1 : Charge pump current = 220 µA
T1, T0
Test bits (see ”Test Modes” on page 15)
RSA, RSB
Reference divider bits (see ”Reference Divider Ratio” on page 15)
OS
Tuning amplifier control bit:
Bit = 0 : Enable VTUNE
Bit = 1 : Disable VTUNE
PO, P1, P2, P3 NPN ports control bits
Bit = 0 : NPN open-collector output is inactive, TTL inputs at P0, P1
Bit = 1 : NPN open-collector output is active
UHF/VHF bandswitch (see ”UHF/VHF Bandswitch” on page 14)
A0, A1, A2
ADC bits (see ”A/D Converter Levels” on page 15)
I0, I1
Input data from P0/I0, P1/I1
FL
PLL lock flag
Bit = 1 : Loop is locked
POR
Power-on reset flag
Flag is set at power-on and reset at the end of READ operation
x
don‘t care
2.3.3 UHF/VHF Bandswitch
IC is in UHF Mode
Ports Pn
P0
P1
P2
P3
TUA 6012XS
x
1
x
x
TUA 6014XS
x
1
x
x
TUA 6014-K
x
x
1
x
TUA 6014-S
x
x
x
1
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TUA 6012
TUA 6014
2.3.4 Address Selection
Voltage at CAS
MA1
MA0
(0...0.1) * VVCC
0
0
Open circuit
0
1
(0.4...0.6) * VVCC
1
0
(0.9...1) * VVCC
1
1
Test Mode
T1
T0
Normal operation
0
0
Charge pump output,
CHGPMP is in high-impedance state
0
1
P1 = Cy output, P0 = fref output
1
0
TTL-inputs I1/I0 are Cy / fref inputs of phase detector
1
1
Reference Divider Ratio
RSA
RSB
80
x
0
128
0
1
64
1
1
2.3.5 Test Modes
2.3.6 Reference Divider Ratio
2.3.7 A/D Converter Levels
Voltage at ADC
A2
A1
A0
(0...0.15) * VVCC
0
0
0
(0.15...0.3) * VVCC
0
0
1
(0.3...0.45) * VVCC
0
1
0
(0.45...0.6) * VVCC
0
1
1
(0.6...1) * VVCC
1
0
0
Semiconductor Group
15
1998-09-01
TUA 6012
TUA 6014
2.3.8 I2C-Bus Timing Diagram
Addressing
Ack. 1st Byte Ack. 2nd Byte Ack. 3rd Byte Ack. 4th Byte
MA1 MA0 R/W
SDA
SCL
Telegram examples:
Start-Addr-DR1-DR2-CW1-CW2-Stop
Start-Addr-CW1-CW2-DR1-DR2-Stop
Start-Addr-DR1-DR2-Stop
Start-Addr-CW1-CW2-Stop
Abbreviations:
Start = Start Condition
Addr = Address Byte
DR1 = Prog. Divider Byte 1
DR2 = Prog. Divider Byte 2
CW1 = Control Byte 1
CW2 = Control Byte 2
Stop = Stop Condition
UED10672
Figure 3
Semiconductor Group
16
1998-09-01
TUA 6012
TUA 6014
3
Electrical Characteristics
3.1
Absolute Maximum Ratings
Parameter 1)
Supply voltage
Junction temperature
Storage temperature
Thermal resistance
(junction to ambient)
Symbol
VVCC
TJ
TStg
RthSA
Limit Values
Unit Test Conditions
min.
max.
- 0.3
5.5
V
125
°C
125
°C
125
K/W
3
V
1
mA
VVCC
V
- 40
PLL
VCHGPMP
ICHGPMP
VQ
Crystal oscillator pins Q
IQ
VSDA
Bus input/output SDA
ISDA(L)
Bus output current SDA
VSCL
Bus input SCL
Chip address switch CAS VCAS
VTUNE
VCO tuning output
CHGPMP
- 0.3
-5
mA
VVCC
V
5
mA
V
- 0.3
VVCC
VVCC
- 0.3
35
V
- 0.3
VVCC
V
-1
15
mA
tmax = 0.1 s at 5.5 V
20
mA
tmax = 0.1 s at 5.5 V
3
V
2
V
-5
6
mA
- 0.3
3
V
VVCC
V
6
V
6
V
- 0.3
- 0.3
Open collector
V
(loop filter)
Port outputs P0...P3
Total port output current
VP
IP(L)
ΣIP(L)
Mixer-Oscillator
Mix inputs VHF/HYPER
VMIXV
Mix inputs UHF
VMIXU
VCO base voltage
VCO collector voltage
IF output
Semiconductor Group
IMIXU
VB
VC
VIFout
VIFout
- 0.3
17
1998-09-01
TUA 6012
TUA 6014
3.1
Absolute Maximum Ratings (cont’d)
Parameter 1)
Symbol
Limit Values
min.
Unit Test Conditions
max.
ESD-Protection 2)
All pins
VESD
1
kV
1)
All values are referred to ground (pin), unless stated otherwise.
Currents with a positive sign flows into the pin and currents with a negative sign flows out of pin.
2)
According to MIL STD 883D, method 3015.7 and EOS/ESD assn. standard S5.1 - 1993
Ambient Temperature under bias: TA = - 20 °C to + .....
Note: The maximal ratings may not be exceeded under any circumstances, not even
momentary and individual, as permanent damage to the IC will result.
3.2
Operating Range
Parameter
Symbol
Limit Values
Unit Test Conditions
min.
max.
VVCC
VIFout
VIFout
4.5
5.5
V
4.5
5.5
V
Programmable
divider factor
N
256
32767
VHF mixer input
frequency range
fMIXV
40
500
MHz
UHF mixer input
frequency range
fMIXU
350
900
MHz
VHF oscillator
frequency range
fOV
75
560
MHz
UHF oscillator
frequency range
fOU
380
950
MHz
Ambient temperature
Tamb
- 20
85
°C
Supply voltage
Mixer output voltage
Open collector
Note: Within the operational range the IC operates as described in the circuit
description. The AC/DC characteristic limits are not guaranteed.
Semiconductor Group
18
1998-09-01
TUA 6012
TUA 6014
3.3
AC/DC Characteristics
Parameter
Symbol
Limit Values
Unit Test Conditions
min.
typ.
max.
3.2
4.0
4.8
MHz Series resonance
10
100
Ω
3.99975 4.000
4.00025
MHz fQ = 4 MHz
- 500
- 700
- 900
Ω
± 90
± 220 ± 300 µA
5I = 1, VCP = 2 V
± 22
± 50
µA
5I = 0, VCP = 2 V
nA
T0 = 1, VCP = 2 V
2.5
V
Locked
10
µA
0.5
V
VTH = 33 V, OS = 1
ITL = 1.0 mA, T0 = 1
3
5.5
V
0
1.5
V
10
µA
Digital Unit
PLL
Crystal Oscillator Connection Q
Crystal frequency
Crystal resistance
Oscillation frequency
Input impedance
fQ
RQ
fQ
ZQ
Series resonance
fQ = 4 MHz
Charge Pump Output CHGPMP
HIGH output current
LOW output current
Tristate current
Output voltage
ICPH
ICPL
ICPZ
VCP
± 75
1
1.0
Drive Output TUNE (open collector)
HIGH output current
LOW output voltage
ITH
VTL
I2C-Bus
Bus Inputs SCL, SDA
HIGH input voltage
LOW input voltage
HIGH input current
LOW input current
VIH
VIL
IIH
IIL
µA
- 10
VIH = VS
VIL = 0 V
Bus Output SDA (open collector)
HIGH output current
LOW output voltage
IOH
VOL
10
µA
0.4
V
tr
tf
300
ns
300
ns
400
kHz
VOH = 5.5 V
IOL = 3 mA
Edge Speed SCL, SDA
Rise time
Fall time
Clock Timing SCL
Frequency
Semiconductor Group
fSCL
0
19
1998-09-01
TUA 6012
TUA 6014
3.3
AC/DC Characteristics (cont’d)
Parameter
Symbol
Limit Values
min.
typ.
Unit Test Conditions
max.
tH
tL
0.6
µs
1.3
µs
tsusta
thsta
0.6
µs
0.6
µs
tsusto
tbuf
0.6
µs
1.3
µs
tsudat
thdat
Hold time
Input hysteresis SCL, SDA Vhys
tsp
Pulse width of spikes
0.1
µs
0
µs
HIGH pulse width
LOW pulse width
Start Condition
Set-up time
Hold time
Stop Condition
Setup time
Bus free
Data Transfer
Setup time
200
0
mV
50
ns
400
pF
1
µA
0.5
V
which are suppressed
Capacitive load for each
bus line
CL
Port Outputs P0, P1, P2, P3 (open collector)
HIGH output current
LOW output voltage
IPOH
VPOL
VPOH = 5 V
IPOL = 15 mA
TTL Port Inputs P0, P1
HIGH input voltage
LOW input voltage
HIGH input current
LOW input current
VPIH
VPIL
IPIH
IPIL
2.7
V
0.8
V
10
µA
µA
- 10
VPIH = 5.5 V
VPIL = 0 V
ADC Port Input
HIGH input current
LOW input current
IADCH
IADCL
- 10
VVCC
2.6
10
µA
µA
Power on Reset
POR = 1
Semiconductor Group
3.2
20
3.6
V
1998-09-01
TUA 6012
TUA 6014
3.3
AC/DC Characteristics (cont’d)
Parameter
Symbol
Limit Values
min.
typ.
Unit Test Conditions
max.
Address Selection Input CAS
HIGH input current
LOW input current
ICASH
ICASL
50
µA
µA
- 50
VCASH = 5 V
VCASL = 0 V
Analog Unit
Mixer-Oscillator
Mixer current
Mixer output impedance
IIF-V/IF-U
RIFout,
RIFout
4
6
8
mA
13
20
27
kΩ
Parallel equivalent
circuit,
fIF = 38.9 MHz
(see Figure 11)
CIFout,
CIFout
0.35
0.5
0.7
pF
Parallel equivalent
circuit,
fIF = 38.9 MHz
(see Figure 11)
28
38
48
mA
1
4
7
dB
VHF Low and VHF High Band Section
Current consumption
Mixer gain
IVCC
GMIXV
fRF = 43.25 to
463.25 MHz, fIF =
33.4 to 58.75 MHz
Mixer noise figure
FMIXV
5
8
dB
fRF = 43.25 to
463.25 MHz
Mixer input impedance
RMIXV
1
2
3
kΩ
Parallel equivalent
circuit,
fMIXV = 300 MHz
(see Figure 9)
1
3
pF
Parallel equivalent
circuit,
fMIXV = 300 MHz
(see Figure 9)
∆fOscV
400
kHz
∆fOscV
500
∆fOscV
100
CMIXV
Oscillator drift,
PLL unlocked
VS = 5 V ±10%
kHz ∆T = 25 °C
kHz t = 5 s up to 15 min
after switching on
Semiconductor Group
21
1998-09-01
TUA 6012
TUA 6014
3.3
AC/DC Characteristics (cont’d)
Parameter
Oscillator pulling,
PLL unlocked
N + 5 pulling,
PLL unlocked
Symbol
Limit Values
Unit Test Conditions
min.
typ.
VMIXV
100
108
dBµV ∆f = 10 kHz
fRF = 48.25 MHz
VMIXV
100
108
dBµV ∆f = 10 kHz
fRF = 399.25 MHz
VMIXV
max.
- 50
dBc
fRF = 48.25 MHz,
fRF1 = 48.25 MHz,
PRF = PRF1 =
80 dBµV
VMIXV
- 50
dBc
fRF = 399.25 MHz,
fRF1 = 437.25 MHz,
PRF = PRF1 =
80 dBµV
Oscillator phase noise
L(fM)VHF - 80
- 86
dBc/ fM = 10 kHz,
Hz
application circuit 1
IVCC
GMIXU
30
41
52
mA
11
14
17
dB
UHF Section
Current consumption
Mixer gain
fRF = 367.25 to
863.25 MHz, fIF =
33.4 to 58.75 MHz
Mixer noise figure
FMIXU
6
9
dB
fRF = 367.25 to
615.25 MHz
FMIXU
7
10
dB
fRF = 623.25 to
863.25 MHz
Mixer input impedance
Semiconductor Group
RMIXU
14
20
26
Ω
Serial equivalent
circuit,
fMIXU = 600 MHz
(see Figure 10)
LMIXU
3
6
9
nH
Serial equivalent
circuit,
fMIXU = 600 MHz
(see Figure 10)
22
1998-09-01
TUA 6012
TUA 6014
3.3
AC/DC Characteristics (cont’d)
Parameter
Symbol
Limit Values
min.
Oscillator drift,
PLL unlocked
typ.
Unit Test Conditions
max.
∆fOscU
400
kHz
VS = 5 V ±10%
∆fOscU
800
kHz
∆T = 25 °C
∆fOscU
100
kHz
t = 5 s up to 15 min
after switching on
Oscillator pulling,
PLL unlocked
N + 5 pulling,
PLL unlocked
VMIXU
100
108
dBµV ∆f = 10 kHz
fRF = 375.25 MHz
VMIXU
100
108
dBµV ∆f = 10 kHz
fRF = 847.25 MHz
VMIXU
- 50
dBc
fRF = 471.25 MHz,
fRF1 = 510.25 MHz,
PRF = PRF1 =
80 dBµV
VMIXU
- 50
dBc
fRF = 847.25 MHz,
fRF1 = 886.25 MHz,
PRF = PRF1 =
80 dBµV
Oscillator phase noise
L(fM)UHF - 80
- 86
dBc/ fM = 10 kHz,
Hz
application circuit 1
INTCH6
66
dBc
Rejection at the IF Output
Channel 6 beat
Channel A-5 beat
60
VRFpix = VRFsnd =
80 dBµV 1)
INTCHA-5 63
69
dBc
VRFpix = 80 dBµV 2)
1)
Channel 6 beat is the interfering product of fRFpix, fRFsnd - fOSC of channel 6 at 42 MHz.
2)
Channel A-5 beat is the interfering product of fRFpix + fRFsnd - fOSC of channel A-5, fBEAT = 45.5 MHz.
The possible mechanisms are: fOSC - 2 fIF or 2 fRFpix - fOSC . For the measurement VRF = 80 dBµV.
*
Supply Voltage
Ambient Temperature
Semiconductor Group
*
VVCC = 5 V
Tamb = 25 °C
23
1998-09-01
TUA 6012
TUA 6014
4
Test Circuit
4.1
DC and RF Parameter Measurement
R Load = 50 Ω
R Gen = 50 Ω
V VCC
UHF
VHF
1:1
1:1 2)
SDA SCL CAS ADC
IFout
4 MHz
22 pF
22 pF 50 Ω
2.2 pF
28
27
1 nF
1 nF
26
25
100
pF
22 pF
1)
22 pF
P3
10
Ω
24
23
18 pF
47 nF
22
21
20
19
18
17
16
15
11
12
13
14
TUA 6014XS, TUA 6014-K, TUA 6014-S
1
2
3
4
5
6
7
8
9
1.2 pF 1.2 pF 1.2 pF 1.2 pF 2.2 pF 2.2 pF 2.2 pF 2.2 pF
3.9 pF
22 nF
100 pF
4.7 pF
10
100 pF
P0 / I0 P1 / I1 P2
22 k Ω
4.7
nF
BB 639C
BB 639C
470 pF
33 kΩ
33 k Ω
1 kΩ
33 kΩ
4.7 nF
22 k Ω
+33 V
22 kΩ
1 nF
1)
2)
UES10676
Not for noise measurement
1:2 transformer for noise measurement
Note: Circuitry is also valid for TUA 6012XS (circuit has to be flipped)
Figure 4
Semiconductor Group
24
1998-09-01
TUA 6012
TUA 6014
4.2
Measurement of Crystal Oscillator Frequency
V VCC
Ι VCC
Q
18 pF
4 MHz
5V
Test mode:
5 kΩ
f REF
P0
TUA 6012XS
TUA 6014XS
TUA 6014-K
TUA 6014-S
T1 = HIGH
T2 = LOW
P1
5 kΩ
f CY
GND D
Counter
f Q = f REF * Reference Divider Ratio
Counter
f VCO = f CY * N
N: divider ratio
UES10677
Figure 5
Semiconductor Group
25
1998-09-01
TUA 6012
TUA 6014
4.3
Equivalent I/O-Schematic
1
28
(28)
(1)
2
27
(27)
(2)
3
26
(26)
(3)
4
25
(25)
(4)
5
24
(24)
(5)
6
23
(23)
(6)
7
22
(22)
(7)
8
21
(21)
(8)
9
20
(20)
(9)
10
19
(19)
(10)
11
18
(18)
(11)
12
17
(17)
(12)
13
16
(16)
(13)
14
15
(15)
(14)
The pin numbers in the parenthesis refer to the TUA 6012XS
UES10678
Figure 6
Semiconductor Group
26
1998-09-01
TUA 6012
TUA 6014
5
Application Circuits
5.1
Application Circuit 1, PAL (evaluation board)
R Load = 75 Ω
R Gen = 75 Ω
UHF
VHF
12 pF
1:1
22 pF
1:2
220 Ω 220 Ω
4 MHz
2)
L5
L6
22 pF
47
Ω
2.2 pF
28
1 nF
1 nF
26
25
27
P3
27 pF
47 pF
1)
SDA SCL CAS ADC
IFout
V VCC
24
23
100
pF
100
pF
4.7
nF
4.7
nF
20
19
18
17
16
15
11
12
13
14
18 pF
4.7 nF
22
21
TUA 6014XS, TUA 6014-K, TUA 6014-S
1
2
3
4
5
6
7
8
9
1.2 pF 1.2 pF 1.2 pF 1.2 pF 2.7 pF 2.2 pF 2.2 pF 2.7 pF
L3
L4
4.7 pF
P0 /
I0 P1 / I1 P2
22 nF
22 k Ω
4.7
nF
1 kΩ
82 pF
4.7 pF
BA 592
100 kΩ
33 kΩ
2.7 k Ω
1 kΩ
4.7 nF
BB 639C
470 pF
L2
4.7 kΩ
4.7 nF
1 µF
4.7 nF
BB 639C
4.7 k Ω
220 Ω
3.3 kΩ
2.2 pF 100 pF
L1
10
2.2 k Ω
2.2 k Ω
4.7 nF
+33 V
1 nF
1)
TOKO B4F
Type 617DB-1023
RF - Bands:
43.25 to 126.25 MHz
2)
TOKO B4F
Type 617PT-1026
133.25 to 423.25 MHz
423.25 to 863.25 MHz
L1:
L2:
L3:
L4:
2 turns, 0.5 mm, 2.5 mm
4 turns, 0.5 mm, 2.5 mm
L5: 16 turns, 0.3 mm, 4 mm
L6: 16 turns, 0.3 mm, 4 mm
3 turns, 0.5 mm, 3 mm
10 turns, 0.5 mm, 3 mm
Note: Circuitry is also valid for TUA 6012XS (circuit has to be flipped)
UES10679
Figure 7
Semiconductor Group
27
1998-09-01
TUA 6012
TUA 6014
5.2
Application Circuit 2, NTSC (Evaluation Board)
R Load = 75 Ω
R Gen = 75 Ω
UHF
SDA SCL CAS ADC
VHF
220 Ω 220 Ω
18 pF
27 pF
27 pF
1:1 1)
22 pF
1:2 2)
L5
4 MHz
L6
22 pF
47
Ω
2.2 pF
28
P3
IFout
V VCC
27
1 nF
1 nF
26
25
24
23
100
pF
100
pF
4.7
nF
4.7
nF
20
19
18
17
16
15
11
12
13
14
18 pF
4.7 nF
22
21
TUA 6014XS, TUA 6014-K, TUA 6014-S
1
2
3
4
5
6
7
8
9
1.2 pF 1.2 pF 1.2 pF 1.2 pF 2.7 pF 2.2 pF 2.2 pF 2.7 pF
L3
L4
4.7 pF
P0 /
I0 P1 / I1 P2
22 nF
22 k Ω
4.7
nF
1 kΩ
82 pF
4.7 pF
BA 592
100 kΩ
33 kΩ
2.7 k Ω
1 kΩ
4.7 nF
BB 639C
470 pF
L2
4.7 kΩ
4.7 nF
1 µF
4.7 nF
BB 639C
4.7 k Ω
220 Ω
3.3 kΩ
2.2 pF 100 pF
L1
10
2.2 k Ω
2.2 k Ω
1)
TOKO B4F
Type 617DB-1023
RF - Bands:
55.25 to 127.25 MHz
2)
TOKO B4F
Type 617PT-1026
133.25 to 361.25 MHz
367.25 to 801.25 MHz
L1:
L2:
L3:
L4:
+33 V
4.7 nF
2 turns, 0.5 mm, 2.5 mm
4 turns, 0.5 mm, 2.5 mm
3 turns, 0.5 mm, 3 mm
10 turns, 0.5 mm, 3 mm
4.7 nF
L5: 15 turns, 0.3 mm, 4 mm
L6: 15 turns, 0.3 mm, 4 mm
UES10680
Note: Circuitry is also valid for TUA 6012XS (circuit has to be flipped)
Figure 8
Semiconductor Group
28
1998-09-01
TUA 6012
TUA 6014
6
Electrical Diagrams
6.1
Input Admittance VHF Mixer Input Y0 = 20 ms
(symmetrical and single ended)
1 0.9 0.8
0.7
1.5
2
0.6
0.5
0.4
3
0.3
4
0.2
5
0.1
10
20
5
3
2
1
0.3 0.2
0.1
40 MHz
R diff
40 MHz
R se
20
10
500 MHz
5
500 MHz
4
0.2
0.3
3
0.4
2
1.5
0.7
1 0.9 0.8
0.6
0.5
UED10673
Figure 9
Semiconductor Group
29
1998-09-01
TUA 6012
TUA 6014
6.2
Input Impedance UHF Mixer Input Z0 = 50 Ω (symmetrical)
0.5
0.7 0.8
0.6
0.9 1
1.5
2
0.4
3
0.3
900 MHz
0.2
4
R diff
500 MHz
300 MHz
0.1
0.1 0.2 0.3
0
5
1
2
3
10
20
5
20
10
0.1
5
0.2
4
0.3
3
0.4
0.5
0.6
2
0.7 0.8
1.5
0.9 1
UED10674
Figure 10
6.3
Output Admittance IF Output Y0 = 20 ms (symmetrical)
1 0.9 0.8
0.7
1.5
2
0.6
0.5
0.4
3
0.3
4
0.2
5
0.1
10
20
5
3
2
1
0.3 0.2
0.1
30 MHz
60 MHz
20
10
0.1
5
0.2
4
0.3
3
0.4
2
1.5
0.7
1 0.9 0.8
0.6
0.5
UED10675
Figure 11
Semiconductor Group
30
1998-09-01
TUA 6012
TUA 6014
7
Package Outlines
P-TSSOP-28-1
(Plastic Thin Shrink Small Outline Package)
GPS05867
Figure 12
Semiconductor Group
31
1998-09-01