A/D, D/C Converters for Image Signal Processing MN65742 6-Bit, 2-Channel CMOS A/D Converter Overview The MN65742 is a 6-bit, 2-channel CMOS analog-todigital converter. It uses a totally parallel structure based on differential comparators to achieve high-speed operation. Pin Assignment CLK 1 28 DA5 AVDD 2 27 DA4 AVSS 3 26 DA3 Features VRT 4 25 DA2 Resolution: 6 bits Maximum conversion rate: 60 MSPS (min.) Linearity error: ±1.3 LSB (typ.) Differential linearity error: ±1.3 LSB (typ.) Analog input voltage level: 1.5 Vp-p (typ.) (1.0 to 2.5 V) Power supply voltage: 5.0 ±0.25 V 3.0 to 5.25 V (power supply for output pins) Power consumption: 250 mW (typ.) (FC= 60 MSPS, not including reference current) N.C. 5 24 DA1 VINA 6 23 DA0 AVSS 7 22 AVSS AVDD 8 21 AVDDL POWD 9 20 DB5 VRM 10 19 DB4 VINB 11 18 DB3 VRB 12 17 DB2 AVSS 13 16 DB1 AVDD 14 15 DB0 Applications Digital satellite broadcasting receivers Digital video equipment (TOP VIEW) SOP028-P-0375 Multimedia equipment Communications equipment 1 MN65742 A/D, D/C Converters for Image Signal Processing 2 5 N.C. VINB 11 VRB VINA 6 12 AVDDL 21 Reference resistor array DA5 27 DA4 DA3 25 DA2 24 DA1 23 DA0 20 DB5 19 26 Clock generator Output logic circuits DB4 18 DB3 17 DB2 16 Comparator Encoder Output logic circuits DB1 15 DB0 1 Clock generator POWD 9 Encoder Reference resistor array CLK Channel A (Ach.) 28 Channel B (Bch.) Comparator 10 VRM 4 VRT 22 AV SS 13 AV SS AVSS 3 7 AVSS AVDD 14 AVDD 8 2 AVDD Block Diagram A/D, D/C Converters for Image Signal Processing MN65742 Pin Descriptions Pin No. 1 Symbol CLK Function Descriptions Clock input 2 AVDD Power supply for analog circuits 3 AVSS Ground for analog circuits 4 VRT Reference voltage (top) 5 N.C. No connection 6 VINA Analog signal input pin 7 AVSS Ground for analog circuits 8 AVDD Power supply for analog circuits 9 POWD 10 VRM Intermediate reference voltage 11 VINB Analog signal input pin 12 VRB Reference voltage (bottom) 13 AVSS Ground for analog circuits 14 AVDD Power supply for analog circuits 15 DB0 Digital output pin 16 DB1 Digital output pin 17 DB2 Digital output pin 18 DB3 Digital output pin 19 DB4 Digital output pin Power-down selection pin 20 DB5 21 AVDDL Digital output pin 22 AVSS Ground for analog circuits 23 DA0 Digital output pin 24 DA1 Digital output pin 25 DA2 Digital output pin 26 DA3 Digital output pin 27 DA4 Digital output pin 28 DA5 Digital output pin Power supply pin for digital output circuits Absolute Maximum Ratings Ta=25˚C Parameter Power supply voltage Symbol AVDD Rating – 0.3 to +7.0 Power supply voltage for output circuits AVDDL – 0.3 to AVDD +0.3 V VI – 0.3 to AVDD +0.3 V Output voltage VO – 0.3 to AVDD +0.3 V Operating ambient temperature Topr –20 to +70 ˚C Storage temperature Tstg –55 to +125 ˚C Input voltage Unit V 3 MN65742 A/D, D/C Converters for Image Signal Processing Recommended Operating Conditions Symbol VDD min 4.75 typ 5.00 Power supply voltage for digital outputs DVDDL 3.00 3.30 VIH 2.2 Digital input "H" level max 5.25 Unit V 5.25 V AVDD V voltage "L" level VIL AVSS 0.8 V Reference "H" level VRT 2.0 2.5 3.5 V voltage "L" level VRB 0.5 1.0 2.0 Clock "H" level pulse width tWH 7 "L" level pulse width Analog input voltage Electrical Characteristics Current Parameter AVDD tWL 7 VAIN AVSS ns AVDD Symbol Conditions IDD fCLK= 60 MSPS min AVDDL V typ max Unit 47 80 mA IDDL 3 6 mA RES 6 (not including reference current) Resolution V ns AVDD=5.0V, AVDDL=3.3V, AVSS=0V, VRT=2.5V, VRB=1.0V, Ta=25˚C consumption bit ±0.7 ±1.3 LSB ±0.7 ±1.3 LSB Linearity error EL Differential linearity error ED Maximum conversion rate FC(max.) 60 fCLK 1 60 1.4 VRT–VRB V –2.0 mA Clock frequency 4 AVDD=5.0V, AVDDL=3.3V, AVSS=0V, Ta=25˚C Parameter Power supply voltage fCLK=60MSPS Analog input dynamic range DR Output "H" level IOH VOH=DVDDL– 0.8V current "L" level IOL VOL=0.4V 2.0 Output delay time td CL=20pF 3 Analog input capacitance CI MSPS MHz mA 7 20 11 ns pF A/D, D/C Converters for Image Signal Processing MN65742 Timing Chart The chip samples the analog input at the rising edge of the clock signal and provides the corresponding digital output one clock cycle later at the rising edge of the clock signal. tWH tWL Analog input N N+1 N+2 tsd N+3 Clock 1.5V Data output N-2 N-1 N N+1 N+2 N+3 1.5V td Note: The circles indicate analog signal sampling points. 5 MN65742 A/D, D/C Converters for Image Signal Processing Package Dimensions (Unit:mm) SOP028-P-0375 17.80±0.20 15 (0.65) 1.27 0.40±0.10 SEATING PLANE 6 +0.10 9.40±0.30 2.40max. 0.15 -0.05 7.20±0.20 14 0.10±0.10 1 1.10±0.20 2.00±0.20 28 0 to 10° 0.30min.