NX2307 SINGLE SUPPLY 12V SYNCHRONOUS PWM CONTROLLER ADVANCE DATA SHEET Pb Free Product DESCRIPTION The NX2307 controller IC is a compact synchronous Buck controller IC with 8 lead SOIC8 package designed for step down DC to DC converter applications. The NX2307 controller is optimized to convert single supply 12V bus voltage to as low as 0.8V output voltage. Internal UVLO keeps the regulator off until the supply voltage exceeds 7V where internal digital soft starts get initiated to ramp up output. The NX2307 employs fixed current limiting followed by HICCUP feature. Other features includes: 12V gate drive capability , Converter Shutdown by pulling COMP pin to Gnd, Adaptive dead band control. FEATURES n 12V Gate Driver n Bus voltage operation from 7V to 15V n Fixed hiccup current limit by sensing Rdson of Synchronous MOSFET n Internal 300kHz n Internal Digital Soft Start Function n Adaptive deadband Control n Shut Down via pulling COMP pin n Pb-free and RoHS compliant APPLICATIONS n n n n Graphic Card on board converters Vddq Supply in mother board applications On board DC to DC such as 12V to 3.3V, 2.5V or 1.8V Set Top Box and LCD Display TYPICAL APPLICATION L2 1uH Vin +12V C4 100uF C5 1uF R6 10 7 HI=SD M3 5 1 Vcc BST COMP R4 5.36k C7 200pF C2 6.8nF 6 D1 MBR0530T1 Hdrv C6 0.1uF 2 M1 IRFR3706 L1 1.5uH NX2307 C3 1uF Cin 16SVP180M 16V,180uF SW Ldrv Vout +1.8V 10A 8 4 FB R1 1.43k M2 IRFR3706 R2 10k Co 4SEPC560M 560uF,7mohm C1 2.7nF Gnd 3 R3 8k Figure1 - Typical application of NX2307 ORDERING INFORMATION Device NX2307CSTR Rev. 3.2 06/22/06 Temperature 0 to 70oC Package SOIC - 8L Frequency 300kHz Pb-Free Yes 1 NX2307 ABSOLUTE MAXIMUM RATINGS Vcc to PGND & BST to SW voltage .................... -0.3V to 16V BST to PGND Voltage ...................................... -0.3V to 35V SW to PGND .................................................... -2V to 35V All other pins .................................................... -0.3V to 6.5V Storage Temperature Range ............................... -65oC to 150oC Operating Junction Temperature Range ............... -40oC to 125oC ESD Susceptibility ........................................... 2kV CAUTION: Stresses above those listed in "ABSOLUTE MAXIMUM RATINGS", may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. PACKAGE INFORMATION 8-LEAD PLASTIC SOIC θJA ≈ 130o C/W BST 1 8 SW HDrv 2 7 COMP Gnd 3 6 Fb LDrv 4 5 Vcc ELECTRICAL SPECIFICATIONS Unless otherwise specified, these specifications apply over Vcc =12V, VBST-VSW =12V, and T A = 0 to 70oC. Typical values refer to TA = 25oC. PARAMETER SYM Test Condition Min TYP MAX Units Reference Voltage Ref Voltage VREF 0.8 V Ref Voltage line regulation 10V<=VCC<=14V 0.2 % Supply Voltage(Vcc) VCC Voltage Range VCC V 7 14 VCC Supply Current ICC (Static) Outputs not switching 5 mA (Static) VCC Supply Current (Dynamic) ICC CL=3300PF (Dynamic) Supply Voltage(VBST) VBST Voltage Range VBST to VSW VBST Supply Current Under Voltage Lockout VCC-Threshold VCC-Hysteresis Rev. 3.2 06/22/06 17 7 mA 14 V VBST CL=3300PF (Dynamic) 12 mA VCC_UVLO VCC Rising VCC_Hyst VCC Falling 6.6 0.3 V V 2 NX2307 PARAMETER Oscillator (Rt) Frequency Ramp-Amplitude Voltage Max Duty Cycle Min Duty Cycle Error Amplifiers Transconductance Input Bias Current Comp SD threshold Soft Start Soft Start time High Side Driver(CL=3300pF) Output Impedance , Sourcing Current Output Impedance , Sinking Current Rise Time Fall Time Deadband Time SYM Test Condition FS Min TYP MAX Units 0 KHz V % % 300 1.1 94 VRAMP 2000 0.2 umho nA V 6.8 mS Ib 100 Tss Rsource(Hdrv) I=200mA 3.6 ohm Rsink(Hdrv) I=200mA 1 ohm THdrv(Rise) 10% to 90% THdrv(Fall) 90% to 10% Tdead(L to Ldrv going Low to Hdrv going H) High, 10% to 10% 30 20 50 ns ns ns Rsource(Ldrv) I=200mA 2.2 ohm Rsink(Ldrv) I=200mA 1 ohm 30 20 50 ns ns ns 240 mV Low Side Driver (CL=3300pF) Output Impedance, Sourcing Current Output Impedance, Sinking Current Rise NTime Fall Time Deadband Time Fixed OCP OCP voltage threshold Rev. 3.2 06/22/06 TLdrv(Rise) 10% to 90% TLdrv(Fall) 90% to 10% Tdead(H to SW going Low to Ldrv going L) High, 10% to 10% 3 NX2307 PIN DESCRIPTIONS PIN # PIN SYMBOL 5 VCC Power supply voltage. A high freq 1uF ceramic capacitor is placed as close as possible to and connected to this pin and ground pin. The maximum rating of this pin is 16V. 1 BST This pin supplies voltage to high side FET driver. A high freq minimum 0.1uF ceramic capacitor is placed as close as possible to and connected to this pin and SW pin. 3 GND Power ground. 6 FB 7 COMP 8 SW 2 HDRV High side gate driver output. 4 LDRV Low side gate driver output. Rev. 3.2 06/22/06 PIN DESCRIPTION This pin is the error amplifiers inverting input. This pin is connected via resistor divider to the output of the switching regulator to set the output DC voltage. This pin is the output of the error amplifier and together with FB pin is used to compensate the voltage control feedback loop. This pin is also used as a shut down pin. When this pin is pulled below 0.2V, both drivers are turned off and internal soft start is reset. This pin is connected to source of high side FETs and provide return path for the high side driver. It is also used to hold the low side driver low until this pin is brought low by the action of high side turning off. LDRV can only go high if SW is below 1V threshold . 4 NX2307 BLOCK DIAGRAM VCC Bias Regulator 1.25V Bias Generator 0.8V UVLO BST POR 6.6/6.3V START HDRV COMP 0.2V SW OC Control Logic START 0.8V OSC Digital start Up PWM VCC ramp S R LDRV Q OC FB 0.6V CLAMP COMP START 1.3V CLAMP 240mV Hiccup Logic OCP comparator GND Figure 2 - Simplified block diagram of the NX2307 Rev. 3.2 06/22/06 5 NX2307 J12V BUS 1 2 12V 4 3 A R15 2k PWR K 2 3 4 C6 100u/16V 6 7 L1 DO1608C-102 8 C2 VD 5 U1 GND 1 2 C5B 3.3V 3.3V 3.3V -12V GND GND PS_ON GND GND 5V GND GND GND PWR_OK 9 D1 MBR0530T1 12V 5V 5 1u GND J1 1 R2 10 12V 10 -5V 5VSB 5V 12V 5V 11 12 13 R24 14 1k 15 16 17 18 19 20 1u VCC C5A 8 7 6 5 16SVP180M JSW 1 R11 NX2307-SOIC8 4 VOUT M1 IRF3706 R3 2 1 5 4 3 2 OP C4 0.1u HDRV M3 OP OUT 1 2 1 2 3 BST 0 (1.5uH , 4m) DO5010P-152HC 8 1 L2 M4 R12 OP LDRV JVOUT SW R20 4SEPC560M 10 M2 IRF3706 R4 4 C8 OP C9 OP 5 4 3 2 SW C12 .1u D3 OP 0 C19 470pF GND FB * COMP 3 R8 6 5.49k C10 200p R5 OP 10k C7 R6 7 6800p C20 OP R13 OP R9 8.06k R7 C13 1.43k 2700p R10 OP C11 OP SW Figure 3- Demo board schematic based on ORCAD Rev. 3.2 06/22/06 6 NX2307 Bill of Materials Item 1 2 3 4 5 6 7 8 Quantity 2 2 1 1 1 1 1 11 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 1 1 1 1 1 2 1 1 1 1 2 1 2 2 1 1 1 1 1 1 1 Rev. 3.2 06/22/06 Reference VOUT,BUS C5B,C2 C4 C5A C6 C7 C8 M3,D3,M4,R5,C9,R10,C10, R11,C11,R12,R13 C12 C13 C19 C10 D1 JVOUT,JSW J1 J12V L1 L2 M1,M2 PWR R2,R20 R3,R4 R6 R7 R8 R9 R15 R24 U1 Value CON2 1u 0.1u 16SVPA180M 100u/16V 6800p 4SEPC560M OP .1u 2700p 470pF 200p MBR0530T1 SCOPE TP ATX con ATX-12V DO3316P-102 DO5010P-152HC IRF3706 LED 10 0 5.49k 1.43k 10k 8.06k 2k 1k NX2307-SOIC8 Manufacture SANYO SANYO Tektronics Coilcraft Coilcraft International Rectifier NEXSEM INC. 7 NX2307 Demoboard waveforms Figure 4 - Output ripple for power output Figure 6 - Start up time Figure 8 - Shutdown via pulling comp pin down Rev. 3.2 06/22/06 Figure 5 - Output voltage transient response for load current 0A-5A Figure 7 - Prebias startup Figure 9 - Short circuit protection 8 NX2307 APPLICATION INFORMATION IRIPPLE = Symbol Used In Application Information: VIN = - Input voltage VOUT - Output voltage IOUT - Output current VIN -VOUT VOUT 1 × × LOUT VIN FS ...(2) 12V-1.8V 1.8V 1 × × = 3.4A 1.5uH 12V 300kHz Output Capacitor Selection DVRIPPLE - Output voltage ripple Output capacitor is basically decided by the amount FS - Switching frequency of the output voltage ripple allowed during steady DIRIPPLE - Inductor current ripple state(DC) load condition as well as specification for the load transient. The optimum design may require a couple VIN=12V of iterations to satisfy both condition. Based on DC Load Condition The amount of voltage ripple during the DC load VOUT=1.8V condition is determined by equation(3). Design Example Power stage design requirements: IOUT =10A ∆VRIPPLE = ESR × ∆IRIPPLE + DVRIPPLE <=25mV DVTRAN<=100mV @ 5A step ∆IRIPPLE 8 × FS × COUT ...(3) Where ESR is the output capacitors' equivalent se- FS=300kHz ries resistance,COUT is the value of output capacitors. Typically when large value capacitors are selected Output Inductor Selection such as Aluminum Electrolytic,POSCAP and OSCON The selection of inductor value is based on induc- types are used, the amount of the output voltage ripple tor ripple current, power rating, working frequency and is dominated by the first term in equation(3) and the efficiency. Larger inductor value normally means smaller second term can be neglected. ripple current. However if the inductance is chosen too For this example, OSCON are chosen as output large, it brings slow response and lower efficiency. Usu- capacitors, the ESR and inductor current typically de- ally the ripple current ranges from 20% to 40% of the termines the output voltage ripple. output current. This is a design freedom which can be decided by design engineer according to various application requirements. The inductor value can be calcu- ESR desire = ∆VRIPPLE 25mV = = 7.3mΩ ∆IRIPPLE 3.4A ...(4) If low ESR is required, for most applications, mul- lated by using the following equations: tiple capacitors in parallel are better than a big capaci- V -V V 1 L OUT = IN OUT × OUT × IRIPPLE VIN FS tor. For example, for 25mV output ripple, OSCON IRIPPLE =k × IOUTPUT ...(1) where k is between 0.2 to 0.4. Select k=0.4, then 12V-1.8V 1.8V 1 × × 0.4 × 10A 12V 300kHz LOUT =1.3uH LOUT = Choose LOUT=1.5uH, then coilcraft inductor DO5010P-152HC is a good choice. 4SEPC560M with 7mΩ are chosen. N = E S R E × ∆ IR I P P L E ∆ VR IPPLE ...(5) Number of Capacitor is calculated as N= 7m Ω × 3.4A 25mV N =0.95 The number of capacitor has to be round up to a integer. Choose N =1. Current Ripple is calculated as Rev. 3.2 06/22/06 9 NX2307 If ceramic capacitors are chosen as output ca- put inductor is smaller than the critical inductance, the pacitors, both terms in equation (3) need to be evalu- voltage droop or overshoot is only dependent on the ESR ated to determine the overall ripple. Usually when this of output capacitor. For low frequency capacitor such type of capacitors are selected, the amount of capaci- as electrolytic capacitor, the product of ESR and ca- tance per single unit is not sufficient to meet the tran- pacitance is high and L ≤ L crit is true. In that case, the sient specification, which results in parallel configura- transient spec is mostly like to dependent on the ESR tion of multiple capacitors. of capacitor. For example, one 100uF, X5R ceramic capacitor with 2mΩ ESR is used. The amount of output ripple is Most case, the output capacitor is multiple capacitor in parallel. The number of capacitor can be calculated by the following 3.4A 8 × 300kHz × 100uF = 6.8mV + 14.1mV = 20.9mV ∆VRIPPLE = 2mΩ × 3.4A + N= Although this meets DC ripple spec, however it needs to be studied for transient requirement. Based On Transient Requirement Typically, the output voltage droop during transient ESR E × ∆Istep ∆Vtran + VOUT × τ2 2 × L × C E × ∆Vtran ...(9) where 0 if L ≤ L crit τ = L × ∆Istep − ESR E × CE V OUT if L ≥ L crit ...(10) is specified as ∆V droop < ∆V tran @step load DISTEP For example, assume voltage droop during tran- During the transient, the voltage droop during the transient is composed of two sections. One section is sient is 100mV for 5A load step. dependent on the ESR of capacitor, the other section is If the OSCON 4SEPC560M (560uF, 7mohm ESR) is used, the crticial inductance is given as a function of the inductor, output capacitance as well as input, output voltage. For example, for the over- L crit = shoot when load from high load to light load with a DISTEP transient load, if assuming the bandwidth of 7mΩ × 560µF × 1.8V = 1.42µH 5A system is high enough, the overshoot can be estimated as the following equation. ∆Vovershoot VOUT = ESR × ∆Istep + × τ2 2 × L × COUT ...(6) where τ is the a function of capacitor,etc. 0 if L ≤ L crit τ = L × ∆Istep − ESR × COUT V OUT if L ≥ L crit The selected inductor is 1.5uH which is bigger than critical inductance. In that case, the output voltage transient not only dependent on the ESR, but also capacitance. number of capacitor is τ= ...(7) = where L crit = ESR × COUT × VOUT ESR E × C E × VOUT = ...(8) ∆Istep ∆Istep where ESRE and CE represents ESR and capacitance of each capacitor if multiple capacitors are used in parallel. The above equation shows that if the selected out- Rev. 3.2 06/22/06 ESR E × C E × VOUT = ∆Istep N= L × ∆I step VOUT − ESR E × C E 1.5µH × 5A − 7mΩ × 560µF = 0.25us 1.8V ESR E × ∆I step ∆Vtran + VOUT × τ2 2 × L × C E × ∆ Vtran 7mΩ × 5A 1.8V + × (0.25us) 2 100mV 2 × 1.5µH × 560µF × 100mV = 0.35 = 10 NX2307 The number of capacitors has to satisfied both ripple and transient requirement. Overall, we choose N=1. FZ1 = 1 2 × π × R 4 × C2 ...(11) FZ2 = 1 2 × π × (R 2 + R3 ) × C3 ...(12) FP1 = 1 2 × π × R3 × C3 ...(13) It should be considered that the proposed equation is based on ideal case, in reality, the droop or overshoot is typically more than the calculation. The equation gives a good start. For more margin, more capacitors have to be chosen after the test. Typically, for high frequency capacitor such as high quality POSCAP es- FP2 = pecially ceramic capacitor, 20% to 100% (for ceramic) 1 2 × π × R4 × more capacitors have to be chosen since the ESR of capacitors is so low that the PCB parasitic can affect the results tremendously. More capacitors have to be selected to compensate these parasitic parameters. Compensator Design Due to the double pole generated by LC filter of the power stage, the power system has 180o phase shift , and therefore, is unstable by itself. In order to achieve accurate output voltage and fast transient response, compensator is employed to provide highest possible bandwidth and enough phase margin. Ideally, the Bode plot of the closed loop system has crossover frequency between 1/10 and 1/5 of the switching frequency, phase margin greater than 50o and the gain crossing 0dB with 20dB/decade. Power stage output capacitors usually decide the compensator type. If electrolytic capacitors ...(14) C1 × C2 C1 + C2 where FZ1,FZ2,FP1 and FP2 are poles and zeros in the compensator. The transfer function of type III compensator for transconductance amplifier is given by: Ve 1 − gm × Z f = VOUT 1 + gm × Zin + Z in / R1 For the voltage amplifier, the transfer function of compensator is Ve −Z f = VOUT Zin To achieve the same effect as voltage amplifier, the compensator of transconductance amplifier must satisfy this condition: R4>>2/gm. And it would be desirable if R1||R2||R3>>1/gm can be met at the same time. are chosen as output capacitors, type II compensator can be used to compensate the system, because the zero caused by output capacitor ESR is lower than cross- Zin Zf C1 Vout over frequency. Otherwise type III compensator should be chosen. R3 A. Type III compensator design C3 R2 caused by output capacitors is higher than the cross- R4 Fb For low ESR output capacitors, typically such as Sanyo oscap and poscap, the frequency of ESR zero C2 gm Ve R1 Vref over frequency. In this case, it is necessary to compensate the system with type III compensator. The following figures and equations show how to realize the type III compensator by transconductance amplifier. Rev. 3.2 06/22/06 Figure 10 - Type III compensator using transconductance amplifier(C1 can also be connected from comp pin to ground) 11 NX2307 Case 1: FLC<FO<FESR(for most ceramic or low ESR POSCAP, OSCON) 2. Set R2 equal to 10kΩ. R1= R 2 × VREF 10k Ω × 0.8V = = 8k Ω VOUT -VREF 1.8V-0.8V Gain(db) Choose R1=8.06kΩ. power stage 3. Set zero FZ2 = FLC and Fp1 =FESR, calculate C3. FLC 40dB/decade C3 = 1 1 1 ) ×( 2 × π × R2 Fz2 Fp1 1 1 1 ×( ) 2 × π × 10kΩ 5.5kHz 40.6kHz =2.5nF = loop gain FESR 20dB/decade compensator Choose C3=2.7nF. 4. Calculate R 4 with the crossover frequency at 1/ 10~ 1/5 of the switching frequency. Set FO=30kHz. R4 = VOSC 2 × π × FO × L × × Cout Vin C3 1.1V 2 × π × 30kHz × 1.5uH × × 560uF 12V 2.7nF =5.38kΩ = FZ1 FZ2 FO FP1 FP2 Choose R4=5.36kΩ. 5. Calculate C2 with zero Fz1 at 75% of the LC Figure 11 - Bode plot of Type III compensator (FLC<FO<FESR) Typical design example of type III compensator in which the crossover frequency is selected as FLC<FO<FESR and FO<=1/10~1/5Fs is shown as the following steps. 1. Calculate the location of LC double pole F LC and ESR zero FESR. FLC = = C2 = 1 2 × π × FZ1 × R 4 1 2 × π × 0.75 × 5.5kHz × 5.36kΩ = 7.1nF = Choose C2=6.8nF. 6. Calculate C 1 by equation (14) with pole F p2 at half the switching frequency. 1 2 × π × L OUT × COUT 1 2 × π × 1.5uH × 560uF = 5.5kHz FESR = double pole by equation (11). 1 2 × π × ESR × C OUT C1 = 1 2 × π × R 4 × FP2 1 2 × π × 5.36kΩ × 150kHz = 197pF = Choose C1=200pF. 7. Calculate R3 by equation (13) with Fp1 =FESR. 1 2 × π × 7m Ω × 560uF = 40.6kHz = Rev. 3.2 06/22/06 12 NX2307 R3 = 1 2 × π × FP1 × C3 FESR = 1 2 × π × 40.6kHz × 2.5nF = 1.45kΩ = 1 2 × π × ESR × COUT 1 2 × π × 15mΩ × 2000uF = 5.3kHz = Choose R3 =1.43kΩ. Gain(db) Case 2: FLC<FESR<FO(for electrolytic capacitors) 2. Set R2 equal to 15kΩ. R1= power stage FLC 40dB/decade FESR R 2 × VREF 15k Ω × 0.8V = = 12k Ω VOUT -VREF 1.8V-0.8V Choose R1=12kΩ. 3. Set zero FZ2 = FLC and Fp1 =FESR . 4. Calculate C3 . C3 = loop gain 1 1 1 ×( ) 2 × π × R2 Fz2 Fp1 1 1 1 ) ×( 2 × π × 15k Ω 1.8kHz 5.3kHz =2.4nF = 20dB/decade Choose C3=2.7nF. 5. Calculate R3 . compensator R3 = 1 2 × π × FP1 × C 3 1 2 × π × 5.3kHz × 2.7F = 11.1k Ω = FZ1 FZ2 FP1 FO FP2 Figure 12 - Bode plot of Type III compensator (FLC<FESR<FO) If electrolytic capacitors are used as output capacitors, typical design example of type III compensator in which the crossover frequency is selected as FLC<FESR<FO and FO<=1/10~1/5Fs is shown as the following steps. Here two SANYO MV-WG1000 with 30 mΩ is chosen as output capacitor, output inductor is 2.2uH. See figure 18. Choose R3 =11kΩ. 6. Calculate R4 with FO=30kHz. R4 = VOSC 2 × π × FO × L R 2 × R 3 × × Vin ESR R2 + R3 1.1V 2 × π × 30kHz × 2.2uH 15k Ω × 11k Ω × × 12V 15m Ω 15k Ω + 11k Ω =16k Ω = Choose R4=16kΩ. 7. Calculate C2 with zero Fz1 at 75% of the LC double pole by equation (11). 1. Calculate the location of LC double pole F LC C2 = and ESR zero FESR. FLC = = 1 2 × π × LOUT × COUT 1 2 × π × 2.2uH × 2000uF = 1.8kHz Rev. 3.2 06/22/06 1 2 × π × FZ1 × R 4 1 2 × π × 0.75 × 1.8kHz × 16k Ω = 4.2nF = Choose C2=4.7nF. 8. Calculate C 1 by equation (14) with pole F p2 at half the switching frequency. 13 NX2307 1 2 × π × R 4 × FP2 1 2 × π × 16k Ω × 150kHz = 66pF = Choose C1=68pF. power stage Gain(db) C1 = 40dB/decade loop gain B. Type II compensator design If the electrolytic capacitors are chosen as power 20dB/decade stage output capacitors, usually the Type II compensator can be used to compensate the system. For this type of compensator, FO has to satisfy compensator FLC<FESR<<FO<=1/10~1/5Fs. Gain Case 1: Type II compensator can be realized by simple FZ FLC FESR RC circuit as shown in figure 14. R3 and C1 introduce a FO FP zero to cancel the double pole effect. C2 introduces a pole to suppress the switching noise. To achieve the same effect as voltage amplifier, the compensator of transconductance amplifier must satisfy this condition: R3>>1/gm and R1||R2>>1/gm. The following equations show the compensator pole zero location and constant gain. Gain= Fz = R3 R2 1 2 × π × R3 × C1 Fp ≈ 1 2 × π × R 3 × C2 Figure 13 - Bode plot of Type II compensator C2 Vout R3 C1 R2 Fb Ve ... (15) R1 ... (16) ... (17) Vref Figure 14 - Type II compensator with transconductance amplifier(case 1) The following parameters are used as an example for type II compensator design, three 1500uF with 19mohm Sanyo electrolytic CAP 6MV1500WGL are used as output capacitors. Coilcraft DO5010P152HC 1.5uH is used as output inductor. See figure 19. The power stage information is that: VIN=12V, VOUT=1.2V, IOUT =12A, FS=300kHz. 1.Calculate the location of LC double pole F LC and ESR zero FESR. Rev. 3.2 06/22/06 14 NX2307 FLC = Case 2: 1 2 × π × L OUT × COUT 1 = 2 × π × 1.5uH × 4500uF = 1.94kHz FESR = 1 2 × π × ESR × COUT 1 = 2 × π × 6.33m Ω × 4500uF = 5.6kHz 2.Set crossover frequency FO=30kHz>>FESR. 3. Set R2 equal to10kΩ. Based on output Type II compensator can also be realized by simple RC circuit without feedback as shown in figure 15. R3 and C1 introduce a zero to cancel the double pole effect. C2 introduces a pole to suppress the switching noise. The following equations show the compensator pole zero location and constant gain. Gain=gm × Fz = R1 × R3 R1 +R 2 1 2 × π × R3 × C1 Fp ≈ 1 2 × π × R 3 × C2 ... (18) ... (19) ... (20) voltage, using equation 21, the final selection of R 1 is 20kΩ. 4.Calculate R3 value by the following equation. V 2 × π × FO × L R 3 = OSC × × R2 V in ESR 1.1V 2 × π × 3 0 k H z × 1 .5uH × × 10kΩ 12V 6.33m Ω =37.2kΩ Vout R2 Fb gm = R1 Ve R3 Vref C2 Choose R 3 =37.4kΩ. C1 5. Calculate C1 by setting compensator zero FZ at 75% of the LC double pole. 1 2 × π × R3 × Fz C1= 1 2 × π × 37.4kΩ × 0.75 × 1.94kHz =2.9nF Figure 15 - Type II compensator with transconductance amplifier(case 2) = The following is parameters for type II compensa- Choose C1=2.7nF. tor design. Input voltage is 12V, output voltage is 2.5V, 6. Calculate C 2 by setting compensator pole Fp output inductor is 2.2uH, output capacitors are two 680uF at half the swithing frequency. 1 C2= π × R 3 × Fs 1 π × 3 7 .4k Ω × 1 5 0 k H z =57pF = Choose C2=56pF. Rev. 3.2 06/22/06 with 41mΩ electrolytic capacitors. See figure 20. 1.Calculate the location of LC double pole F LC and ESR zero FESR. FLC = = 1 2 × π × L OUT × COUT 1 2 × π × 2.2uH × 1360uF = 2.9kHz 15 NX2307 FESR = 1 2 × π × ESR × COUT 1 2 × π × 20.5m Ω × 1360uF = 5.7kHz = 2.Set R2 equal to10kΩ. Using equation 18, the final selection of R1 is 4.7kΩ. Output Voltage Calculation Output voltage is set by reference voltage and external voltage divider. The reference voltage is fixed at 0.8V. The divider consists of two ratioed resistors so that the output voltage applied at the Fb pin is 0.8V when the output voltage is at the desired value. The following equation applies to figure 17, which shows the relationship between VOUT , VREF and voltage divider.. 3. Set crossover frequency at 1/10~ 1/5 of the swithing frequency, here FO=30kHz. Vout 4.Calculate R3 value by the following equation. V 2 × π × FO × L 1 VOUT R 3 = OSC × × × Vin RESR gm VREF 1.1V 2 × π × 30kHz × 2.2uH 1 × × 12 20.5m Ω 2mA/V 2.5V × 0.8V =2.9k Ω R2 Fb R1 = Choose R3 =2.87kΩ. 5. Calculate C1 by setting compensator zero FZ at 75% of the LC double pole. C1 = 1 2 × π × R3 × Fz 1 2 × π × 2.87kΩ × 0.75 × 2.9kHz =25nF = Choose C1=27nF. 6. Calculate C2 by setting compensator pole Fp at half the swithing frequency. C2= 1 π × R 3 × Fs 1 π × 2 .87k Ω × 150kH z =369pF = Choose C2=390pF. Vref Figure 16 - Voltage divider R 1= R 2 × VR E F V O U T -V R E F ...(21) where R2 is part of the compensator, and the value of R1 value can be set by voltage divider. Input Capacitor Selection Input capacitors are usually a mix of high frequency ceramic capacitors and bulk capacitors. Ceramic capacitors bypass the high frequency noise, and bulk capacitors supply switching current to the MOSFETs. Usually 1uF ceramic capacitor is chosen to decouple the high frequency noise.The bulk input capacitors are decided by voltage rating and RMS current rating. The RMS current in the input capacitors can be calculated as: IRMS = IOUT × D × 1- D D= VOUT VIN ...(22) VIN = 12V, VOUT=1.8V, IOUT=10A, the result of input RMS current is 3.6A. For higher efficiency, low ESR capacitors are recommended. One Sanyo OS-CON 16SVP180M 16V 180uF 20mΩ with 3.64A RMS rating are chosen as input bulk capacitors. Rev. 3.2 06/22/06 16 NX2307 Power MOSFETs Selection The NX2307 requires two N-Channel power This power dissipation should not exceed maximum power dissipation of the driver device. MOSFETs. The selection of MOSFETs is based on maximum drain source voltage, gate source voltage, Over Current Limit Protection maximum current rating, MOSFET on resistance and Over current Limit for step down converter is power dissipation. The main consideration is the power achieved by sensing current through the low side loss contribution of MOSFETs to the overall converter efficiency. In this design example, two IRFR3706 are used. They have the following parameters: VDS=30V, ID MOSFET. For NX2307, the current limit is decided by =75A,RDSON =9mΩ,QGATE =23nC. the over current occurs. The over current limit can be There are two factors causing the MOSFET power Conduction loss is simply defined as: calculated by the following equation. The MOSFET RDSON is calculated in the worst case situation, then the current limit for MOSFET IRFR3706 is PHCON =IOUT × D × RDS(ON) × K 2 PTOTAL =PHCON + PLCON FET is on, and the voltage on SW pin is below 240mV, ISET = 240mV/R DSON loss:conduction loss, switching loss. PLCON =IOUT 2 × (1 − D) × RDS(ON) × K the RDSON of the low side mosfet. When synchronous ...(23) ISET = 240mV 240mV = = 17A RDSON 1.4 × 9mΩ where the RDS(ON) will increases as MOSFET junction temperature increases, K is RDS(ON) temperature Layout Considerations dependency. As a result, RDS(ON) should be selected for The layout is very important when designing high the worst case, in which K approximately equals to 1.4 frequency switching converters. Layout will affect noise at 125oC according to IRFR3706 datasheet. Conduction pickup and can cause a good design to perform with loss should not exceed package rating or overall sys- less than expected results. tem thermal budget. There are two sets of components considered in Switching loss is mainly caused by crossover the layout which are power components and small sig- conduction at the switching transition. The total nal components. Power components usually consist of switching loss can be approximated. input capacitors, high-side MOSFET, low-side MOSFET, 1 × VIN × IOUT × TSW × FS ...(24) 2 where IOUT is output current, TSW is the sum of TR and TF which can be found in mosfet datasheet, and FS is switching frequency. Swithing loss PSW is frequency dependent. Also MOSFET gate driver loss should be considered when choosing the proper power MOSFET. MOSFET gate driver loss is the loss generated by discharging the gate capacitor and is dissipated in driver circuits.It is proportional to frequency and is defined as: inductor and output capacitors. A noisy environment is PSW = Pgate = (QHGATE × VHGS + QLGATE × VLGS ) × FS ...(25) where QHGATE is the high side MOSFETs gate generated by the power components due to the switching power. Small signal components are connected to sensitive pins or nodes. A multilayer layout which includes power plane, ground plane and signal plane is recommended . Layout guidelines: 1. First put all the power components in the top layer connected by wide, copper filled areas. The input capacitor, inductor, output capacitor and the MOSFETs should be close to each other as possible. This helps to reduce the EMI radiated by the power loop due to the high switching currents through them. charge,QLGATE is the low side MOSFETs gate charge,VHGS 2. Low ESR capacitor which can handle input RMS is the high side gate source voltage, and VLGS is the low ripple current and a high frequency decoupling ceramic side gate source voltage. Rev. 3.2 06/22/06 cap which usually is 1uF need to be practically touch17 NX2307 ing the drain pin of the upper MOSFET, a plane connection is a must. 3. The output capacitors should be placed as close as to the load as possible and plane connection is required. 4. Drain of the low-side MOSFET and source of the high-side MOSFET need to be connected thru a plane ans as close as possible. A snubber nedds to be placed as close to this junction as possible. 5. Source of the lower MOSFET needs to be connected to the GND plane with multiple vias. One is not enough. This is very important. The same applies to the output capacitors and input capacitors. 6. Hdrv and Ldrv pins should be as close to MOSFET gate as possible. The gate traces should be wide and short. A place for gate drv resistors is needed to fine tune noise if needed. 7. Vcc capacitor, BST capacitor or any other bypassing capacitor needs to be placed first around the IC and as close as possible. The capacitor on comp to GND or comp back to FB needs to be place as close to the pin as well as resistor divider. 8. The output sense line which is sensing output back to the resistor divider should not go through high frequency signals. 9. All GNDs need to go directly thru via to GND plane. 10. The feedback part of the system should be kept away from the inductor and other noise sources, and be placed close to the IC. 11. In multilayer PCB, separate power ground and analog ground. These two grounds must be connected together on the PC board layout at a single point. The goal is to localize the high current path to a separate loop that does not interfere with the more sensitive analog control function. Rev. 3.2 06/22/06 18 NX2307 TYPICAL APPLICATIONS L2 1uH Vin +12V C4 100uF C5 1uF R6 10 C3 1uF 7 5 1 BST M1 half FDS6912A 2 L1 2.2uH NX2307 C7 68pF 6 C6 0.1uF Hdrv R4 16k C2 4.7nF D1 MBR0530T1 Vcc COMP M3 HI=SD Cin 16MV1000WGL 16V,1000uF SW Ldrv Vout +1.8V 5A 8 R1 11k M2 half FDS6912A 4 FB R2 15k Co 2 x MV1000WG 1000uF,30mohm C1 2.7nF Gnd 3 R3 12k Figure 17 - NX2307 application with electrolytic capacitor and type III compensator L2 1uH Vin +12V C4 100uF C5 1uF R6 10 7 HI=SD M3 5 1 Vcc BST COMP R4 37.4k C7 62pF C2 2.7nF 6 Hdrv C6 0.1uF 2 M1 IRFR3709 L1 1.5uH NX2307 C3 1uF D1 MBR0530T1 Cin 16SVP180M 16V,180uF SW Ldrv FB Vout +1.2V 12A 8 4 M2 IRFR3709 R2 10k Co 3 x 6MV1500WGL 1500uF,13mohm Gnd 3 R3 20k Figure 18 - NX2307 application with type II compensator(case 1) Rev. 3.2 06/22/06 19 NX2307 L2 1uH Vin +12V C4 100uF C5 1uF R6 10 7 HI=SD M3 5 1 Vcc BST COMP R4 2.87k C7 390pF C2 27nF 6 Hdrv C6 0.1uF 2 M1 IRFR3706 L1 2.2uH NX2307 C3 1uF D1 MBR0530T1 Cin 16SVP180M 16V,180uF SW Ldrv FB Vout +2.5V 9A 8 4 M2 IRFR3706 Co 2 x (680uF,41mohm) R2 10k Gnd 3 R3 4.7k Figure 19 - NX2307 application with type II compensator(case 2) Rev. 3.2 06/22/06 20 NX2307 SOIC8 PACKAGE OUTLINE DIMENSIONS Rev. 3.2 06/22/06 21 NX2307 Rev. 3.2 06/22/06 22