CA3141 CT T ODU CEMEN 7 R P E A 74 T L 7 E OL REP 00-442OBS ENDED 8 1 m s.co MM ions ECO pplicat p@harri R O N ral A centap High-Voltage Diode Array For Cent : Call or email Industrial and Military Semiconductor January 1999 Commercial, Applications Features Description • Matched Monolithic Construction - VF Match (Each Diode Pair) . . . . 0.55mV At IF = 1mA The CA3141E High Voltage Diode Array Consists of ten general purpose high reverse breakdown diodes. Six diodes are internally connected to form three common cathode diode pairs, and the remaining four diodes are internally connected to form two common anode diode pairs. Integrated circuit construction assures excellent static and dynamic matching of the diodes, making the CA3141 extremely useful for a wide variety of applications in communications and switching systems. • Low Diode Capacitance. . . . . . . 0.3pF (Typ) at VR = 2V • High Diode-to-Substrate Breakdown. . . . . . . . . 30V (Min) • Low Reverse (Leakage) Current . . . . . . . 100nA (Max) Applications • Balanced Modulators or Demodulators • Analog Switches • High-Voltage Diode Gates • Current Ratio Detectors Part Number Information PART NUMBER CA3141E TEMP. RANGE (oC) -55 to 125 PACKAGE 16 Ld PDIP PKG. NO. E16.3 Pinout CA3141 (PDIP) TOP VIEW 1 D1 D10 15 2 3 4 5 D2 D9 D3 D7 D4 D8 D5 D6 14 13 12 11 6 7 16 10 9 8 CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © Harris Corporation 1999 1 File Number 906.4 CA3141 Absolute Maximum Ratings Thermal Information Inverse Voltage (PIV) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30V Peak Diode -to-Substrate Voltage . . . . . . . . . . . . . . . . . . . . . . . 30V Peak Forward Surge Current [IF (Surge)] . . . . . . . . . . . . . . . . 100mA DC Forward Current (IF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25mA Thermal Resistance (Typical, Note 1) θJA (oC/W) PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Maximum Power Dissipation (Any One Diode) . . . . . . . . . . . . . . 50mW Maximum Junction Temperature (Die). . . . . . . . . . . . . . . . . . . . 175oC Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC Operating Conditions Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications TA = 25oC PARAMETER SYMBOL DC Forward Voltage Drop TEST CONDITIONS IF (Anode) VF MIN TYP MAX UNITS 100µA - 0.7 0.9 V 1mA - 0.78 1 V 10mA - 0.93 1.2 V DC Reverse Breakdown Voltage V(BR)R IF = -10µA 30 50 - V DC Breakdown Voltage Between Any Diode and Substrate V(BR)DI IDI = 10µA 30 50 - V DC Reverse (Leakage) Current IR VF = -20V - - 100 nA DC Reverse (Leakage) Current Between Any Diode and Substrate IDI VDI = 20V - - 100 nA VDI = 20V, IFA = 1mA - 0.55 - mV IF = 1mA - -1.5 - mV/oC IF = 2mA, IR = 2mA - 50 - ns Magnitude of Diode Offset Voltage Between Diode Pairs ∆VF/∆T Temperature Coefficient of Forward Voltage Drop Reverse Recovery Time tRR Diode Capacitance CD See Figure 4 pF CDAI See Figure 5 pF Diode Anode-to-Substrate Capacitance Diode Cathode-to-Substrate Capacitance CDCI Magnitude of Cathode-to-Anode Current Ratio See Figure 6 |IFC/IFA| IFA = 1mA, VDS = 10V 0.9 0.96 pF - - Typical Performance Curves 1.2 TA = 25oC DC FORWARD VOLTAGE DROP (V) DC FORWARD VOLTAGE DROP (V) 1 0.8 0.6 0.4 0.2 0 0.1 1 10 102 103 1 0.4 IF = 3mA IF = 1mA IF = 300µA IF = 100µA IF = 10µA 0.2 IF = 1µA IF = 100nA 0.6 0 104 FORWARD CURRENT (µA) FIGURE 1. DC FORWARD VOLTAGE DROP vs FORWARD CURRENT IF = 10mA 0.8 -100 -50 0 50 100 TEMPERATURE (oC) FIGURE 2. DC FORWARD VOLTAGE DROP vs TEMPERATURE 2 150 CA3141 Typical Performance Curves 1.2 TA = 25oC |VF1 - VF2| , |VF3 - VF4| , |VF5 - VF6| |VF7 - VF8| , |VF9 - VF10| 2.5 TA = 25oC 1 DIODE CAPACITANCE (pF) DIODE OFFSET VOLTAGE (mV) 3 (Continued) 2 1.5 1 0.5 0.8 0.6 D5, D9 D2 0.4 D7, D8 D4 D1, D6 0.2 D3, D10 0 102 103 104 MAGNITUDE OF ANODE CURRENT (µA) 1 10 0 105 0 FIGURE 3. 3. DIODE OFFSET VOLTAGE vs MAGNITUDE OF ANODE CURRENT 12 DIODE CATHODE-TO-SUBSTRATE CAPACITANCE (pF) DIODE ANODE-TO-SUBSTRATE CAPACITANCE (pF) FIGURE 4. DIODE CAPACITANCE vs CATHODE-TO-ANODE REVERSE VOLTAGE TA = 25oC 1.6 1.5 1.4 ANODE (TERMINALS 2, 8, 11, 16) 1.3 1.2 1.1 ANODE (TERMINAL 1) 1 0.9 0.8 ANODE (TERMINAL 15) 0.7 0.6 0 6 CATHODE (TERMINALS 3, 6, 14) 4 2 CATHODE (TERMINALS 7, 10, 12, 13) 0 0 5 10 15 20 CATHODE-TO-SUBSTRATE DC REVERSE VOLTAGE (V) FIGURE 6. DIODE CATHODE-TO-SUBSTRATE CAPACITANCE vs CATHODE-TO-SUBSTRATE DC REVERSE VOLTAGE 105 TA = 25oC VDI = 10V DC LEAKAGE CURRENT (pA) FORWARD (CATHODE) CURRENT (mA) 8 1 2 3 4 5 6 7 8 9 10 ANODE-TO-SUBSTRATE DC REVERSE VOLTAGE (V) FIGURE 5. DIODE ANODE-TO-SUBSTRATE CAPACITANCE vs REVERSE VOLTAGE 10 1 0.1 0.01 0.01 TA = 25oC 10 ANODE (TERMINALS 4, 5) 0.5 5 10 15 20 CATHODE-TO-ANODE DC REVERSE VOLTAGE (V) 104 DIODE-TO-SUBSTRATE LEAKAGE CURRENT 103 102 10 DIODE REVERSE (LEAKAGE) CURRENT 1 0.1 0.1 -100 10 1 FORWARD (ANODE) CURRENT (mA) -50 0 50 100 150 TEMPERATURE (oC) FIGURE 7. FORWARD (CATHODE) CURRENT vs FORWARD (ANODE) CURRENT FIGURE 8. DC LEAKAGE CURRENT vs TEMPERATURE 3 CA3141 Dual-In-Line Plastic Packages (PDIP) E16.3 (JEDEC MS-001-BB ISSUE D) N 16 LEAD DUAL-IN-LINE PLASTIC PACKAGE E1 INDEX AREA 1 2 3 INCHES N/2 SYMBOL -B- A2 -C- SEATING PLANE e B1 D1 B 0.010 (0.25) M A1 eC C A B S MAX NOTES - 0.210 - 5.33 4 0.015 - 0.39 - 4 A2 0.115 0.195 2.93 4.95 - B 0.014 0.022 0.356 0.558 - C L B1 0.045 0.070 1.15 1.77 8, 10 eA C 0.008 0.014 0.204 0.355 - D 0.735 0.775 18.66 D1 0.005 - 0.13 A L D1 MIN A E D MAX A1 -ABASE PLANE MILLIMETERS MIN C eB NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication No. 95. - 5 5 E 0.300 0.325 7.62 8.25 6 E1 0.240 0.280 6.10 7.11 5 e 0.100 BSC 2.54 BSC - eA 0.300 BSC 7.62 BSC 6 eB - 0.430 - 10.92 7 L 0.115 0.150 2.93 3.81 4 N 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 19.68 16 16 9 Rev. 0 12/93 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). 4