IXYS IXDD414CI

IXDD414PI / 414YI / 414CI
14 Amp Low-Side Ultrafast MOSFET Driver
Features
General Description
• Built using the advantages and compatibility
of CMOS and IXYS HDMOSTM processes.
• Latch-Up Protected
• High Peak Output Current: 14A Peak
• Wide Operating Range: 4.5V to 25V
• Ability to Disable Output under Faults
• High Capacitive Load
Drive Capability: 15nF in <30ns
• Matched Rise And Fall Times
• Low Propagation Delay Time
• Low Output Impedance
• Low Supply Current
The IXDD414 is a high speed high current gate driver
specifically designed to drive the largest MOSFETs and
IGBTs to their minimum switching time and maximum
practical frequency limits. The IXDD414 can source and
sink 14A of peak current while producing voltage rise and
fall times of less than 30ns. The input of the driver is
compatible with TTL or CMOS and is fully immune to
latch up over the entire operating range. Designed with
small internal delays, cross conduction/current shootthrough is virtually eliminated in the IXDD414. Its features
and wide safety margin in operating voltage and power
make the IXDD414 unmatched in performance and value.
Applications
The IXDD414 incorporates a unique ability to disable the
output under fault conditions. When a logical low is
forced into the Enable input, both final output stage
MOSFETs (NMOS and PMOS) are turned off. As a
result, the output of the IXDD414 enters a tristate mode
and achieves a Soft Turn-Off of the MOSFET/IGBT when
a short circuit is detected. This helps prevent damage
that could occur to the MOSFET/IGBT if it were to be
switched off abruptly due to a dv/dt over-voltage transient.
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Driving MOSFETs and IGBTs
Limiting di/dt under Short Circuit
Motor Controls
Line Drivers
Pulse Generators
Local Power ON/OFF Switch
Switch Mode Power Supplies (SMPS)
DC to DC Converters
Pulse Transformer Driver
Class D Switching Amplifiers
The IXDD414 is available in the standard 8-pin P-DIP (PI),
5-pin TO-220 (CI) and in the TO-263 (YI) surface-mount
package.
Figure 1 - Functional Diagram
200 k
Copyright © IXYS CORPORATION 2001
Patent Pending
First Release
IXDD414PI/414YI/414CI
Absolute Maximum Ratings (Note 1)
Parameter
Supply Voltage
All Other Pins
Operating Ratings
Parameter
Maximum Junction Temperature
Value
25 V
-0.3 V to VCC + 0.3 V
Operating Temperature Range
-40 oC to 85 oC
Thermal Impedance (Junction To Case)
TO220 (CI), TO263 (YI) (θJC)
0.55 oC/W
Power Dissipation, TAMBIENT ≤25 oC
8 Pin PDIP (PI)
975mW
TO220 (CI), TO263 (YI)
12W
Derating Factors (to Ambient)
8 Pin PDIP (PI)
7.6mW/oC
TO220 (CI), TO263 (YI)
0.1W/oC
Storage Temperature
-65 oC to 150 oC
Lead Temperature (10 sec)
Value
150 oC
300 oC
Electrical Characteristics
Unless otherwise noted, TA = 25 oC, 4.5V ≤ VCC ≤ 25V .
All voltage measurements with respect to GND. IXDD414 configured as described in Test Conditions.
Symbol
Parameter
VIH
High input voltage
VIL
Low input voltage
VIN
Input voltage range
IIN
Input current
VOH
High output voltage
VOL
Low output voltage
ROH
Output resistance
@ Output high
Output resistance
@ Output Low
Peak output current
IOUT = 10mA, VCC = 18V
VEN
Continuous output
current
Enable voltage range
8 Pin Dip (PI) (Limited by pkg power dissipation)
TO220 (CI), TO263 (YI)
- 0.3
VENH
High En Input Voltage
VENL
Low En Input Voltage
1/3 Vcc
V
tR
Rise time
CL=15nF Vcc=18V
23
25
29
ns
tF
Fall time
CL=15nF Vcc=18V
21
22
26
ns
tONDLY
CL=15nF Vcc=18V
29
30
33
ns
CL=15nF Vcc=18V
29
31
34
ns
Vcc=18V
40
ns
Vcc=18V
30
ns
VCC
On-time propagation
delay
Off-time propagation
delay
Enable to output high
delay time
Disable to output low
disable delay time
Power supply voltage
18
25
V
ICC
Power supply current
VIN = 3.5V
VIN = 0V
VIN = + VCC
1
0
3
10
10
REN
Enable Pull-up Resistor
mA
µA
µA
kΩ
ROL
IPEAK
IDC
tOFFDLY
tENOH
tDOLD
Test Conditions
Min
Typ
Max
3.5
0V ≤ VIN ≤ VCC
Units
V
0.8
V
-5
VCC + 0.3
V
-10
10
µA
VCC - 0.025
V
0.025
V
600
1000
mΩ
IOUT = 10mA, VCC = 18V
600
1000
mΩ
VCC is 18V
14
A
3
4
Vcc + 0.3
2/3 Vcc
4.5
V
200
Specifications Subject To Change Without Notice
2
A
A
V
IXDD414PI/414YI/414CI
Pin Configurations
2 IN
3 EN
4 GND
I
X
D
D
4
1
4
VCC 8
1
2
3
4
OUT 7
OUT 6
5
GND 5
Vcc
OUT
GND
IN
EN
IX D D 4 1 4 Y I
IX D D 4 1 4 C I
1 VCC
TO220 (CI)
TO263 (YI)
8 PIN DIP (PI)
Pin Description
SYMBOL
FUNCTION
VCC
Supply Voltage
IN
Input
EN
Enable
OUT
Output
GND
Ground
DESCRIPTION
Positive power-supply voltage input. This pin provides power to the
entire chip. The range for this voltage is from 4.5V to 25V.
Input signal-TTL or CMOS compatible.
The system enable pin. This pin, when driven low, disables the chip,
forcing high impedance state to the output.
Driver Output. For application purposes, this pin is connected,
through a resistor, to Gate of a MOSFET/IGBT.
The system ground pin. Internally connected to all circuitry, this pin
provides ground reference for the entire chip. This pin should be
connected to a low noise analog ground plane for optimum
performance.
Note 1: Operating the device beyond parameters with listed “absolute maximum ratings” may cause permanent
damage to the device. Typical values indicate conditions for which the device is intended to be functional, but do not
guarantee specific performance limits. The guaranteed specifications apply only for the test conditions listed.
Exposure to absolute maximum rated conditions for extended periods may affect device reliability.
CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD procedures
when handling and assembling this component.
Figure 2 - Characteristics Test Diagram
VIN
3
IXDD414PI/414YI/414CI
Typical Performance Characteristics
Rise Time vs. Supply Voltage
Fig. 3
Fall Time vs. Supply Voltage
Fig. 4
40
40
30
30
Fall Time (ns)
Rise Time (ns)
CL=15,000 pF
CL=15,000 pF
20
20
7,500 pF
10
3,600 pF
10
7,500 pF
3,600 pF
0
0
8
10
12
14
16
8
18
10
12
Fig. 5
40
14
16
18
Supply Voltage (V)
Supply Voltage (V)
Rise And Fall Times vs. Junction Temperature
CL = 15 nF, Vcc = 18V
Fig. 6
Rise Time vs. Load Capacitance
50
35
8V
40
30
tR
12V
Rise Time (ns)
25
Time (ns)
10V
tF
20
15
30
18V
14V 16V
20
10
10
5
0
-40
-20
0
20
40
60
80
100
0
0k
120
10k
15k
20k
Load Capacitance (pF)
Temperature (°C)
Fig. 7
5k
Fig. 8
Fall Time vs. Load Capacitance
Max / Min Input vs. Junction Temperature
VCC=18V CL=15nF
3.2
40
3.0
Fall Time (ns)
30
8V
Minimum Input High
2.8
10V
Max / Min Input (V)
14V 12V
16V18V
20
2.6
2.4
2.2
Maximum Input Low
2.0
10
1.8
0
0k
1.6
-60
5k
10k
15k
20k
-40
-20
0
20
40
Temperature (oC)
Load Capacitance (pF)
4
60
80
100
IXDD414PI/414YI/414CI
Fig. 9
Supply Current vs. Load Capacitance
Vcc=18V
Fig. 10
Supply Current vs. Frequency
Vcc=18V
1000
1000
15 nF
100
100 2 MHz
Supply Current (mA)
Supply Current (mA)
CL= 30 nF
1 MHz
500 kHz
10
100 kHz
5000 pF
10
2000 pF
1
50 kHz
1
1k
0.1
10k
10
100k
Fig. 11
100
1000
10000
Frequency (kHz)
Load Capacitance (pF)
Supply Current vs. Load Capacitance
Vcc=12V
Fig. 12
1000
Supply Current vs. Frequency
Vcc=12V
1000
CL = 30 nF
100
Supply Current (mA)
Supply Current (mA)
100
2 MHz
1 MHz
500 kHz
10
15 nF
5000 pF
10
2000 pF
1
100 kHz
50 kHz
1
1k
0.1
10k
10
100k
Load Capacitance (pF)
Fig. 13
100
1000
10000
Frequency (kHz)
Fig. 14
Supply Current vs. Load Capacitance
Vcc=8V
Supply Current vs. Frequency
Vcc=8V
1000
1000
CL= 30 nF
100
Supply Current (mA)
Supply Current (mA)
100
2 MHz
1 MHz
10 500 kHz
15 nF
10
5000 pF
2000 pF
1
100 kHz
1 50 kHz
1k
0.1
10k
10
100k
100
Frequency (kHz)
Load Capacitance (pF)
5
1000
10000
IXDD414PI/414YI/414CI
Propagation Delay vs. Supply Voltage
CL=15nF [email protected]
Fig. 15
50
50
tOFFDLY
Propagation Delay vs. Input Voltage
CL=15nF VCC=15V
40
Propagation Delay (ns)
40
Propagation Delay (ns)
Fig. 16
tONDLY
30
20
10
tONDLY
30
tOFFDLY
20
10
0
0
8
10
12
14
16
2
18
4
6
8
10
12
Input Voltage (V)
Supply Voltage (V)
Fig. 17 Propagation Delay Times vs. Junction Temperature
Fig. 18 Quiescent Supply Current vs. Junction Temperature
CL = 2500pF, VCC = 18V
VCC=18V [email protected]
0.60
50
45
Quiescent Supply Current (mA)
35
Time (ns)
0.58
tONDLY
40
tOFFDLY
30
25
20
15
0.56
0.54
0.52
0.50
10
-40
-20
0
20
40
60
80
100
-40
120
-20
P Channel Peak Output Current vs. Case Temperature
CI and YI Packages, VCC=18V CL=.1uF
40
60
80
Fig. 20 N Channel Peak Output Current vs. Case Temperature
CI and YI Packages, VCC=18V CL=.1uF
16
17
15
N Channel Output Current (A)
P Channel Output Current (A)
20
Temperature (oC)
Temperature (°C)
Fig. 19
0
14
13
16
15
14
12
-40
-20
0
20
40
60
80
-40
100
-20
0
20
40
Temperature (oC)
Temperature (oC)
6
60
80
100
IXDD414PI/414YI/414CI
Fig. 22
High State Output Resistance
vs. Supply Voltage
Enable Threshold vs. Supply Voltage
Fig. 21
1.0
14
12
High State Output Resistance (Ohm)
Enable Threshold (V)
0.8
10
0.6
8
6
0.4
4
0.2
2
0
8
10
12
14
16
18
20
22
24
0.0
26
8
10
Supply Voltage (V)
Low-State Output Resistance
vs. Supply Voltage
Fig. 23
15
20
25
Supply Voltage (V)
VCC vs. P Channel Output Current
CL=.1uF [email protected]
Fig. 24
1.0
0
-4
0.8
P Channel Output Current (A)
Low-State Output Resistance (Ohms)
-2
0.6
0.4
0.2
-6
-8
-10
-12
-14
-16
-18
-20
-22
-24
0.0
8
10
15
20
25
8
Supply Voltage (V)
22
N Channel Output Current (A)
20
18
16
14
12
10
8
6
4
2
0
10
15
20
Figure 26 - Typical Application Short Circuit di/dt Limit
24
8
15
Vcc
Vcc vs. N Channel Output Current
CL=.1uF [email protected]
Fig. 25
10
20
25
Vcc
7
25
IXDD414PI/414YI/414CI
APPLICATIONS INFORMATION
Short Circuit di/dt Limit
ground. (Those glitches might cause false triggering of the
comparator).
A short circuit in a high-power MOSFET module such as the
VM0580-02F, (580A, 200V), as shown in Figure 26, can cause
the current through the module to flow in excess of 1500A for
10µs or more prior to self-destruction due to thermal runaway.
For this reason, some protection circuitry is needed to turn off
the MOSFET module. However, if the module is switched off
too fast, there is a danger of voltage transients occuring on the
drain due to Ldi/dt, (where L represents total inductance in
series with drain). If these voltage transients exceed the
MOSFET's voltage rating, this can cause an avalanche breakdown.
The comparator's output should be connected to a SRFF(Set
Reset Flip Flop). The flip-flop controls both the Enable signal,
and the low power MOSFET gate. Please note that CMOS 4000series devices operate with a VCC range from 3 to 15 VDC, (with
18 VDC being the maximum allowable limit).
A low power MOSFET, such as the 2N7000, in series with a
resistor, will enable the VMO580-02F gate voltage to drop
gradually. The resistor should be chosen so that the RC time
constant will be 100us, where "C" is the Miller capacitance of
the VMO580-02F.
The IXDD414 has the unique capability to softly switch off the
high-power MOSFET module, significantly reducing these
Ldi/dt transients.
For resuming normal operation, a Reset signal is needed at
the SRFF's input to enable the IXDD414 again. This Reset can
be generated by connecting a One Shot circuit between the
IXDD414 Input signal and the SRFF restart input. The One Shot
will create a pulse on the rise of the IXDD414 input, and this
pulse will reset the SRFF outputs to normal operation.
Thus, the IXDD414 helps to prevent device destruction from
both dangers; over-current, and avalanche breakdown due to
di/dt induced over-voltage transients.
The IXDD414 is designed to not only provide ±14A under
normal conditions, but also to allow it's output to go into a high
impedance state. This permits the IXDD414 output to control
a separate weak pull-down circuit during detected overcurrent
shutdown conditions to limit and separately control dVGS/dt gate
turnoff. This circuit is shown in Figure 27.
When a short circuit occurs, the voltage drop across the lowvalue, current-sensing resistor, (Rs=0.005 Ohm), connected
between the MOSFET Source and ground, increases. This
triggers the comparator at a preset level. The SRFF drives a low
input into the Enable pin disabling the IXDD408 output. The
SRFF also turns on the low power MOSFET, (2N7000).
Referring to Figure 27, the protection circuitry should include
a comparator, whose positive input is connected to the source
of the VM0580-02. A low pass filter should be added to the input
of the comparator to eliminate any glitches in voltage caused
by the inductance of the wire connecting the source resistor to
In this way, the high-power MOSFET module is softly turned off
by the IXDD414, preventing its destruction.
Figure 27 - Application Test Diagram
+
Ld
10uH
VCC
VCCA
Rg
OUT
IN
EN
-
VCC
+
-
VIN
High_Power
VMO580-02F
1ohm
Rsh
1600ohm
GND
SUB
Rs
Low_Power
2N7002/PLP
Ls
R+
10kohm
20nH
One ShotCircuit
Rcomp
5kohm
NAND
CD4011A
NOT1
CD4049A
NOT2
CD4049A
Ccomp
1pF
Ros
0
Comp
LM339
+
V+
V-
C+
100pF
+
R
1Mohm
REF
Cos
1pF
Q
NOT3
CD4049A
NOR1
CD4001A
EN
NOR2
CD4001A
SR Flip-Flop
8
VB
Rd
0.1ohm
IXDD414
+
-
S
-
IXDD414PI/414YI/414CI
Supply Bypassing and Grounding Practices,
Output Lead inductance
TTL to High Voltage CMOS Level Translation
When designing a circuit to drive a high speed MOSFET
utilizing the IXDD414, it is very important to keep certain design
criteria in mind, in order to optimize performance of the driver.
Particular attention needs to be paid to Supply Bypassing,
Grounding, and minimizing the Output Lead Inductance.
The enable (EN) input to the IXDD414 is a high voltage
CMOS logic level input where the EN input threshold is ½ VCC,
and may not be compatible with 5V CMOS or TTL input levels.
The IXDD414 EN input was intentionally designed for
enhanced noise immunity with the high voltage CMOS logic
levels. In a typical gate driver application, VCC =15V and the
EN input threshold at 7.5V, a 5V CMOS logical high input
applied to this typical IXDD414 application’s EN input will be
misinterpreted as a logical low, and may cause undesirable
or unexpected results. The note below is for optional
adaptation of TTL or 5V CMOS levels.
Say, for example, we are using the IXDD414 to charge a
5000pF capacitive load from 0 to 25 volts in 25ns.
Using the formula: I= ∆V C / ∆t, where ∆V=25V C=5000pF &
∆t=25ns we can determine that to charge 5000pF to 25 volts
in 25ns will take a constant current of 5A. (In reality, the charging
current won’t be constant, and will peak somewhere around
8A).
SUPPLY BYPASSING
In order for our design to turn the load on properly, the IXDD414
must be able to draw this 5A of current from the power supply
in the 25ns. This means that there must be very low impedance
between the driver and the power supply. The most common
method of achieving this low impedance is to bypass the
power supply at the driver with a capacitance value that is a
magnitude larger than the load capacitance. Usually, this
would be achieved by placing two different types of bypassing
capacitors, with complementary impedance curves, very close
to the driver itself. (These capacitors should be carefully
selected, low inductance, low resistance, high-pulse currentservice capacitors). Lead lengths may radiate at high frequency
due to inductance, so care should be taken to keep the lengths
of the leads between these bypass capacitors and the IXDD414
to an absolute minimum.
GROUNDING
In order for the design to turn the load off properly, the IXDD414
must be able to drain this 5A of current into an adequate
grounding system. There are three paths for returning current
that need to be considered: Path #1 is between the IXDD414
and it’s load. Path #2 is between the IXDD414 and it’s power
supply. Path #3 is between the IXDD414 and whatever logic
is driving it. All three of these paths should be as low in
resistance and inductance as possible, and thus as short as
practical. In addition, every effort should be made to keep these
three ground paths distinctly separate. Otherwise, (for
instance), the returning ground current from the load may
develop a voltage that would have a detrimental effect on the
logic line driving the IXDD414.
The circuit in Figure 28 alleviates this potential logic level
misinterpretation by translating a TTL or 5V CMOS logic input
to high voltage CMOS logic levels needed by the IXDD414 EN
input. From the figure, VCC is the gate driver power supply,
typically set between 8V to 20V, and VDD is the logic power
supply, typically between 3.3V to 5.5V. Resistors R1 and R2
form a voltage divider network so that the Q1 base is
positioned at the midpoint of the expected TTL logic transition
levels.
A TTL or 5V CMOS logic low, VTTLLOW=~<0.8V, input applied to
the Q1 emitter will drive it on. This causes the level translator
output, the Q1 collector output to settle to VCESATQ1 +
VTTLLOW=<~2V, which is sufficiently low to be correctly
interpreted as a high voltage CMOS logic low (<1/3VCC=5V for
VCC =15V given in the IXDD414 data sheet.)
A TTL high, VTTLHIGH=>~2.4V, or a 5V CMOS high,
V5VCMOSHIGH=~>3.5V, applied to the EN input of the circuit in
Figure 28 will cause Q1 to be biased off. This results in Q1
collector being pulled up by R3 to VCC=15V, and provides a
high voltage CMOS logic high output. The high voltage CMOS
logical EN output applied to the IXDD414 EN input will enable
it, allowing the gate driver to fully function as an 8 Amp output
driver.
The total component cost of the circuit in Figure 28 is less
than $0.10 if purchased in quantities >1K pieces. It is
recommended that the physical placement of the level
translator circuit be placed close to the source of the TTL or
CMOS logic circuits to maximize noise rejection.
Figure 28 - TTL to High Voltage CMOS Level Translator
CC
(From Gate Driver
Power Supply)
OUTPUT LEAD INDUCTANCE
Of equal importance to Supply Bypassing and Grounding are
issues related to the Output Lead Inductance. Every effort
should be made to keep the leads between the driver and it’s
load as short and wide as possible. If the driver must be placed
farther than 2” from the load, then the output leads should be
treated as transmission lines. In this case, a twisted-pair
should be considered, and the return line of each twisted pair
should be placed as close as possible to the ground pin of the
driver, and connect directly to the ground terminal of the load.
10K
R3
High Voltage
CMOS EN
Output
VDD
(From Logic
Power Supply)
3.3K
R1
Q1
2N3904
3.3K
or TTL Input)
9
R2
(To IXDD414
EN Input)
IXDD414PI/414YI/414CI
Ordering Information
Part Number
IXDD414PI
IXDD414YI
IXDD414CI
Package Type
8-Pin PDIP
5-Pin TO-263
5-Pin TO-220
Temp. Range
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
Grade
Industrial
Industrial
Industrial
NOTE: Mounting or solder tabs on all
packages are connected to ground
IXYS Corporation
3540 Bassett St; Santa Clara, CA 95054
Tel: 408-982-0700; Fax: 408-496-0670
e-mail: [email protected]
IXYS Semiconductor GmbH
Edisonstrasse15 ; D-68623; Lampertheim
Tel: +49-6206-503-0; Fax: +49-6206-503627
e-mail: [email protected]
Directed Energy, Inc.
An IXYS Company
2401 Research Blvd. Ste. 108, Ft. Collins, CO 80526
Tel: 970-493-1901; Fax: 970-493-1903
e-mail: [email protected]
10
Doc #9200-0228 R6