Jens Ejury July 13, 2006 San Jose, CA Data Sheet High-Performance DrMOS 6mm x 6mm x 0.8mm IQFN TDA21211- Data Sheet August - 2009 Published by Infineon Technologies AG http://www.infineon.com/DCDC Power Management & Drive N e v e r s t o p t h i n k i n g. Data Sheet Page 1 of 20 TDA21211 6x6 QFN High-Performance DrMOS Features: • Intel compliant DrMOS, Power MOSFET and Driver in one package • For Synchronous Buck - step down voltage applications • Maximum Average Current of 35A • Wide input voltage range +5V to +30V • Low power dissipation • Extremely fast switching technology for Type improved performance at high switching TDA21211 frequencies (>1MHz) • Remote Driver Disable function • Switching Modulation (SMOD#) of low side MOS • Marking 6x6x0.8mm3 PG-IQFN-40-1 TDA21211 Applications: Includes active PMOS structure as integrated bootstrap circuit for reduced part count • Shoot through protection • +5V High and Low Side Driving voltage • Compatible to standard PWM controller ICs with +3.3 and 5V logic • Three-State PWM input functionality • Small Package: IQFN40 (6 x 6 x 0.8 mm3) • RoHS Compliant Data Sheet Package Page 2 of 20 • Desktop and Server VR11.X and VR12 Vcore and non-Vcore buckconverters • Network and Telecom processor VR • Single Phase and MultiPhase POL • CPU/GPU Regulation in Notebook, Graphics Cards, and Gaming • Voltage Modules requiring high power density • Memory (DDR2/3) TDA21211 GH CGND BOOT VDRV VCIN SMOD# 9 NC 10 PHASE VIN VIN Pinout 8 7 6 5 4 3 2 1 VIN 11 40 PWM VIN 12 39 DISB# 38 NC VIN VIN 13 CGND VIN 14 37 CGND VSWH 15 36 GL PGND 16 35 VSWH PGND 17 34 VSWH PGND 18 33 VSWH PGND 19 32 VSWH PGND 20 31 VSWH 21 22 23 24 25 26 27 28 29 30 PGND PGND PGND PGND PGND PGND PGND PGND VSWH VSWH VSWH Note: Signals marked with "#" at the end are active low signals. Figure 1. Pinout, numbering and name of pins (Transparent Top View) Pin Description Pin Name Pin No. Description Remarks CGND 5, 37,CGND Pad Control signal ground Should be connected to PGND externally SMOD# 1 Low side gate disable pin when SMOD# is “low” the GL is OFF VCIN 2 Logic supply voltage 5V bias voltage for the internal logic. VDRV 3 FET gate supply voltage High & Low Side gate drive 5V BOOT 4 Bootstrap voltage pin Connect to boot capacitor GH 6 High side gate signal pin for monitoring gate of HS FET PHASE 7 Switch node output Internally connected to VSWH pin NC 8, 38 No connect Can be connected to any potential VIN 9 to 14, Vin Pad Input Voltage connection to the drain of the HS FET Switch node output high current output switch node VSWH 15, 29 to 35, VSWH Pad All of these pins must be connected to the power GND plane PGND 16 to 28 Power ground GL 36 Low side gate signal pin for monitoring gate of LS FET DISB# 39 Disable Signal (active low) pull to GND to disable the IC PWM 40 PWM drive logic input Data Sheet through multiple, low inductance vias. the three-state PWM input is compatible with 3.3V and 5V logic Page 3 of 20 TDA21211 General Description The Infineon TDA21211 is a multichip module that incorporates Infineon’s premier MOSFET technology for a single high side and a single low side MOSFET coupled with a robust, high performance, high switching frequency gate driver in a single 40 pin QFN package. The optimized gate timing allows for significant light load efficiency improvements over discrete solutions. State of the art MOSFET technology provides exceptional full load performance. Thus this device has a clear advantage over exisiting approaches in the marketplace when both full load and light load efficiencies are important. The Driver+MOSFET IC TDA21211 (DrMOS) is pin to pin compatible and compliant with the Intel 6x6 DrMOS specification. The device package height is only 0.8mm, and is an excellent choice for applications with critical height limitations. BLOCK DIAGRAM VCIN PHASE GU BOOT VDRV HS MOS HS Driver VIN Level Shifter UVLO 500k DISB# 500k HS Logic CGND VCIN Shoot Through Protection 33k Input Logic 3-State PWM 14k VSWH VDRV LS MOS CGND VCIN 400k SMOD# LS Logic LS Driver 600K CGND 500k PGND IC DRIVER CGND VDRV GL Figure 2. Simplified block diagram Data Sheet Page 4 of 20 TDA21211 Electrical Specification Table Absolute Maximum Ratings (Ta = 25°C) Item Symbol Rating Units Frequency fSW 1.2 MHz Average output current Iout 35 A Input voltage VIN (DC) -0.3 to +30 V Supply voltage VCIN (DC) -0.3 to +5.5 V High and Low side driver voltage VDRV (DC) -0.3 to +5.5 V Switch node voltage VSWH (DC) -1 to +30 V BOOT voltage VBOOT-PHASE (DC) -1 to +5.5 V SMOD# voltage VSMOD# (DC) -0.3 to +5.5 V DISB# voltage 1 VDISB -0.3 to +5.5 V Vpwm -0.3 to +5.5 V Operating junction temperature Tj-opr -40 to +150 °C Storage temperature Tstg -55 to +150 °C PWM voltage 1 Note: All rated voltages are relative to voltages on the CGND and PGND pins unless otherwise specified. 1 Latch Up class II- Level B (Jedec 78). Please refer to Quality Report for details. Thermal Characteristics Parameter Values Symbol Min. Thermal resistance, junction-soldering point 1 θJS Typ. Unit Max. 5 K/W Thermal resistance, junction-top of package 1 θJtop 20 junction-soldering point is referred to the VSWH bottom exposed pad. Data Sheet Page 5 of 20 TDA21211 Recommended Operating Conditions and Electrical Characteristics (VCIN = 5V, Ta = 25°C) Parameter Symbol Min Typ Units Test Conditions Input Voltage VIN Driving Voltage VDRV Bias Supply Voltage VCIN 4.5 5 5.5 UVLO Rising VUVLO_R 2.9 3.5 3.9 VCIN rising UVLO Falling VUVLO_F 2.5 3.1 3.3 VCIN falling Driver Current IC Current (Control) IC quiescent 5 Max 25 5 V IVDRV_300kHz 10 mA DISB# = 5V, fSW = 300kHz IVDRV_PWML 25 µA DISB# = 5V, PWM = 0V IVCIN_PWML 250 µA IVCIN_O 370 µA ICIN+IDRV 270 µA DISB# = 5V, PWM = 0V SMOD# = Open DISB# = 5V, PWM = Open SMOD# = Open DISB# = 0V PWM SMOD# DISB# Logic Inputs and Thresholds Input low VDISB_L 0.7 1.1 1.3 Input high VDISB_H 1.9 2.1 2.4 Sink Current IDISB Input low VSMOD#_L 0.7 1.1 1.3 Input high VSMOD#_H 1.9 2.1 2.4 Open Voltage VSMOD#_O 3.0 Sink Current ISMOD# -8 Input low VPWM_L Input high VPWM_H 2.4 Input resistance RIN-PWM 6.5 Open Voltage VPWM_O Tri-state Shutdown Window VPWM_S 2 µA 0.7 9.5 12.5 1.5 1.2 V VDISB falling VDISB rising VDISB = 1V VSMOD# falling V VSMOD# rising µA VSMOD# = 1V V VPWM falling VPWM rising kΩ VPWM = 1V V VPWM_O ns GH, GL unloaded. 1.9 Dynamic Characteristic Three State to GL/GH rising propagation delay GL/GH Three State Shutdown Hold-Off time, T_pts 15 T_tsshd 240 GH Turn-on propagation delay T_pdhu 15 GH Turn-off propagation delay T_pdlu 20 GL Turn-on propagation delay T_pdhl 20 GL Turn-off propagation delay T_pdll 10 T_pdl_DISB 20 T_pdh_DISB 20 DISB#Turn-off propogation delay falling DISB#Turn-on propogation delay rising 1 Unless otherwise specified, VCIN=VDRV Data Sheet Page 6 of 20 TDA21211 Typical Application VCIN VIN +5 V +12 V Cboot Rboot + 3.3 V VDD VIN_SEN PHASE VIN BOOT VCIN VID7 SEN1N PWM1 VID6 SEN1P ISEN1N VID5 ISEN1P VID4 PWM2 VID3 ISEN2N VID2 ISEN2P VID1 PWM3 VID0 PSI# OUTEN PWM2 PWM Rboot PHASE VIN BOOT L VSWH VCIN PWM Cb Rb TDA 21211 VDRV PGND CGND SEN2N ISEN3N SEN2P Cboot ISEN3P PWM4 Rboot VIN BOOT VR_READY ISEN4N FAULT1 ISEN4P VDRV FAULT2 PWM5 PWM3 PWM FAULT3 ISEN5N SEN3N SDA SEN3P ISEN5P SCL PWM6 SADDR_M PGND CGND Cboot Cb Rb TDA 21211 VDRV PX3560PWM1 L VSWH PHASE L VSWH VCIN PGND CGND Cboot ISEN6N VIN BOOT ISEN6P VCIN Cb Rb TDA 21211 Rboot PHASE L VSWH VDRV TDA 21211 PWM CGND Rb Cb SADDR_L PWM4 VD25 PGND SEN4N GND SEN4P VOUT VSENP VSENP COUT VSENN VSENN Figure 3. Four Phases Voltage Regulator Typical Application (Simplified Schematic) Data Sheet Page 7 of 20 TDA21211 Theory of Operation The TDA21211 incorporates a high performance gate driver, one high side power MOSFET and one low-side power MOSFET in a single 40 lead QFN package. The advantages of this arrangement are found in the areas of increased performance, increased efficiency and lower overall package and layout inductance.This module is ideal for use in Synchronous Buck Regulators either as a stand-alone power stage that can deliver up to 35A or with an interleaved approach for higher current loads. The power MOSFETs are tailored for this device. The gate driver is an extremely robust high-performance driver rated at the switching node for DC voltages ranging from -1V to +30V. The closely coupled driver and MOSFETs enable efficiency improvements that are hard to match using discrete components. The power density for transmitted power of this approach is approximately 30W within a 36mm2 area. Driver Characteristics The gate driver of the TDA21211 has 2 voltage inputs, VCIN and VDRV. VCIN is the 5V bias supply for the driver. VDRV is also 5V and is used to drive the High and Low Side MOSFETs. Ceramic capacitors should be placed very close to these input voltage pins to decouple the sensitive control circuitry from a noisy environment. The MOSFETs selected for this application are optimized for 5V gate drive, thus giving the end user optimized high load as well as light load efficiency. The reference for the power circuitry including the driver output stage is PGND and the reference for the gate driver control circuit (VCIN) is CGND. Referring to the Block Diagram, Figure 2 VCIN is internally connected to the UVLO circuit and for VCIN voltages less than required for proper circuit operation will provide shut-down. VDRV supplies both, the floating high side drive and the low-side drive circuits. An active boot circuit for the high side gate drive is also included. A second UVLO circuitry, sensing the BOOT voltage level, is implemented to prevent false GH turn on during insufficient power supply level condition (BOOT Cap charging/discharging sequence). During undervoltage both GH and GL are driven low actively; further passive pull down (500k Ohm) is placed on each gate. Note: output signal from UVLO unit. UVLO Output Logic Level “H” Enable Shutdown “L” VUVLO_F Data Sheet VUVLO_R Page 8 of 20 VCIN TDA21211 Inputs to the internal control circuit are PWM, DISB# and SMOD#: The PWM is the control input to the IC from an external PWM controller and is compatible with 3.3V and 5V logic. The PWM input has three-state functionality. When the voltage remains in the specified PWM-shutdown-window for at least the PWM-shutdown-holdoff time T_tsshd, the operation will be suspended by keeping both MOSFET gate outputs low. Once left open, the pin is internally fixed to VPWM_O = 1.5 V level PWM Driver Output L GL=H, GH = L H GL=L, GH = H Open GL=L, GH = L The DISB# is an active low signal. When DISB# is pulled low, the power stage is disabled. DISB# Driver Output L Shutdown Æ GL, GH = L H EnableÆ GL, GH = “Active” Open Shutdown Æ GL, GH = L The SMOD# feature is provided to disable the low-side MOSFET during active operation. When synchronized with the PWM signal (as shown in Figure 7), SMOD# is intended to improve light load efficiency by saving the gate charge loss of the low-side MOSFET. Once left open, the pin is internally fixed to VSMOD#_O = 3 V level. SMOD# GL Status L L H Enable Æ GL= “Active” Open Enable Æ GL= “Active” The TDA21211 driver includes gate drive functionality to protect against shoot through. In order to protect the power stage from overlap, both HS and LS MOSFETs being on at the same time, the adaptive control circuitry monitors the voltage at the “VSWH” pin. When the PWM signal goes low, HS, the High-side MOSFET will begin to turn off, after the propagation delay (T_pdlu). Once the “VSWH” pin falls below 1V, LS, the Low-side MOSFET is gated on after the predefined delay time, (T_pdhl). Additionally, the gate to source voltage of the HS-MOSFET is also monitored. When VGS(HS) is discharged below 1V, a threshold known to turn HS off, a secondary delay is initiated, (T_pdhl), which results in LS being gated “ON” irregardless of the state of the “VSWH” pin.This way it will be ensured that the converter can sink current efficiently and the bootstrap capacitor will be refreshed appropriately during each switching cycle. See Figure 5 for more detail. GH and GL are monitoring pins to check the internal gate drive signals. Data Sheet Page 9 of 20 TDA21211 +5v CBOOT 0.1 ÷ 1u F 1u F RBOOT CGND CIN 10 9 8 7 6 5 4 3 SMOD VCIN VDRV BOOT CGND GH NC VIN VIN (+ 5 ÷ 24 v) PHASE 0÷5Ω 2 CGND 1 PWM 4x10u F 11 40 12 39 DISB# VIN CGND VIN 13 14 37 CGND VSWH 15 36 GL PGND 16 35 VSWH 17 34 VSWH 18 33 19 32 20 31 Power GND 22 23 24 25 26 27 28 PGND 21 29 30 L VOUT VSWH Signal GND 38 NC Figure 4. Pin interconnection outline (Transparent Top View) NOTE: RBOOT value is related to the input voltage level. Pin PHASE is internally connected to VSWH node. Data Sheet Page 10 of 20 TDA21211 Gate Driver Timing Diagrams VPWM_H VPWM_H Three State VPWM_L VPWM_L PWM T_pdll T_tsshd T_pts GL T_pdhl 1V T_tsshd T_pdlu T_pts T_pdhu GH 1V VSWH Note: VSWH during entering/exit to tristate behaves accordingly to inductor current. Figure 5: Adaptive Gate Driver Timing Diagram Data Sheet Page 11 of 20 TDA21211 DISBL# VDISB_H VDISB_L T_pdh(DISB) T_pdl(DISB) GH/GL Figure 6: Disable Timing Diagram SMOD SMOD disabled SMOD active PWM GL T_pdlu T_pdlu VSWH T_pdlu DCM CCM CCM Figure 7 SMOD# Timing Diagram Data Sheet Page 12 of 20 TDA21211 Test Circuit IIN VIN A CIN V ICIN VCIN A V CCIN IDRV VDRV A CDRV V VDRV PWM VIN PWM BOOT CBOOT PHASE VCIN TDA21211 VOUT VSWH DISBL# PX3560 L 300n H SMOD# Rb CGND IOUT Cb PGND ISENN ISENP VSENP COUT VSENN Figure 8. Test Circuit Efficiency = POUT PIN PIN = VDRV × I DRV + VCIN × I CIN + VIN × I IN POUT = VOUT × I OUT PLOSS = PIN − POUT Data Sheet Page 13 of 20 TDA21211 Performance Curves – Typical Data Operating conditions (unless otherwise specified): VIN= +12V, VCIN=VDRV= +5V, VOUT=1.1 V, F=362k Hz, 300nH inductor (VITEC59P9081N01, DCR (typ) =0.43m Ω) TA=25° C, load line=0mΩ, airflow=100 LFM, no heatsink. Power Efficiency and Power Loss data reported herein includes TDA21211 and inductor losses but no other system losses (unless otherwise specified). 94 7 1.6V 1.5V 1.2V 1.0V 0.8V 92 0.8V 1.2V 1.5V 90 1.6V 5 Power Loss (W) Efficiency (%) 1.0V 6 88 86 4 3 84 2 82 1 80 0 0 5 10 15 20 Output Current (A) 25 30 0 Figure 9. Efficiency vs. VOUT 10 15 20 Output Current (A) 25 30 25 30 Figure 10. Power Loss vs. VOUT 94 7 296Khz 592Khz 465Khz 362Khz 92 6 407Khz 407Khz 362Khz 465Khz 296Khz 592Khz 5 Power Loss (W) 90 Efficiency (%) 5 88 86 4 3 84 2 82 1 80 0 0 5 10 15 20 25 0 30 Output Current (A) Figure 11. Efficiency vs. Switching Frequency Data Sheet 5 10 15 20 Output Current (A) Figure 12. Power Loss vs. Switching Frequency Page 14 of 20 TDA21211 94 7 10V 12V 14V 92 18V 6 16V 18V 20V 16V 14V 12V 5 Power Loss (W) 90 Efficiency (%) 20V 88 86 4 3 84 2 82 1 80 10V 0 0 5 10 15 20 Output Current (A) 25 30 0 Figure 13. Efficiency vs. VIN 5 25 30 Figure 14. Power Loss vs. VIN 94 7 105C 25C 65C 92 85C 6 85C 65C 25C 105C 90 5 Power Loss (W) Efficiency (%) 10 15 20 Output Current (A) 88 86 4 3 84 2 82 1 80 0 0 5 10 15 20 Output Current (A) 25 30 0 Figure 15. Efficiency vs. TCASE Data Sheet 5 10 15 20 Output Current (A) 25 Figure 16. Power Loss vs. TCASE Page 15 of 20 TDA21211 30 7 1,20 Vin=12V Vin=12V VCIN=VDRV=5V 6 1,15 Vout=1.3V Vout=1.3V F=600kHz 5 1,10 Power Loss (W) L=510nH 1,05 3 1,00 2 0,95 1 0,90 0 0 Iout=25A L=510nH T= 25° C 4 VCIN=VDRV=5V 5 10 15 20 25 30 0,85 300 Output Current (A) T= 25° C 400 500 600 700 800 900 1000 Switching Frequency (kHz) Figure 17. Power Loss vs. Iout Figure 18. Normalized Power Loss @ Iout=25 A (inductor losses not included) (inductor losses not included) 35 Vin=12V 30 VCIN=VDRV=5V Vout=1.3V 25 Iout=25A IDRV + ICIN (mA) L=510nH 20 T= 25° C 15 10 5 0 100 200 300 400 500 600 700 800 900 1000 Switching Frequency (kHz) Figure 19. Power Supply Current (IDRV + ICIN) vs. Fsw Data Sheet Page 16 of 20 TDA21211 Package Outline PIN#1 IDENT Data Sheet Page 17 of 20 TDA21211 Figure 20: Footprint and Solder Stencil Recommendation Data Sheet Page 18 of 20 TDA21211 PCB Layout Example. Figure 21 Single Phase DrMOS typical Application Circuit Figure 22 Single Phase DrMOS PCB Layout Example (Top Side View) (for DrMOS Design support a customer PCB layout guide is available upon request) Data Sheet Page 19 of 20 TDA21211 For questions on technology, delivery and prices please contact the Infineon Technologies Offices in Germany or the Infineon Technologies Companies and Representatives worldwide: see the address list on the last page or our webpage at http://www.infineon.com/DCDC CoreControlTM, OptiMOS™ and OptiMOS II™ are trademarks of Infineon Technologies AG. We listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continously improve the quality of this document. Edition 2004-11-10 Published by Infineon Technologies AG, St.-Martin-Strasse 53, D-81541 München © Infineon Technologies AG 2004. All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as warranted characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Infineon Technologies is an approved CECC manufacturer. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide (see address list). Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. Data Sheet Page 20 of 20 TDA21211