ICs for Communications Primary Rate Access Clock Generator and Transceiver PRACT PEB 22320 Version 2.1 Data Sheet 04.95 PEB 22320 Revision History Current Version: 04.95 Previous Version: 05.93 Page Subjects (changes since last revision) 10 Architecture of the PRACT 14 Input Jitter Specification 16 Jitter Attenuator Block Diagram 17 Clock- and Synchronization Table 18 Jitter Attenuation Characteristics 23 Master/Slave Selection 24 Reset 28 Delay Times 29 DC Characteristics 31 Recommended Oscillator Circuits 32, 33 Crystal Tuning Range Data Classification Maximum Ratings Maximum ratings are absolute ratings; exceeding only one of these values may cause irreversible damage to the integrated circuit. Characteristics The listed characteristics are ensured over the operating range of the integrated circuit. Typical characteristics specify mean values expected over the production spread. If not otherwise specified, typical characteristics apply at TA = 25 °C and the given supply voltage. Operating Range In the operating range the functions given in the circuit description are fulfilled. For detailed technical information about “Processing Guidelines” and “Quality Assurance” for ICs, see our Product Overview “ICs for Communications” PEB 22320 General Information Page Table of Contents 1 1.1 1.2 1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Pin Configuration (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 System Integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 2 2.1 2.1.1 2.1.2 2.1.3 2.1.4 2.2 2.2.1 2.2.2 2.3 2.4 2.5 2.6 2.7 2.8 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Basic Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Clock and Data Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Input Jitter Tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Jitter Attenuator and Clock Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Basic Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Output Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Local Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Remote Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Bypass Jitter Attenuator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Microprocessor Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Receiver Loss of Signal Indication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Master/Slave Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 3 3.1 3.1.1 3.1.2 3.2 Operational Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Reset with CS Pin Fixed to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Reset Using CS Pin to Latch Programming (a controller is used) . . . . . . . . .26 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 4 4.1 4.2 4.2.1 4.2.2 4.3 4.4 4.5 4.6 4.6.1 4.6.2 4.6.3 4.6.4 Electrical Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 Delay Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 Delay from XDIP/XDIN to XL1/XL2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 Delay from RL1/RL2 to RDOP/RDON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 Recommended Oscillator Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 Dual Rail Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 System Clock Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 Microprocessor Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 XTAL Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 Semiconductor Group 3 PEB 22320 4.7 4.8 Pulse Templates - Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 Overvoltage Tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 5 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 IOM®, IOM®-1, IOM®-2, SICOFI®, SICOFI®-2, SICOFI®-4, SICOFI®-4µC, SLICOFI®, ARCOFI® , ARCOFI®-BA, ARCOFI®-SP, EPIC®-1, EPIC®-S, ELIC®, IPAT®-2, ITAC®, ISAC®-S, ISAC®-S TE, ISAC®-P, ISAC®-P TE, IDEC®, SICAT®, OCTAT®-P, QUAT®-S are registered trademarks of Siemens AG. MUSAC™-A, FALC™54, IWE™, SARE™, UTPT™, ASM™, ASP™ are trademarks of Siemens AG. Purchase of Siemens I2C components conveys a license under the Philips’ I2C patent to use the components in the I2C-system provided the system conforms to the I2C specifications defined by Philips. Copyright Philips 1983. Semiconductor Group 4 Primary Rate Access Clock Generator and Transceiver PRACT PEB 22320 Preliminary Data 1 CMOS Features • ISDN line interface for 1544 and 2048 kbit/s (T1 and CEPT) • Data and clock recovery • Transparent to ternary codes • Low transmitter output impedance for a high return loss with reasonable protection resistors (CCITT G.703 requirements for the line input return loss P-LCC-44 fulfilled) • Adaptively controlled receiver threshold • Programmable pulse shape for T1 applications • Jitter specifications of CCITT I.431 and BELLCORE TR-NWT-000499 publications met • Wander and jitter attenuation • Jitter tolerance of receiver: 0.5 UI s • Implements local and remote loops for diagnostic purposes • Monolithic line driver for a minimum of external components • Low power, reliable CMOS technology • Loss of signal indication for receiver • Clock generator for system clocks Type Ordering Code Package PEB 22320 N Q67100-A6059 P-LCC-44 (SMD) The Primary Rate Access Clock Generator and Transceiver PRACT (PEB 22320) is a monolithic CMOS device which implements the analog receive and transmit line interface functions to primary rate PCM carriers. It may be programmed or hard wired to operate in 1.544-Mbit/s (T1) or 2.048-Mbit/s (CEPT) carrier systems. The PRACT recovers clock and data using an adaptively controlled receiver threshold. It will meet the requirement of CCITT I.431 and Bellcore TR-NWT-000499 Issue 5, December 1993 (Transport System Generic Requirements) in case of pulse shape, jitter tolerance and jitter transfer characteristic. Semiconductor Group 5 04.95 PEB 22320 Features Specially designed line interface circuits simplify the tedious task of protecting the device against overvoltage damage while still meeting the return loss requirements. The PRACT is suitable for use in a wide range of voice and data applications such as for connections of digital switches and PBX’s to host computers, for implementations of primary ISDN subscriber loops as well as for terminal applications. The maximum range is determined by the maximum allowable attenuation. In the T1 case the PRACT’s power consumption is mainly determined by the line length and type of the cable. Semiconductor Group 6 PEB 22320 Features 3 2 CLK2M RL2 V DD2 4 V SSR LL 5 JATT V DDR CLK4M 6 RL1 CLK4M Pin Configuration (top view) FSC 1.1 1 44 43 42 41 40 FSC 7 39 CLK2M LS0 8 38 RCLK XTAL4 9 37 RDON XTAL3 10 36 LS1 11 35 RDOP V SSD XTAL2 12 34 V DDD XTAL1 13 33 CS LS2 14 32 XCLK CLK16M 15 31 XDIP CLK12M 16 30 XDIN SYNC 17 29 XTIP PRACT PEB 22320 Semiconductor Group 7 XTIN RL MODE N.C. XL2 V SSX N.C. V SSX XL1 V DDX V DDX 18 19 20 21 22 23 24 25 26 27 28 ITP04874 PEB 22320 Features 1.2 Pin Definitions and Functions Pin Definitions and Functions Pin No. Symbol Input (I) Function Output (O) 1 VDD2 O Reference voltage for tapping the input transformer 2 RL2 I Line receiver pin 2 3 LL I Local loopback: A high level selects the device for the local loopback mode. 4 5 CLK4M CLK4M O O System clock 4.096 MHz inverted and non-inverted 6 7 FSC FSC O O 8-kHz frame synchronization pulse inverted and non-inverted 8 LS0 I Line length select 9 10 XTAL4 XTAL3 O I Crystal connection 12.352 MHz If an external clock generator is used and T1 mode is selected the PRACT works as a master. 11 LS1 I Line length select 12 13 XTAL2 XTAL1 O I Crystal connection 16.384 MHz When an external clock is used, normally if the MODE pin is set high, the PRACT functions as a master. 14 LS2 I Line length select 15 CLK16M O System clock 16.384 MHz 16 CLK12M O System clock 12.352 MHz 17 SYNC I If a clock is detected at the SYNC pin the PRACT synchronizes to this clock (2.048 MHz for CEPT, 1.544 MHz for T1). (Please refer to table 3). 18, 19 VDDX I Positive power supply for transmit subcircuits 20 XL1 O Line transmit pin 1 21, 25 N.C. 22, 23 VSSX I Ground for transmit subcircuits 24 XL2 O Line transmit pin 2 Semiconductor Group not connected 8 PEB 22320 Features Pin Definitions and Functions (cont’d) Pin No. Symbol Input (I) Function Output (O) 26 RL I Remote loopback: High level puts the device to the remote loopback mode. 27 MODE I Master/Slave selection If the MODE pin is set to a low level the PRACT functions as a slave. (Please refer to table 3) 28 29 XTIN XTIP I I Positive and negative test data inputs, active low, full bauded 30 31 XDIN XDIP I I Positive and negative data inputs, active low, full bauded 32 XCLK I/O If the T1 mode is selected the XCLK is a clock output with a clock frequency of 1.544 MHz. Otherwise the XCLK is a clock input whose frequency is 2.048 MHz. (Please refer to table 3) 33 CS I Chip Select: A low level selects the PEB 22320 for a register write operation. 34 I Positive power supply for the digital subcircuits. 35 VDDD VSSD I Power ground supply for digital subcircuits. 36 37 RDOP RDON O O Receive data output positive and negative, fully bauded, active low. 38 RCLK O Receive clock refer to table 3. 39 40 CLK2M CLK2M O O System clock 2.048 MHz inverted and non-inverted. 41 I Power ground supply for receive subcircuits. 42 VSSR VDDR I Positive power supply for the receive subcircuits. 43 JATT I If the JATT pin is set to a low level the jitter attenuator is bypassed. 44 RL1 I Line receiver pin 1. Semiconductor Group 9 PEB 22320 Features 1.3 System Integration Figure 1 shows the architecture of a primary access board for data transmission. It exhibits the following functions: – – – – – – – – – – Line Interface (PEB 22320, PRACT) Clock and Data Recovery (PEB 22320, PRACT) Jitter Attenuation (PEB 22320, PRACT) Clock Generation (PEB 22320, PRACT) Coding/Decoding (PEB 2035, ACFA) Framing (PEB 2035, ACFA) Elastic Buffer (PEB 2035, ACFA) Multichannel Protocol Controller (PEB 20320, MUNICH32) System Adaptation (PEB 20320, MUNICH32) µP Interface (all devices) MPU Memory MUNICH32 PEB 20320 ACFA PEB 2035 PC Interface TCLK/RCLK TSP/RSP SYPQ PRACT PEB 22320 SCLK CLK4M FSC FSC CLK2M 4.096 MHz 8 kHz 8 kHz 2.048 MHz ITS04875 Figure 1 Architecture of the PRACT Semiconductor Group 10 PEB 22320 Functional Description Functional Description MODE SYNC JATT RL1 Receive Input RL2 Local Loop LL XTIP Transmit XTIN Test Data Receiver Clock & Data Recovery Loss of Signal Detection XL1 Transmit Output XTAL1, 2, 3, 4 RRCLK P N Jitter Attenuator & Clock Generator LOS Driver D/A XCLK (T1) System Clocks ROM Timing & Pulseshaper Remote Loop 2 XL2 LS0, 1, 2 Figure 2 Functional Block Diagram of the PRACT Semiconductor Group 11 RL RCLK RDOP RDON XDIP XDIN XCLK (CEPT) ITB04876 PEB 22320 Functional Description 2.1 Receiver 2.1.1 Basic Functionality The receiver recovers data from the ternary coded signal at the ternary interface and outputs it as 2 unipolar signals at the dual rail interface. One of the lines carries the positive pulses, the other the negative pulses of the ternary signal. The signal at the ternary interface is received at both ends of a center-tapped transformer as shown in figure 3. . R L1 t 11 R2 t2 Line VDD 2 R2 t 12 R L2 ITS00560 Figure 3 Receiver Configuration The transformer is center-tapped at the PRACT side. The recommended transmission factors for the different line characteristic impedances are listed in table 1. Table 1 Recommended Receiver Configuration Values Application T1 CEPT Characteristic Impedances [Ω] 100 140 (ICOT) 120 75 R2 ± (2.5%) [Ω] 28.7 39.2 60 60 t2 : t1 = t2 : (t11 + t12) 69:52 69:52 69:(26 + 26) 69:(26 + 26) 52:52 41:52 52:(26 + 26) 41:(26 + 26) Wired in this way the receiver has a return loss ar > 12 dB ar > 18 dB ar > 14 dB for for for 0.025 fb 0.05 fb 1.0 fb ≤f ≤ ≤f ≤ ≤f ≤ 0.05 fb, 1.0 fb and 1.5 fb, with fb being 2048 kHz. Thus it complies with CCITT G.703. Semiconductor Group 12 PEB 22320 Functional Description The receiver is transparent to the logical 1’s polarity and outputs positive logical 1’s on RDOP and negative logical 1’s on RDON. RDON and RDOP are active low and fully bauded. The comparator threshold to detect logical 1’s and logical 0’s is automatically adjusted to be 45% of the peak signal level. Provided the noise is below 10 µV/√Hz the bit error rate will be less than 10–7. 2.1.2 Clock and Data Recovery An analog PLL extracts the internal recovered route clock RRCLK from the data stream received at the RL1 and RL2 lines. The PLL uses as a reference the system clock CLK16M for CEPT and CLK12M for T1 applications. The clock and data recovery is tolerant to long strings of consecutive zeros, because the data sampler will continuously sample data based on its last input. A block diagram of the clock and data recovery circuit is shown in figure 4. Data Sampling Input Data derived from RL 1, 2 PD Filter Figure 4 Clock and Data Recovery Circuit Semiconductor Group 13 P Data N VCO RRCLK CLK16M (CEPT) CLK12M (T1) ITS04877 PEB 22320 Functional Description 2.1.3 Input Jitter Tolerance The PRACT receiver’s tolerance to input jitter complies to CCITT and Bellcore requirements for CEPT and T1 application. Figure 5 shows the curves of the different input jitter specifications stated above as well as the PRACT performance for the various line codes used at the S1/S2 interfaces. In figure 5 the curves show that the PRACT at low frequencies has more than 20 dB/ decade fall off, and at high frequencies is in a steady state of 0.5 UI (horizontal). ITD06576 100 TR-NWT 000499 Cat I TR-NWT 000499 Cat II PRACT CEPT PRACT T1 CCITT G.823 Jitter Input Tolerance UI 10 1 0.1 1 10 100 1000 10000 Jitter Frequency Figure 5 Comparison of Input Jitter Specification and PRACT Performance Semiconductor Group 14 Hz 100000 PEB 22320 Functional Description Table 2 Jitter Input Tolerance Frequency Hz 1 10 20 192.9 500 2400 6430 8000 10000 18000 20000 25000 40000 50000 100000 2.1.4 CCITT G.823 2.9 TR-NWT 000499 Cat I TR-NWT 000499 Cat II 5 10 PRACT PRACT CEPT T1 90 5.8 70 4.5 1.15 0.95 0.62 0.58 0.55 0.5 0.55 0.55 0.95 0.8 0.58 0.55 0.55 0.5 0.55 0.55 1.5 10 5 1.5 0.3 0.1 0.2 0.1 0.3 Jitter Attenuator and Clock Generator The jitter attenuator reduces wander and jitter in the recovered clock which are produced by the line-, clock- and data-recovery characteristics. The attenuator consists of one PLL with a tunable crystal oscillator and a 288-bit FIFO. To provide for T1 mode a 1.544-MHz clock (XCLK) and a 2.048-MHz clock (CLK2M) for the system, a second PLL is placed in series with the first one (refer to figure 6). If the JATT pin is set to low the FIFO is bypassed and the propagation delay from RL1, 2 to RDOP/RDON is reduced by the pass time of the FIFO. After loss of signal detection, the internal PLL is synchronized to the 2.048 MHz (CEPT) provided at the SYNC pin (1.544 MHz in the case of T1). If this SYNC pin is not connected or connected to logical zero, the PRACT switches automatically to master operating mode (refer to table 3). With the MODE pin a master selection is provided. That means if the MODE pin is set to high the master function is selected in which the VCO’s of the jitter attenuator are centered (± 50 ppm of the crystal frequencies). If a clock is detected at the SYNC pin the PRACT automatically synchronized to this clock. Semiconductor Group 15 PEB 22320 Functional Description The jitter attenuator meets the jitter transfer requirements of the Bellcore TR-NWT 000 499 and Rec. I.431 (refer to figure 7 and table 4). The amount of generated output jitter when no input jitter is shown in table 5. JATT FIFO W RL1, 2 Clock & Data Recovery R P Data N Data RDOP RDON RCLK RRCLK MODE SYNC LOS 12.352 MHz <_ 193 8 kHz PD VCO <_ 193 <_ 8 <_ 256 12 MHz 1.5 MHz (XCLK-T1) T1 16.384 MHz <_ 256 8 kHz PD VCO <_ 2 <_ 4 2 MHz 4 MHz Figure 6 Jitter Attenuator Block Diagram Semiconductor Group 16 16 MHz ITB04879 1.5 M 1.5 M 1 1 X X X 0 1 1 X X X 0 1 1 X X X 0 1 1 X X X 1 1 1 1 1 Semiconductor Group 1 1 1 1 1 1 0 0 0 17 0 0 0 0 0 0 0 0 0 X 1 1 0 0 0 X 1 1 0 0 0 X 1 1 0 0 0 X 1 1 0 0 0 Pin MODE CEPT CEPT CEPT CEPT CEPT CEPT T1 T1 T1 T1 T1 T1 CEPT CEPT CEPT CEPT CEPT CEPT T1 T1 T1 T1 T1 T1 Pin LS0..2 LOS = 0: Input above receiver threshold LOS = 1: Input below receiver threshold JATT = 1: Jitter attenuator enabled JATT = 0: Bypass jitter attenuator X 0 2M 2M 0 X X 0 1.5 M 1.5 M 0 X X 0 2M 2M 0 X X 0 0 X 0 1 Pin SYNC Int. Sig LOS Pin JATT X X N.C. 16 M in N.C. 16 M Crystal 16 M Crystal 16 M Crystal 16 M Crystal 16 M Crystal 16 M Crystal 16 M Crystal 16 M Crystal 16 M Crystal 16 M Crystal 16 M Crystal 16 M in 16 M Crystal 16 M Crystal 16 M Crystal 16 M Crystal 16 M Crystal 16 M Crystal 16 M Crystal 16 M Crystal 16 M Crystal 16 M Crystal 16 M in 16 M crystal sync. freq. centered 16 M crystal sync. on SYNC 16 M crystal sync. on SYNC 16 M crystal sync. freq. centered 16 M crystal sync. on RRCLK 16 M crystal sync. on XCLK 16 M crystal sync. on XCLK 16 M crystal sync. on XCLK 16 M crystal sync. on XCLK 16 M crystal sync. on XCLK 16 M crystal sync. on XCLK 16 M in 16 M crystal sync. freq. centered 16 M crystal sync. on SYNC 16 M crystal sync. on SYNC 16 M crystal sync. freq. centered 16 M crystal sync. on RRCLK 16 M crystal sync. on XCLK 16 M crystal sync. on XCLK 16 M crystal sync. on XCLK 16 M crystal sync. on XCLK 16 M crystal sync. on XCLK 16 M crystal sync. on XCLK System Clocks 4M, 2M, 8K Derived from Pin XCLK =RRCLK =RRCLK =RRCLK =RRCLK =RRCLK =RRCLK =RRCLK =RRCLK =RRCLK =RRCLK =RRCLK =RRCLK =2 M =2 M =2 M =2 M =2 M =2 M =1.5 M =1.5 M =1.5 M =1.5 M =1.5 M =1.5 M Pin RCLK MODE = 0 Slave mode selected MODE = 1: Master mode selected 8k = 8.0 kHz = don’t care X N.C. = No Connection input (2 M from ACFA) input (2 M from ACFA) input (2 M from ACFA) input (2 M from ACFA) input (2 M from ACFA) input (2 M from ACFA) output: 1.5 M sync. on XTAL3 output: 1.5 M freq. centered output: 1.5 M sync. on SYNC output: 1.5 M sync. on SYNC output: 1.5 M, freq. centered output: 1.5 M sync. on RRCLK input (2 M from ACFA) input (2 M from ACFA) input (2 M from ACFA) input (2 M from ACFA) input (2 M from ACFA) input (2 M from ACFA) output: 1.5 M sync. on XTAL3 output: 1.5 M freq. centered output: 1.5 M sync. on SYNC output: 1.5 M sync. on SYNC output: 1.5 M, freq. centered output: 1.5 M sync. on RRCLK RRCLK = Internal recovered route clock SYNC = 0: Input tied to low SYNC = 2 M: Input connected to 2 M SYNC = 1.5 M: Input connected to 1.5 M Pin XTAL2 16 M Crystal Pin XTAL1 12 M = 12.352 MHz 16 M = 16.384 MHz 4 M = 4.096 MHz 2 M = 2.048 MHz 1.5 M = 1.544 MHz X X X X X X X X N.C X X X X 12 M in 12 M Crystal 12 M Crystal 12 M Crystal 12 M Crystal 12 M Crystal X X X X X X X X N.C. Pin XTAL4 X X 12 M in 12 M Crystal 12 M Crystal 12 M Crystal 12 M Crystal 12 M Crystal Pin XTAL3 PEB 22320 Functional Description Table 3 Clock and Synchronization Table PEB 22320 Functional Description ITD06577 2 0 dB Jitter Transfer Characteristics -10 -20 -30 -40 CCITT G.735 CCITT I.431 TR-NWT 000499 Cat I to Cat I PRACT CEPT PRACT T1 -50 -60 1 0.1 10 100 1000 10000 Hz 100000 Jitter Frequency Figure 7 Jitter Attenuation Characteristics Table 4 Jitter Transfer Characteristics Frequency CCITT G. 735 TR-NWT 000499 PRACT PRACT Hz CCITT I.431 Cat I to Cat II CEPT T1 0.3 0.00 1 3 10 0.5 0.5 100 Semiconductor Group – 20.00 – 20.00 – 40.00 0.10 30 40 0.00 18 PEB 22320 Functional Description Table 4 Jitter Transfer Characteristics (cont’d) Frequency CCITT G. 735 TR-NWT 000499 PRACT PRACT Hz CCITT I.431 Cat I to Cat II CEPT T1 – 39.40 – 60.00 – 60.00 – -80.00 200 250 300 350 400 – 19.50 9650 1000 1412 2500 – 34.07 3000 10000 15000 – 19.50 – 49.63 Table 5 Generated Output Jitter Specification I.431 Measurement Filter Bandwidth Lower Cutoff Upper Cutoff (UI peak to peak) 20 Hz 700 Hz 100 kHz 100 kHz ≤ 0.125 ≤ 0.02 8 kHz 40 kHz 40 kHz ≤ 0.02 ≤ 0.025 ≤ 0.025 PUB 62411 Dez. 90 10 Hz 8 kHz 10 Hz broad band ETS 300 011 Semiconductor Group Output Jitter 40 Hz 100 kHz 19 ≤ 0.05 ≤ 0.11 PEB 22320 Functional Description 2.2 Transmitter 2.2.1 Basic Functionality The transmitter transforms unipolar data to ternary (alternate bipolar) return to zero signals of the appropriate shape. The unipolar data is provided at XDIP (positive pulses) and XDIN (negative pulses), synchronously with the transmit clock XCLK. XDIP and XDIN are active low and full bauded. Data is sampled on the falling edge of the input clock (XCLK). The input clock (XCLK) must be derived from the (system) clocks generated by the PRACT. This ensures the recommended fixed relationship between XLCK and internal generated clock (4 times XCLK) for the pulse shaper. The transmitter includes a programmable pulse shaper to satisfy the requirements of the AT&T Technical Advisory # 34 at the cross connect point for T1 applications. The pulse shaper is programmed via the line length selection pins LS0, LS1 and LS2. For T1 application the line length selection supports both low capacitance cable with a characteristic line capacitance of C’ ≤ 40 nF/km = 65 nF/mile (e.g. MAT, ICOT) and higher capacitance cable with a characteristic line capacitance of 40 nF/ km ≤ C’ ≤ 54 nF/km (65 nF/mile ≤ C’ ≤ 87 nF/mile) e.g. ABAM, PIC and PULP cables. This ensures that for various cable types the signal at the DSX-1 cross connect point complies with the pulse shape of the AT&T Technical Advisory # 34. The line length is selected programming the LS0, LS1 and LS2 pins as shown for typical values in table 6. Table 6 Line Length Selection LS2 LS1 LS0 0 0 0 CEPT 0 0 0 1 1 0 T1/G.703 T1 0 1 1 0 1 0 1 1 0 1 1 1 PIC/PULP Cable 24 AWG range/m – ICOT Cable range/m* – 0 20 – – 50 80 0 65 – – 80 145 T1 T1 60 110 – – 130 200 130 195 – – 210 275 1 0 T1 T1 140 210 – – 230 290 260 325 – – 340 405 1 T1 270 – 320 390 – 470 Note: * For ICOT-cable the characteristic impedance is 140 Ω By selecting an all-zero code for LS0, LS1 and LS2 the PRACT can be adapted for CEPT applications. Semiconductor Group 20 PEB 22320 Functional Description The pulse shape according to CCIT G.703 (1544-kbit/s interface) is achieved by using the same line length selection code as for the lowest T1 cable range. To switch the device into a low power dissipation mode, XDIP and XDIN should be held high. The transmitter requires an external step up transformer to drive the line. The transmission factor and the source serial resistor values can be seen in figure 8 and table 7 for the various applications. R1 XL1 t 11 t2 Line t 12 R1 XL 2 ITS00562 Figure 8 Transmitter Configuration Table 7 Transmitter Configuration Values Application T1 CEPT Characteristic line impedance [Ω] 100 140 (ICOT) 120 75 t11 : t2 = t12 : t2 R1 (± 2.5%) [Ω] 26:69 26:69 26:52 26:41 4.3 6 15 15 Wired in this way the transmitter has a return loss ar > 8 dB ar > 14 dB ar > 10 dB for for for 0.025 fb 0.05 fb 1.0 fb ≤f≤ ≤f≤ ≤f≤ 0.05 fb, 1.0 fb and 1.5 fb, with fb being 2048 kHz (CEPT applications). A termination resistor of 120 Ω is assumed. In T1 applications the return loss is higher than 10 dB. Please note, that the transformer ratio at the receiver is half of that at the transmitter. The same type of transformer can thus be used at the receiver and at the transmitter. At the transmitter the two windings are connected in parallel, at the receiver in series. Thus, unbalances are avoided. Semiconductor Group 21 PEB 22320 Functional Description 2.2.2 Output Jitter In the absence of any input jitter the PRACT generates the output jitter, which is specified in table 5. Note: The generated output jitter on the line is the same as the output jitter of the system clocks. 2.3 Local Loopback The local loopback mode disconnects the receive lines RL1 and RL2 from the receiver. Instead of the signals coming from the line the data provided at XTIP and XTIN are routed through the receiver. The XDIN and XDIP signals continue to be transmitted on the line. The local loopback occurs in response to LL going high. 2.4 Remote Loopback In the remote loopback mode the clock and data recovered from the line inputs RL1 and RL2 are routed back to the line outputs XL1 and XL2 via the transmitter. As in normal mode they are also output at RDOP and RDON. XDIP and XDIN are disconnected from the transmitter. The remote loopback mode is selected by a high RL signal. 2.5 Bypass Jitter Attenuator If the JATT pin is set to low the jitter attenuator (FIFO) is bypassed and the propagation delay from the line to the dual rail interface is reduced by the path time of the FIFO. Also in this mode the jitter in the system clocks (CLK2M, CLK4M, FSC) is attenuated. 2.6 Microprocessor Interface The PRACT is fully controlled by six parallel data lines (LS0, LS1, LS2, LL, RL and JATT) and one control line (CS). To adapt the device to a standard microprocessor interface the low state of CS is decoded from the microprocessor address, CS, WR and ALE lines. To hardwire the chip, CS must be fixed to ground. 2.7 Receiver Loss of Signal Indication In the case that the signal at the line receiver input (pins RL1, RL2) becomes smaller than Vin ≤ 0.3 VOP loss of signal is indicated. This voltage value corresponds to a line attenuation of about 14 dB in the CEPT case. This is performed by turning both signals RDOP, RDON after at least 32 bits simultaneously to 5 V, i.e. a logical 0 on both lines. The following ACFA processes this indication for the system. In this mode the PRACT synchronizes to the clock at the SYNC pin. Semiconductor Group 22 PEB 22320 Functional Description 2.8 Master/Slave Selection If the MODE pin is set to high and the SYNC pin is not connected or connected to VSS the PRACT works as a master for the system. The VCO’s of the jitter attenuator are centered (± 50 ppm of the crystal frequencies) and the system clocks are stable (divided from the VCO frequencies). If a clock (2.048 MHz for CEPT, 1.544 MHz for T1) is detected at the SYNC pin the PRACT synchronizes automatically to this clock. In master mode, the PRACT is independent from the receiver loss of signal detection. Note: The MODE pin can not be controlled by the µP interface and requires CMOS levels as input signals. It must always be connected either to VDD or VSS. A voltage of 2.5 V at the MODE Pin switch the PRACT into test mode. Semiconductor Group 23 PEB 22320 Operational Description 3 Operational Description 3.1 Reset After power up resetting the device is necessary to synchronize the internal circuitries. After reset a stabel RCLK is available after 65536 clock cycles. This results in 32 ms in CEPT mode and 42.5 ms in T1 mode. A reset can be performed by two ways. 3.1.1 Reset with CS Pin Fixed to VSS In this reset operation the CS pin is normally hardwired to VSS. Before giving a reset the operational mode has to be selected (CEPT, T1) by setting the pins LS2, LS1, LS0 to 000 for CEPT-application, to 001 for NTT-application or 001 … 111 for T1 application. A reset is made by simultaneously setting both RL and LL to high (CS = 0) for at least 1 µs. Reset will be initiated on the falling edge of RL or LL, the one that falls first. The following figures explain the procedure in some examples. CS LS2 LS1 LS0 RL LL 1µs 1. 2. 1. Start of Reset 2. End of Reset ITD04881 Figure 9 Resetting PRACT for CEPT Applications Semiconductor Group t 24 PEB 22320 Operational Description CS LS2 LS1 LS0 RL LL JATT t 1. 2. 1. Start of Reset 2. End of Reset and local loop is initiated ITD04882 Figure 10 Resetting PRACT for CEPT Applications and Setting Local Loop with Jitter Attenuation CS LS2 LS1 LS0 RL LL t 1. 2. 1. Start of Reset 2. End of Reset, regular operation in T1 Mode 3. Remote loop is initiated 3. ITD04883 Figure 11 Resetting PRACT for T1 Applications (max. line length selected) and Setting Remote Loop Note: If the PRACT is initiated for T1 applications the line length selection can be changed without a new reset. Semiconductor Group 25 PEB 22320 Operational Description 3.1.2 Reset Using CS Pin to Latch Programming (a controller is used) Reset is done by setting the pins RL and LL to logical 1 for at least 1 µs and latching these values into PRACT by a rising edge at pin CS. The selection of CEPT, T1 applications is achieved by setting the pins LS2, LS1, LS0 simultaneously with the reset to 000 for CEPT application or a T1 line length code (001 … 111 see table 6). The logical level of the RL, LL, LS2, LS1, LS0, JATT input parts are latched with the rising edge of the CS. Refer to figure 20. The following figures explain the procedure in some examples. CS RL JATT LL LS0, 1, 2 1 µs 1. t 2. 1. Start of Reset 2. End of Reset, Regular operation in CEPT Mode ITD04884 Figure 12 Resetting PRACT for CEPT Applications and Jitter Attenuation CS RL LL LS0, 1, 2 t 1. 2. 1. Start of Reset 2. End of Reset and setting remote loop ITD04885 Figure 13 Resetting PRACT for CEPT Application and Setting Remote Loop Semiconductor Group 26 PEB 22320 Operational Description CS RL LL LS0, 1, 2 xxx xxx 001 001 xxx xxx 010 xxx t 1. 2. 3. 1. Start of Reset 2. End of Reset and setting line length code, Regular operation in T1 Mode 3. Changing line length code, Regular operation in T1 Mode with changed line length code ITD04886 Figure 14 Resetting PRACT for T1 Applications and Changing Line Length Code CS RL LL LS0, 1, 2 xxx xxx 111 111 xxx t 1. 2. 1. Start of Reset 2. End of Reset and setting local loop and line length code ITD04887 Figure 15 Resetting PRACT for T1 Application and Setting Local Loop 3.2 Operation The PRACT is in normal operation as soon as the reset phase is finished. The CS pin is activated again only when PRACT is reprogrammed (for example setting a loop or changing line length code). That means CS pin could be kept high for normal operation. Semiconductor Group 27 PEB 22320 Electrical Specification 4 Electrical Specification 4.1 Absolute Maximum Ratings Parameter Symbol Limit Values Voltage on any pin with respect to ground VS – 0.4 to VDD + 0.4 V Ambient temperature under bias TA 0 to 70 °C Storage temperature Tstg – 65 to 125 °C 4.2 Delay Times 4.2.1 Delay from XDIP/XDIN to XL1/XL2 Unit The delay from XDIP/XDIN to XL1,XL2 is 770 ns in T1 mode and 860 ns in CEPT mode. This relates to the falling edge of the XCLK and the leading edge of XL1 or XL2. 4.2.2 Delay from RL1/RL2 to RDOP/RDON The delay from RL1/RL2 to RDOP/RDON is given with 700 ns in T1 mode and 540 ns in CEPT mode. This relates to the leading edge of the RL1 or RL2 to the falling edge of RDOP or RDON. Semiconductor Group 28 PEB 22320 Electrical Specification 4.3 DC Characteristics TA = 0 to 70 °C; VDD = 5 V ± 5%, VSS = 0 V DC Characteristics Parameter L-input voltage H-input voltage L-output voltage H-output voltage H-output voltage Symbol VIL VIH VOL VOH VOH Limit Values Unit Test Condition Pins V All pins except MODE, RLx, XLx XTALx, VDD2, SYNC min. max. – 0.4 0.8 2.0 VDD + 0.4 V 0.45 V 2.4 V VDD – V IOL = 2 mA IOH = – 400 µA IOH = – 100 µA 0.5 µA Input leakage current ILI Output leakage current ILO Peak voltage of a mark (CEPT) VXCEPT 2.7 3.3 V wired according figure 8 and table 7 Peak voltage of a mark (T1) VXT1 1.8 3.4 V T1 application: depending on line length Transmitter output RX impedance 0.3 Ω Transmitter output IX current 50 mA CEPT application 150 mA T1 application: depending on line length 2.5 V 1 0 V < VOUT < VDD to 0V Receiver input peak voltage of a mark VR1) 0.4 Loss of signal threshold VLOS 0.3 Receiver input threshold VRTH Voltage at VDD2 VDD2 Semiconductor Group 0 V < VIN < VDD to 0V 2.4 V 45 % 2.6 V 29 XL1, XL2 RL1, RL2 PEB 22320 Electrical Specification DC Characteristics (cont’d) Parameter L-input voltage H-input voltage Symbol VXTALIL VXTALIH Limit Values Unit Test Condition Pins XTAL1, XTAL2, XTAL3, XTAL4 min. max. – 0.4 1.0 V 4.0 VDD + V 0.4 1 µA 0 V ≤ VIN ≤ VDD to 0V 40 110 mA CEPT application 55 190 mA T1 application, min value for all zeros, max value for all ones and max. line length for T1 appl. VIL – 0.4 0.8 V VIH 4.0 VDD + V Input leakage current IXTALI Operational power supply current ICC L-input voltage H-input voltage MODE, SYNC 0.4 Input leakage current 1) ILI1 ILI2 ILI3 ILI4 µA µA µA µA 800 100 800 200 VIL = 0.8 V VIL = 0.1 V VIH = 4 V VIH = VDD Measured against VDD2 4.4 Characteristics TA = 25 °C; VDD = 5 V ± 5 %, VSS = 0 V Parameter Symbol Limit Values min. Unit Pins max. Input capacitance CIN 10 pF all except RLx, XLx, XTALx Output capacitance COUT 15 pF all except RLx, XLx, XTALx Input capacitance CIN COUT 7 pF RLx 20 pF XLx Output capacitance Semiconductor Group 30 PEB 22320 Electrical Specification 4.5 Recommended Oscillator Circuits XTAL1 (XTAL3) C L = 14 pF (4 pF) 16.384 MHz (12.352 MHz) PRACT XTAL1 (XTAL3) PRACT XTAL2 (XTAL4) XTAL2 (XTAL4) External Oscillator Signal 16.384 MHz (12.352 MHz) N.C. 14 pF Crystal Oscillator mode (slave mode/ master mode) Driving from external source (master mode) ITS04888 Figure 16 Oscillator Circuits In CEPT mode if an external source is connected to XTAL1, the PRACT works, independent of the MODE pin, in master mode. In T1 mode if an external source is connected to XTAL3, the PRACT works, independent of the MODE pin, in master mode. This operational mode requires a crystal (16.384 MHz) at pins XTAL1 and XTAL2. The frequency is locked to the external source. The jitter attenuator requires unique performance specifications for the crystals. The following typical crystal parameters will meet this specifications: – Motional capacitance – Shunt capacitance – Load capacitance – Resonance resistance Semiconductor Group C1 = 25 fF min C0 = 7 pF max CL = 18 pF typ, f0 = 16.384 MHz CL = 10 pF typ, f0 = 12.352 MHz Rr ≤ 25 Ω 31 PEB 22320 Electrical Specification PRACT Tuning Range 16.384 MHz PLL Crystal specified for CL = 18 pF ITD06578 150 d f ppm f 0 100 50 0 -50 -100 -150 14 16 18 20 22 24 pF CL Figure 17 16.384-MHz Crystal Tuning Range Semiconductor Group 32 26 PEB 22320 Electrical Specification PRACT Tuning Range 12.352 MHz PLL Crystal specified for CL = 10 pF ITD06579 250 ppm d f 200 f0 150 100 50 0 -50 -100 -150 -200 -250 6 8 10 12 14 16 pF CL Figure 18 12.352-MHz Crystal Tuning Range Semiconductor Group 33 18 PEB 22320 Electrical Specification 4.6 AC Characteristics TA = 0 to 70 °C; VDD = 5 V ± 5 % 2.4 2.0 2.0 Device Under Test Test Points 0.8 0.8 C Load = 150 pF 0.45 ITS00621 Figure 19 Input/Output Waveforms for AC Tests Except from the line interface, inputs are driven at 2.4 V for a logical 1 and 0.4 V for a logical 0. Timing measurements are made at 2.0 V for a logical 1 and at 0.8 V for a logical 0. AC testing input/output waveforms are shown in figure 19. 4.6.1 Dual Rail Interface RDOP, RDON, XDIP, XDIN, XTIP, XTIN are active low. t CPR t CPRH t CPRL RCLK t DROS t DROH RDOP, RDON t CPX t CPXH t CPXL XCLK t DRIS t DRIH XDIP, XDIN XTIP, XTIN ITT04889 Figure 20 Timing of the Dual Rail Interface Semiconductor Group 34 PEB 22320 Electrical Specification Parameter Symbol Limit Values PCM 30 min. max. Unit PCM 24 min. max. RCLK clock period tCPR RCLK clock period low tCPRL 200 260 ns RCLK clock period high tCPRH 200 260 ns Dual rail output setup tDROS 200 260 ns Dual rail output hold tDROH 200 260 ns XCLK clock period tCPX XCLK clock period low tCPXL 200 250 ns XCLK clock period high tCPXH 200 250 ns Dual rail input setup tDRIS 25 25 ns Dual rail input hold tDRIH 25 25 ns Semiconductor Group typ. 488 typ. 648 typ. 488 35 typ. 648 ns ns PEB 22320 Electrical Specification 4.6.2 System Clock Interface t CP16L t CP16 t CP16H CLK16M t CP4L t CP4 t CP4H CLK4M CLK4M t CP2 t CP2L t CP2H CLK2M CLK2M t SS t SH FSC FSC t CP12L t CP12 t CP12H CLK12M t CP15 t CP15L t CP15H XCLK (T1) ITT04890 Figure 21 Timing of the System Clock Interface Semiconductor Group 36 PEB 22320 Electrical Specification System Clock Interface Timing Parameter Values Parameter Symbol Limit Values min. CLK16M period 16 MHz CLK16M period 16 MHz low CLK16M period 16 MHz high CLK4M period 4 MHz CLK4M period 4 MHz low CLK4M period 4 MHz high CLK2M period 2 MHz CLK2M period 2 MHz low CLK2M period 2 MHz high FSC setup time FSC hold time CLK12M period 12 MHz CLK12M period 12 MHz low CLK12M period 12 MHz high XCLK period 1.5 MHz XCLK period 1.5 MHz low XCLK period 1.5 MHz high Semiconductor Group tCP16 tCP16L tCP16H tCP4 tCP4L tCP4H tCP2 tCP2L tCP2H tSS tSH tCP12 tCP12L tCP12H tCP15 tCP15 L tCP15 H 37 Unit max. typ. 61 ns 20 ns 20 ns typ. 244 ns 110 ns 110 ns typ. 488 ns 220 ns 220 ns 110 ns 240 ns typ. 81 ns 30 ns 30 ns typ. 648 ns 300 ns 300 ns PEB 22320 Electrical Specification 4.6.3 Microprocessor Interface t CYC t WC CS t DW t WD DATA (JATT, RL, LL, LS0, 1, 2) ITT04891 Figure 22 Timing of the Microprocessor Interface Parameter CS pulse width Data setup time to CS Data hold time from CS Cycle time Semiconductor Group Symbol tWC tDW tWD tCYC Limit Values min. max. 60 – ns 35 – ns 10 – ns 120 38 Unit ns PEB 22320 Electrical Specification 4.6.4 XTAL Timing tP t WH XTAL1 XTAL3 t WL 3.5 V 0.8 V ITT04892 Figure 23 Timing of XTAL1/XTAL3 XTAL1/XTAL3 Timing Parameter Values Parameter Symbol Limit Values min. typ. Unit Condition ns XTAL1 XTAL3 max. Clock period of crystal/ clock tP High phase crystal/clock tWH 20 30 ns XTAL1 XTAL3 Low phase of crystal/clock tWL 20 30 ns XTAL1 XTAL3 61 81 Note: If an external clock is used the PRACT works as a master. Please refer to Pin Definitions. Semiconductor Group 39 PEB 22320 Electrical Specification 4.7 Pulse Templates - Transmitter The PRACT meets both CCITT and T1 pulse template requirements. 269 ns (244 + 25) V=100 % 10 % 10 % 20 % 20 % 194 ns (244 - 50) Nominal Pulse 50 % 244 ns 10 % 10 % 20 % 0% 10 % 10 % 219 ns (244 - 25) 488 ns (244 + 244) ITD00573 Figure 24 Pulse Template at the Transmitter Output for CEPT Applications Semiconductor Group 40 PEB 22320 Electrical Specification Normalized Amplitude V = 100 % 50 % 0 -50 % 0 250 500 750 1000 ns ITD00574 Figure 25 T1 Pulse Shape at the Cross Connect Point Table 8 T1 Pulse Template Corner Points at the Cross Connect Point Maximum Curve Minimum Curve (0 0.05) (0, – 0.05 (250, 0.05) (350, – 0.05) (325, 0.80) (350, – 0.50) (325, 1.15) (400, 0.95) (425, 1.15) (500, 0.95) (500, 1.05) (600, 0.90) (675, 1.05) (650, 0.50) (725, – 0.07) (650, – 0.45) (1100, 0.05) (800, – 0.45) (1250, 0.05) (925, – 0.20) (1100, – 0.05) (1250, – 0.05) Semiconductor Group 41 t PEB 22320 Electrical Specification 3.0 0.7 0.7 V 50 ns 50 ns 1.5 1.2 0.3 0 - 3T T 8 4 0 T 8 T 4 3T 8 T 2 T = 1/1544 kHz ITD00575 Figure 26 Pulse Shape According to CCITT G.703 4.8 Overvoltage Tolerance To prevent the PRACT from being damaged by overvoltage (i.e. from lightning), external devices like diodes or resistors have to be connected to one or both sides of the line interface transformers. Thus, overvoltage peaks are cut off. However, some residual overvoltage may remain. The PRACT simplifies the task of designing external protection circuits. Its transmitter exhibits a low line impedance so that reasonable external resistors can be connected to the line outputs. Figure 8 with the element values of table 7 gives an example of how an overvoltage protection against residual overvoltages at the ternary interface can be accomplished. The solution shown also meets the stated return loss requirements. A similar consideration applies to the receiver. The resistors R2 of figure 3 provide protection against residual overvoltages by attenuating voltages of both polarities across RL1 and RL2. The maximum input current allowed to reach the PRACT pins under overvoltage conditions is given as a function of the width of a rectangular input current pulse according to figure 27. Figure 29 shows the curve of the maximum allowed input current across the pins RL1 and RL2, figure 28 across the pins XL1 and XL2. Semiconductor Group 42 PEB 22320 Electrical Specification Ι FALC TM -54 Ιp t t WI ITS04893 Condition: All other pins grounded Figure 27 Measurement of Overvoltage Stress ΙP A 100 50 10 dB/Decade R i <_ 2 Ω 10 5 1 0.5 2x10 -1 10 -9 10 -6 10 -3 10 -2 1 t WI s ITD00578 Figure 28 Tolerated Input Current at the XL1, XL2 Pins Semiconductor Group 43 PEB 22320 Electrical Specification ΙP A 20 10 10 dB/Decade R i <_ 300 Ω 1 6x10 -1 10 -1 2x10 -1 10 -10 10 -9 10 -6 10 -4 10 -3 t WI s 1 ITD00577 Figure 29 Tolerated Input Current at the RL1, RL2 Pins Semiconductor Group 44 PEB 22320 Package Outlines 5 Package Outlines GPL05102 Plastic Package, P-LCC-44 (SMD) (Plastic Leaded Chip Carrier) Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book “Package Information”. SMD = Surface Mounted Device Semiconductor Group 45 Dimensions in mm