TLE 4261 TLE 4261 5-V Low-Drop Voltage Regulator Bipolar IC Features ● ● ● ● ● ● ● ● ● ● ● ● ● Very low-drop voltage Very low quiescent current Low starting-current consumption Proof against reverse polarity Input voltage up to 42 V Overvoltage protection up to 65 V (≤ 400 ms) Short-circuit proof External setting of reset delay Integrated watchdog circuit Wide temperature range Overtemperature protection Suitable for automotive use EMC proofed (100 V/m) P-TO220-7-1 P-TO220-7-2 Type Ordering Code Package ▼ TLE 4261 Q67000-A9003 P-TO220-7-1 ▼ TLE 4261 S Q67000-A9109 P-TO220-7-2 ▼ TLE 4261 G Q67000-A9059 P-DSO-20-6 (SMD) ▼ Please also refer to the new pin compatible device TLE 4271 P-DSO-20-6 Functional Description TLE 4261 is a 5-V low-drop voltage regulator in a P-TO220-7 or in a P-DSO package. The maximum input voltage is 42 V (65 V/≤ 400 ms). The device can produce an output current of more than 500 mA. It is short-circuit proof and incorporates temperature protection that disables the circuit at impermissibly high temperatures. Semiconductor Group 1 1998-11-01 TLE 4261 Application Description The IC regulates an input voltage VI in the range VI = 6 V to 40 V to VQrated = 5.0 V. A reset signal is generated for a maximum output voltage of VQ less than 4.75 V. The reset delay can be set externally with a capacitor. A connected microprocessor is monitored by the integrated watchdog circuit. Connecting this input to the input voltage makes the watchdog function inactive. The presence of a voltage less than 2 V on inhibit input disables the regulator. The current consumption drops to max. 50 µA. Design Notes for External Components The input capacitor CI causes a low-resistant powerline and limits the rise times of the input voltage. The IC is protected against rise times up to 100 V/µs. It is possible to damp the tuned circuit consisting of supply inductance and input capacitance with a resistor of approx. 1 Ω in series to CI. The output capacitor maintains the stability of the regulating loop. Stability is guaranteed with a rating of 22 µF at an ESR of 3 Ω max. in the operating temperature range. Circuit Description The control amplifier compares a reference voltage, which is kept highly accurate by resistance adjustment, to a voltage that is proportional to the output voltage and controls the base of the series PNP transistor via a buffer. Saturation control as a function of the load current prevents any over-saturation of the power element. If the output voltage drops below 95.5 % of its typical value for more than 2 µs, a reset signal is triggered on pin 3 and an external capacitor is discharged on pin 5. The reset signal is not cancelled until the voltage on the capacitor has exceeded the upper switching threshold VDT. A positive-edge-triggered watchdog circuit monitors the connected microprocessor and will likewise trigger a reset if pulses are missing. The IC can be disabled by a low level on the inhibit input and the current consumption drops to < 50 µA. The IC also incorporates a number of circuits for protection against: ● ● ● ● Overload Overvoltage Overtemperature Reverse polarity Semiconductor Group 2 1998-11-01 TLE 4261 Pin Configuration (top view) TLE 4261 1 VΙ 2 3 4 5 TLE 4261 S 6 7 1 INH GND Watch QRES DRES VQ VΙ 2 3 4 5 6 7 INH GND Watch QRES DRES V Q AEP00592 AEP01181 Pin Definitions and Functions (TLE 4261; S) Pin Symbol Function 1 VI Input voltage; block a capacitor directly to ground on the IC. The capacitor rating will depend on the vehicle electrical system. Oscillation of the input voltage can be damped by a resistor of approx. 1 Ω in series with the input capacitor. 2 INH Inhibit; switches off the IC when low. 3 QRES Reset output; open-collector output controlled by the rese delay. 4 GND Ground 5 DRES Reset delay; wired to ground using a capacitor. 6 Watch Watchdog; monitors the microprocessor when active. 7 VQ 5-V output voltage; block to ground using a capacitor of ≥ 22 µF. ESR is ≤ 3 Ω in the operating temperature range. Semiconductor Group 3 1998-11-01 TLE 4261 Pin Configuration (top view) TLE 4261 G N.C. N.C. QRES GND GND GND GND N.C. DRES N.C. 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 INH N.C. VΙ GND GND GND GND N.C. VQ Watch AEP01182 Pin Definitions and Functions (TLE 4261 G) Pin Symbol Function 18 VI Input voltage; block a capacitor directly to ground on the IC. The capacitor rating will depend on the vehicle electrical system. Oscillation of the input voltage can be damped by a resistor of approx. 1 Ω in series with the input capacitor. 20 INH Inhibit; switches off the IC when low. 3 QRES Reset output; open-collector output controlled by the reset delay. 4-7 14 - 17 GND Ground; internally connected with pins 14 to 17. 9 DRES Reset delay; wired to ground using a capacitor. 11 Watch Watchdog; monitors the microprocessor when active. 12 VQ 5-V output voltage; block to ground using a capacitor of ≥ 22 µF. ESR is ≤ 3 Ω in the operating temperature range. 1, 2, 8, 10, N.C. 13, 19 Semiconductor Group Not connected 4 1998-11-01 TLE 4261 Overvoltage Monitoring Input Saturation Control and Protection Temperature Sensor 1 (18) 7 Output (12) Control Amplifier Adjustment BANDGAP Reference Buffer + RESET Generator - 5 (9) 3 (3) RESET Delay RESET Output Watchdog Inhibit (20) 2 (4-7) (14-17) 4 Inhibit GND (11) 6 Watchdog AEB00002 Numbers in parentheses for TLE 4261 G Block Diagram Semiconductor Group 5 1998-11-01 TLE 4261 Absolute Maximum Ratings Tj = – 40 to 150 °C Parameter Symbol Limit Values Unit Remarks min. max. VI VI II – 42 – – 45 65 1.6 V V A – V2 I2 – 0.3 – 42 5 V mA – – VR IR – 0.3 – 42 – V – – limited internally IGND – 0.5 A – VD ID – 0.3 – 42 – V – – limited internally VW – 0.3 VI V – VI – VQ IQ – 5.25 – VI V A – – Input Input voltage Input voltage Input current – t ≤ 400 ms Inhibit Voltage Current Reset Output Voltage Current Ground Current Reset Delay Voltage Current Watchdog Voltage Output Differential voltage Current Semiconductor Group 6 1.4 1998-11-01 TLE 4261 Absolute Maximum Ratings (cont’d) Tj = – 40 to 150 °C Parameter Symbol Limit Values Unit Remarks min. max. Tj Tstg – – 50 150 150 °C °C – – Input voltage VI – 32 V see diagram Junction temperature Tj – 40 150 °C – – 65 (70) 1) K/W – 3 (15) 1) K/W – Temperature Junction temperature Storage temperature Operating Range Thermal Resistances System-air System-case 1) Rth SA Rth SC Figures in parenthesis refer to TLE 4261 G. Semiconductor Group 7 1998-11-01 TLE 4261 Characteristics VI = 13.5 V; Tj = 25 °C; V2 ≥ 6 V; (unless specified otherwise) Parameter Symbol Limit Values min. typ. max. Unit Test Condition Normal Operation Output voltage VQ 4.75 5.00 5.25 V 25 mA ≤ IQ ≤ 500 mA; 6 V ≤ VI ≤ 28 V; – 40 °C ≤ Tj ≤ 125 °C Output voltage VQ 4.85 5.00 5.15 V 25 mA ≤ IQ ≤ 150 mA 6 V ≤ VI ≤ 40 V Output current IQ – – 50 µA 0 V ≤ VI ≤ 2 V; V2 = VI; – 40 °C ≤ Tj ≤ 125 °C Output current IQ 500 1000 – mA VI = 17 V to 28 V Current consumption; Iq = II – IQ Iq – – 3.5 mA IQ = 0; VW > 6 V Current consumption; Iq = II – IQ Iq – 5.0 10 mA 6 V ≤ VI ≤ 28 V IQ = 150 mA Current consumption; Iq = II – IQ Iq – 40 65 mA 6 V ≤ VI ≤ 28 V IQ = 500 mA Current consumption; Iq = II – IQ Iq – 45 80 mA VI < 6 V; IQ ≤ 500 mA; Drop voltage VDr – 0.35 0.5 V VI = 4.5 V; IQ = 0.5 A Drop voltage VDr – 0.2 0.3 V VI = 4.5 V; IQ = 0.15 A Load regulation ∆VQ – 15 35 mV 25 mA ≤ IQ ≤ 500 mA Supply voltage regulation ∆VQ – 15 50 mV 6 V ≤ VI ≤ 28 V IQ = 100 mA Supply voltage regulation ∆VQ – 5 25 mV 6 V ≤ VI ≤ 16 V IQ = 100 mA Semiconductor Group 8 1998-11-01 TLE 4261 Characteristics (cont’d) VI = 13.5 V; Tj = 25 °C; V2 ≥ 6 V; (unless specified otherwise) Parameter Symbol Limit Values min. typ. max. Unit Test Condition fr = 100 Hz; Vr = 0.5 Vpp Ripple rejection SVR – 54 – dB Temperature drift of output voltage αVQ – 2× 10– 4 – 1/°C – 40 °C ≤ Tj ≤ 150 °C Current consumption I1 – – 50 µA V2 < 2 V; IQ = 0 Current consumption I2 – – 100 µA V2 = 6 V Switching threshold for inhibit V2 5.0 5.5 6.0 V IC turned ON Switching threshold for inhibit V2 2.0 2.7 3.7 V IC turned OFF Switching threshold VRT 94 95.5 97 % in % of VQ IQ > 500 mA; VI = 6 V Saturation voltage, reset output VR – 0.25 0.40 V IR = 1 mA Reverse current IR – – 1 µA VR = 5 V Charge current Id 18.75 25 31.25 µA VC = 1.5 V Switching threshold VST 0.9 1 1.1 V – Delay switching threshold VDT 2.25 2.50 2.75 V – Saturation voltage, delay output VC – – 100 mV VI = 4.5 V and Id Inhibit Operation Reset Generator Semiconductor Group 9 1998-11-01 TLE 4261 Characteristics (cont’d) VI = 13.5 V; Tj = 25 °C; V2 ≥ 6 V; (unless specified otherwise) Parameter Symbol Limit Values min. typ. max. Unit Test Condition Delay time tD – 10 – ms CD = 100 nF Delay time tt – 2 – µs – Turn-OFF voltage VW 5.2 5.6 6.0 V – Discharge current ICD 5.6 7.5 9.4 µA VC = 1.5 V Switching voltage VCD 2.95 3.05 3.15 V – Pulse interval TW – 35 – ms CD = 100 nF Turn-OFF voltage VIOFF 41 43 45 V IQ < 1 mA Turn-OFF hysteresis ∆VI – 6.5 – V – Leakage current IQS – – 50 µA VQ = 0 V; VI = 45 V Reverse output current IQR – – 1.5 mA VQ = 5 V; VI and V2 open Watchdog General Data Semiconductor Group 10 1998-11-01 TLE 4261 Input 6 V to 40 V 470 nF 1 7 2 5 TLE 4261 6 Output 22 µF 100 k Ω 100 nF 3 RESET 4.7 k Ω 4 From µ C AES00021 KL15 7 V to 18 V Application Circuit ΙΙ 7 Ι Q / Ι SC 1 1000 µF 22 µF 470 nF TLE 4261 4.7 kΩ VQ Ι3 VΙ + VR V2 2 VC 3 5 4 ΙD Ι GND CD 100 nF VDr = VΙ -VQ 6 ΙR VR VW AES00135 V SVR = 20 log R ∆VQ Test Circuit Semiconductor Group 11 1998-11-01 TLE 4261 ( V CD – V ST ) ( I CD + I D ) ( V DT – V ST ) - C D ; t dw = ------------------------------- CD t W ---------------------------------------------------------I D × I CD ID Time Response in Watchdog Condition V Wmin > 6 V VW V ΙOFF ∆V Ι < V ΙOFF VΙ 3.3 V ∆V RT <t t V V Q RT dV Ι D = dt C D V DT VC V ST tD VR Overvoltage OverSpike voltage Overtemperature Undervoltage Secondary Spike Shortcircuit on Output AET00593 Timing with Watchdog OFF Semiconductor Group 12 1998-11-01 TLE 4261 Drop Voltage versus Output Current VDr Current Consumption versus Output Current AED00586 800 mV 700 Ιq AED00588 80 mA 70 VΙ = 4.5 V VΙ = 13.5 V 600 60 500 50 T j = 125 C 400 40 300 30 200 20 T j = 25 C 100 0 10 0 100 200 300 400 mA 0 600 0 100 200 300 400 ΙQ ΙQ Current Consumption versus Input Voltage Output Voltage versus Input Voltage AED00026 120 AED00027 12 Ι q mA VQ V 10 100 R L =10 Ω RL =10 Ω 80 8 60 6 40 4 20 2 0 600 mA 0 10 20 30 0 40 V 50 VΙ Semiconductor Group 0 2 4 6 8 V 10 VΙ 13 1998-11-01 TLE 4261 Output Voltage versus Temperature Output Current versus Input Voltage AED00028 5.20 VQ AED00594 1.2 V Ι Q mA 5.10 1.0 T j = 25 C VΙ = 13.5 V 5.00 0.8 4.90 0.6 4.80 0.4 4.70 0.2 4.60 -40 0 40 80 0 120 C 160 0 10 20 30 40 V 50 VΙ j Input Step Response ∆VΙ Load Step Response AED00595 2 V 1 ∆Ι Q AED00596 mA 500 t R = t F ~_ 1 µs 0 25 40 ∆VQ mV 20 200 ∆VQ mV 100 C Q = 22 µs 0 0 -20 -40 -10 C Q = 22 µs -100 0 10 20 30 µs -200 -10 50 t Semiconductor Group 0 10 20 30 µs 50 t 14 1998-11-01 TLE 4261 Charge Current ID and Discharge Current ICD versus Temperature Ι Switching Voltage VCD and VST versus Temperature AED01322 40 µA 35 V V Ι = 13.5 V V C = 1.5 V 30 25 AED01323 4 V V Ι = 13.5 V V Cd 3 Ιd 20 2 15 V ST 10 1 Ι Cd 5 0 -40 0 40 80 0 -40 120 C 160 Tj Pulse Interval TW versus Temperature 0 40 80 120 C 160 Tj Current Consumption of Inhibit at the Switching Point versus Temperature AED01324 1.6 ms T W 1.4 AED01325 120 µA Ι 20 100 V Ι = 13.5 V C d = 100 nF 1.2 80 1.0 0.8 60 ON 0.6 40 0.4 20 0.2 0 -40 0 40 Semiconductor Group 80 0 -40 120 C 160 Tj 15 OFF 0 40 80 120 C 160 Tj 1998-11-01 TLE 4261 Package Outlines P-TO220-7-1 (Plastic Transistor Single Outline) 10 +0.4 10.2 -0.2 1 x 45˚ +0.1 1.27 +0.1 8.6 ±0.3 15.4 ±0.3 8.8 -0.2 2.6 7 10.2 ±0.3 1 16 ±0.4 19.5 max 2.8 3.75 4.6 -0.2 0.4 +0.1 1.27 0.6 +0.1 1) 4.5 ±0.4 0.6 M 7x 8.4 ±0.4 1) 0.75 -0.15 at dam bar (max 1.8 from body) 1) 0.75 -0.15 im Dichtstegbereich (max 1.8 vom Körper) GPT05108 Weight approx. 2.1 g Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book “Package Information”. Dimensions in mm Semiconductor Group 16 1998-11-01 TLE 4261 Package Outlines (cont’d) P-TO220-7-2 (Plastic Transistor Single Outline) 10 +0.4 10.2 -0.2 1 x 45˚ +0.1 1.27 +0.1 7 15.4 13 0.4 +0.1 1.27 0.6 +0.1 1) 0.6 M 7x 1) 0.75 -0.15 at dam bar (max 1.8 from body) 1) 0.75 -0.15 im Dichtstegbereich (max 1.8 vom Körper) Weight approx. 2.1 g 2.6 GPT05257 1 11 8.8 -0.2 2.8 3.75 4.6 -0.2 Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book “Package Information”. Dimensions in mm Semiconductor Group 17 1998-11-01 TLE 4261 Package Outlines (cont’d) 1.27 0.35 0.35 x 45˚ 7.6 -0.2 1) 0.23 +0.0 9 8˚ ma x 2.65 max 2.45 -0.2 0.2 -0.1 P-DSO-20-6 (Plastic Dual Small Outline) 0.4 +0.8 +0.15 2) 0.2 24x 20 10.3 ±0.3 0.1 11 GPS05094 1 12.8 1) 10 -0.2 Index Marking 1) Does not include plastic or metal protrusions of 0.15 max per side 2) Does not include dambar protrusion of 0.05 max per side Weight approx. 0.6 g Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book “Package Information”. SMD = Surface Mounted Device Semiconductor Group 18 Dimensions in mm 1998-11-01