Data Sheet No.PD60217 Rev A IR2011(S) & (PbF) HIGH AND LOW SIDE DRIVER Features • Floating channel designed for bootstrap operation • • • • • • • • Fully operational up to +200V Tolerant to negative transient voltage, dV/dt immune Gate drive supply range from 10V to 20V Independent low and high side channels Input logicHIN/LIN active high Undervoltage lockout for both channels 3.3V and 5V input logic compatible CMOS Schmitt-triggered inputs with pull-down Matched propagation delay for both channels 8-Lead SOIC is also available LEAD-FREE (PbF) Product Summary VOFFSET 200V max. IO+/- 1.0A /1.0A typ. VOUT 10 - 20V ton/off 80 & 60 ns typ. Delay Matching 20 ns max. Applications • Audio Class D amplifiers • High power DC-DC SMPS converters • Other high frequency applications Packages Description The IR2011 is a high power, high speed power MOSFET driver with independent high and low side referenced output channels, ideal for Audio Class D and DC-DC converter applications. Logic inputs are compatible with standard CMOS or LSTTL output, down to 3.0V logic. The output drivers feature a high pulse current buffer stage designed for minimum driver cross-conduction. Propagation delays are matched to simplify use in high frequency applications. The floating channel can be used to drive an N-channel power MOSFET in the high side configuration which operates up to 200 volts. Proprietary HVIC and latch immune CMOS technologies enable ruggedized monolithic construction. 8-Lead SOIC IR2011S also available LEAD-FREE (PbF) 8-Lead PDIP IR2011 Typical Connection 200V HIN 5 LIN HIN VS LIN HO COM COM 8 LO 4 VB VCC TO LOAD 1 VCC (Refer to Lead Assignments for correct configuration). This/These diagram(s) show electrical connections only. Please refer to our Application Notes and DesignTips for proper circuit board layout. www.irf.com 1 IR2011(S) & (PbF) Absolute Maximum Ratings Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are absolute voltages referenced to COM. The thermal resistance and power dissipation ratings are measured under board mounted and still air conditions. Symbol Definition VB High side floating supply voltage VS Min. Max. -0.3 250 Units High side floating supply offset voltage VB - 25 VB + 0.3 VHO High side floating output voltage VS - 0.3 VB + 0.3 VCC Low side fixed supply voltage -0.3 25 VLO Low side output voltage -0.3 VCC +0.3 VIN Logic input voltage (HIN & LIN) COM -0.3 VCC +0.3 dVs/dt PD RTHJA Allowable offset supply voltage transient (figure 2) — 50 Package power dissipation @ TA ≤ +25°C (8-lead DIP) — 1.0 (8-lead SOIC) — 0.625 Thermal resistance, junction to ambient (8-lead DIP) — 125 (8-lead SOIC) — 200 TJ Junction temperature — 150 TS Storage temperature -55 150 TL Lead temperature (soldering, 10 seconds) — 300 V V/ns W °C/W °C Recommended Operating Conditions For proper operation the device should be used within the recommended conditions. The VS and COM offset ratings are tested with all supplies biased at 15V differential. Symbol Definition Min. Max. VB High side floating supply absolute voltage VS + 10 VS + 20 VS High side floating supply offset voltage Note 1 200 VHO High side floating output voltage VS VB VCC Low side fixed supply voltage 10 20 VLO Low side output voltage 0 VCC VIN Logic input voltage (HIN & LIN) TA Ambient temperature COM 5.5 -40 125 Units V °C Note 1: Logic operational for VS of -4 to +200V. Logic state held for VS of -4V to -VBS. 2 www.irf.com IR2011(S) & (PbF) Dynamic Electrical Characteristics VBIAS (VCC, VBS) = 15V, CL = 1000 pF, TA = 25°C unless otherwise specified. Figure 1 shows the timing definitions. Symbol Definition Min. Typ. Max. Units Test Conditions ton Turn-on propagation delay — 80 — VS = 0V toff Turn-off propagation delay — 75 — VS = 200V tr Turn-on rise time — 35 50 tf Turn-off fall time — 20 35 DM1 Turn-on delay matching | ton (H) - ton (L) | — 5 20 DM2 Turn-off delay matching | toff (H) — 5 20 - toff (L) | ns Static Electrical Characteristics VBIAS (VCC, VBS) = 15V, and TA = 25°C unless otherwise specified. The VIN, VTH and IIN parameters are referenced to COM and are applicable to all logic input leads: HIN and LIN. The VO and IO parameters are referenced to COM and are applicable to the respective output leads: HO or LO. Symbol Definition Min. Typ. Max. Units Test Conditions VIH Logic “1” input voltage 2.2 — — VIL Logic “0” input voltage — — 0.7 VOH High level output voltage, VBIAS - VO — — 2.0 VOL Low level output voltage, VO — — 0.2 20mA ILK Offset supply leakage current — — 50 VB=VS = 200V IQBS Quiescent VBS supply current — 90 210 IQCC Quiescent VCC supply current — 140 230 IIN+ Logic “1” input bias current — 7.0 20 VIN = 3.3V — 8.2 — 9.0 1.0 9.8 VIN = 0V 7.4 8.2 9.0 8.2 9.0 9.8 7.4 8.2 9.0 IO+ Logic “0” input bias current VBS supply undervoltage positive going threshold VBS supply undervoltage negative going threshold VCC supply undervoltage positive going threshold VCC supply undervoltage negative going threshold Output high short circuit pulsed current — 1.0 — IO- Output low short circuit pulsed current — 1.0 — IINVBSUV+ VBSUVVCCUV+ VCCUV- www.irf.com VCC = 10V - 20V V IO = 0A µA VIN = 0V or 3.3V VIN = 0V or 3.3V V A VO = 0V, PW ≤ 10 µs VO = 15V, PW ≤ 10 µs 3 IR2011(S) & (PbF) Functional Block Diagram VB 3V S-TRIGGER LOW VOLTAGE LEVEL SHIFT HIN BUFFER HIGH VOLTAGE LEVEL SHIFT CIRCUIT UV DETECT UV Q S HO R VS VCC 3V S-TRIGGER UV DETECT LOW VOLTAGE LEVEL SHIFT LIN LO DELAY COM Lead Definitions Symbol Description HIN LIN VB HO VS VCC LO COM Logic input for high side gate driver output (HO), in phase Logic input for low side gate driver output (LO), in phase High side floating supply High side gate drive output High side floating supply return Low side supply Low side gate drive output Low side return Lead Assignments 5 HIN VS 4 5 HIN VS 4 6 LIN HO 3 6 LIN HO 3 7 COM VB 2 7 COM VB 2 8 LO VCC 1 8-Lead PDIP 8 LO V CC 1 8-Lead SOIC also available LEAD-FREE (PbF) IR2011 IR2011S Part Number 4 www.irf.com IR2011(S) & (PbF) 50% 50% HIN / LIN trise tfall 90% 90% ton(H) toff(H) 10% 10% HO DM2 DM1 90% toff(L) ton(L) LO 10% Figure 1. Timing Diagram www.irf.com 5 IR2011(S) & (PbF) Turn-on Propagation Delay (ns) Turn-on Propagation Delay (ns) 500 400 300 200 100 Typ. 0 -50 -25 0 25 50 75 100 500 400 300 200 Typ. 100 0 125 10 12 o Temperature ( C) Turn-off Propagation Delay (ns) Turn-off Propagation Delay (ns) 400 300 200 Typ. -25 0 25 50 75 100 o Temperature ( C) Figure 3A. Turn-off Propagation Delay vs. Temperature 6 18 20 Figure 2B. Turn-on Propagation Delay vs. Supply Voltage 500 0 -50 16 Supply Voltage (V) Figure 2A. Turn-on Propagation Delay vs. Temperature 100 14 125 500 400 300 200 100 Typ. 0 10 12 14 16 18 20 Supply Voltage (V) Figure 3B. Turn-off Propagation Delay vs. Supply Voltage www.irf.com IR2011(S) & (PbF) 100 Turn-on Rise Time (ns) Turn-on Rise Time (ns) 100 80 60 M ax. 40 Typ. 20 0 -50 80 M ax. 60 Typ. 40 20 0 -25 0 25 50 75 100 125 10 12 16 18 Figure 4A. Turn-on Rise Time vs. Temperature Figure 4B. Turn-on Rise Time vs. Supply Voltage 50 50 40 M ax. 30 20 Typ. 10 0 -50 40 M ax. 30 Typ. 20 10 0 -25 0 25 50 Temperature 75 100 (oC) Figure 5A. Turn-off Fall Time vs. Temperature www.irf.com 20 Supply Voltage (V) Turn-off Fall Time (ns) Turn-off Fall Time (ns) Temperature (oC) 14 125 10 12 14 16 18 20 Supply Voltage (V) Figure 5B. Turn-off Fall Time vs. Supply Voltage 7 IR2011(S) & (PbF) 50 Dealy Matching Time (ns) Delay Matching Time (ns) 50 40 30 M ax. 20 10 Typ. 0 -50 40 30 M ax. 20 10 Typ. 0 -25 0 25 50 75 100 125 10 12 o Temperature ( C) Dealy Matching Time (ns) Delay Matching Time (ns) 20 50 40 30 M ax. Typ. 0 -50 40 30 M ax. 20 10 Typ. 0 -25 0 25 50 Temperature 75 100 (oC) Figure 7A. Turn-off Delay Matching Time vs. Temperature 8 18 Figure 6B. Turn-on Delay Matching Time vs. Supply Voltage 50 10 16 Supply Voltage (V) Figure 6A. Turn-on Delay Matching Time vs. Temperature 20 14 125 10 12 14 16 18 20 Supply Voltage (V) Figure 7B. Turn-off Delay Matching Time vs. Supply Voltage www.irf.com IR2011(S) & (PbF) 5 Logic "1" Input Voltage (V) Logic "1" Input Voltage (V) 5 4 3 M in. 2 1 4 3 M in. 2 1 0 0 -50 -25 0 25 50 75 100 10 125 12 Figure 8A. Logic "1" Input Voltage vs. Temperature 18 20 Figure 8B. Logic "1" Input Voltage vs. Supply Voltage 5 Logic "0" Input Voltage (V) 5 Logic "0" Input Voltage (V) 16 Supply Voltage (V) Temperature (oC) 4 3 2 1 14 M ax. 0 -50 4 3 2 M ax. 1 0 -25 0 25 50 Temperature 75 (oC) Figure 9A. Logic "0" Input Voltage vs. Temperature www.irf.com 100 125 10 12 14 16 18 20 Supply Voltage (V) Figure 9B. Logic "0" Input Voltage vs. Supply Voltage 9 5 5 4 4 High Level Output (V) High Level Output (V) IR2011(S) & (PbF) 3 M ax. 2 1 0 -50 3 M ax. 2 1 0 -25 0 25 50 75 100 10 125 12 o 0.5 0.5 0.4 0.4 0.3 0.2 M ax. 20 0.3 0.2 M ax. 0.1 0.0 -25 0 25 50 Temperature 75 100 125 (oC) Figure 11A. Low Level Output vs. Temperature 10 18 Figure 10B. High Level Output vs. Supply Voltage Low Level Output (V) Low Level Output (V) Figure 10A. High Level Output vs.Temperature 0.0 -50 16 Supply Voltage (V) Temperature ( C) 0.1 14 10 12 14 16 18 20 Supply Voltage (V) Figure 11B. Low Level Output vs. Supply Voltage www.irf.com 500 400 300 200 100 M ax. 0 -50 -25 0 25 50 75 100 125 Offset Supply Leakage Current (µA) Offset Supply Leakage Current (µA) IR2011(S) & (PbF) 500 400 300 200 100 0 M ax. 50 80 o Temperature ( C) 110 140 170 200 18 20 V B Boost Voltage (V) Figure 12A. Offset Supply Leakage Current vs. Temperature 600 V BS Supply Current (µA) V BS Supply Current (µA) 600 500 400 300 200 100 M ax. 0 -50 400 300 200 100 M ax. 0 Typ. -25 0 25 50 75 (o Temperature C) www.irf.com 500 100 125 Typ. 10 12 14 16 V BS Floating Supply Voltage (V) 11 IR2011(S) & (PbF) 600 V CC Supply Current (µA) V CC Supply Current (µA) 600 500 400 300 M ax. 200 Typ. 100 0 -50 -25 0 25 50 75 100 500 400 300 200 M ax. 100 Typ. 0 125 10 12 (o Temperature C) 60 40 M ax. Typ. 0 25 50 75 100 Temperature (oC) 125 Logic "1" Input Bias Current (µA) Logic "1" Input Bias Current (µA) 80 -25 18 20 Figure 14B. V CC Supply Current vs. V CC Supply Voltage 100 0 -50 16 V CC Supply Voltage (V) Figure 14A. V CC Supply Current vs. Tem perature 20 14 100 80 60 40 20 M ax. 0 10 Typ. 12 14 16 18 20 Supply Voltage (V) Figure 15A. Logic "1" Input Bias Current vs. Tem perature 12 www.irf.com 5 Logic "0" Input Bias Current (µA) Logic "0" Input Bias Current (µA) IR2011(S) & (PbF) 4 3 2 M ax. 1 0 -50 -25 0 25 50 75 100 5 4 3 2 M ax. 1 0 125 10 12 14 Temperature (oC) Typ. M in. 8 7 -50 -25 0 25 50 75 100 125 Temperature (oC) Figure 17. VCC and VBS Undervoltage Threshold (+) vs. Temperature www.irf.com V CC and V BS UV Threshold (-) (V) V CC and V BS UV Threshold (+) (V) 11 9 20 Figure 16B. Logic "0" Input Bias Current vs. Supply Voltage 12 M ax. 18 Supply Voltage (V) Figure 16A. Logic "0" Input Bias Current vs. Tem perature 10 16 12 11 10 9 M ax. Typ. 8 M in. 7 -50 -25 0 25 50 75 100 125 o Temperature ( C) Figure 18. VCC and VBS Undervoltage Threshold (-) vs. Temperature 13 IR2011(S) & (PbF) 5 Output Source Current (A) Output Source Current (A) 5 4 3 2 Typ. 1 0 -50 4 3 2 Typ. 1 0 -25 0 25 50 75 100 125 10 12 Temperature (oC) Output Sink Current (A) Output Sink Current (A) 20 5 4 3 2 Typ. 4 3 2 1 Typ. 0 -25 0 25 50 75 Temperature (oC) Figure 20A. Output Sink Current vs. Temperature 14 18 Figure 19B. Output Source Current vs. Supply Voltage 5 0 -50 16 Supply Voltage (V) Figure19A. Output Source Current vs. Temperature 1 14 100 125 10 12 14 16 18 20 Supply Voltage (V) Figure 20B. Output Sink Current vs. Supply Voltage www.irf.com Maximum VS Negative Offset (V) IR2011(S) & (PbF) 0 -3 Typ. -6 -9 -12 -15 10 12 14 16 18 20 V BS Floating Supply Voltage (V) Figure 21. Maximum VS Negative Offset vs. V BS Floating Supply Voltage www.irf.com 15 IR2011(S) & (PbF) Case outlines 01-6014 01-3003 01 (MS-001AB) 8-Lead PDIP D DIM B 5 A FOOTPRINT 8 6 7 6 5 H E 1 6X 2 3 0.25 [.010] 4 e A 6.46 [.255] 3X 1.27 [.050] e1 0.25 [.010] A1 .0688 1.35 1.75 A1 .0040 .0098 0.10 0.25 b .013 .020 0.33 0.51 c .0075 .0098 0.19 0.25 D .189 .1968 4.80 5.00 .1574 3.80 4.00 E .1497 e .050 BASIC e1 MAX 1.27 BASIC .025 BASIC 0.635 BASIC H .2284 .2440 5.80 6.20 K .0099 .0196 0.25 0.50 L .016 .050 0.40 1.27 y 0° 8° 0° 8° y 0.10 [.004] 8X L 8X c 7 C A B NOTES: 1. DIMENSIONING & TOLERANCING PER ASME Y14.5M-1994. 2. CONTROLLING DIMENSION: MILLIMETER 3. DIMENSIONS ARE SHOWN IN MILLIMETERS [INCHES]. 4. OUTLINE C ONFORMS TO JEDEC OUTLINE MS-012AA. 8-Lead SOIC 16 MIN .0532 K x 45° A C 8X b 8X 1.78 [.070] MILLIMETERS MAX A 8X 0.72 [.028] INCHES MIN 5 DIMENSION DOES NOT INCLUDE MOLD PROTRUSIONS. MOLD PROTRUSIONS NOT TO EXCEED 0.15 [.006]. 6 DIMENSION DOES NOT INCLUDE MOLD PROTRUSIONS. MOLD PROTRUSIONS NOT TO EXCEED 0.25 [.010]. 7 DIMENSION IS THE LENGTH OF LEAD FOR SOLDERING TO A SUBSTRATE. 01-6027 01-0021 11 (MS-012AA) www.irf.com IR2011(S) & (PbF) LEADFREE PART MARKING INFORMATION Part number Date code IRxxxxxx YWW? Pin 1 Identifier ? P MARKING CODE Lead Free Released Non-Lead Free Released IR logo ?XXXX Lot Code (Prod mode - 4 digit SPN code) Assembly site code Per SCOP 200-002 ORDER INFORMATION Basic Part (Non-Lead Free) 8-Lead PDIP IR2011 order IR2011 8-Lead SOIC IR2011S order IR2011S Leadfree Part 8-Lead PDIP IR2011 Not available 8-Lead SOIC IR2011S order IR2011SPbF This product has been designed and qualified for the industrial market. Qualification Standards can be found on IR’s Web Site http://www.irf.com/. Data and specifications subject to change without notice WORLD HEADQUARTERS: 233 Kansas Street, El Segundo, California 90245 Tel: (310) 252-7105 5/25/2004 www.irf.com 17