Data Sheet No. PD94126 IRU1050 5A LOW DROPOUT POSITIVE ADJUSTABLE REGULATOR DESCRIPTION FEATURES Guaranteed < 1.3V Dropout at Full Load Current Fast Transient Response 1% Voltage Reference Initial Accuracy Output Current Limiting Built-In Thermal Shutdown The IRU1050 is a low dropout three-terminal adjustable regulator with minimum of 5A output current capability. This product is specifically designed to provide well regulated supply for low voltage IC applications such as Pentium P54C ,P55C as well as GTL+ termination for Pentium Pro and Klamath processor applications. The IRU1050 is also well suited for other processors such as Cyrix , AMD and Power PC applications. The IRU1050 is guaranteed to have <1.3V dropout at full load current making it ideal to provide well regulated outputs of 2.5V to 3.3V with 4.75V to 7V input supply. APPLICATIONS Low Voltage Processor Applications such as: P54C , P55C , Cyrix M2 , POWER PC , AMD GTL+ Termination PENTIUM PRO , KLAMATH Low Voltage Memory Termination Applications Standard 3.3V Chip Set and Logic Applications TYPICAL APPLICATION 5V C1 1500uF IRU1050 VIN 3 VOUT 2 3.38V / 5A R1 121 Adj 1 R2 205 C2 2x 1500uF Figure 1 - Typical Application of IRU1050 in a 5V to 3.38V regulator designed to meet the Intel P54C processors. Notes: Pentium P54C, P55C, Klamath, Pentium Pro,VRE are trademarks of Intel Corp. Cyrix M2 is trademark of Cyrix Corp. Power PC is trademark of IBM Corp. PACKAGE ORDER INFORMATION TJ (°C) 0 To 150 Rev. 1.8 08/20/02 2-PIN PLASTIC TO-252 (D-Pak) IRU1050CD 3-PIN PLASTIC TO-263 (M) IRU1050CM www.irf.com 2-PIN PLASTIC Ultra Thin-PakTM (P) IRU1050CP 3-PIN PLASTIC TO-220 (T) IRU1050CT 1 IRU1050 ABSOLUTE MAXIMUM RATINGS Input Voltage (V IN) .................................................... Power Dissipation ..................................................... Storage Temperature Range ...................................... Operating Junction Temperature Range ..................... 7V Internally Limited -65°C To 150°C 0°C To 150°C PACKAGE INFORMATION 2-Pin Plastic TO-252 (D-Pak) 3-Pin Plastic TO-263 (M) 2-Pin Plastic ULTRA THIN-PAKTM (P) FRONT VIEW FRONT VIEW 3 3 V IN Tab is V OUT Tab is V OUT 1 Adj θJA=70°C/W for 0.5" Sq pad 3-Pin Plastic TO-220 (T) FRONT VIEW 2 V OUT 1 Adj θJA=35°C/W for 1" Square pad FRONT VIEW 3 V IN V IN Tab is VOUT Tab is V OUT 1 Adj θJA=70°C/W for 1" Square pad 3 VIN 2 VOUT 1 Adj θJT=2.7°C/W θJA=60°C/W ELECTRICAL SPECIFICATIONS Unless otherwise specified, these specifications apply over CIN=1mF, COUT=10mF, and TJ=0 to 1508C. Typical values refer to TJ=258C. PARAMETER Reference Voltage Line Regulation Load Regulation (Note 1) Dropout Voltage (Note 2) SYM VREF DVo Current Limit Minimum Load Current (Note 3) Thermal Regulation Ripple Rejection Adjust Pin Current Adjust Pin Current Change Temperature Stability Long Term Stability RMS Output Noise IADJ TEST CONDITION Io=10mA, TJ=258C, VIN-Vo=1.5V Io=10mA, VIN-Vo=1.5 Io=10mA, 1.3V<(V IN-Vo)<7V VIN=3.3V, VADJ=0V, 10mA<Io<5A Note 2, Io=4A Io=5A VIN=3.3V, DVo=100mV VIN=3.3V, V ADJ=0V 30ms Pulse, VIN-Vo=3V, Io=5A f=120Hz, Co=25mF Tantalum, Io=2.5A, VIN-Vo=3V Io=10mA, VIN-Vo=1.5V, TJ=258C, Io=10mA, VIN-Vo=1.5V Io=10mA, VIN-Vo=1.5V, TJ=258C VIN=3.3V, VADJ=0V, Io=10mA TJ=1258C, 1000Hrs TJ=258C, 10Hz<f<10KHz Note 1: Low duty cycle pulse testing with Kelvin connections is required in order to maintain accurate data. Note 2: Dropout voltage is defined as the minimum differential voltage between VIN and VOUT required to maintain regulation at VOUT. It is measured when the output voltage drops 1% below its nominal value. 2 MIN 1.238 1.225 TYP 1.25 1.25 1.1 MAX 1.262 1.275 0.2 0.4 1.2 1.3 5 0.01 10 0.02 5.1 60 70 55 0.2 0.5 0.3 0.003 UNITS V % % V A mA %/W dB 120 5 1 mA mA % % %Vo Note 3: Minimum load current is defined as the minimum current required at the output in order for the output voltage to maintain regulation. Typically the resistor dividers are selected such that it automatically maintains this current. www.irf.com Rev. 1.8 08/20/02 IRU1050 PIN DESCRIPTIONS PIN # PIN SYMBOL PIN DESCRIPTION 1 Adj A resistor divider from this pin to the VOUT pin and ground sets the output voltage. 2 VOUT The output of the regulator. A minimum of 10mF capacitor must be connected from this pin to ground to insure stability. 3 VIN The input pin of the regulator. Typically a large storage capacitor is connected from this pin to ground to insure that the input voltage does not sag below the minimum drop out voltage during the load transient response. This pin must always be 1.3V higher than V OUT in order for the device to regulate properly. BLOCK DIAGRAM VIN 3 2 VOUT + + 1.25V CURRENT LIMIT THERMAL SHUTDOWN 1 Adj Figure 2 - Simplified block diagram of the IRU1050. APPLICATION INFORMATION Introduction The IRU1050 adjustable Low Dropout (LDO) regulator is a three-terminal device which can easily be programmed with the addition of two external resistors to any voltages within the range of 1.25 to 5.5 V. This regulator unlike the first generation of the three-terminal regulators such as LM117 that required 3V differential between the input and the regulated output, only needs 1.3V differential to maintain output regulation. This is a key requirement for today’s microprocessors that need typically 3.3V supply and are often generated from the 5V supply. Another major requirement of these microprocessors such as the Intel P54C is the need to switch the load current from zero to several amps in tens of Rev. 1.8 08/20/02 nanoseconds at the processor pins, which translates to an approximately 300 to 500ns current step at the regulator. In addition, the output voltage tolerances are also extremely tight and they include the transient response as part of the specification.For example Intel VRE specification calls for a total of ±100mV including initial tolerance, load regulation and 0 to 4.6A load step. The IRU1050 is specifically designed to meet the fast current transient needs as well as providing an accurate initial voltage, reducing the overall system cost with the need for fewer output capacitors. www.irf.com 3 IRU1050 Output Voltage Setting The IRU1050 can be programmed to any voltages in the range of 1.25V to 5.5V with the addition of R1 and R2 external resistors according to the following formula: ( VOUT = VREF3 1+ R2 R1 ) +I 3R2 ADJ Where: VREF = 1.25V Typically IADJ = 50mA Typically R1 and R2 as shown in Figure 3: regulator and the load is gained up by the factor of (1+R2/ R1), or the effective resistance will be RP(eff) =RP3(1+R2/ R1). It is important to note that for high current applications, this can represent a significant percentage of the overall load regulation and one must keep the path from the regulator to the load as short as possible to minimize this effect. PARASITIC LINE RESISTANCE VIN RP Vin VOUT IRU1050 VI N VO U T V OUT V IN Adj RL R1 IRU1050 R2 Adj V REF IADJ = 50uA R1 R2 Figure 4 - Schematic showing connection for best load regulation. Figure 3 - Typical application of the IRU1050 for programming the output voltage. The IRU1050 keeps a constant 1.25V between the output pin and the adjust pin. By placing a resistor R1 across these two pins a constant current flows through R1, adding to the IADJ current and into the R2 resistor producing a voltage equal to the (1.25/R1)3R2 + IADJ3R2 which will be added to the 1.25V to set the output voltage. This is summarized in the above equation. Since the minimum load current requirement of the IRU1050 is 10mA, R1 is typically selected to be 121V resistor so that it automatically satisfies the minimum current requirement. Notice that since IADJ is typically in the range of 50mA it only adds a small error to the output voltage and should only be considered when a very precise output voltage setting is required. For example, in a typical 3.3V application where R1=121V and R2=200V the error due to IADJ is only 0.3% of the nominal set point. Load Regulation Since the IRU1050 is only a three-terminal device, it is not possible to provide true remote sensing of the output voltage at the load. Figure 4 shows that the best load regulation is achieved when the bottom side of R2 is connected to the load and the top side of R1 resistor is connected directly to the case or the VOUT pin of the regulator and not to the load. In fact, if R1 is connected to the load side, the effective resistance between the 4 Stability The IRU1050 requires the use of an output capacitor as part of the frequency compensation in order to make the regulator stable. Typical designs for microprocessor applications use standard electrolytic capacitors with a typical ESR in the range of 50 to 100mV and an output capacitance of 500 to 1000mF. Fortunately as the capacitance increases, the ESR decreases resulting in a fixed RC time constant. The IRU1050 takes advantage of this phenomena in making the overall regulator loop stable. For most applications a minimum of 100mF aluminum electrolytic capacitor such as Sanyo MVGX series, Panasonic FA series as well as the Nichicon PL series insures both stability and good transient response. Thermal Design The IRU1050 incorporates an internal thermal shutdown that protects the device when the junction temperature exceeds the maximum allowable junction temperature. Although this device can operate with junction temperatures in the range of 1508C, it is recommended that the selected heat sink be chosen such that during maximum continuous load operation the junction temperature is kept below this number. The example below shows the steps in selecting the proper regulator heat sink for the worst case current consumption using Intel 200MHz microprocessor as the load. www.irf.com Rev. 1.8 08/20/02 IRU1050 Assuming the following specifications: 0 VIN = 5V VOUT = 3.5V IOUT(MAX) = 4.6A TA = 358C Thermalloy AAVID The steps for selecting a proper heat sink to keep the junction temperature below 1358C is given as: 6021PB Air Flow (LFM) 100 200 300 400 6021PB 6073PB 7141D 534202B 534202B 507302 6109PB 575002 576802B Note: For further information regarding the above companies and their latest product offerings and application support contact your local representative or the numbers listed below: 1) Calculate the maximum power dissipation using: AAVID.................PH# (603) 528 3400 Thermalloy...........PH# (214) 243-4321 PD = IOUT3(V IN - VOUT) PD = 4.63(5 - 3.5) = 6.9W 2) Select a package from the regulator data sheet and record its junction to case (or tab) thermal resistance. Selecting TO-220 package gives us: uJC = 2.78C/W 3) Assuming that the heat sink is black anodized, calculate the maximum heat sink temperature allowed: Assume, ucs=0.05°C/W (heat-sink-to-case thermal resistance for black anodized) TS = TJ - PD3(uJC + uCS) TS = 135 - 6.93(27 + 0.05) = 1168C 4) With the maximum heat sink temperature calculated in the previous step, the heat-sink-to-air thermal resistance (uSA) is calculated by first calculating the temperature rise above the ambient as follows: DT = TS - TA = 116 - 35 = 818C ∆T = Temperature Rise Above Ambient uSA = DT 81 = = 11.78C/W PD 6.9 5) Next, a heat sink with lower uSA than the one calculated in Step 4 must be selected. One way to do this is to simply look at the graphs of the “Heat Sink Temp Rise Above the Ambient” vs. the “Power Dissipation” and select a heat sink that results in lower temperature rise than the one calculated in previous step. The following heat sinks from AAVID and Thermalloy meet this criteria. Rev. 1.8 08/20/02 Designing for Microprocessor Applications As it was mentioned before, the IRU1050 is designed specifically to provide power for the new generation of the low voltage processors requiring voltages in the range of 2.5V to 3.6V generated by stepping down the 5V supply. These processors demand a fast regulator that supports their large load current changes. The worst case current step seen by the regulator is anywhere in the range of 1 to 7A with the slew rate of 300 to 500ns which could happen when the processor transitions from “Stop Clock” mode to the “Full Active” mode. The load current step at the processor is actually much faster, in the order of 15 to 20ns, however, the decoupling capacitors placed in the cavity of the processor socket handle this transition until the regulator responds to the load current levels. Because of this requirement the selection of high frequency low ESR and low ESL output capacitor is imperative in the design of these regulator circuits. Figure 5 shows the effects of a fast transient on the output voltage of the regulator. As shown in this figure, the ESR of the output capacitor produces an instantaneous drop equal to the (DVESR =ESR3DI) and the ESL effect will be equal to the rate of change of the output current times the inductance of the capacitor. (DVESL =L3DI/Dt). The output capacitance effect is a droop in the output voltage proportional to the time it takes for the regulator to respond to the change in the current, (DVc=Dt3DI/C) where Dt is the response time of the regulator. www.irf.com 5 IRU1050 2) The output capacitance is 531500mF = 7500mF V ESR V ESL DVc = VC Dt 3 DI 2 3 4.6 = = 1.2mV C 7500 Where: Dt = 2ms is the regulator response time T LOAD CURRENT 1050plt1-1.0 To set the output DC voltage, we need to select R1 and R2: LOAD CURRENT RISE TIME 3) Assuming R1=121V, 0.1%: Figure 5 - Typical regulator response to the fast load current step. R2 = An example of a regulator design to meet the Intel P54C VRE specification is given below. Assume the specification for the processor as shown in Table 1: Type of Processor Intel-P54C VRE V OUT Nominal 3.50 V IMAX Max Allowed Output Tolerance 4.6 A ±100 mV Table 1 - Processor Specification 1) Assuming the regulator’s initial accuracy plus the resistor divider tolerance is ≈ ±53mV (±1.5% of 3.5V nominal), then the total step allowed for the ESR and the ESL is −47mV. Assuming that the ESL drop is −10mV, the remaining ESR step will be −37mV. Therefore the output capacitor ESR must be: 37 = 8mV 4.6 The Sanyo MVGX series is a good choice to achieve both price and performance goals. The 6MV1500GX, 1500mF, 6.3V has an ESR of less than 36mV typical. Selecting 5 of these capacitors in parallel has an ESR of ≈ 7.2mV which achieves our design goal. The next step is to calculate the drop due to the capacitance discharge and make sure that this drop in voltage is less than the selected ESL drop in the previous step. 6 OUT REF Select R2=218V, 0.1% Selecting both R1 and R2 resistors to be 0.1% tolerance, results in the least amount of error introduced by the resistor dividers leaving ≈ ±1.3% error budget for the IRU1050 reference which is within the initial accuracy of the device. Finally, the input capacitor is selected as follows: The first step is to select the voltage step allowed in the output due to the output capacitor’s ESR: ESR [ 3.5 -1)3121 = 217.8V ( VV -1)3R1 =( 1.25 4) Assuming that the input voltage can drop 150mV before the main power supply responds, and that the main power supply response time is ≈ 50ms, then the minimum input capacitance for a 4.6A load step is given by: CIN = 4.6 3 50 = 1530mF 0.15 The ESR should be less than: ESR = (V IN - VOUT - DV - VDROP) DI Where: VDROP L Input voltage drop allowed in step 4 DV L Maximum regulator dropout voltage DI L Load current step ESR = (5 - 3.5 - 1.2 - 0.15) = 0.032V 4.6 Selecting two Sanyo 1500mF, the same type as the output capacitors, meets our requirements. www.irf.com Rev. 1.8 08/20/02 IRU1050 Figure 6 shows the completed schematic for our example. 5V C1 1500uF 3.50V V OUT V IN C2 5x 1500uF IRU1050 Adj R1 121 0.1% Layout Consideration The output capacitors must be located as close to the VOUT terminal of the device as possible. It is recommended to use a section of a layer of the PC board as a plane to connect the V OUT pin to the output capacitors to prevent any high frequency oscillation that may result due to excessive trace inductance. R2 218 0.1% Figure 6 - Final schematic for the Intel VRE application. IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information Data and specifications subject to change without notice. 02/01 Rev. 1.8 08/20/02 www.irf.com 7 IRU1050 (D) TO-252 Package 2-Pin K A C B L M 78 458 D J N E O P Q R G F S H R1 SYMBOL MIN MAX A 6.477 6.731 B 5.004 5.207 C 0.686 0.838 D 7.417 8.179 E 9.703 10.084 F 0.635 0.889 2.286 BSC G H 4.521 4.623 J &1.52 &1.62 K 2.184 2.388 L 0.762 0.864 M 1.016 1.118 N 5.969 6.223 O 1.016 1.118 P 0 0.102 Q 0.534 0.686 R R0.31 TYP R1 R0.51 TYP S 0.428 0.588 C L NOTE: ALL MEASUREMENTS ARE IN MILLIMETERS. 8 www.irf.com Rev. 1.8 08/20/02 IRU1050 (M) TO-263 Package 3-Pin A E U K S V B M H L P D G N R C C L SYMBOL A B C D E G H K L M N P R S U V MIN MAX 10.05 10.312 8.28 8.763 4.31 4.572 0.66 0.91 1.14 1.40 2.54 REF 14.73 15.75 1.40 1.68 0.00 0.254 2.49 2.74 0.33 0.58 2.286 2.794 08 88 2.41 2.67 6.50 REF 7.75 REF NOTE: ALL MEASUREMENTS ARE IN MILLIMETERS. Rev. 1.8 08/20/02 www.irf.com 9 IRU1050 (P) Ultra Thin-PakTM 2-Pin A A1 E U K V B H M L P G D G1 N C R C L SYMBOL A A1 B C D E G G1 H K L M N P R U V MIN MAX 5.91 6.17 5.54 5.79 6.02 6.27 1.70 2.03 0.63 0.79 0.17 0.33 2.16 2.41 4.45 4.70 9.42 9.68 0.76 1.27 0.02 0.13 0.89 1.14 0.25 0.25 0.94 1.19 28 68 2.92 3.30 5.08 NOM NOTE: ALL MEASUREMENTS ARE IN MILLIMETERS. 10 www.irf.com Rev. 1.8 08/20/02 IRU1050 (T) TO-220 Package 3-Pin H1 L Q b1 e3 e e1 C L E b R E-PIN CP a (5x) C1 A J1 D F C L SYMBOL MIN MAX A 4.06 4.83 a 38 7.58 b 0.63 1.02 b1 1.14 1.52 C1 0.38 0.56 CP 3.71D 3.96D D 14.22 15.062 E 9.78 10.54 e 2.29 2.79 e1 4.83 5.33 e3 1.14 1.40 F 1.14 1.40 H1 5.94 6.55 J1 2.29 2.92 L 13.716 14.22 Q 2.62 2.87 R 5.588 6.17 NOTE: ALL MEASUREMENTS ARE IN MILLIMETERS. Rev. 1.8 08/20/02 www.irf.com 11 IRU1050 PACKAGE SHIPMENT METHOD PKG DESIG PACKAGE DESCRIPTION PIN COUNT PARTS PER TUBE PARTS PER REEL T&R Orientation D TO-252, (D-Pak) 2 75 2500 Fig A M TO-263 3 50 750 Fig B 2 75 2500 Fig C 3 50 --- --- P Ultra Thin-Pak T TO-220 1 TM 1 1 1 Feed Direction Figure A 1 1 Feed Direction FigureB 1 1 1 Feed Direction FigureC IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information Data and specifications subject to change without notice. 02/01 12 www.irf.com Rev. 1.8 08/20/02