Microcomputer Components Standalone Full-CAN Controller SAE 81C90/91 Data Sheet 01.97 Preliminary Stand Alone Full CAN Controller SAE 81C90/91 ● Full CAN controller for data rate up to 1 Mbaud ● Complies with CAN specification V2.0 part A ● ● ● ● ● ● ● ● ● ● (part B passive) Up to 16 messages simultaneous (each with maximum data length) Message identifier reprogrammable “on the fly” Several transmit jobs can be sent with a single command Transmit check Basic CAN feature Time stamp for eight messages Two host interfaces (parallel and serial) User-configurable outputs for different bus concepts Programmable clock output Two 8 bit I/O-Port extension (P-LCC-44-1 package only) P-LCC-44-1 P-LCC-28-1 The device comes in two versions: SAE 81C90 in a P-LCC-44-1 package with two 8-bit l/O ports, and SAE 81C91 in a P-LCC-28-1 package without l/O ports. SAE 81C90/91 Revision History: Previous Releases: Version 01.97 06.95 05.94 (Copy version) Page Subjects 1056 Figure 1 corrected. 1057 Figure 2 corrected. 1059 Notes updated. 1065 - 1084 Register description and arrangement improved. 1066, 1069 New register maps. 1093 tAVLL, tLLAX, tDVWH changed to 10 ns. 1093 tWHDX changed to 5 ns. Controller Area Network (CAN): License of Robert Bosch GmbH Semiconductor Group 1 01.97 SAE 81C90/91 07Feb95@09:05h Intermediate Version Introduction The Siemens Stand Alone Full CAN (SFCAN) circuit incorporates all the parts for completely autonomous transmission and reception of messages using the CAN protocol. The flexible, programmable interface allows hookup to different implementations of the physical layer. The link to a host controller can be made either by a multiplexed 8-bit address/data bus or by a high-speed, serial synchronous interface. Figure 1 Logic Symbol Ordering Information Type Ordering Code Package Function SAE 81C91 Q67121-F0001 P-LCC-28-1 Stand Alone Full CAN Controller Temperature range – 40 to + 110 ˚C SAE 81C90 Q67121-H9038 P-LCC-44-1 Stand Alone Full CAN Controller Temperature range – 40 to + 110 ˚C Semiconductor Group 2 07Feb95@09:05h Intermediate Version Pin Configurations (top view) Figure 2 Semiconductor Group 3 SAE 81C90/91 07Feb95@09:05h Intermediate Version SAE 81C90/91 Pin Definitions and Functions Symbol Pin Number Input (I) PLCC-48 PLCC-28 Output (O) Function X1 1) 11 28 O Crystal oscillator output. Must be unconnected for external clock input. X2 1) 10 27 I Crystal oscillator input. Used for external clock input. CLKOUT 1) 14 3 O Clock output RES 19 4 I Reset. (Schmitt trigger characteristic) AD0/DI 42 19 I/O PI: Address / Data bus / SI: Data input AD1/DO 43 20 I/O PI: Address / Data bus / SI: Data output AD2/CLK 44 21 I/O PI: Address / Data bus / SI: Clock input AD3/W 1 22 I/O PI: Address / Data bus / SI: Write select AD4/TIM 2 23 I/O PI: Address / Data bus / SI: TIM = 0: Timing A; TIM = 1: Timing B AD5 3 24 I/O PI: Address/Data bus AD6 4 25 I/O PI: Address/Data bus AD7 5 26 I/O PI: Address/Data bus RD 35 16 I PI: Read / SI: no Function WR 36 17 I PI: Write / SI: no Function ALE 34 15 I PI: Address Latch Enable / SI:no Function CS 27 12 I Chip Select INT 41 18 O Interrupt MS 26 11 I Mode Select (PI ↔ SI) P00 … P03, 28, 29, 30, 31, P04 … P07 37, 38, 39, 40 – I/O – I/O Port 0 These pins provide internal pullup resistors of about 10...200 kΩ. P10 … P13, 18, 17, 16, 15, P14 … P17 9, 8, 7, 6 – I/O – I/O Port 1 These pins provide internal pullup resistors of about 10...200 kΩ. TX0 25 10 O Transmitter output 0 TX1 24 9 O Transmitter output 1 RX0 23 8 I Comparator input 0 / Digital input 2) RX1 22 7 I Comparator input 1 2) VDDA 20 5 I Analog power supply for comparator (may be unconnected using the digital mode) Semiconductor Group 4 07Feb95@09:05h Intermediate Version SAE 81C90/91 Pin Definitions and Functions (cont’d) Symbol Pin Number Input (I) PLCC-48 PLCC-28 Output (O) Function VSSA 21 6 I Analog power ground for comparator (must always be connected) VDD1 13 2 I Digital power supply 3) VDD2 32 13 I Digital power supply VSS1 12 1 I Digital power ground 3) VSS2 33 14 I Digital power ground 1) For best results keep the crystal circuitry connections as short as possible and keep the CLKOUT line away from it. 2) If the bus lines work according to the ISO specification, additional circuitry is necessary for interconnection of the input comparator to the bus lines. The digital mode is enabled by setting bit DI in register BL2. When using the digital mode pin RX1 should be on VSS. 3) It is recommended to decouple these supply pins close to the device using a 10 pF capacitor in addition to the standard 100 nF capacitor. Semiconductor Group 5 07Feb95@09:05h Intermediate Version SAE 81C90/91 Functional Description The Siemens stand-alone Full-CAN (SFCAN) circuit is a large-scale-integrated peripheral device that executes the entire protocol of an automobile or industrial network. Figure 3 Block Diagram Semiconductor Group 6 07Feb95@09:05h Intermediate Version SAE 81C90/91 Bus communication is based on the controller-area-network (CAN) protocol. With features like short message length, guaranteed reaction time for messages of appropriate priority, which is defined by the message identifiers. Also included are powerful error detection and treatment capabilities plus ease of operation. The CAN protocol is especially designed for the requirements of automobile and industrial electronic networks. The SFCAN circuit incorporates all the parts for completely independent transmission and reception of messages using the CAN protocol. The flexible, programmable interface allows connection to different implementations of the physical layer. The link to a host controller can be made either by a multiplexed 8-bit address/data bus or by a high-speed, serial synchronous interface. Message Memory The SFCAN circuit filters incoming messages with an associative memory (CAM = contentaddressable memory). For this the identifier and RTR bits of the required message must be written to the appropriate memory location. The identifier of each incoming message is compared with the identifiers stored in the CAM. Upon a match the received data bytes are written into the RAM buffer of the matching message. At the same time the corresponding receive-ready bit is set and a receive interrupt is generated, if it is enabled. If no match is detected, the received message is rejected. Identifiers can be reprogrammed at any time, although it is possible that data of the old or new identifier may be lost during reprogramming. An incoming transmit request will only be satisfied automatically by the hardware if the RTR bit of the particular identifier is set in CAM. To ensure data consistency when reading or writing several data bytes of a specific message the message objects are not accessed directly but via a 64-bit shadow register (see figure below). This shadow register stores the complete data field of a certain message object for both reading and writing. For read accesses the message’s data field is copied to the shadow register... ...with the 1st read access to the respective data field (e.g. 80H ... 87H for message 0), or ...with any read access to byte 7 of the respective data field (e.g. 87H for message 0). This ensures that all bytes read via the shadow register belong to the same message, even though a new one might have been received in the meantime. For write accesses the shadow register is copied to the respective message data field... ...with any write access to byte 0 of the respective data field (e.g. 80H for message 0). This ensures that only completely updated message are transmitted. It is therefore recommended to begin all read and write accesses with the most-significant data byte of a message and end with data byte 0. This ensures operations on consistent data and correct transfers between the shadow register and the message RAM. Note: For these reasons it is absolutely essential to ensure that the writing of data is not interrupted by a read operation and vice versa, a read operation should not be interrupted by a write. Semiconductor Group 7 07Feb95@09:05h Intermediate Version Figure 4 CAM, Message Memory and Time-Stamp Registers Semiconductor Group 8 SAE 81C90/91 07Feb95@09:05h Intermediate Version SAE 81C90/91 Bit Stream Processor (BSP) The bit-stream processor controls the entire protocol, differentiates between the frames types and detects frame errors. Error Management Logic (EML) The error-management logic receives error messages from the BSP and, in turn, sends back information about error state to the BSP and CIL. Bit Timing Logic (BTL) The bit-timing logic determines the timing of the bits and synchronizes with the edges of the bit stream on the CAN bus. Transceiver Control Logic (TCL) The transceiver-control logic consists of programmable output driver, input comparator and input multiplexer. Clock Generator (CG) The clock generator consists of an oscillator and a programmable divider. The oscillator can be fed from an external quartz crystal, ceramic resonator or an external timing source. The permissible crystal frequency is 1 to 20 MHz, and the external clock may be between 0 and 20 MHz. A programmable frequency, dependent on the crystal clock, is available with the CLKOUT pin, e.g. for the clocking of a host controller. CPU Interface Logic (ClL) The CPU interface logic controls the access of the host via the parallel or serial interface, interprets the commands and outputs status and interrupt information. Transmit Check The CAN protocol ensures a very high integrity for the data transferred over the bus. The on-chip path from the data stored in parallel to the serial bit stream is not protected by the protocol. To eliminate any possible uncertainties at this point too, the SFCAN circuit incorporates a transmitcheck unit. This unit reads back a transmitted message via the normal receive path from the bus interface and compares the data with those written into the message memory by the host controller. If any inconsistency of the data is detected, the current message will be invalidated by an error frame. The transmit-check error counter TCEC is then incremented by 1. If this counter reaches 4 an error interrupt (bit TCI in the INT register) is generated, provided that this has not been masked (bit ETCI in the IMSK register). This count will also produce the Bus Off status. The TCEC is set to 0 after a reset and can be read and also written for test purposes at any time. Note: The transmit-check is an additional feature of the Siemens Full CAN Chip and is not part of the CAN protocol. Semiconductor Group 9 07Feb95@09:05h Intermediate Version SAE 81C90/91 Time Stamp It is impossible to determine from the received data in the message memory when they were received. So the host controller is unable to derive any information about the actuality or the repetition rate of the data. To enable an indication of the time of reception for at least some of the messages, a 16-bit timer is implemented on the SAE 81C90/91. The content of this gets written into the time-stamp registers of the particular message when it is received (for the messages 0 through 7). There are two timestamp bytes for each of the messages 0 through 7, and these hold the value of the 16-bit timer. The actuality of a message is determined by subtracting the old time-stamp of a message, stored in the host controller, from the new one, with respect to the timer overflow bit. Overflow of the timer can be detected by bit TSOV in the CTRL register. This bit does not trigger an interrupt and has to be reset by the host controller. Depending on the setting of bitfield TSP in register CTRL, the counter is fed with 1/32, 1/64, 1/128 or 1/256 of the bus clock. The momentary timer status can be read and set at any time. The timer starts at 0 after a reset and cannot be stopped. I/O-Ports There are two parallel I/O ports in the SAE 81C90, each with eight pins. These ports are configured pin by pin as input or output, depending on the contents of the port-direction register. The output data for the port pins can be written (latched) into the port-latch register. Reading this register reproduces the contents of the latch. The levels on the port pins can be read from the portpin register. For the SAE 81C91 in its P-LCC-28-1 package, the pads of the I/O ports are not bonded and therefore unavailable to the user. Note: Registers PxPDR and PxPL may be used for general purpose storage if the ports are not used. Semiconductor Group 10 07Feb95@09:05h Intermediate Version SAE 81C90/91 Device Control and Registers The operation of the SAE 81C90/91 is controlled via a number of registers. These registers allow initialization and function control, provide status information and configure the message objects. The upper part of the address space provides access to the data buffers of the message objects. The data buffers are ordered sequentially as shown in the table below. The register map on the next page summarizes the other registers (i.e. except the data registers) ordered by their address, while the following pages describe these registers in more detail from a functional point of view. Note: Locations marked “Reserved” in the register map must not be written in initialization mode. This also applies to locations 60H through 7FH. Data Registers Address Function 80H Byte 0 81H Byte 1 82H Byte 2 83H Byte 3 84H Byte 4 85H Byte 5 86H Byte 6 87H Byte 7 88H Byte 0 89H Byte 1 : : : F6H Byte 6 Message 14 F7H Byte 7 F8H Byte 0 F9H Byte 1 FAH Byte 2 FBH Byte 3 FCH Byte 4 FDH Byte 5 FEH Byte 6 FFH Byte 7 Semiconductor Group Message 0 Message 1 Message 15 11 SAE 81C90/91 07Feb95@09:05h Intermediate Version Register Map (ordered by address) Addr. Reg. Name Reset Addr. Reg. Name Reset Addr. Reg. Name Reset 00H BL1 00H 20H Reserved 40H DR0H UUH 01H BL2 00H 21H Reserved 41H DR0L UUH 02H OC 00H 22H Reserved 42H DR1H UUH 03H BRP 00H 23H Reserved 43H DR1L UUH 04H RRR1 00H 24H Reserved 44H DR2H UUH 05H RRR2 00H 25H Reserved 45H DR2L UUH 06H RIMR1 00H 26H Reserved 46H DR3H UUH 07H RIMR2 00H 27H Reserved ----------------- 47H DR3L UUH 08H TRS1 00H 28H P0PDR 00H 48H DR4H UUH 09H TRS2 00H 29H P0PR XXH 49H DR4L UUH 0AH IMSK 00H 2AH P0LR 00H 4AH DR5H UUH 0BH Reserved 2BH Reserved --- 4BH DR5L UUH 0CH Reserved 2CH P1PDR 00H 4CH DR6H UUH 0DH Reserved 2DH P1PR XXH 4DH DR6L UUH 0EH Reserved 2EH P1LR 00H 4EH DR7H UUH 0FH Reserved ----------- 2FH Reserved --- 4FH DR7L UUH 10H MOD 00H 30H TSR0H UUH 50H DR8H UUH 11H INT 00H 31H TSR0L UUH 51H DR8L UUH 12H CTRL 00H 32H TSR1H UUH 52H DR9H UUH 13H Reserved --- 33H TSR1L UUH 53H DR9L UUH 14H CC 01H 34H TSR2H UUH 54H DR10H UUH 15H TCEC 00H 35H TSR2L UUH 55H DR10L UUH 16H TCD XXH 36H TSR3H UUH 56H DR11H UUH 17H Reserved --- 37H TSR3L UUH 57H DR11L UUH 18H TRR1 00H 38H TSR4H UUH 58H DR12H UUH 19H TRR2 00H 39H TSR4L UUH 59H DR12L UUH 1AH RRP1 00H 3AH TSR5H UUH 5AH DR13H UUH 1BH RRP2 00H 3BH TSR5L UUH 5BH DR13L UUH 1CH TSCH 00H 3CH TSR6H UUH 5CH DR14H UUH 1DH TSCL 00H 3DH TSR6L UUH 5DH DR14L UUH 1EH Reserved 3EH TSR7H UUH 5EH DR15H UUH 1FH Reserved ----- 3FH TSR7L UUH 5FH DR15L UUH Note: The locations marked “UUH” are not changed upon a reset. After a power on reset they are undefined (XXH), of course. Semiconductor Group 12 SAE 81C90/91 07Feb95@09:05h Intermediate Version Descriptor Registers A descriptor register is available for each message object and contains the eleven bits of the message identifier (ID.0 through ID.10), the remote-transmission-request bit (RTR) and the data length code (DLC) of a message. DRnH 7 6 5 4 3 2 1 0 ID.10 ID.9 ID.8 ID.7 ID.6 ID.5 ID.4 ID.3 Reset Value: UUH rw rw rw rw rw rw rw rw DRnL 7 6 5 4 3 2 1 0 ID.2 ID.1 ID.0 RTR rw rw rw rw rw rw Address: XXH Address: XXH Reset Value: UUH DLC rw rw Bit(field) Function DLC Data Length Code Defines the number of data bytes of message n. Defined values are 0000...1000, i.e. 0...8 bytes. Other values are not permitted. RTR Remote Transmission Request Bit ‘0’: This message operates as a data frame. ‘1’: This message operates as a remote frame. Note: See description and table below. ID.10-0 Identifier Identifier associated with message n, controls the acceptance of received frames and is inserted into transmitted frames. n = 0...15 Bit RTR determines the function of the corresponding message object when it is transmitted, and its reaction on a received data frame or remote frame. The table below summarizes the message object’s behaviour in the different cases. RTR bit Object is transmitted ’0’ (data frame) The message object is transmitted as a standard data frame. ’1’ The message object is (remote transmitted as a remote frame) frame (i.e. a request). Matching Data Frame received Matching Remote Frame received The data frame is stored in the message object. The remote frame is ignored. The data frame is ignored and not stored. The message object is sent as a data frame. Note: For the transmission of remote frames (RTR = 1) the data-length-code should be set to ‘0’. Semiconductor Group 13 07Feb95@09:05h Intermediate Version SAE 81C90/91 Descriptor Register Arrangement Address Function 40H High Byte 41H Low Byte 42H High Byte 43H Low Byte : : 5CH High Byte 5DH Low Byte 5EH High Byte 5FH Low Byte Semiconductor Group Descriptor Register for Message Object 0 Descriptor Register for Message Object 1 : Descriptor Register for Message Object 14 Descriptor Register for Message Object 15 14 07Feb95@09:05h Intermediate Version SAE 81C90/91 Control Register Summary Register Name Address Function Reset Value Read Write 1) OC 02H Output-control register 00H r/w, I CC 14H Clock-control register 01H wo CTRL 12H Control register 00H r/w MOD 10H Mode/status register 00H r/w INT 11H Interrupt register 00H r/w IMSK 0AH Interrupt-mask register 00H r/w BL1 00H Bit-length register 1 00H r/w, I BL2 01H Bit-length register 2 00H r/w, I BRP 03H Baud-rate prescaler 00H wo, I RRR1 04H Receive-ready register 1 00H r/w RRR2 05H Receive-ready register 2 00H r/w RIMR1 06H Receive-interrupt-mask register 1 00H r/w RIMR2 07H Receive-interrupt-mask register 2 00H r/w TRSR1 08H Transmit-request-set register 1 00H r/w TRSR2 09H Transmit-request-set register 2 00H r/w TRRR1 18H Transmit-request-reset register 1 00H wo TRRR2 19H Transmit-request-reset register 2 00H wo RRPR1 1AH Remote-request-pending register 1 00H ro RRPR2 1BH Remote-request-pending register 2 00H ro TSCH 1CH Time-Stamp counter high byte 00H r/w TSCL 1DH Time-Stamp counter low byte 00H r/w TCEC 15H Transmit-check error counter 00H r/w TCD 16H Transmit-check data register XX ro P0PDR 28H Port 0 port-direction register 00H r/w P1PDR 2CH Port 1 port-direction register 00H r/w P0LR 2AH Port 0 latch register 00H r/w P1LR 2EH Port 1 latch register 00H r/w P0PR 29H Port 0 pin register XXH ro P1PR 2DH Port 1 pin register XXH ro Note: 1) ro: read only, r/w: read and write access, wo: write only, I: access only with bit IM set. Semiconductor Group 15 SAE 81C90/91 07Feb95@09:05h Intermediate Version Output-Control Register The output drivers of the SAE 81C90/91’s transmit pins (TXn) can be individually configured. Thus they can be adapted to the requirements of the external bs system. OC 7 Address: 02H 6 OCTP1 OCTN1 Reset Value: 00H rw rw Bit(field) Function OCM Output Mode ’0X’: Normal Mode: ’10’: Test Mode: ’11’: Clock Mode: 5 OCP1 4 3 2 OCTP0 OCTN0 rw rw rw TX0 = Bit Sequence, TX0 = Bit Sequence, TX0 = Bit Sequence, 1 OCP0 rw 0 OCM rw TX1 = Bit Sequence. TX1 = RX0. TX1 = Bit Clock. OCPn Output Polarity ’0’: Output is driven directly with CAN data. ’1’: Output is driven with inverted CAN data. OCTNn Negative Output Transistor Control ’0’: The low side output transistor TnN is disabled. ’1’: The low side output transistor TnN drives the pin according to data. OCTPn Positive Output Transistor Control ’0’: The high side output transistor TnP is disabled. ’1’: The high side output transistor TnP drives the pin according to data. n = 0, 1 Note: This register can only be written when bit IM (MOD.0) is set. Figure 5 Output Control Circuitry Semiconductor Group 16 rw SAE 81C90/91 07Feb95@09:05h Intermediate Version Output Programming OCTP.n 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 OCTN.n 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 OCP.n 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Data 0 = dominant 1 = recessive 0 1 0 1 0 1 0 1 0 1 0 1 0 1 TnP OFF OFF OFF OFF OFF OFF OFF OFF OFF ON ON OFF OFF ON ON OFF TnN OFF OFF OFF OFF ON OFF OFF ON OFF OFF OFF OFF ON OFF OFF ON TXn-Level float float float float LOW float float LOW float HIGH HIGH float LOW HIGH HIGH LOW TnP is the output transistor switching to VDD, TnN switches to VSS. TXn is the output level at the transmit pin. Clock Control Register The Clock Control Register determines the output frequency at pin CLKOUT which is derived from the oscillator frequency. CCR 7 6 5 4 3 2 1 0 Address: 14H CC Reset Value: 01H w w w w Bit(field) CC Function Clock Output Control ’0000’: fCLKOUT = fOSC ’0001’: fCLKOUT = fOSC / 2 ’0010’: fCLKOUT = fOSC / 4 ’0011’: fCLKOUT = fOSC / 6 ’0100’: fCLKOUT = fOSC / 8 ’0101’: fCLKOUT = fOSC / 10 ’0110’: fCLKOUT = fOSC / 12 ’0111’: fCLKOUT = fOSC / 14 ’1XXX’: fCLKOUT = LOW (clock output is switched off) The Clock Control Register requires a special protocol for writing in order to prevent the clock output from being changed inadvertently: ● Step 1: Write 80H to CC ● Step 2: Write desired value to CC (bits 7...4 must be ’0000’) Note: Not defined bit positions must be ’0’ for write accesses. Semiconductor Group 17 SAE 81C90/91 07Feb95@09:05h Intermediate Version Control Register CTRL 7 6 Address: 12H RX TST Reset Value: 00H rw rw 5 4 TSP rw rw 3 2 1 0 TSOV SME TCE MM rw rw rw rw Bit(field) Function MM Monitor Mode ’0’: Message object 0 operates like all other objects. ’1’: Message object 0 receives all identifiers that are not accepted by other objects (corresponds to a Basic CAN receive register). TCE Transmit Check Enable ’0’: If the transmit check detects an error, there is no intervention. ’1’: If the transmit check detects an error, the message is invalidated by an error frame and the error counter TCEC is incremented by 1. If the counter reaches 4, the Bus Off status is initiated and, if enabled, an interrupt (TCI) is generated. SME Sleep Mode Enable ’0’: Normal operation. ’1’: The sleep mode is enabled: the crystal oscillator is deactivated, all other activities are inhibited. The wake up is done by a reset signal or by an active signal at the CS pin or by an input edge going from recessive to dominant at pin Rx0 or Rx1. TSOV Time Stamp Overflow ’0’: There has been no overflow ’1’: There was at least one overflow of the time-stamp timer. TSP Time Stamp Prescaler (Defines the input clock of the time-stamp timer) ’00’: fBL / 32 ’01’: fBL / 64 ’10’: fBL / 128 ’11’: fBL / 256 (For fBL see baud-rate prescaler BRP). TST Time Stamp Test ’0’: The prescaler is activated. ’1’: The time-stamp prescaler is deactivated. (Only for testing purposes, bit IM = MOD.0 must be set to ’1’). RX Input Monitor RX This bit monitors the actual state of the digital input pin RX0. Semiconductor Group 18 SAE 81C90/91 07Feb95@09:05h Intermediate Version Mode/Status-Register MOD Address: 10H Reset Value: 00H 7 6 5 4 3 2 1 0 ADE RS TC TWL RWL BS RES IM rw r r r r r rw rw Bit(field) Function IM Init Mode ’0’: Normal mode. ’1’: Initialization mode: write access to the configuration registers BL1, BL2, OC, BRP is enabled. If the bit stays set, the chip enters the normal mode, with enabled access to the configuration registers. If this bit is set in conjunction with bit RES a hard software reset is activated. RES Reset Request ’0’: Normal mode. ’1’: The chip enters the reset state: – if bit IM = ’0’ a soft software reset takes place. – if bit IM = ’1’ a hard software reset takes place. Further details see below. BS Bus State (read only) ’0’: Normal mode. ’1’: Bus Off state, the IC does not participate in bus activities. RWL Receiver Warning Level (read only) ’0’: Receive-error counter below 96. ’1’: Receive-error counter equal or above 96. TWL Transmit Warning Level (read only) ’0’: Transmit-error counter below 96. ’1’: Transmit-error counter equal or above 96. TC Transmission Complete (read only) ’0’: The last transmission request is not yet executed successfully. ’1’: The last transmission request was executed successfully. RS Receive State (read only) ’0’: No reception active. ’1’: Currently the SAE 81C90/91 is in receive mode. ADE Auto Decrement Enable ’0’: No automatic address decrement. ’1’: With every read or write access using the serial synchronous interface SI the address is automatically decremented by one. So data can be accessed sequentially without the need of writing a new address. Semiconductor Group 19 07Feb95@09:05h Intermediate Version SAE 81C90/91 Notes on Bit TC Scanning this bit is particularly useful if only one transmission is active. If there are several transmission jobs at the same time, it is better to scan the transmit-request register, because bit TC may possibly only be set very briefly between acknowledgment of the previous message and the start of the next one. Notes on Bit RES and IM and reset modes There are three different reset modes implemented in the SAE 81C90/91: hardware reset (activated by low level on pin RES) hard software reset (activated by setting both bits RES and IM to 1) soft software reset (activated by setting bit RES to 1 and bit IM to 0) The only difference between hardware and hard software reset affect bits RES and IM, that are not changed by software reset. With soft software reset the registers RRR1, RRR2, TRSR1, TRSR2, RRPR1 and RRPR2 are cleared, all bus activities are stopped, the error counters are not cleared, the Bus Off state is cancelled only after 128 idle phases (according to the CAN protocol 1 idle phase = 11 recessive bits in sequence). Simply spoken a soft software reset interrupts and cancels all bus activities and - if necessary - recovers from Bus Off state. Notes on Bit RS Bit RS directly reflects the internal status. RS is ’0’ during transmission or when the SAE 81C90/91 is idle. RS is ’1’ during reception or during the synchronization after a reset. Semiconductor Group 20 SAE 81C90/91 07Feb95@09:05h Intermediate Version Interrupt Register INT 7 6 5 4 3 2 1 0 Address: 11H TCI EPI BOI WUPI RFI WLI TI RI Reset Value: 00H rw rw rw rw rw rw rw rw Bit(field) Function RI Receive Interrupt After a valid message has been received and filed, this bit is set and an interrupt generated. This bit will remain set until all bits of the registers RRR1 and RRR2 are reset. TI Transmit Interrupt This bit is set and an interrupt generated as soon as a transmit request has been processed. WLI Warning Level Interrupt If at least one of the two error counters is greater than or equals 96, this bit is set and an interrupt generated. RFI Remote Frame Interrupt This interrupt is generated after reception of a remote frame. WUPI Wake Up Interrupt After a wake-up this bit is set and an interrupt generated. BOI Bus Off Interrupt This bit is set and an interrupt generated when the Bus Off status is entered. EPI Error Passive Interrupt If at least one of the two error counters is greater than or equals 128, this bit is set and an interrupt generated. TCI Transmit Check Interrupt If the transmit-check error counter reaches 4, this bit is set and an interrupt generated. Note: All bits of this register must be reset by software. This is done by writing ’0’ to the respective bit location, writing ’1’ has no effect. An interrupt is only generated if the respective IMSK bit is set. The bits in this register are set independent of register IMSK (see below). The interrupt output is active for at least one bit time. The interrupt output is deactivated when all enabled request bits are cleared. A request bit is enabled by setting its corresponding mask bit. Masked request bits do not activate the interrupt output. Semiconductor Group 21 SAE 81C90/91 07Feb95@09:05h Intermediate Version Interrupt-Mask Register These mask bits determine if an event activates the INT pin. They do not influence the INT register. IMSK Address: 0AH 7 6 5 4 3 2 1 0 ETCI EEPI EBOI EWUPI ERFI EWLI ETI ERI rw rw rw rw rw rw rw rw Reset Value: 00H Bit(field) Function ERI Enable Receive Interrupt ’0’: No receive interrupt enabled. ’1’: Receive interrupts are enabled. ETI Enable Transmit Interrupt ’0’: No transmit interrupt enabled. ’1’: Completed transmit jobs generate interrupts. EWLI Enable Warning Level Interrupt ’0’: No warning level interrupt enabled. ’1’: There is an interrupt when the warning level is reached. ERFI Enable Remote Frame Interrupt ’0’: No remote frame interrupt enabled. ’1’: A receive interrupt is generated after receiving a remote frame EWUPI Enable Wake Up Interrupt ’0’: No wake up interrupt enabled. ’1’: Wake-up interrupt is enabled. EBOI Enable Bus Off Interrupt ’0’: No bus off interrupt enabled. ’1’: Bus off interrupt is enabled. EEPI Enable Error Passive Interrupt ’0’: No error passive interrupt enabled. ’1’: Error passive interrupt is enabled. ETCI Enable Transmit Check Error Interrupt ’0’: No transmit check interrupt enabled. ’1’: Transmit-check error interrupt is enabled. Semiconductor Group 22 SAE 81C90/91 07Feb95@09:05h Intermediate Version Bit-Length Registers BL1 7 Address: 00H 6 SAM Reset Value: 00H rw 5 4 3 2 TS2 rw 0 rw rw TS1 rw rw rw rw Bit(field) Function TS1 Length of Timing Segment 1 (TSeg1). tTSeg1 = (TS1 + 1) × tSCL. For tSCL see baud-rate prescaler BRP. TS2 1 Length of Timing Segment 2 (TSeg2). tTSeg2 = (TS2 + 1) × tSCL. For tSCL see baud-rate prescaler BRP. SAM Sample Rate ’0’: Input signal is sampled once per bit. ’1’: Input signal is sampled three times per bit. Note: Bit SAM should only be set to ’1’ using very low baud rates. BL2 Address: 01H 7 6 5 4 3 2 IPOL DI – – – SM rw rw - - - rw Reset Value: 00H 1 0 SJW rw Bit(field) Function SJW Maximum Synchronization Jump Width. tSJWidth = (SJW + 1) × tSCL. For tSCL see baud-rate prescaler BRP. SM Speed Mode (Defines edge used for synchronization) ’0’: Recessive to dominant is used. ’1’: Both edges are used. Note: According to the CAN specification this bit should not be set to ’1’. DI Digital Input ’0’: The input signal is applied to the input comparator. 1) ’1’: The input signal on pin RX0 is evaluated digitally. The input comparator is inactive. Pin RX1 should be on VSS. IPOL Input Polarity ’0’: The input level remains unaltered. ’1’: The input level is inverted. rw Note: Not defined bit positions must be ’0’ for write accesses. The Bit Length Registers BL1 and BL2 can only written while bit IM (MOD.0) is set. 1) If the bus lines work according to the ISO specification, additional circuitry is necessary for interconnection of the input comparator to the bus lines. Semiconductor Group 23 SAE 81C90/91 07Feb95@09:05h Intermediate Version Baud Rate Prescaler Register The register is not readable and can only be written when bit IM (MOD.0) is set. BRPR 7 6 Address: 03H – – Reset Value: 00H - - 5 4 3 2 1 0 w w w BRP w w w Bit(field) Function BRP Baud Rate Prescaler This prescaler determines the period of the system clock: tSCL = (BRP + 1) × 2 × tOSC, where tOSC = 1 / fcrystal. Note: Not defined bit positions must be ’0’ for write accesses. The bit length tBL is computed as follows: tBL = tTSeg1 + tTSeg2 + 1 tSCL The baudrate BR can be computed with the following formula: BR = fcrystal / (2 x (BRP + 1) x (TS1 + TS2 + 3) ) Note: BRP TS1 TS2 see Baud Rate Prescaler Register see Bit Length Register 1 see Bit Length Register 1 Semiconductor Group 24 SAE 81C90/91 07Feb95@09:05h Intermediate Version Receive-Ready Registers RRR2 7 6 5 4 3 2 1 0 RR15 RR14 RR13 RR12 RR11 RR10 RR9 RR8 Reset Value: 00H rw rw rw rw rw rw rw rw RRR1 7 6 5 4 3 2 1 0 RR7 RR6 RR5 RR4 RR3 RR2 RR1 RR0 rw rw rw rw rw rw rw rw Address: 05H Address: 04H Reset Value: 00H Bit(field) Function RRn Receive Ready Bit ’0’: No new message received in object n. ’1’: A new message has been received and stored in object n. These register bits can be reset by writing ’0’ to the respective bit, writing ’1’ has no effect. Bit RRn is set when a message has arrived and been written into the memory location of message n. Setting this bit by hardware can generate a receive interrupt, which can be blocked by bit RIMn in the receive-interrupt-mask register. Bits RRn must be reset by software. Receive-Interrupt-Mask Registers Setting bit RIMn enables a receive interrupt to be generated if the receive-ready bit RRn has been set, i.e. a message has arrived and was written into the memory location of message n. RIMR2 7 6 5 4 3 2 1 0 RIM15 RIM14 RIM13 RIM12 RIM11 RIM10 RIM9 RIM8 Reset Value: 00H rw rw rw rw rw rw rw rw RIMR1 7 6 5 4 3 2 1 0 RIM7 RIM6 RIM5 RIM4 RIM3 RIM2 RIM1 RIM0 rw rw rw rw rw rw rw rw Address: 07H Address: 06H Reset Value: 00H Bit(field) Function RIMn Receive Interrupt Mask Bit ’0’: No interrupt upon reception of object n. ’1’: When a new message is stored in object n an interrupt is generated. Note: Bit ERI in the interrupt-mask register IM blocks all receive interrupts, even if bits RIMn are set. Semiconductor Group 25 SAE 81C90/91 07Feb95@09:05h Intermediate Version Transmit Request Registers The Transmit Request Set Registers provide a transmission request bit (TRSn) for each message object. Setting a transmission request bit causes the respective message x to be transmitted. The bit is cleared by hardware after transmission. Several bits can be set simultaneously. In this way all messages whose request bits are set are transmitted in turn, starting with the memory location with the highest number. Note: A transmission request bit is set by writing ’1’ to the respective bit location (TRSn). Writing ’0’ has no effect. TRSR2 7 6 5 4 3 2 1 0 TRS15 TRS14 TRS13 TRS12 TRS11 TRS10 TRS9 TRS8 Reset Value: 00H rw rw rw rw rw rw rw rw TRSR1 7 6 5 4 3 2 1 0 TRS7 TRS6 TRS5 TRS4 TRS3 TRS2 TRS1 TRS0 rw rw rw rw rw rw rw rw Address: 09H Address: 08H Reset Value: 00H Bit(field) Function TRSn Transmit Request Set Bit ’0’: No change of the respective transmit request bit. ’1’: The respective transmit request bit is cleared. n = 0...15 The Transmit Request Reset Registers provide a transmit request reset bit (TRRn) for each transmit request bit TRSn, i.e. for each message object. Writing ’1’ to a TRRn bit clears the corresponding transmission request bit TRSn. This causes a transmission request, initiated by the corresponding bit TRSn, to be cancelled, provided that it is not currently processed. This scheme avoids conflicts when writing to register bits while they are cleared by hardware because of a completed transmission. Note: Registers TRRRx cannot be read. Semiconductor Group 26 SAE 81C90/91 07Feb95@09:05h Intermediate Version TRRR2 7 6 5 4 3 2 1 0 TRR15 TRR14 TRR13 TRR12 TRR11 TRR10 TRR9 TRR8 Reset Value: 00H w w w w w w w w TRRR1 7 6 5 4 3 2 1 0 TRR7 TRR6 TRR5 TRR4 TRR3 TRR2 TRR1 TRR0 w w w w w w w w Address: 19H Address: 18H Reset Value: 00H Bit(field) Function TRRx Transmit Request Reset Bit ’0’: No change of the respective transmit request bit. ’1’: The respective transmit request bit is cleared. Remote-Request-Pending Registers RRPR2 7 6 5 4 3 2 1 0 RRP15 RRP14 RRP13 RRP12 RRP11 RRP10 RRP9 RRP8 Reset Value: 00H r r r r r r r r RRPR1 7 6 5 4 3 2 1 0 RRP7 RRP6 RRP5 RRP4 RRP3 RRP2 RRP1 RRP0 r r r r r r r r Address: 1BH Address: 1AH Reset Value: 00H Bit(field) Function RRPn Remote Request Pending Bit ’0’: No remote request pending. ’1’: A remote request (remote frame) for message n was received but is not yet answered by the transmission of the corresponding data frame. n = 0...15 Semiconductor Group 27 SAE 81C90/91 07Feb95@09:05h Intermediate Version Message Time Stamp This mechanism stores the time at which a specific message was received, i.e. it assigns a time stamp to that message. For this purpose the contents of the free-running time stamp counter TSC is copied to the time stamp register TSRn of the respective message object upon reception of this message. The Time Stamp Counter Registers provide access to the free-running time stamp counter. TSCH 7 6 5 4 3 2 TSC.15 TSC.14 TSC.13 TSC.12 TSC.11 TSC.10 Address: 1CH 1 0 TSC.9 TSC.8 Reset Value: 00H rw rw rw rw rw rw rw rw TSCL 7 6 5 4 3 2 1 0 TSC.7 TSC.6 TSC.5 TSC.4 TSC.3 TSC.2 TSC.1 TSC.0 rw rw rw rw rw rw rw rw Address: 1DH Reset Value: 00H Bit(field) Function TSC Time Stamp Counter Current contents of the free running time stamp counter. The Time-Stamp Registers are available for each of message objects 0...7 (see table below) and contain the time-stamp of the corresponding message. These registers can only be read. TSRnH 7 6 5 4 3 2 1 0 TSn.15 TSn.14 TSn.13 TSn.12 TSn.11 TSn.10 TSn.9 TSn.8 Reset Value: UUH r r r r r r r r TSRnL 7 6 5 4 3 2 1 0 TSn.7 TSn.6 TSn.5 TSn.4 TSn.3 TSn.2 TSn.1 TSn.0 r r r r r r r r Address: 3XH Address: 3XH Reset Value: UUH Bit(field) Function TSn Time Stamp n A 16-bit timer value to identify the time of reception of message n. n = 0...7 Semiconductor Group 28 SAE 81C90/91 07Feb95@09:05h Intermediate Version Time Stamp Register Table Address Function 30H High Byte 31H Low Byte 32H High Byte 33H Low Byte : : 3CH High Byte 3DH Low Byte 3EH High Byte 3FH Low Byte Time-Stamp 0 Time-Stamp 1 : Time-Stamp 6 Time-Stamp 7 Transmit Check Error Counter TCEC 7 6 5 4 3 Address: 15H - - - - - Reset Value: 00H - - - - - 2 1 0 TCECV rw rw Bit(field) Function TCECV Transmit Check Error Counter Value Number of errors detected by the transmit check unit. When a count of 4 is reached an interrupt is generated if enabled. If bit TCE (CTRL.1) is set to ’1’ the Bus Off status is entered in this case. rw Note: Not defined bit positions must be ’0’ for write accesses. Transmit Check Data Register This register supports an error analysis when a transmit check error is encountered. Reading TCD provides the byte which was actually being sent when the error occurred. TCD 7 6 5 4 Address: 16H 3 2 1 0 r r r Data Byte Reset Value: XXH r r r r r Bit(field) Function Data Byte The data byte which was attempted to be sent while a transmit check error was encountered. Semiconductor Group 29 SAE 81C90/91 07Feb95@09:05h Intermediate Version Port Control Registers These registers control the parallel ports P0 and P1 which are provided in the SAE 81C90. The Port Direction Registers PxPDR select each port pin separately for input (PxPDR.n=’0’) or output (PxPDR.n=’1’). After reset the ports are switched as inputs. P1PDR Address: 2CH 7 6 5 4 3 2 1 0 P1PD.7 P1PD.6 P1PD.5 P1PD.4 P1PD.3 P1PD.2 P1PD.1 P1PD.0 Reset Value: 00H rw rw rw rw rw rw rw rw P0PDR 7 6 5 4 3 2 1 0 Address: 28H P0PD.7 P0PD.6 P0PD.5 P0PD.4 P0PD.3 P0PD.2 P0PD.1 P0PD.0 Reset Value: 00H rw rw rw rw rw rw rw rw The Port Latch Registers PxLR store the output data for those port pins that are switched to output. P1LR 7 6 5 4 3 2 1 0 P1L.7 P1L.6 P1L.5 P1L.4 P1L.3 P1L.2 P1L.1 P1L.0 Reset Value: 00H rw rw rw rw rw rw rw rw P0LR 7 6 5 4 3 2 1 0 P0L.7 P0L.6 P0L.5 P0L.4 P0L.3 P0L.2 P0L.1 P0L.0 rw rw rw rw rw rw rw rw Address: 2EH Address: 2AH Reset Value: 00H The Port Pin Registers PxPR provide the current level of the port pins. These registers can only be read. P1PR 7 6 5 4 3 2 1 0 P1P.7 P1P.6 P1P.5 P1P.4 P1P.3 P1P.2 P1P.1 P1P.0 Reset Value: 00H r r r r r r r r P0PR 7 6 5 4 3 2 1 0 P0P.7 P0P.6 P0P.5 P0P.4 P0P.3 P0P.2 P0P.1 P0P.0 r r r r r r r r Address: 2DH Address: 29H Reset Value: 00H In parallel to the standard CMOS structure there are additional internal pullup devices of about 10...200 kΩ at each port pin. Note: Registers PxPDR and PxPL may be used for general purpose storage if the ports are not used. Semiconductor Group 30 07Feb95@09:05h Intermediate Version SAE 81C90/91 Bit Timing A regular bit period is composed of the following three segments: ● synchronization segment ● timing segment 1 ● timing segment 2. The sampling point is between timing segment 1 and timing segment 2. Figure 6 Bit Time Segments Synchronization The edge of the input signal is expected during the sync segment (duration = 1 system clock cycle = 1 tSCL). Timing Segment 1 (TSeg1) Timing segment 1 determines the sampling point within a bit period. This point is always at the end of segment 1. The segment is programmable from 1 to 16 tSCL (see bit-length register BL1). Timing Segment 2 (TSeg2) Timing segment 2 provides extra time for internal processing after the sampling point. The segment is programmable from 1 to 8 tSCL (see bit-length register BL1). Synchronization Jump Width (SJW) To compensate for phase shifts between the oscillator frequencies of the different bus stations, each CAN controller must be able to synchronize to the relevant signal edge of the incoming signal. The synchronization jump width (SJW) determines the maximum number of system clock pulses by which the bit period can be lengthened or shortened for resynchronization. The synchronization jump width is programmable from 1 to 4 tSCL (see bit-length register BL2). Semiconductor Group 31 07Feb95@09:05h Intermediate Version SAE 81C90/91 Figure 7 Lengthening a Bit Period Figure 8 Shortening a Bit Period Delay Times The total delay is calculated from the following single delays: ● ● ● ● 2 × physical bus tBus (max. 100 ns acc. to CAN specification) 2 × input comparator tComp (depends on application circuit) 2 × output driver tDriver (depends on application circuit) 1 × input to output of CAN controller tInOut (max. 1 tSCL + 80 ns) tDelay = 2 × (tBus + tComp + tDriver) + tInOut Recommendations On the premise of the stated conditions, there are the following essential requirements to be maintained: tTSeg1 tTSeg1 tTSeg2 tTSeg2 ≥ ≥ > ≥ tSeg2 tDelay tSJW 3 × tSCL + tSJW Semiconductor Group if bit SAM = 1 (otherwise bit recognition does not work). 32 07Feb95@09:05h Intermediate Version SAE 81C90/91 Host Interfaces There are two different host interfaces implemented in the SAE 81C90/91. Data and addresses on a multiplexed 8-bit bus, compatible with Siemens microcontrollers (C5xx, C16x), can be transferred via the parallel interface (PI). Using the serial synchronous interface (Sl), any host controller with a serial three-lead interface can be connected with. The interface is selected by hardware through the wiring of the MS (Mode Select) pin. This pin may not be switched during operation. If there is a High level on the MS pin, the SI and thus pins DI, DO, CLK, W and TIM are activated, while pins AD5 through AD7, RD, WR and ALE are inactive. A Low level on the MS pin switches to the Pl and thus activates pins AD0 through AD7, RD, WR and ALE. Parallel Interface Pl The parallel interface uses a multiplexed 8-bit address/data bus. First the address of the required register is applied to the pins AD0 through AD7. A falling edge on pin ALE means that this address is transferred to an on-chip latch. After this, data can either be written into the selected register (pin WR = 0) or read from it (pin RD = 0) via the address/data bus. Pin CS must be 0 for the entire duration of the RD/WR active time so that the circuit is activated. Serial Synchronous Interface Sl If the SI is used the unused pins of PI must be set to inactive levels (RD, WR to VDD and ALE, AD5, AD6, AD7 to VSS). Communication on the SI is accomplished according to the following procedure: Each access to the stand-alone Full-CAN circuit has to be started by activating the device (CS = 0). After the beginning of access, an address must be written first and then data can be read or written. The required function is determined by pin W (W = 1: read; W = 0: write). If the automatic decrementing of the address is activated (bit ADE in the MOD register), any number of data bytes can be accessed in succession. Finally the device has to be deactivated. Procedure: ● ● ● ● ● Activate device (CS = 0) Set pin W to 1 for read, to 0 for write Write in address of first data byte Read out/write in one or more data bytes Deactivate device (CS = 1) The most-significant bit is always output as the first bit of an address or a data byte. Data from pin DI are transferred into the internal shift register with the rising edge of the clock. The active clock edge of pin DO is selectable via the pin TIM. If this pin is 0 the data are output from the shift register to pin DO with the rising clock edge (Timing A). If the pin TIM is 1, the output of data is done with the falling edge (Timing B). The timing for reading and writing of two data bytes with automatic decrementing activated is illustrated below. Semiconductor Group 33 07Feb95@09:05h Intermediate Version Figure 9 Serial Interface Timing (for 2 Data Bytes) Semiconductor Group 34 SAE 81C90/91 07Feb95@09:05h Intermediate Version SAE 81C90/91 Absolute Maximum Ratings Ambient temperature under bias (TA): ..................................................................... – 40 to + 110 ˚C Storage temperature (TST)........................................................................................ – 50 to + 150 ˚C Voltage on VCC pins with respect to ground (VSS) ..................................................... – 0.5 to + 6.0 V Voltage on any pin with respect to ground (VSS) .................................................– 0.5 to VCC + 0.5 V Input current on any pin during overload condition .................................................. – 10 to + 10 mA Absolute sum of all input currents during overload condition ............................................. |100 mA| Power dissipation..................................................................................................................... 0.5 W Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. During overload conditions (VIN > VCC or VIN < VSS) the voltage on pins with respect to ground (VSS) must not exceed the values defined by the Absolute Maximum Ratings. Parameter Interpretation The parameters listed in the following partly represent the characteristics of the SAE 81C90/91 and partly its demands on the system. To aid in interpreting the parameters right, when evaluating them for a design, they are marked in column “Symbol”: DC (Device Characteristics): The logic of the SAE 81C90/91 will provide signals with the respective timing characteristics. SR (System Requirement): The external system must provide signals with the respective timing characteristics to the SAE 81C90/91. Semiconductor Group 35 SAE 81C90/91 07Feb95@09:05h Intermediate Version DC Characteristics VCC = 5 V ± 10 %; VSS = 0 V TA = – 40 to + 110 ˚C Parameter Symbol Limit Values min. Unit Test Condition 0.3 VCC V – max. Input low voltage (all except XTAL1 and XTAL2) VIL Input low voltage (XTAL1 and XTAL2) VILX SR 0 0.5 V – Input high voltage (all except XTAL1 and XTAL2) VIH VCC V – Input high voltage (XTAL1 and XTAL2) VIHX SR VCC – 1.0 VCC V – VCI SR 0.5 VCC + 0.5 V – VICOM SR 1.5 VCC – 1.5 V – Hysteresis 2) VHYS DC – 100 3) mV – Offset voltage 2) VOFF DC – 100 3) mV – Output low voltage (all except CLKOUT, TX0, TX1) VOL DC – 0.2 VCC V IOL = 1.6 mA Output low voltage (CLKOUT) VOLC DC – 0.4 V IOL1 = 10 mA Output high voltage (all except CLKOUT, TX0, TX1) VOH DC 0.8 VCC VCC V IOH = – 1.6 mA Output high voltage (CLKOUT) VOHC DC VCC – 0.8 VCC V IOH = – 10 mA Input leakage current II ±1 µA 0 V < VIN < VCC 4) Source output current (TX0, TX1) ISRC DC 5 – mA VO = VCC – 1 V Sink output current (TX0, TX1) ISNK DC 5 – mA VO = 1 V CL DC 6.8 12 pF CI DC – 10 pF – 30 mA Comparator input voltage 1) Common mode voltage Low end capacitance 5) Pin capacitance 2) Power supply current 2) ICC SR 0 SR 0.7 VCC DC – f = 1 MHz TA = 25 ˚C Notes 1) 2) 3) 4) 5) If the bus lines work according to the ISO specification, additional circuitry is necessary for interconnection of the input comparator to the bus lines. Not 100% tested, guaranteed by design characterization. This value is a typical value! This specification does not apply to the port pins (P00...P07, P10...P17) due to the implemented pullups! In oscillator mode the size of the low-end capacitance must correspond to the specification of the crystal manufacturer. The optimum values depend on the selected crystal, the intended frequency and the actual application hardware (stray capacitances). 10 pF are recommended for CL. For best results keep the crystal circuitry connections as short as possible and keep the CLKOUT line away from it. If the CLKOUT signal is not required by the system it should be switched off. Semiconductor Group 36 SAE 81C90/91 07Feb95@09:05h Intermediate Version AC Characteristics (General Timing) VCC = 5 V ± 10 %; VSS = 0 V TA = – 40 to + 110 ˚C Parameter Symbol Limit Values min. Unit Test Conditions max. Oscillator period tOSC SR 50 - ns Clock input high time tH SR 23.5 – ns Clock input low time tL SR 23.5 – ns Reset pulse width tRES SR 2 – tOSC Output rise time 1) tQR DC – 40 ns CL = 70 pF tQF DC – 40 ns CL = 70 pF tQRC DC – 20 ns CL = 50 pF tQFC DC – 20 ns CL = 50 pF Unit Test Conditions Output fall time 1) CLKOUT rise time 1) CLKOUT fall time 1) 1) Not 100% tested, guaranteed by design characterization. AC Characteristics (SI Timing) VCC = 5 V ± 10 %; TA = – 40 to + 110 ˚C; Parameter VSS = 0 V CL = 50 pF Symbol Limit Values min. max. Chip Select Setup tCSS SR 10 ns Clock High Time tCH SR 1.5 tOSC + 10 ns Clock Low Time tCL SR 1.5 tOSC + 10 ns Clock Period tC SR 4 tOSC ns DI Setup tDIS SR 10 ns DI Hold tDIH SR 0 ns Address to Data Out tADO DC 3 tOSC Output Delay tOD DC 25 ns Data Float after CS high tDF DC 25 ns Chip Select Hold tCSH SR 1 tOSC ns Write to Clock tWC 0 ns W to CS high tWCS SR 0 ns Address to Data In tADI ns Semiconductor Group DC 0 37 ns 07Feb95@09:05h Intermediate Version Figure 10 SI-Read-Timing (Timing A: Pin TIM = 0) Figure 11 SI-Read-Timing (Timing B: Pin TIM =1) Semiconductor Group 38 SAE 81C90/91 SAE 81C90/91 07Feb95@09:05h Intermediate Version Figure 12 SI-Write-Timing AC Characteristics (PI Timing) VCC = 5 V ± 10 %; VSS = 0 V TA = – 40 to + 110 ˚C; CL = 50 pF Parameter Symbol Limit Values min. Unit max. Read-Cycle time tCYR DC 4 tOSC ns Write-Cycle time tCYW DC 4 tOSC ns ALE pulse width tLHLL DC 30 ns Address setup to ALE low tAVLL SR 10 ns Address hold after ALE low tLLAX SR 10 ns RD pulse width tRLRH SR 2 tOSC + 30 ns WR pulse width tWLWH SR 2 tOSC + 30 ns ALE low to WR active tLLWL SR 20 ns ALE low to RD active tLLRL SR 20 ns Data float after RD high tRFDX DC 0 20 ns RD low to data valid tRLDV DC 2 tOSC + 20 ns Data setup before WR high tDVWH SR 10 ns Data hold after WR high tWHDX SR 5 ns CS low to RD low tCLRL / SR 0 ns CS low to WR low tCLWL SR 0 ns WR high to next ALE low tWHLL SR 1.5 tOSC ns Semiconductor Group 39 Test Condition 07Feb95@09:05h Intermediate Version Figure 13 PI Timing: Read-Cycle-Timing Figure 14 PI Timing: Write-Cycle-Timing Semiconductor Group 40 SAE 81C90/91