IRF IRLMS6702

PD - 91414C
IRLMS6702
HEXFET® Power MOSFET
l
l
l
l
Generation V Technology
Micro6 Package Style
Ultra Low RDS(on)
P-Channel MOSFET
D
D
G
Description
Fifth Generation HEXFET® power MOSFETs from
International Rectifier utilize advanced processing
techniques to achieve extremely low on-resistance
per silicon area. This benefit, combined with the fast
switching speed and ruggedized device design that
HEXFET® power MOSFETs are well known for,
provides the designer with an extremely efficient and
reliable device for use in a wide variety of applications.
1
6
2
5
3
4
A
D
VDSS = -20V
D
RDS(on) = 0.20Ω
S
Top View
The Micro6 package with its customized leadframe
produces a HEXFET® power MOSFET with RDS(on)
60% less than a similar size SOT-23. This package is
ideal for applications where printed circuit board space
is at a premium. It's unique thermal design and RDS(on)
reduction enables a current-handling increase of
nearly 300% compared to the SOT-23.
Micro6
Absolute Maximum Ratings
Parameter
ID @ TA = 25°C
ID @ TA = 70°C
IDM
PD @TA = 25°C
V GS
dv/dt
TJ, TSTG
Max.
Continuous Drain Current, VGS @ -4.5V
Continuous Drain Current, VGS @ -4.5V
Pulsed Drain Current 
Power Dissipation
Linear Derating Factor
Gate-to-Source Voltage
Peak Diode Recovery dv/dt ‚
Junction and Storage Temperature Range
Units
-2.4
-1.9
-13
1.7
13
± 12
5.0
-55 to + 150
A
W
mW/°C
V
V/ns
°C
Thermal Resistance Ratings
Parameter
RθJA
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Maximum Junction-to-Ambient „
Min.
Typ.
–––
–––
Max
Units
75
°C/W
1
3/18/04
IRLMS6702
Electrical Characteristics @ TJ = 25°C (unless otherwise specified)
Parameter
Drain-to-Source Breakdown Voltage
∆V(BR)DSS/∆TJ Breakdown Voltage Temp. Coefficient
V (BR)DSS
RDS(on)
Static Drain-to-Source On-Resistance
VGS(th)
gfs
Gate Threshold Voltage
Forward Transconductance
IDSS
Drain-to-Source Leakage Current
I GSS
Qg
Qgs
Qgd
td(on)
tr
td(off)
tf
Ciss
Coss
Crss
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Total Gate Charge
Gate-to-Source Charge
Gate-to-Drain ("Miller") Charge
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Min.
-20
–––
–––
–––
-0.70
1.5
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
Typ. Max. Units
Conditions
––– –––
V
V GS = 0V, ID = -250µA
-0.005 ––– V/°C Reference to 25°C, ID = -1mA
––– 0.200
V GS = -4.5V, ID = -1.6A ƒ
Ω
––– 0.375
V GS = -2.7V, ID = -0.80A ƒ
––– –––
V
V DS = V GS, ID = -250µA
––– –––
S
V DS = -10V, I D = -0.80A
––– -1.0
V DS = -16V, V GS = 0V
µA
––– -25
V DS = -16V, V GS = 0V, TJ = 125°C
––– -100
V GS = -12V
nA
––– 100
V GS = 12V
5.8 8.8
I D = -1.6A
1.8 2.6
nC V DS = -16V
2.1 3.1
V GS = -4.5V, See Fig. 6 and 9 ƒ
13 –––
V DD = -10V
20 –––
I D = -1.6A
ns
21 –––
R G = 6.0Ω
18 –––
R D = 6.1Ω, See Fig. 10 ƒ
210 –––
V GS = 0V
130 –––
pF
V DS = -15V
73 –––
ƒ = 1.0MHz, See Fig. 5
Source-Drain Ratings and Characteristics
IS
I SM
VSD
trr
Qrr
Parameter
Continuous Source Current
(Body Diode)
Pulsed Source Current
(Body Diode) 
Diode Forward Voltage
Reverse Recovery Time
Reverse RecoveryCharge
Min. Typ. Max. Units
–––
–––
-1.7
–––
–––
-13
–––
–––
–––
–––
25
15
-1.2
37
22
A
V
ns
nC
Conditions
MOSFET symbol
showing the
G
integral reverse
p-n junction diode.
TJ = 25°C, IS = -1.6A, VGS = 0V ƒ
TJ = 25°C, I F = -1.6A
di/dt = -100A/µs ƒ
D
S
Notes:
 Repetitive rating; pulse width limited by
ƒ Pulse width ≤ 300µs; duty cycle ≤ 2%.
‚ ISD ≤ -1.6A, di/dt ≤ -100A/µs, VDD ≤ V(BR)DSS,
„ Surface mounted on FR-4 board, t ≤ 5sec.
max. junction temperature. ( See fig. 11 )
TJ ≤ 150°C
2
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IRLMS6702
100
100
VGS
- 7.5V
- 5.0V
- 4.0V
- 3.5V
- 3.0V
- 2.5V
- 2.0V
BOTTOM -1.75V
VGS
- 7.5V
- 5.0V
- 4.0V
- 3.5V
- 3.0V
- 2.5V
- 2.0V
BOTTOM -1.75V
TOP
-ID , Drain-to-Source Current (A)
-I D , Drain-to-Source Current (A)
TOP
10
1
-1.75V
20µs PULSE WIDTH
TJ = 25°C
A
0.1
0.1
1
10
1
-1.75V
20µs PULSE WIDTH
TJ = 150°C
0.1
10
0.1
1
-VDS , Drain-to-Source Voltage (V)
Fig 2. Typical Output Characteristics
2.0
R DS(on) , Drain-to-Source On Resistance
(Normalized)
-ID , Drain-to-Source Current (A)
100
10
TJ = 25°C
TJ = 150°C
1
VDS = -10V
20µs PULSE WIDTH
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
-VGS , Gate-to-Source Voltage (V)
Fig 3. Typical Transfer Characteristics
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A
-VDS , Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
0.1
10
A
I D = -1.6A
1.5
1.0
0.5
V GS = -4.5V
0.0
-60
-40
-20
0
20
40
60
80
A
100 120 140 160
TJ , Junction Temperature (°C)
Fig 4. Normalized On-Resistance
Vs. Temperature
3
IRLMS6702
400
10
-VGS , Gate-to-Source Voltage (V)
V GS = 0V,
f = 1MHz
C iss = Cgs + C gd , Cds SHORTED
C rss = C gd
C oss = C ds + C gd
C, Capacitance (pF)
300
Ciss
Coss
200
Crss
100
0
10
8
6
4
2
FOR TEST CIRCUIT
SEE FIGURE 9
0
A
1
I D = -1.6A
VDS = -16V
0
100
6
8
A
10
Fig 6. Typical Gate Charge Vs.
Gate-to-Source Voltage
Fig 5. Typical Capacitance Vs.
Drain-to-Source Voltage
100
100
OPERATION IN THIS AREA LIMITED
BY R DS(on)
-I D , Drain Current (A)
-ISD , Reverse Drain Current (A)
4
Q G , Total Gate Charge (nC)
-VDS , Drain-to-Source Voltage (V)
10
TJ = 150°C
TJ = 25°C
1
VGS = 0V
0.1
0.4
0.6
0.8
1.0
1.2
-VSD , Source-to-Drain Voltage (V)
Fig 7. Typical Source-Drain Diode
Forward Voltage
4
2
A
1.4
10
100µs
1ms
1
10ms
TA = 25°C
TJ = 150°C
Single Pulse
0.1
1
A
10
100
-VDS , Drain-to-Source Voltage (V)
Fig 8. Maximum Safe Operating Area
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IRLMS6702
RD
V DS
QG
-4.5V
QGS
VGS
D.U.T.
RG
QGD
+
VDD
-4.5V
VG
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
Charge
Fig 9a. Basic Gate Charge Waveform
Fig 10a. Switching Time Test Circuit
Current Regulator
Same Type as D.U.T.
td(on)
t d(off)
tf
VGS
50KΩ
.2µF
12V
tr
10%
.3µF
D.U.T.
+VDS
VGS
90%
-3mA
IG
VDS
ID
Current Sampling Resistors
Fig 9b. Gate Charge Test Circuit
Fig 10b. Switching Time Waveforms
100
Thermal Response (Z thJA )
D = 0.50
0.20
10
0.10
0.05
0.02
PDM
0.01
1
t1
SINGLE PULSE
(THERMAL RESPONSE)
0.1
0.00001
t2
Notes:
1. Duty factor D = t 1 / t 2
2. Peak T J = P DM x Z thJA + TA
0.0001
0.001
0.01
0.1
1
10
100
t1 , Rectangular Pulse Duration (sec)
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Ambient
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5
IRLMS6702
Peak Diode Recovery dv/dt Test Circuit
+
D.U.T
ƒ
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
+
‚
-
-
+
**

RG
• dv/dt controlled by RG
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
VGS*
*
„
+
-
*
VDD
Reverse Polarity of D.U.T for P-Channel
Driver Gate Drive
P.W.
Period
D=
P.W.
Period
[VGS=10V ] ***
D.U.T. ISD Waveform
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt
Re-Applied
Voltage
Body Diode
[VDD]
Forward Drop
Inductor Curent
Ripple ≤ 5%
[ISD ]
*** VGS = 5.0V for Logic Level and 3V Drive Devices
Fig 12. For P-channel HEXFET® power MOSFETs
6
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IRLMS6702
Package Outline
Micro6ä
3.00 (.118 )
2.80 (.111 )
1.75 (.068 )
1.50 (.060 )
6
-A-
5
1
2
0.95 ( .0375 )
LEAD ASSIGNMENTS
RECOMMENDED FOOTPRINT
-B-
4
3.00 (.118 )
2.60 (.103 )
3
2X 0.95 (.0375 )
D
D
S
6
5
4
1
2
3
D
D
G
6X (1.06 (.042 )
2.20 (.087 )
0.50 (.019 )
6X
0.35 (.014 )
2X
6X 0.65 (.025 )
0.15 (.006 ) M C A S B S
O
O
0 -10
1.30 (.051 )
0.90 (.036 )
6X
1.45 (.057 )
0.90 (.036 )
-C-
0.10 (.004 )
6 SURFACES
0.15 (.006 )
MAX.
0.20 (.007 )
0.09 (.004 )
0.60 (.023 )
0.10 (.004 )
NOTES :
1. DIMENSIONING & TOLERANCING PER ANSI Y14.5M-1982.
2. CONTROLLING DIMENSION : MILLIMETER.
3. DIMENSIONS ARE SHOWN IN MILLIMETERS (INCHES).
Part Marking Information
Micro6ä
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IRLMS6702
Tape & Reel Information
Micro6ä
8mm
FEED DIRECTION
4mm
NOTES :
1. OUTLINE CONFORMS TO EIA-481 & EIA-541.
178.00
( 7.008 )
MAX.
9.90 ( .390 )
8.40 ( .331 )
NOTES:
1. CONTROLLING DIMENSION : MILLIMETER.
2. OUTLINE CONFORMS TO EIA-481 & EIA-541.
Data and specifications subject to change without notice.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information. 03/04
8
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Datasheets for electronics components.