PD - 9.1529A
IRFI9Z24N
HEXFET® Power MOSFET
Advanced Process Technology
l Isolated Package
l High Voltage Isolation = 2.5KVRMS
l Sink to Lead Creepage Dist. = 4.8mm
l P-Channel
l Fully Avalanche Rated
Description
l
D
VDSS = -55V
RDS(on) = 0.175Ω
G
ID = -9.5A
S
Fifth Generation HEXFETs from International Rectifier
utilize advanced processing techniques to achieve
extremely low on-resistance per silicon area. This
benefit, combined with the fast switching speed and
ruggedized device design that HEXFET Power
MOSFETs are well known for, provides the designer
with an extremely efficient and reliable device for use
in a wide variety of applications.
The TO-220 Fullpak eliminates the need for additional
insulating hardware in commercial-industrial
applications. The moulding compound used provides
a high isolation capability and a low thermal resistance
between the tab and external heatsink. This isolation
is equivalent to using a 100 micron mica barrier with
standard TO-220 product. The Fullpak is mounted to
a heatsink using a single clip or by a single screw
fixing.
TO-220 FULLPAK
Absolute Maximum Ratings
ID @ TC = 25°C
ID @ TC = 100°C
IDM
PD @TC = 25°C
VGS
EAS
IAR
EAR
dv/dt
TJ
TSTG
Parameter
Max.
Continuous Drain Current, VGS @ -10V
Continuous Drain Current, VGS @ -10V
Pulsed Drain Current
Power Dissipation
Linear Derating Factor
Gate-to-Source Voltage
Single Pulse Avalanche Energy
Avalanche Current
Repetitive Avalanche Energy
Peak Diode Recovery dv/dt
Operating Junction and
Storage Temperature Range
Soldering Temperature, for 10 seconds
Mounting torque, 6-32 or M3 screw
- 9.5
- 6.7
- 48
29
0.19
± 20
96
-7.2
2.9
- 5.0
-55 to + 175
Units
A
W
W/°C
V
mJ
A
mJ
V/ns
°C
300 (1.6mm from case )
10 lbf•in (1.1N•m)
Thermal Resistance
Parameter
RθJC
RθJA
Junction-to-Case
Junction-to-Ambient
Typ.
Max.
Units
–––
–––
5.2
65
°C/W
8/25/97
IRFI9Z24N
Electrical Characteristics @ TJ = 25°C (unless otherwise specified)
RDS(on)
VGS(th)
gfs
Parameter
Drain-to-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
Static Drain-to-Source On-Resistance
Gate Threshold Voltage
Forward Transconductance
Qg
Q gs
Q gd
t d(on)
tr
t d(off)
tf
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Total Gate Charge
Gate-to-Source Charge
Gate-to-Drain ("Miller") Charge
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Min.
-55
–––
–––
-2.0
2.5
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
Typ.
–––
-0.05
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
13
55
23
37
IDSS
Drain-to-Source Leakage Current
LD
Internal Drain Inductance
–––
4.5
LS
Internal Source Inductance
–––
7.5
Ciss
Coss
Crss
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
–––
–––
–––
350
170
92
V(BR)DSS
∆V(BR)DSS/∆TJ
I GSS
Max. Units
Conditions
–––
V
VGS = 0V, I D = - 250µA
––– V/°C Reference to 25°C, I D = -1mA
0.175
Ω
VGS = -10V, ID = - 5.4A
-4.0
V
VDS = VGS , ID = - 250µA
–––
S
V DS = - 25V, I D = -7.2A
-25
VDS = - 55V, VGS = 0V
µA
-250
VDS = - 44V, VGS = 0V, T J = 150°C
100
V GS = 20V
nA
-100
VGS = - 20V
19
ID = -7.2A
5.1
nC VDS = - 44V
10
V GS = -10V, See Fig. 6 and 13
–––
VDD = -28V
–––
I D = - 7.2A
ns
–––
RG = 24Ω
–––
RD = 3.7Ω, See Fig. 10
D
Between lead,
–––
6mm (0.25in.)
nH
G
from package
–––
and center of die contact
S
–––
VGS = 0V
–––
pF
VDS = - 25V
–––
ƒ = 1.0MHz, See Fig. 5
Source-Drain Ratings and Characteristics
IS
ISM
V SD
t rr
Q rr
t on
Parameter
Continuous Source Current
(Body Diode)
Pulsed Source Current
(Body Diode)
Diode Forward Voltage
Reverse Recovery Time
Reverse RecoveryCharge
Forward Turn-On Time
Min. Typ. Max. Units
Conditions
D
MOSFET symbol
––– ––– -9.5
showing the
A
G
integral reverse
––– ––– -48
p-n junction diode.
S
––– ––– -1.3
V
TJ = 25°C, IS = - 5.4A, VGS = 0V
––– 47
71
ns
TJ = 25°C, IF = - 7.2A
––– 84 130
µC di/dt = -100A/µs
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Notes:
Repetitive rating; pulse width limited by
Pulse width ≤ 300µs; duty cycle ≤ 2%.
max. junction temperature. ( See fig. 11 )
Starting TJ = 25°C, L = 3.7mH
RG = 25Ω, IAS = -7.2A. (See Figure 12)
ISD ≤ -7.2A, di/dt ≤ -280A/µs, VDD ≤ V(BR)DSS,
TJ ≤ 175°C
t=60s, ƒ=60Hz
Uses IRF9Z24N data and test conditions
IRFI9Z24N
100
VGS
- 15V
- 10V
- 8.0V
- 7.0V
- 6.0V
- 5.5V
- 5.0V
BOTT OM - 4. 5V
10
1
10
-4.5 V
-4.5 V
A
1
0.1
VGS
- 15V
- 10V
- 8.0V
- 7.0V
- 6.0V
- 5.5V
- 5.0V
BOTT OM - 4. 5V
TOP
-ID , D ra in -to -S o u rc e C u rre n t (A )
-ID , D ra in -to -S o u rce C u rre n t (A )
100
2 0µ s PU LS E W ID TH
TcTJ==225°C
5°C
TOP
10
1
100
0.1
-VD S , Drain-to-Source Voltage (V)
2.0
R D S (o n ) , D ra in -to -S o u rc e O n R e si sta n ce
(N o rm a li ze d )
- I D , D ra in-t o-S o urc e C urre nt (A )
TJ = 2 5 °C
TJ = 1 7 5 °C
V DS = -2 5 V
2 0 µ s P U L S E W ID T H
4
5
6
7
8
9
-VG S , Ga te-to-S o urce V oltage (V )
Fig 3. Typical Transfer Characteristics
10
A
100
Fig 2. Typical Output Characteristics
100
1
1
-VD S , Drain-to-Source V oltage (V )
Fig 1. Typical Output Characteristics
10
20 µ s PU LSE W ID TH
TTCJ = 175°C
1 75°C
10
A
I D = -12 A
1.5
1.0
0.5
VG S = -10 V
0.0
-60 -40 -20
0
20
40
60
80
A
100 120 140 160 180
T J , Junction T emperature (°C)
Fig 4. Normalized On-Resistance
Vs. Temperature
IRFI9Z24N
20
V GS
C is s
C rs s
C os s
C , C a p a c ita n c e (p F )
600
500
C is s
400
C os s
=
=
=
=
0V ,
f = 1MH z
C gs + C g d , Cds SH OR TED
Cgd
C ds + C gd
-V G S , G a te -to -S o u rc e V o lta g e (V )
700
300
C rs s
200
100
0
10
V DS = -4 4V
V DS = -2 8V
16
12
8
4
FO R TEST C IR C U IT
SEE F IGU R E 1 3
0
A
1
I D = -7.2 A
0
100
V D S , Drain-to-Source V oltage (V)
10
15
20
A
25
Q G , Total Gate Charge (nC)
Fig 6. Typical Gate Charge Vs.
Gate-to-Source Voltage
Fig 5. Typical Capacitance Vs.
Drain-to-Source Voltage
100
100
O PER ATIO N IN TH IS AR EA LIM ITED
BY R D S(o n)
1 0µs
-I D , D ra in C u rre n t (A )
-IS D , R e ve rse D ra in C u rre n t (A )
5
TJ = 1 50°C
10
TJ = 25 °C
1
10
100µ s
1m s
VG S = 0 V
0.1
0.4
0.6
0.8
1.0
1.2
1.4
1.6
A
1.8
TTCJ = 25°C
2 5°C
T J = 1 75°C
Sin gle Pu lse
1
1
10m s
10
-VS D , S ource-to-Drain V oltage (V )
-VD S , Drain-to-Source V oltage (V )
Fig 7. Typical Source-Drain Diode
Forward Voltage
Fig 8. Maximum Safe Operating Area
100
A
IRFI9Z24N
10
RD
VDS
VGS
-I D , Drain Current (A)
8
D.U.T.
RG
+
VDD
6
-10V
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
4
Fig 10a. Switching Time Test Circuit
2
td(on)
tr
t d(off)
tf
VGS
10%
0
25
50
75
100
125
TC , Case Temperature
150
175
( ° C)
90%
Fig 9. Maximum Drain Current Vs.
Case Temperature
VDS
Fig 10b. Switching Time Waveforms
(Z thJC)
10
D = 0.50
1
0.20
Thermal Response
0.10
0.05
0.02
0.01
0.1
SINGLE PULSE
(THERMAL RESPONSE)
PDM
t1
t2
0.01
0.00001
Notes:
1. Duty factor D = t1 / t 2
2. Peak T J = P DM x Z thJC + TC
0.0001
0.001
0.01
0.1
t1, Rectangular Pulse Duration (sec)
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
1
IRFI9Z24N
D .U .T
RG
IA S
- 20V
tp
VD D
A
D R IV E R
0 .0 1 Ω
15V
Fig 12a. Unclamped Inductive Test Circuit
E A S , S in g le P u ls e A va la n c h e E n e rg y (m J)
250
L
VDS
TO P
B OTTO M
200
150
100
50
0
A
25
I AS
ID
-2.9A
-5.1 A
-7.2 A
50
75
100
125
150
Starting T J , Junction Temperature (°C)
Fig 12c. Maximum Avalanche Energy
Vs. Drain Current
tp
V(BR)DSS
Fig 12b. Unclamped Inductive Waveforms
Current Regulator
Same Type as D.U.T.
50KΩ
QG
12V
.3µF
-10V
QGS
.2µF
QGD
D.U.T.
+VDS
VGS
VG
-3mA
Charge
Fig 13a. Basic Gate Charge Waveform
IG
ID
Current Sampling Resistors
Fig 13b. Gate Charge Test Circuit
175
IRFI9Z24N
Peak Diode Recovery dv/dt Test Circuit
+
D.U.T*
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
+
-
-
+
• dv/dt controlled by RG
• I SD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
RG
VGS
*
+
-
VDD
Reverse Polarity of D.U.T for P-Channel
Driver Gate Drive
P.W.
Period
D=
P.W.
Period
[
] ***
VGS=10V
D.U.T. ISD Waveform
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt
Re-Applied
Voltage
Body Diode
[
]
VDD
Forward Drop
Inductor Curent
[
Ripple ≤ 5%
*** VGS = 5.0V for Logic Level and 3V Drive Devices
Fig 14. For P-Channel HEXFETS
]
ISD
IRFI9Z24N
Package Outline
TO-220 Fullpak Outline
Dimensions are shown in millimeters (inches)
10.60 (.41 7)
10.40 (.40 9)
ø
3.40 (.133 )
3.10 (.123 )
4.8 0 (.189)
4.6 0 (.181)
-A 3.70 (.145)
3.20 (.126)
16 .0 0 (.630)
15 .8 0 (.622)
2 .80 (.110)
2 .60 (.102)
LE AD A S SIGN M E N T S
1 - GA TE
2 - D R AIN
3 - SO U R C E
7 .10 (.280)
6 .70 (.263)
1.15 (.04 5)
M IN .
N O T ES :
1 D IM EN SION IN G & T O LER A N C IN G
PE R AN S I Y14.5 M , 1982
1
2
3
2 C O N TR OLLIN G D IM EN S ION : IN C H .
3.30 (.130 )
3.10 (.122 )
-B-
13 .7 0 (.540)
13 .5 0 (.530)
C
A
1.40 (.05 5)
3X
1.05 (.04 2)
0.9 0 (.035)
3X 0.7 0 (.028)
0.25 (.010 )
3X
M
A M
0.48 (.019)
0.44 (.017)
2.85 (.112 )
2.65 (.104 )
B
2 .54 (.100)
2X
D
B
M IN IM U M C R E EP AG E
D IST A NC E B ET W E EN
A-B -C -D = 4.80 (.189 )
Part Marking Information
TO-220 Fullpak
E X AM
PLE PLE
: T HI
IS AISN AIRF
1010
E XAM
: S
T HIS
N IRF
I840G
W ITW
H ITH
A S SAS
E MB
SE LY
MBLY
CODE
E401
LO TLOT
CO DE
9B 1M
A
IN TE R NA T ION A L
INT ER NAT IONA L
R EC T IF IER
IRIRF
F 1010
RE CTIF IER
I840G
LO GO
9246
LOGO
A SAS
S EM
B LY
SE MBLY
LOLOT
T CO
DE E
COD
9BE 401 1M
9 24 5
P A RT NU M BE R
A
PA RT NU MBE R
D A TE C OD E
(YDYW
ATEW )CODE
W )A R
Y(YYW
Y = YE
AR
WYY
W == YE
WE
EK
W W = W E EK
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IR SOUTHEAST ASIA: 315 Outram Road, #10-02 Tan Boon Liat Building, Singapore 0316 Tel: 65 221 8371
http://www.irf.com/
Data and specifications subject to change without notice.
8/97