SN54ALVTH32244, SN74ALVTH32244 2.5-V/3.3-V 32-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS SCES279 – SEPTEMBER 1999 D D D D D D D State-of-the-Art Advanced BiCMOS Technology (ABT) Widebus Design for 2.5-V and 3.3-V Operation and Low Static Power Dissipation Support Mixed-Mode Signal Operation (5-V Input and Output Voltages With 2.3-V to 3.6-V VCC ) Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C High Drive (–24/24 mA at 2.5-V VCC and –32/64 mA at 3.3-V VCC) Ioff and Power-Up 3-State Support Hot Insertion Use Bus Hold on Data Inputs in Place of External Pullup/Pulldown Resistors to Prevent the Bus From Floating Auto3-State Eliminates Bus Current Loading When Output Exceeds VCC + 0.5 V Flow-Through Architecture Facilitates Printed Circuit Board Layout Distributed VCC and GND Pin Configuration Minimizes High-Speed Switching Noise ESD Protection Exceeds JESD-22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II Packaged in Plastic Fine-Pitch Ball Grid Array Package D D D D D NOTE: For tape and reel order entry: The GKER package is abbreviated to KR. description The ’ALVTH32244 devices are 32-bit buffers/line drivers designed for 2.5-V or 3.3-V VCC operation, but with the capability to provide a TTL interface to a 5-V system environment. These devices can be used as eight 4-bit buffers, four 8-bit buffers, two 16-bit buffers, or one 32-bit buffer. These devices provide true outputs and symmetrical active-low output-enable (OE) inputs. When VCC is between 0 and 1.2-V, the devices are in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.2-V, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. These devices are fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. The SN54ALVTH32244 is characterized for operation over the full military temperature range of –55°C to 125°C. The SN74ALVTH32244 is characterized for operation from –40°C to 85°C. FUNCTION TABLE (each 4-bit buffer) INPUTS OE A OUTPUT Y L H H L L L H X Z Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus is a trademark of Texas Instruments Incorporated. Copyright 1999, Texas Instruments Incorporated UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN54ALVTH32244, SN74ALVTH32244 2.5-V/3.3-V 32-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS SCES279 – SEPTEMBER 1999 GKE PACKAGE (TOP VIEW) 1 2 3 4 5 6 terminal assignments A 1 2 3 4 5 6 B A 1Y2 1Y1 1OE 2OE 1A1 1A2 C B 1Y4 1Y3 GND GND 1A3 1A4 D C 2Y2 2Y1 2A2 2Y4 2Y3 1VCC GND 2A1 D 1VCC GND 2A3 2A4 E 3Y2 3Y1 GND GND 3A1 3A2 E F G H J F 3Y4 3Y3 4Y1 1VCC GND 3A4 4Y2 1VCC GND 3A3 G 4A1 4A2 H 4Y3 4Y4 4OE 3OE 4A4 4A3 J 5Y2 5Y1 5OE 6OE 5A1 5A2 K 5Y4 5Y3 GND GND 5A3 5A4 L L 6Y2 6Y1 6Y4 6Y3 2VCC GND 6A2 M 2VCC GND 6A1 M 6A3 6A4 N N 7Y2 7Y1 GND GND 7A1 7A2 K P P 7Y4 7Y3 8Y2 8Y1 2VCC GND 7A4 R 2VCC GND 7A3 R 8A1 8A2 T T 8Y3 8Y4 8OE 7OE 8A4 8A3 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN54ALVTH32244, SN74ALVTH32244 2.5-V/3.3-V 32-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS SCES279 – SEPTEMBER 1999 logic diagram (positive logic) 1OE 1A1 1A2 1A3 1A4 2OE 2A1 2A2 2A3 2A4 A3 3OE A5 A2 A6 A1 B5 B2 B6 B1 1Y1 3A1 1Y2 3A2 1Y3 3A3 1Y4 3A4 A4 4OE C5 C2 C6 C1 D5 D2 D6 D1 2Y1 4A1 2Y2 4A2 2Y3 4A3 2Y4 4A4 H4 E5 E2 E6 E1 F5 F2 F6 F1 3Y1 3Y2 3Y3 3Y4 H3 G5 G2 G6 G1 H6 H1 H5 H2 4Y1 4Y2 4Y3 4Y4 NOTE A: 1VCC is associated with these channels. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN54ALVTH32244, SN74ALVTH32244 2.5-V/3.3-V 32-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS SCES279 – SEPTEMBER 1999 logic diagram (positive logic) 5OE 5A1 5A2 5A3 5A4 6OE 6A1 6A2 6A3 6A4 J3 7OE J5 J2 J6 J1 K5 K2 K6 K1 5Y1 7A1 5Y2 7A2 5Y3 7A3 5Y4 7A4 J4 8OE L5 L2 L6 L1 M5 M2 M6 M1 6Y1 8A1 6Y2 8A2 6Y3 8A3 6Y4 8A4 T4 N5 N2 N6 N1 P5 P2 P6 P1 7Y1 7Y2 7Y3 7Y4 T3 R5 R2 R6 R1 T6 T1 T5 T2 8Y1 8Y2 8Y3 8Y4 NOTE A: 2VCC is associated with these channels. absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Voltage range applied to any output in the high-impedance or power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Voltage range applied to any output in the high state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Current into any output in the low state, IO: SN54ALVTH32244 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA SN74ALVTH32244 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA Current into any output in the high state, IO (see Note 2): SN54ALVTH32244 . . . . . . . . . . . . . . . . . . . . 48 mA SN74ALVTH32244 . . . . . . . . . . . . . . . . . . . . 64 mA Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA Package thermal impedance, θJA (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. This current flows only when the output is in the high state and VO > VCC. 3. The package thermal impedance is calculated in accordance with JESD 51. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN54ALVTH32244, SN74ALVTH32244 2.5-V/3.3-V 32-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS SCES279 – SEPTEMBER 1999 recommended operating conditions, VCC = 2.5 V ± 0.2 V (see Note 4) SN54ALVTH32244 SN74ALVTH32244 MIN MAX MIN MAX 2.7 2.3 2.7 VCC VIH Supply voltage 2.3 High-level input voltage 1.7 VIL VI Low-level input voltage IOH High-level output current 1.7 0.7 Input voltage 0 5.5 –6 Low-level output current V –8 mA 6 8 18 24 ∆t/∆v Input transition rise or fall rate 10 10 ∆t/∆VCC TA Power-up ramp rate 200 Operating free-air temperature –55 Outputs enabled –40 mA ns/V µs/V 200 125 V 5.5 Low-level output current; current duty cycle ≤ 50%; f ≥ 1 kHz IOL V V 0.7 0 UNIT 85 °C NOTE 4: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. recommended operating conditions, VCC = 3.3 V ± 0.3 V (see Note 4) SN54ALVTH32244 MIN MAX MIN MAX 3.6 3 3.6 VCC VIH Supply voltage 3 High-level input voltage 2 VIL VI Low-level input voltage IOH High-level output current Low-level output current Low-level output current; current duty cycle ≤ 50%; f ≥ 1 kHz IOL SN74ALVTH32244 2 0.8 Input voltage 0 ∆t/∆v Input transition rise or fall rate ∆t/∆VCC TA Power-up ramp rate 200 Operating free-air temperature –55 Outputs enabled UNIT V V 0.8 V 5.5 V –24 –32 mA 24 32 48 64 5.5 0 10 10 –40 ns/V µs/V 200 125 mA 85 °C NOTE 4: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SN54ALVTH32244, SN74ALVTH32244 2.5-V/3.3-V 32-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS SCES279 – SEPTEMBER 1999 electrical characteristics over recommended operating free-air temperature range, VCC = 2.5 V ± 0.2 V (unless otherwise noted) PARAMETER VIK VOH VCC = 2.3 V, VCC = 2.3 V to 2.7 V, II = –18 mA IOH = –100 µA 3V VCC = 2 2.3 IOH = –6 mA IOH = –8 mA VCC = 2.3 V to 2.7 V, VOL VCC = 2 2.3 3V Control inputs VCC = 2.7 V, VCC = 0 or 2.7 V, Data inputs VCC = 2 2.7 7V II Ioff IBHL‡ IBHH§ IBHLO¶ IBHHO# IEX|| SN54ALVTH32244 MIN TYP† MAX TEST CONDITIONS VCC = 0, VCC = 2.3 V, VCC = 2.3 V, VCC = 2.7 V, VCC = 2.7 V, VCC = 2.3 V, SN74ALVTH32244 MIN TYP† MAX –1.2 VCC–0.2 1.8 –1.2 UNIT V VCC–0.2 V 1.8 IOL = 100 µA IOL = 6 mA 0.2 0.2 0.4 IOL = 8 mA IOL = 18 mA 0.4 V 0.5 IOL = 24 mA VI = VCC or GND 0.5 ±1 ±1 VI = 5.5 V VI = VCC 10 10 1 1 VI = 0 VI or VO = 0 to 4.5 V –5 VI = 0 to VCC VI = 0 to VCC –5 ±100 VI = 0.7 V VI = 1.7 V µA µA 115 115 µA –10 –10 µA 300 µA 300 –300 µA –300 125 125 µA ±100 ±100 µA IOZ(PU/PD)k VO = 5.5 V VCC ≤ 1.2 V, VO = 0.5 V to VCC, VI = GND or VCC, OE = don’t care IOZH VCC = 2.7 V VO = 2.3 V, VI = 0.7 V or 1.7 V 5 5 µA IOZL VCC = 2.7 V VO = 0.5 V, VI = 0.7 V or 1.7 V –5 –5 µA VCC = 2.7 V, IO = 0, VI = VCC or GND Outputs high 0.04 0.1 0.04 0.1 ICC Outputs low 2.3 4.5 2.3 4.5 0.04 0.1 0.04 0.1 VCC = 2.5 V, VCC = 2.5 V, VI = 2.5 V or 0 VO = 2.5 V or 0 Ci Co Outputs disabled 3 3 6 6 mA pF pF † All typical values are at VCC = 2.5 V, TA = 25°C. ‡ The bus-hold circuit can sink at least the minimum low sustaining current at VIL max. IBHL should be measured after lowering VIN to GND and then raising it to VIL max. § The bus-hold circuit can source at least the minimum high sustaining current at VIH min. IBHH should be measured after raising VIN to VCC and then lowering it to VIH min. ¶ An external driver must source at least IBHLO to switch this node from low to high. # An external driver must sink at least IBHHO to switch this node from high to low. || Current into an output in the high state when VO > VCC k High-impedance state during power up or power down PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN54ALVTH32244, SN74ALVTH32244 2.5-V/3.3-V 32-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS SCES279 – SEPTEMBER 1999 electrical characteristics over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted) PARAMETER VIK VOH VCC = 3 V, VCC = 3 V to 3.6 V, II = –18 mA IOH = –100 µA VCC = 3 V IOH = –24 mA IOH = –32 mA VCC = 3 V to 3.6 V, VOL VCC = 3 V Control inputs Ioff IBHL‡ IBHH§ IBHLO¶ IBHHO# IEX|| 2 IOL = 100 µA IOL = 16 mA 0.2 IOL = 24 mA IOL = 32 mA 0.5 IOL = 48 mA IOL = 64 mA 0.55 0.2 0.4 0.5 V 0.55 ±1 ±1 10 10 20 20 1 1 VCC = 3.6 V VI = 0 VI or VO = 0 to 4.5 V –5 VCC = 3.6 V, VCC = 3 V, V V VI = 5.5 V VI = VCC VCC = 3 V, VCC = 3.6 V, –1.2 UNIT VCC–0.2 VI = VCC or GND VI = 5.5 V VCC = 0, VCC = 3 V, SN74ALVTH32244 MIN TYP† MAX –1.2 VCC–0.2 2 VCC = 3.6 V, VCC = 0 or 3.6 V, II Data inputs SN54ALVTH32244 MIN TYP† MAX TEST CONDITIONS VI = 0.8 V VI = 2 V VI = 0 to VCC VI = 0 to VCC µA –5 ±100 µA 75 75 µA –75 –75 µA 500 500 µA –500 µA –500 125 125 µA ±100 ±100 µA IOZ(PU/PD)k VO = 5.5 V VCC ≤ 1.2 V, VO = 0.5 V to VCC, VI = GND or VCC, OE = don’t care IOZH VCC = 3.6 V VO = 3 V, VI = 0.8 V or 2 V 5 5 µA IOZL VCC = 3.6 V VO = 0.5 V, VI = 0.8 V or 2 V –5 –5 µA ICC VCC = 3.6 V, IO = 0, VI = VCC or GND Outputs high 0.07 Outputs low Outputs disabled ∆ICCh VCC = 3 V to 3.6 V, One input at VCC – 0.6 V, Other inputs at VCC or GND Ci VCC = 3.3 V, VCC = 3.3 V, Co 0.1 0.07 0.1 3.2 5 3.2 5 0.07 0.1 0.07 0.1 0.4 0.4 3 3 6 6 mA mA pF pF † All typical values are at VCC = 3.3 V, TA = 25°C. ‡ The bus-hold circuit can sink at least the minimum low sustaining current at VIL max. IBHL should be measured after lowering VIN to GND and then raising it to VIL max. § The bus-hold circuit can source at least the minimum high sustaining current at VIH min. IBHH should be measured after raising VIN to VCC and then lowering it to VIH min. ¶ An external driver must source at least IBHLO to switch this node from low to high. # An external driver must sink at least IBHHO to switch this node from high to low. || Current into an output in the high state when VO > VCC k High-impedance state during power up or power down h This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND. PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 SN54ALVTH32244, SN74ALVTH32244 2.5-V/3.3-V 32-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS SCES279 – SEPTEMBER 1999 switching characteristics over recommended operating free-air temperature range, CL = 30 pF, VCC = 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) tPLH tPHL A Y tPZH tPZL OE Y OE Y tPHZ tPLZ SN54ALVTH32244 SN74ALVTH32244 MIN MAX MIN MAX 1 3.1 1 3 1 3.6 1 3.5 1.1 6 1.1 5.9 1.1 4.8 1.1 4.7 1.5 4.5 1.5 4.4 1 3.5 1 3.4 UNIT ns ns ns switching characteristics over recommended operating free-air temperature range, CL = 50 pF, VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 2) PARAMETER FROM (INPUT) TO (OUTPUT) tPLH tPHL A Y tPZH tPZL OE Y OE Y tPHZ tPLZ SN54ALVTH32244 PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74ALVTH32244 MIN MAX MIN MAX 1 2.6 1 2.4 1 2.6 1 2.5 1 3.9 1 3.8 1 3 1 2.9 1.5 4.3 1.5 4.2 1.5 3.7 1.5 3.6 UNIT ns ns ns SN54ALVTH32244, SN74ALVTH32244 2.5-V/3.3-V 32-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS SCES279 – SEPTEMBER 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.5 V ± 0.2 V 2 × VCC S1 500 Ω From Output Under Test Open GND CL = 30 pF (see Note A) 500 Ω TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 2 × VCC GND LOAD CIRCUIT tw VCC Timing Input VCC/2 VCC/2 VCC/2 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VCC/2 VCC/2 0V tPLH Output Control (low-level enabling) tPLZ VCC VCC/2 tPZH VOH VCC/2 VOL VCC/2 0V Output Waveform 1 S1 at 2 × VCC (see Note B) tPHL VCC/2 VCC VCC/2 tPZL VCC Input VOLTAGE WAVEFORMS PULSE DURATION th VCC Data Input VCC/2 0V 0V tsu Output VCC VCC/2 Input Output Waveform 2 S1 at GND (see Note B) VOL + 0.15 V VOL tPHZ VCC/2 VOH VOH – 0.15 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns. D. The outputs are measured one at a time with one transition per measurement. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 SN54ALVTH32244, SN74ALVTH32244 2.5-V/3.3-V 32-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS SCES279 – SEPTEMBER 1999 PARAMETER MEASUREMENT INFORMATION VCC = 3.3 V ± 0.3 V 6V 500 Ω From Output Under Test S1 Open GND CL = 50 pF (see Note A) 500 Ω TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 6V GND LOAD CIRCUIT tw 3V 3V Timing Input 1.5 V VOLTAGE WAVEFORMS PULSE DURATION th 3V 1.5 V 3V 1.5 V 0V tPZL 1.5 V 0V tPLH Output Output Waveform 1 S1 at 6 V (see Note B) tPLZ 3V 1.5 V tPZH tPHL VOH 1.5 V 1.5 V 0V 3V 1.5 V 1.5 V Output Control VOLTAGE WAVEFORMS SETUP AND HOLD TIMES Input 1.5 V 0V 0V tsu Data Input 1.5 V Input 1.5 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS Output Waveform 2 S1 at GND (see Note B) VOL + 0.3 V VOL tPHZ 1.5 V VOH VOH – 0.3 V ≈0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. Figure 2. Load Circuit and Voltage Waveforms 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. 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INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER’S RISK. In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI’s publication of information regarding any third party’s products or services does not constitute TI’s approval, warranty or endorsement thereof. Copyright 1999, Texas Instruments Incorporated