D a t a S h e e t , R e v. 2 . 1 , M ay 2 00 7 TLE7189F 3 - P h a s e B r i d g e D r i v er I C A u to m o t i v e P o w e r TLE7189F Table of Contents Table of Contents Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 3.1 3.2 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pin Assignment TLE7189F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4 4.1 4.2 4.3 General Product Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Functional Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Default State of Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5 5.1 5.1.1 5.1.2 5.1.3 5.1.4 5.2 5.2.1 5.2.2 5.2.3 5.2.4 5.2.5 5.2.6 5.2.7 5.2.8 5.3 5.3.1 Description and Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MOSFET Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operation at Vs<12V - Integrated Charge Pumps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Sleep Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Protection and Diagnostic Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Short Circuit Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Dead Time and Shoot Through Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Under Voltage Shut Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Over Voltage Shut Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Over Temperature Warning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VCC Check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ERR Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Shunt Signal Conditioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 6.1 Application Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Layout Guide Lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 8 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Data Sheet 2 12 12 12 13 13 14 17 17 17 17 18 18 18 18 19 22 23 Rev. 2.1, 2007-05-30 3-Phase Bridge Driver IC 1 TLE7189F Overview Features • • • • • • • • • • • • • • • • • • Compatible to very low ohmic normal level input N-channel MOSFETs PWM frequency up to 30kHz Fulfils specification down to 5.5V supply voltage Short circuit protection with adjustable detection level Three integrated current sense amplifiers 0 to 100% duty cycle Low EMC sensitivity and emission Control inputs with TTL characteristics Separate input for each MOSFET Separate source connection for each MOSFET Integrated minimum dead time Shoot through protection Disable function and sleep mode Detailed diagnosis Over temperature warning VQFN-48 package with exposed pad for excellent cooling Green Product (RoHS compliant) AEC (Automotive Electronics Council) qualified • • • • SIL3 supporting features: VCC check: Over- and under voltage check of 5V µC supply Test functions for short circuit detection and VCC check High voltage rated inputs PG-VQFN-48 Description The TLE7189F is a driver IC dedicated to control the 6 to 12 external MOSFETs forming the converter for high current 3 phase motor drives in the automotive sector. It incorporates features like short circuit detection, diagnosis and high output performance and combines it with typical automotive specific requirements like full functionality even at low battery voltages. Its 3 high side and 3 low side output stages are powerful enough to drive MOSFETs with 400nC gate charge with approx. 150ns fall and rise times. Type Package Marking TLE7189F PG-VQFN-48 TLE7189F Data Sheet 3 Rev. 2.1, 2007-05-30 TLE7189F Block Diagram 2 Block Diagram CL1 VS CH1 CB1 Charge Pump 1 Under voltage det. INH CL2 CH2 CB2 Charge Pump 2 Under voltage det. VDH Floating HS driver Short circuit detection ERR1 ERR2 ENA SCDL GH1 SH1 Diagnostic logic Under voltage Over voltage Overtemperature Short circuit Reset VCC failure Floating LS driver Short circuit detection GL1 SL1 L E V E L VCT VCC voltage check Floating HS driver Short circuit detection SH2 S H I F T E R VS_OA IL1 GH2 Floating LS driver Short circuit detection GL2 SL2 IH1 IL2 IH2 Input control Shoot through protection dead time Floating HS driver Short circuit detection GH3 SH3 IL3 IH3 Floating LS driver Short circuit detection VS_OA AGND SL3 ISP1 ISN1 ISP2 ISN2 ISP3 ISN3 3x Current sense OpAmp Bias reference buffer Data Sheet GND1 GND2 GND3 VRI Figure 1 GL3 VRO VO1 VO2 VO3 Block Diagram 4 Rev. 2.1, 2007-05-30 TLE7189F Pin Configuration 3 Pin Configuration 3.1 Pin Assignment TLE7189F SL1 GL1 VDH CB1 GND3 CL2 VS CL1 CH1 CH2 36 35 34 33 32 31 30 29 28 27 ERR2 ERR1 26 25 GND1 37 24 IH2 SH1 38 23 IL2 GH1 39 22 IH1 CB2 40 21 IL1 GL2 41 20 IH3 SL2 42 19 IL3 GH2 43 18 ENA SH2 44 17 SCDL GH3 45 16 VCT SH3 46 15 INH GND2 47 14 AGND GL3 48 13 ISP3 TLE 7189 F Topview 1 2 3 SL3 VS_OA VO1 Figure 2 Data Sheet 4 5 6 7 8 9 10 11 12 ISN1 ISP1 VRI VRO VO2 ISN2 ISP2 VO3 ISN3 Pin Configuration 5 Rev. 2.1, 2007-05-30 TLE7189F Pin Configuration 3.2 Pin Definitions and Functions Pin Symbol Function 1 SL3 Connection to source low side switch 3 2 VS_OA Voltage supply I-DC Link OpAmps and voltage reference buffer / input for VCC check 3 VO1 Output of OpAmp 1 for shunt signal amplification 4 ISN1 - Input of OpAmp 1 for shunt signal amplification 5 ISP1 + Input of OpAmp 1 for shunt signal amplification 6 VRI Input of bias reference amplifier 7 VRO Output of bias reference amplifier 8 VO2 Output of OpAmp 2 for shunt signal amplification 9 ISN2 - Input of OpAmp 2 for shunt signal amplification 10 ISP2 + Input of OpAmp 2 for shunt signal amplification 11 VO3 Output of OpAmp 3 for shunt signal amplification 12 ISN3 - Input of OpAmp 3 for shunt signal amplification 13 ISP3 + Input of OpAmp 3 for shunt signal amplification 14 AGND Analog ground especially for the current sense OpAmps 15 INH Inhibit pin (active low) 16 VCT Input pin for VCC check test 17 SCDL Input pin to adjust short circuit detection level 18 ENA Enable pin (active high) 19 IL3 Input for low side switch 3 (active high) 20 IH3 Input for high side switch 3 (active low) 21 IL1 Input for low side switch 1 (active high) 22 IH1 Input for high side switch 1 (active low) 23 IL2 Input for low side switch 2 (active high) 24 IH2 Input for high side switch 2 (active low) 25 ERR1 Error signal 1 26 ERR2 Error signal 2 27 CH2 + terminal for pump capacitor of charge pump 2 28 CH1 + terminal for pump capacitor of charge pump 1 29 CL1 - terminal for pump capacitor of charge pump 1 30 VS Voltage supply 31 CL2 - terminal for pump capacitor of charge pump 2 32 GND3 Logic and power ground 33 CB1 Buffer capacitor for charge pump 1 34 VDH Connection to drain of high side switches for short circuit detection 35 GL1 Output to gate low side switch 1 36 SL1 Connection to source low side switch 1 37 GND1 Logic and power ground 38 SH1 Connection to source high side switch 1 39 GH1 Output to gate high side switch 1 Data Sheet 6 Rev. 2.1, 2007-05-30 TLE7189F Pin Configuration Pin Symbol Function 40 CB2 Buffer capacitor for charge pump 2 41 GL2 Output to gate low side switch 2 42 SL2 Connection to source low side switch 2 43 GH2 Output to gate high side switch 2 44 SH2 Connection to source high side switch 2 45 GH3 Output to gate high side switch 3 46 SH3 Connection to source high side switch 3 47 GND2 Logic and power ground 48 GL3 Output to gate low side switch 3 Data Sheet 7 Rev. 2.1, 2007-05-30 TLE7189F General Product Characteristics 4 General Product Characteristics 4.1 Absolute Maximum Ratings Absolute Maximum Ratings 1) -40 °C ≤ Tj ≤ 150 °C; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Pos. Parameter Symbol Limit Values Unit Conditions Min. Max. -4.0 45 V with 10Ω and 1µF -0.3 45 V – -0.3 47 V tp<200ms -0.3 18 V – -0.3 6.0 V – Voltages 4.1.1 Supply voltage 4.1.2 Supply voltage 4.1.3 4.1.4 4.1.5 VS1 VS2 Supply voltage VS3 Voltage range at IHx, ILx, ENA, VCT VDP1 Voltage range at ERRx, VOx, VRI, VRO, VDP2 SCDL 4.1.6 Voltage range at ERRx, VRI, SCDL VDP3 -0.3 18 V with 10kΩ2) 4.1.7 Voltage range at VOx -0.3 18.0 V with 1kΩ2) 4.1.8 Voltage range at INH -0.3 18.0 V – 4.1.9 Voltage range at VS_OA -0.3 18.0 V – 4.1.10 Voltage range at SLx -7 7 V – -7 45 V – -7 18 V – -7 55 V – -0.3 15 V – -0.3 55 V – -7.0 55 V with 100Ω 200ms; 10x 4.1.11 Voltage range at SHx 4.1.12 Voltage range at GLx 4.1.13 Voltage range at GHx 4.1.14 Voltage difference Gxx-Sxx 4.1.15 Voltage range at VDH 4.1.16 Voltage range at VDH VVO VINH VVS_OA VSL VSH VGL VGH VGS VVDH1 VVDH2 4.1.17 Voltage range at VDH VVDH3 -9.0 55 V with 100Ω 1ms; 10x 4.1.18 Voltage range at VDH -0.3 20 V 4.1.19 Voltage range at VDH VVDH4 VVDH5 -7.0 28 V VINH=low VINH=low with 100Ω 200ms; 10x 4.1.20 Voltage range at VDH VVDH6 -9.0 28 V VINH=low with 100Ω 200ms; 10x 4.1.21 Voltage range at VDH VVDH7 -0.3 28 V VINH=low; 5min; 3x 4.1.22 Voltage range at CL1 4.1.23 Voltage range at CH1, CB1 4.1.24 Voltage difference CH1-CL1 4.1.25 Voltage range at CL2 4.1.26 Voltage range at CH2, CB2 Data Sheet VCL1 VCH1 VCP1 VCL2 VCH2 8 -0.3 25 V – -0.3 25 V – -0.3 25 V – -0.3 25 V – -0.3 55 V – Rev. 2.1, 2007-05-30 TLE7189F General Product Characteristics Absolute Maximum Ratings (cont’d)1) -40 °C ≤ Tj ≤ 150 °C; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Pos. 4.1.27 4.1.28 Parameter Symbol Unit Conditions 25 V – -2 +2 V – VISI IVOx -5 5 V – -10 10 mA – RG VCCB2a VCCB2b 2 – Ω – -20 20 V – -31 +31 V VS > 20V; VINH=low TJ Tstg Tsol -40 150 °C – -55 150 °C – – 260 °C – Tref – 260 °C – RthJC – 5 K/W – VESD VESD -2 2 kV – 750 V VCP2 DC voltage difference between VDH and VVDHVS Voltage difference CH2-CL2 Limit Values Min. Max. -0.3 VS3) 4.1.29 Voltage range at ISPx, ISNx 4.1.30 Output current range at VOx External components 4.1.31 Gate resistor 4.1.32 Min. Voltage rating of CB2 capacitor 4.1.33 Min. Voltage rating of CB2 capacitor Temperatures 4.1.34 Junction temperature 4.1.35 Storage temperature 4.1.36 Lead soldering temperature (1/16’’ from body) 4.1.37 Peak reflow soldering temperature5) Thermal Resistance 4.1.38 Junction to case ESD Susceptibility 4.1.39 4.1.40 1) 2) 3) 5) 6) 7) ESD Resistivity6) 7) ESD Resistivity (charge device model) Not subject to production test, specified by design. after 50h the chip must be replaced; resistor in series High frequent transient ringing above 1MHz exceeding the +/-2V is allowed Reflow profile IPC/JEDEC J-STD-020C ESD susceptibility HBM according to EIA/JESD 22-A 114B ESD susceptibility CDM according to EIA/JESD 22-C 101 Note: Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Note: Integrated protection functions are designed to prevent IC destruction under fault conditions described in the data sheet. Fault conditions are considered as “outside” normal operating range. Protection functions are not designed for continuous repetitive operation. 4.2 Pos. Functional Range Parameter Symbol Limit Values Min. 4.2.1 Supply voltage VS1 5.5 20 4.2.2 Supply voltage1) VS2 5.5 28 9 Conditions Max. 1) Data Sheet Unit V DC TA=25°C; t<1min Rev. 2.1, 2007-05-30 TLE7189F General Product Characteristics Pos. Parameter 2) Symbol Limit Values Unit Conditions Min. Max. D fPWM 0 100 % – 0 25 kHz Total gate charge 400nC – 30 µA – 30 µA – – 110 110 90 90 mA VS ,VVDH<20 V VVDH<20V; VS pin open fPWM=20kHz VS=170nC: VS = 5.5V VS = 14V VS= 18V VS = 20V VS=5.5V... 20V VS=20V... 28V VVS_OA=4.8 ... 5.2V VS=5.5V... 20V; VSHx=0V VS=5.5V... 20V; VS=VVDH=VSHx; VIHx=low 4.2.3 Duty cycle 4.2.4 PWM frequency 4.2.5 Quiescent current3) 4.2.6 Quiescent current into VDH IQ IQ_VDH 4.2.7 Supply current at Vs IVs 4.2.8 Supply current at Vs (device disabled by ENA) IVs(o) – 60 40 mA 4.2.9 Supply current at VS_OA – 30 mA 4.2.10 Current flowing into VDH pin (device not in sleep mode) IVs_OA IVDH1 – 1.5 mA 4.2.11 Current flowing into VDH pin (device not in sleep mode) IVDH2 150 650 µA 4.2.12 Voltage difference CB2-VDH -0.3 20 V 4.2.13 Junction temperature VCB2VDH TJ -40 150 °C Operation mode 1) For proper start up minimum Vs=6.5V is required 2) Duty cycle is referred to the high side input command (IHx); The duty cycles can be driven continuously and fully operational 3) total current consumption from power net (Vs and VDH) Note: Within the functional range the IC operates as described in the circuit description. The electrical characteristics are specified within the conditions given in the related electrical characteristics table. Note: If the voltage difference between CB2 and SHx is smaller than 2V during normal operation, there is a risk that the high side output can switch on and off without a corresponding input signal. As soon as this supply voltage recovers and the input signal changes, the output stage is automatically aligned to the input again. Data Sheet 10 Rev. 2.1, 2007-05-30 TLE7189F General Product Characteristics 4.3 Default State of Inputs Table 1 Default State of Inputs Characteristic State Remark Default state of ILx (if ILx left open -pull down) Low Low side MOSFETs off Default state of IHx (if IHx left open - pull up) High High side MOSFETs off Default state of ENA (if ENA left open - pull down) Low Device/outputs disabled Default state of VCT (if VCT left open - pull up) High Device/outputs disabled Default state of INH (if INH left open - pull down) Low Sleep mode, IQ < 30 µA Default state of SCDL (if SCDL left open - internal voltage divider) Typ. 1.4V – Default State of sense amplifier output VOx (ISPx=ISNx=0V) Zero ampere equivalent – Status of the Device and the Outputs when ENA=INH=high & VCT=low1) Device active and outputs 5.5....28V; No VCC check functional failure 1) No special start up procedure is required Note: The load condition “C=22nF; RLoad=1Ω” in the paragraph “Electrical characteristics / Dynamic characteristic” means that RLoad is connected between the output Gxx and the positive terminal of the C. The negative terminal of the C is connected to GND and the corresponding Sxx. The voltage is measured at the positive terminal of the C. Note: Within the functional range the IC operates as described in the circuit description. The electrical characteristics are specified within the conditions given in the related electrical characteristics table. Data Sheet 11 Rev. 2.1, 2007-05-30 TLE7189F Description and Electrical Characteristics 5 Description and Electrical Characteristics 5.1 MOSFET Driver 5.1.1 Output Stages The 3 low side and 3 high side powerful push-pull output stages of the TLE7189F are all floating blocks, each with its own source pin. This allows the direct connection of the output stage to the source of each single MOSFET, allowing a perfect control of each gate-source voltage even when 200A are driven in the bridge with rise and fall times clearly below 1µs. All 6 output stages have the same output power and thanks to the used charge pump principle they can be switched all up to 30kHz. Its output stages are powerful enough to drive MOSFETs with 400nC gate charge with approx. 150ns fall and rise times or even to run 12 MOSFETs with 200nC each with fall and rise times of approx. 150ns. Maximum allowed power dissipation, max. junction temperature and the capabilities of the charge pump limit the use for higher frequencies. Each output stage has its own short circuit detection block. For more details about short circuit detection see Chapter 5.2.1. VS INH CB1 CL2 CH2 CL1 CH1 Charge pump 1 100Ω VDH CB2 To Vbat CB2 Charge pump 2 SCD UVLO ERR1 +3.3V ERR2 ENA Error logic Reset Power On Reset Under voltage Over voltage Over temperature Short circuit+disable Under voltage lock out + V SCP SCD R1 GHx - Level shifter Floating HS driver 3x SCD SCD SCDL SHx CB1 SCD lock / unlock R2 short circuit filter IH1 IL1 IH2 IL2 IH3 IL3 + Input logic ON / OFF dead time GLx - shoot through protection V SCP Level shifter ON / OFF Floating LS driver 3x SLx Shuntx GND P-GND Figure 3 Data Sheet Block Diagram of Driver Stages including Short Circuit Detection 12 Rev. 2.1, 2007-05-30 TLE7189F Description and Electrical Characteristics 5.1.2 Operation at Vs<12V - Integrated Charge Pumps The TLE7189F provides a feature tailored to the requirements in 12V automotive applications. Often the operation of an application has to be assured even at 9V supply voltage or lower. Normally bridge driver ICs provide in such conditions clearly less than 9V to the gate of the external MOSFETs, increasing their RDSon and the associated power dissipation. The TLE7189F has two charge pump circuitries for external capacitors. The operation of the charge pumps is independent upon the pulse pattern of the MOSFETs. The output of the charge pumps are regulated. The first charge pump doubles the supply voltage as long as it is below 8V. At 8V supply voltage and above, charge pump 1 regulates its output to 15V typically. Above 15V supply voltage, the output voltage of charge pump 1 will increase linearly. Yet, the output will not exceed 25V. Charge pump 2 is regulated as well but it is pumped to the voltage on Vs. Normally VDH and Vs are in the same voltage range. The driver is not designed to have significant different voltages at VDH compared to Vs. This would lead to reduced supply voltages for the high side output stages. Charge pump 1 supplies the low side MOSFETS and output stages for the low side MOSFETs with sufficient voltage to assure 10V at the MOSFETs´ gate even if the supply voltage is below 10V. Charge pump 2 supplies the output stages for the high side MOSFETs with sufficient voltage to assure 10V at the MOSFETs´ gate. In addition, the charge pump 1 supplies most of the internal circuits of the driver IC, including charge pump 2. Output of charge pump 1 is the buffer capacitor CB1 which is referenced to GND. Charge pump 2 supplies the high side MOSFETs and the output stages for the high side MOSFETs with sufficient voltage to assure 10V at the high side MOSFET gate. Output of charge pump 2 is buffer capacitor CB2 which is referenced to VDH. This concept allows to drive all external MOSFETs in the complete duty cycle range of 0 to 100% without taking care about recharging of any bootstrap capacitors. This simplifies the use in all applications especially in motor drives with block wise commutation. The charge pumps are only deactivated when the device is put into sleep mode via INH. The size of the charge pump capacitors (pump capacitors CPx as well as buffer capacitors CBx) can be varied between 1µF and 4.7µF. Yet, larger capacitor values result in higher charge pump voltages and less voltage ripple on the charge pump buffer capacitors CBx (which supply the internal circuits as well as the external MOSFETs, pls. see above). Besides the capacitance values the ESR of the buffer capacitors CBx determines the voltage ripple as well. It is recommended to use buffer capacitors CBx that have small ESR. Pls. see also Chapter 5.1.3 for capacitor selection. 5.1.3 Sleep Mode When the INH pin is set to low, the driver will be set to sleep mode. The INH pin switches off the complete supply structure of the device and leads finally to an under voltage shut down of the complete driver. Enabling the device with the INH pin means to switch on the supply structure. The device will run through power on reset during wake up. It is recommended to perform a Reset by ENA after Wake up to remove possible ERR signals; Reset is performed by keeping ENA pin low until the charge pump voltages have ramped up. Enabling and disabling with the INH pin is not very fast. For fast enable / disable the ENA pin is recommended. When the TLE7189F is in INH mode (INH is low) or when the supply voltage is not available on the Vs pin, then the driver IC is not supplied, the charge pumps are inactive and the charge pump capacitors are discharged. Pin CB2 (+ terminal of buffer capacitor 2) will decay to GND. When the battery voltage is still applied to VDH (- terminal of buffer capacitor 2) the buffer capacitor 2 will slowly charged to battery voltage, yet with reversed polarity compared to the polarity during regular operation. Hence, it is important to use a buffer capacitor 2 (CB2) that can withstand both, +25 V during operation mode and -VBAT during INH mode, e.g. a ceramic capacitor. In case of load dump during INH mode, the negative voltage across CB2 will be clamped to -31 V (CB2 referenced to VDH). Data Sheet 13 Rev. 2.1, 2007-05-30 TLE7189F Description and Electrical Characteristics 5.1.4 Electrical Characteristics Electrical Characteristics MOSFET drivers - DC Characteristics VS = 5.5 to 20V, Tj = -40 to +150 °C, fPWM < 25kHz, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Pos. Parameter Symbol VG_LL VG_HL1 Limit Values Unit Conditions ILoad=30mA VS=8... 20V; ILoad=-2mA VS=5.5... 8V; ILoad=-2mA VS=5.5... 8V; ILoad=-2mA ILoad=-100mA; VS=20V VENA=low or VVCT=high; 5.5V<VS<28V ILoad=10mA UVLO; VS<=5.5V; ILoad=2mA Min. Typ. Max. – – 0.2 V 9 – 13 V 5.1.1 Low level output voltage 5.1.2 High level output voltage 5.1.3 High level output voltage, Low Side VG_HL2 7.5 – 13 V 5.1.4 High level output voltage, High Side VG_HL3 6.5 – 13 V 5.1.5 High level output voltage difference dVG_H – – 1.0 V 5.1.6 Gate drive output voltage VGS_D – – 0.2 V 5.1.7 Gate drive output voltage Tj=-40°C Tj=25°C Tj=150°C VGS1 – – 5.1.8 V 1.4 1.2 1.0 Gate drive output voltage high side VGS2 Tj=-40°C Tj=25°C Tj=150°C – – V Over voltage or VS=open or VINH=low; ILoad=2mA 1.4 1.2 1.0 5.1.9 Gate drive output voltage low side VGS3 – – 0.2 V Over voltage; ILoad=2mA 5.1.10 Low level input voltage of Ixx, ENA VI_LL – – 1.0 V – 5.1.11 High level input voltage of Ixx, ENA VI_HL 2.0 – – V – 5.1.12 Input hysteresis of IHx, ILx, ENA 50 – –- mV 5.1.13 Input hysteresis of IHx, ILx, ENA 100 200 –- mV VS=5.5... 8V VS=8... 20V – – 0.75 V – 2.1 – – V – 18 30 42 kΩ 18 30 42 kΩ 27 45 63 kΩ – 5 – µA -1.6 -1.0 -0.3 mA -1.6 -1.0 -0.3 mA VIHx<5.5V VILx<5.5V VINH; VENA<5.5V 25°C; VINH=low VS=5.5...20V; VSHx=0...(VS+1); VILx=low; VIHx=high VS=5.5...20V; VSLx=0...7V; VILx=low; VIHx=high 5.1.14 Low level input voltage of INH 5.1.15 High level input voltage of INH 5.1.16 IHx pull up resistor 5.1.17 ILx pull down resistor 5.1.18 INH, ENA pull down resistor 5.1.19 Quiescent current VDH 5.1.20 Output bias current SHx dVI1 dVI2 VI_LL VI_HL RIHx RILx RINEN IQVDH ISHx 5.1.21 Output bias current SLx ISLx Data Sheet 14 Rev. 2.1, 2007-05-30 TLE7189F Description and Electrical Characteristics Electrical Characteristics MOSFET drivers - Dynamic Characteristics VS = 5.5 to 20V, Tj = -40 to +150 °C, fPWM < 25kHz, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Pos. Parameter Symbol Limit Values Unit Conditions Min. Typ. Max. 220 400 600 ns – – -1.5 – A VGxx-VSxx=0V; VS=8...20V; CLoad=22nF; RLoad=1Ω VGxx-VSxx=0V; VS=5.5...8V; CLoad=22nF; RLoad=1Ω VGxx-VSxx=10V; VS=8...20V; CLoad=22nF; RLoad=1Ω CLoad=22nF; RLoad=1Ω 5.1.22 Fixed internal dead time 5.1.23 Turn on current, peak tDT IG(on)1 5.1.24 Turn on current, peak IG(on)2 – -0.8 – A 5.1.25 Turn off current, peak IG(off) – 1.5 – A 5.1.26 Rise time (20-80%) Tj = -40°C Tj = 25°C Tj = 150°C tG_rise – 150 400 400 700 Fall time (20-80%) Tj = -40°C Tj = 25°C Tj = 150°C tG_fall 150 230 230 500 5.1.28 Input propagation time (low on) 90 190 5.1.29 Input propagation time (low off) 0 5.1.30 Input propagation time (high on) 5.1.31 Input propagation time (high off) 5.1.32 Absolute input propagation time difference (all channels turn on) tP(ILN) tP(ILF) tP(IHN) tP(IHF) tP(an) 5.1.33 Absolute input propagation time difference (all channels turn off) tP(af) 5.1.34 ns ns CLoad=22nF; RLoad=1Ω; 290 ns 100 200 ns CLoad=22nF; RLoad=1Ω 90 190 290 ns 0 100 200 ns – – 70 ns – – 50 ns Absolute input propagation time tP(1hfln) difference (1channel high off - low on) – – 180 ns 5.1.35 Absolute input propagation time tP(1lfhn) difference (1channel low off - high on) – – 180 ns 5.1.36 Absolute input propagation time tP(ahfln) difference (all channel high off - low on) – – 180 ns 5.1.37 tP(alfhn) Absolute input propagation time difference (all channel low off - high on) – – 180 ns 5.1.38 Wake up time; INH low to high tINH_Pen1 – – 20 ms 5.1.27 Data Sheet – 15 CLoad=22nF; RLoad=1Ω Driver fully functional; VS=6.5...8V; VENA=low; CCPx=CCBx=4,7µF Rev. 2.1, 2007-05-30 TLE7189F Description and Electrical Characteristics Electrical Characteristics MOSFET drivers - Dynamic Characteristics VS = 5.5 to 20V, Tj = -40 to +150 °C, fPWM < 25kHz, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Pos. Parameter Symbol Limit Values 5.1.39 Wake up time; INH low to high tINH_Pen2 – 5.1.40 Wake up time logic functions; INH low tINH_log to high 5.1.41 Wake up time logic functions; INH low tINH_log to high 5.1.42 Min. Unit Conditions Typ. Max. – 10 ms Driver fully functional; VS=8...20V; VENA=low; CCPx=CCBx=4,7µF – – 10 ms Driver fully functional; VS=6.5...8V; VENA=low; CCPx=CCBx=4,7µF – – 5 ms Driver fully functional; VS=8...20V; VENA=low; CCPx=CCBx=4,7µF INH propagation time to disable the output stages tINH_Pdi1 – – 10 µs VS=5.5...8V 5.1.43 INH propagation time to disable the output stages tINH_Pdi2 – – 8 µs VS=8...20V 5.1.44 INH propagation time to disable the entire driver IC tINH_Pdi3 – – 300 µs – 5.1.45 Supply voltage Vs for Wake up VVsWU 6.5 – – V diagnostic, OpAmp working 5.1.46 Charge pump frequency fCP 38 55 72 kHz – Data Sheet 16 Rev. 2.1, 2007-05-30 TLE7189F 5.2 Protection and Diagnostic Functions 5.2.1 Short Circuit Protection The TLE7189F provides a short circuit protection for the external MOSFETs. It is a monitoring of the drain-source voltage of the external MOSFETs. As soon as this voltage is higher than the short circuit detection limit, a capacitor will be charged. The high side and the low side output stage of the same half bridge use the same capacitor (see Figure 3 ). This capacitor is discharged permanently with a current which is about 2 times smaller than the charging current. This charging and discharging ratio is specified with the help of duty cycle where a short is detected or not detected. After a delay of about 12µs all external MOSFETs will be switched off until the driver is reset by the ENA pin. The error flag is set. The drain-source voltage monitoring of the short circuit detection for a certain external MOSFET is active as soon as the corresponding input is set to "on" and the dead time is expired. The short circuit detection level is adjustable in an analogue manner by the voltage setting at the SCDL pin. There is a 1:1 translation between the voltage applied to the SCDL pin and the drain-source voltage limit. E.g. to trigger the SCD circuit at 1V drain-source voltage, the SCDL pin must be set to 1V as well. The drain-source voltage limit can be chosen between 0.7 ... 2.5V. If the SCDL pin is left open, the short circuit detection level will be set internally to a specified value. In case SCDL is connected to GND the detection level is low. If SCDL is connected to 3.3V, the detection level is about 3.2V. In the TLE7189F the short circuit detection functionality can be tested by setting the SCDL pin to voltages lower than 0.4V, switching off the low side MOSFETs and switching on one or more high side MOSFETs. In this test, a short circuit will be detected even without current in the external MOSFET (VDH-SHx > VTSCD1). This test function can be used as well to detect an open VDH pin. If VDH is open during this test, no SCD error will be reported. A setting of 5V at the SCDL pin will disable the short circuit protection function. 5.2.2 Dead Time and Shoot Through Protection In bridge applications it has to be assured that the external high side and low side MOSFETs are not "on" at the same time, connecting directly the battery voltage to GND. The dead time generated in the TLE7189F is fixed to a minimum value. This function assures a minimum dead time if the input signals coming from the µC are faulty. The exact dead time of the bridge is usually controlled by the PWM generation unit of the µC. In addition to this dead time, the TLE7189F provides a locking mechanism, avoiding that both external MOSFETs of one half bridge can be switched on at the same time. This functionality is called shoot through protection. If the command to switch on both high and low side switches in the same half bridge is given at the input pins, the command will be ignored. The conflicting input signals will not generate an error message. 5.2.3 Under Voltage Shut Down The TLE7189F has an integrated under voltage shut down, to assure that the behavior of the device is predictable in all voltage ranges. If the voltage of a charge pump buffer capacitors CBx reaches the under voltage shut down level for a minimum specified filter time, the gate-source voltage of all external MOSFETs will be actively pulled to low. In this situation the short circuit detection of this output stage is deactivated to avoid a latching shut down of the driver. As soon as the charge pump buffer voltage recovers, the output stage condition will be aligned to the input patterns automatically.This allows to continue operation of the motor in case of under voltage shut down without a reset by the µC. Data Sheet 17 Rev. 2.1, 2007-05-30 TLE7189F Under voltage shut down will not occur when VS > 6V, QG < 250nC, fPWM < 25kHz, and the charge pump capacitors Cxx = 4.7 µF. 5.2.4 Over Voltage Shut Down The TLE7189F has an integrated over voltage shut down to avoid destruction of the IC at high supply voltages.The voltage is measured at the Vs and the VDH pin. When one of them or all of them exceed the over voltage shut down level for more than the specified filter time then the external MOSFETs are switched off. In addition, over voltage will shut down the charge pumps and will discharge the charge pump capacitors. This results in an under voltage condition which will be indicated on the ERRx pins. During over voltage shut down the external MOSFETs and the charge pumps remain off until a reset is performed. 5.2.5 Over Temperature Warning If the junction temperature is exceeding typ. 155°C an error signal is given as warning. The driver IC will continue to operate in order not to disturb the application. The warning is removed automatically when the junction temperature is cooling down. It is in the responsibility of the user to protect the device against over temperature destruction. 5.2.6 VCC Check To assure a high level of system safety, the TLE7189F provides an VCC check. The 5.0V system supply connected to the VS_OA pin is checked by an internally monitoring for over- and under voltage. An internal filter time is integrated to avoid faulty triggering. The VCC check is active when the signal on the ENA pin is high and inactive when ENA signal is low (=driver IC disabled). In case of under- or over voltage at VS_OA, the VCC check will disable the driver IC and is latched. To restart the output stages, a reset has to be performed with the ENA pin. The VCT pin decides about the over voltage and under voltage detection level. 5.2.7 ERR Pins The TLE7189F has two status pins to provide diagnostic feedback to the µC. The outputs of these pins are 5V push pull stages, they are either High or Low. Table 2 Overview of error conditions INH ENA ERR1 ERR2 Driver conditions High High Low Low Under voltage or VCC check error High High Low High Over temperature or over voltage High High High Low Short circuit detection High High High High No errors observed High Low High High No errors will be reported Low X Low Low ERR output tristate - low secured by pull down Table 3 Behavior at different error conditions Error condition restart behavior Short circuit detection Latch, reset must be performed at ENA pin All external Power -MOSFETs Under voltage Auto restart Over voltage Latch, reset must be performed at ENA pin All external Power -MOSFETs Data Sheet Shuts down... All external Power -MOSFETs 18 Rev. 2.1, 2007-05-30 TLE7189F Error condition restart behavior Shuts down... Over temperature warning Self clearing VCC check Nothing Latch, reset must be performed at ENA pin All external Power -MOSFETs Note: All errors do NOT lead to sleep mode. Sleep mode is only initiated with the INH pin. The latch and restart behavior allows to distinguish between the different error types combined at the ERR signals. Table 4 Priorisation of Errors Priority Error 1 VCC check 2 Short circuit detection 3 Under voltage detection 4 Over voltage detection 5 Over temperature Reset of ERROR registers and Disable The TLE7189F can be reset with the help of the enable pin ENA. If the ENA pin is pulled to low for a specified minimum time, the error registers are cleared and the external MOSFETs are switched off actively. During disable only the errors under voltage shut down and over temperature warning are shown. Other errors are not displayed. 5.2.8 Electrical Characteristics Electrical Characteristics - Protection and diagnostic functions VS = 5.5 to 20V, Tj = -40 to +150 °C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Pos. Parameter Symbol Limit Values Min. Typ. Max. Unit Conditions Over temperature 5.2.1 Over temperature warning Tj(OW) 135 155 175 °C – 5.2.2 Hysteresis for over temperature warning dTj(OW) – 20 – °C – Filter time of short circuit protection tSCP(off) 8 12 16 µs Default DSCDmax – – 30 % fPWM=100kHz at IHx or ILx and at static applied SC 70 – – % fPWM=100 kHz at Short circuit detection 5.2.3 1) 5.2.4 Maximum duty cycle for no SCD 5.2.5 minimum duty cycle for periodic SCD1) DSCDmin 5.2.6 Voltage range on VSCD pin to adjust the Vds limit VSCDLa1 0.7 – 2.5 V Short circuit detection is active 5.2.7 Short circuit detection level VSCDLa2 2.64 – 3.63 V Short circuit detection is active IHx or ILx and at static applied SC VSCDL=3.3V Data Sheet 19 Rev. 2.1, 2007-05-30 TLE7189F Electrical Characteristics - Protection and diagnostic functions (cont’d) VS = 5.5 to 20V, Tj = -40 to +150 °C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Pos. Parameter Symbol Limit Values Min. Typ. Max. Unit Conditions Short circuit detection is disabled 5.2.8 Short circuit disable voltage at VSCD pin VSCDL(dis) 4.5 – 5.5 V 5.2.9 Accuracy of SCD (VSCDL /VDS(off)) ASC(off)1 – 1.15 – Accuracy of SCD (VSCDL /VDS(off)) ASC(off)2 5.2.11 SCDL pull up resistor – 400 – kΩ Not tested 5.2.12 SCDL pull down resistor – 160 – kΩ Not tested 5.2.13 SCDL default voltage RSCDU RSCDD VSCDLop – 1.4 – V Open pin 5.2.10 0.85 VSCDL(off) set to 1... 2.5V 0.7 – 1.3 – VSCDL(off) set to 0.7... 1V Test of short circuit detection 5.2.14 SCDL voltage for SCD test activation VSCDT – – 0.4 V – 5.2.15 Filter time for SCD test activation 0.5 2.5 – µs – 5.2.16 VDH-SHx voltage for SCD detection in SCD test mode tSCDT VTSCD1 -80 – – mV 5.2.17 VDH-SHx voltage with no SCD detection in SCD test mode VTSCD2 – – -350 mV VOHERR VOLERR RERR 4.0 – 5.2 V -0.1 – 0.4 V 2.7 – 112 kΩ ILoad= -0.2mA ILoad= 0.2mA VERR<5.5V; VINH=low – – 200 ns – VOV(off) tOV VUV1 VUV2 VHUV1,2 28 – 33 V – 30 – 60 µs – 7.4 8.2 9.0 V CB1 to GND 4.6 – 6.8 V CB2 to VDH – 1.0 – V – tUV 3.5 5 7 µs – ERR pins 5.2.18 High level output voltage of ERRx 5.2.19 Low level output voltage of ERRx 5.2.20 ERR pull down resistor 5.2.21 Propagation time difference ERR1 tPD(ERR) and ERR2 Over- and under voltage 5.2.22 Over voltage shut down 5.2.23 Over voltage filter time 5.2.24 Under voltage shut down CB1 5.2.25 Under voltage shut down CB2 5.2.26 Hysteresis of under voltage shut down on CB1 and CB2 5.2.27 Under voltage filter time on CB1 and CB2 Enable and reset 5.2.28 Reset time to clear ERR registers tRes1 3.0 – – µs – 5.2.29 Low time of ENA signal without reset tRes0 – – 1.0 µs – 5.2.30 ENA propagation time (for enable / tPENA disable) – – 4.0 µs – Data Sheet 20 Rev. 2.1, 2007-05-30 TLE7189F Electrical Characteristics - Protection and diagnostic functions (cont’d) VS = 5.5 to 20V, Tj = -40 to +150 °C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Pos. 5.2.31 Parameter Symbol Return time to normal operation at tAR auto-restart Limit Values Unit Conditions 1.0 µs – – 4.7 V 5.3 – 5.8 V 3.3 – 4.3 V VVCT=low VVCT=low VVCT=high 10 – 25 µs – – – 1.0 V – Min. Typ. Max. – – 4.3 VCC Check 5.2.38 VVCU Over voltage detection level VVCOl Over voltage detection level VVCOh Over- and under voltage filter time tVC Low level input voltage of VCT VVCT_LL High level input voltage of VCT VVCT_HL RVCT VCT pull down resistor 5.2.39 Filter time for VCT test 5.2.32 5.2.33 5.2.34 5.2.35 5.2.36 5.2.37 1) Under voltage detection level tVCT 2.0 – – V – 27 45 63 kΩ VVCT<5.5V 1.3 2 3.0 µs – Parameters describe the behavior of the internal SCD circuit. Therefore only internal delay times are considered. In application dead-/ delay times determined by application circuit (switching times of MOSFETs, adjusted dead time) have to be considered as well. Data Sheet 21 Rev. 2.1, 2007-05-30 TLE7189F 5.3 Shunt Signal Conditioning The TLE7189F incorporates three fast and precise operational amplifiers for conditioning and amplification of the shunt signals sensed in the three phases. Additionally, one reference bias buffer is integrated to provide an adjustable bias reference for the three OpAmps. The voltage divider on the VRI pin should be less than 50 kΩ, the filtering capacitor less than 1.2 µF - if needed at all. The gain of the OpAmps is adjustable by external resistors within a range of 3 to 20 or more, as long as the band width satisfies the need of the application. In the circuit example below VO1 provides the reference voltage VVRO, when the shunt voltage is zero. VVRO is normally half of the regulated voltage provided from an external voltage regulator for the ADC used to read the current sense signal. The additional buffer allows bi-directional current sensing and permits the adaptation of the reference bias to different µC I/O voltages. The reference buffer assures a stable reference voltage even in the high frequency range. The reference bias buffer is used for all of the OpAmps. The OpAmps of the TLE7189F demonstrate low offset voltages and very little drift over temperature, thus allowing accurate phase current measurements. 3.3V CVRI < 1.2 µF (if needed) Adjustable bias reference RVRI VRI RVRI < 50 kOhm CVRI RVRI + Bias VRO Reference - Rfb Rfb Rfb ISP1 Rs + I-DC Link OpAmp1 - TLE7189 Shunt Rs ISN1 Rfb Rs + I-DC Link OpAmp2 Dependent on customer specific requirements additional filtering can be necessary ISP2 Rs ISN2 - Rs + I-DC Link OpAmp3 - VO3 VO2 1k ISP3 Rs ISN3 VO1 1k to ADCs Figure 4 Data Sheet Shunt Signal Conditioning Block Diagram 22 Rev. 2.1, 2007-05-30 TLE7189F 5.3.1 Electrical Characteristics Electrical Characteristics - Current sense signal conditioning VS = 5.5 to 20V, VVSOA = 5V, Tj = -40 to +150 °C, fPWM < 25kHz, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Pos. Parameter Symbol Limit Values Min. 5.3.1 Series resistors Unit Conditions Typ. Max. RRS 100 RRfb/RRS1 5 RRfb/RRS2 3 500 1000 Ω – – 20 – – – 20 – 1kΩ and 200pF at VOx 5.3.2 Resistor ratio (gain ratio) 5.3.3 Resistor ratio (gain ratio) 5.3.4 Input differential voltage (ISPx ISNx) VIDR -800 – 800 mV – 5.3.5 Input voltage (Both Inputs - GND) (ISP - GND) or (ISN -GND) VLL1 -800 – 2200 mV VS=8 ... 20V 5.3.6 Input voltage (Both Inputs - GND) (ISP - GND) or (ISN -GND) VLL2 -800 – 1500 mV 5.3.7 Input offset voltage of the I-DC link VIO1 OpAmp, including drift over temperature range -1.58 – 1.28 mV RRS=500Ω; VCM=0V; VO=1.65V; VVRI=1.65V 5.3.8 Input offset voltage of reference buffer VIO2 -3 – 2 mV – 5.3.9 VRI input range 1.2 – 2.6 V – 5.3.10 Input bias current VRI IIB -300 – – µA VCM=0V; VOx=open 5.3.11 Input bias current of reference buffer IIBRB 0.6 1.4 2.4 µA VVRI=1.65V 5.3.12 High level output voltage of VOx VOH 4.0 – 4.5 V 5.3.13 Low level output voltage of VOx VOL -0.1 – 0.2 V 5.3.14 Output voltage of VOx VOR 1.623 1.65 1.668 V VVRI=1.2 ... 2.6V; IOx=-3mA; VVRI=1.2 ... 2.6V; IOx=3mA VIN(SS)=0V; ISC RRI CICM – – -5 mA 100 – – kΩ – – – 10 pF 10kHz CMRR 80 – – db – – db VIN=360mV* 5.3.15 Output short circuit current 1) 5.3.16 Differential input resistance 5.3.17 Common mode input capacitance1) 5.3.18 Common mode rejection ratio at DC CMRR = 20*Log((Vout_diff/Vin_diff) * (Vin_CM/Vout_CM)) 5.3.19 Common mode suppression2) with CMS CMS = 20*Log(Vout_CM/Vin_CM) Freq =100kHz Freq = 1MHz Freq = 10MHz Data Sheet Gain=15; VVRI=1.65V – 62 43 33 23 short to GND sin(2*π*freq*t); RRS=500Ω; RRfb=7500Ω; VVRI=1.65, 2.5V Rev. 2.1, 2007-05-30 TLE7189F Electrical Characteristics - Current sense signal conditioning (cont’d) VS = 5.5 to 20V, VVSOA = 5V, Tj = -40 to +150 °C, fPWM < 25kHz, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Pos. Parameter Symbol ISC Limit Values Unit Conditions – V/µs Gain>= 5; RLoad=1.0kΩ; CLoad=500pF Min. Typ. Max. – 10 5.3.20 Slew rate 5.3.21 Large signal open loop voltage gain AOL (DC) 80 100 – dB – 5.3.22 Unity gain bandwidth GBW 10 20 – MHz RLoad=1kΩ; CLoad=100pF 5.3.23 Phase margin1) ΦM – 50 – ° Gain>= 5; RLoad=1kΩ; CLoad=100pF 5.3.24 Gain margin1) AM – 12 – db RLoad=1kΩ; CLoad=100pF 5.3.25 Bandwidth BWG 1.6 – – MHz Gain=15; RLoad=1kΩ; CLoad=500pF; RRS=500Ω 5.3.26 Output settle time to 98% – 1 1.8 µs 5.3.27 Output rise time 10% to 90% – – 1 µs 5.3.28 Output fall time 90% to 10% tset tIrise tIfall – – 1 µs Gain=15; RLoad=1kΩ; CLoad=500pF; 0.2<VVO< 4.0V; RRS=500Ω 1) Not subject to production test; specified by design 2) Without considering any offsets such as input offset voltage, internal miss match and assuming no tolerance error in external resistors. Data Sheet 24 Rev. 2.1, 2007-05-30 TLE7189F Application Description 6 Application Description In the automotive sector there are more and more applications requiring high performance motor drives, such as electro-hydraulic or electric power steering. In these applications 3 phase motors, synchronous and asynchronous, are used, combining high output performance, low space requirements and high reliability. Reverse polarity switch V S=12V R VS 10 Ω *) C xxxx µF P-GND RVDH 100 Ω V_Bridge INH VS VDH VS_OA >2 Ω SCDL GH1 VRI SH1 >2 Ω GH2 CH2 C CP2 1µF SH2 CL2 CCB2 1 µF ceramic µC and/or System ASIC GH3 TLE7189 V_Bridge CCP1 1 µF >2 Ω CB2 SH3 CH1 >2 Ω CL1 CCB1 2.2µF GL1 CB1 SL1 see 4.1.2: all pump capacitors 1µF to 4.7µF >2 Ω GL2 ENA SL2 RERR *) RERR *) ERR1 >2 Ω GL3 ERR2 IL1 SL3 IH1 IL2 VRO IH2 ISP3 IL3 ISP2 ISP1 IH3 VCT GND VO3 ISN3 VO2 ISN2 VO1 GND Shunt ISN1 RO *) capacitors for shunt signal conditioning only if additional filtering is desired *) see max. Ratings P-GND Figure 5 Application Circuit - TLE7189F Note: This is a very simplified example of an application circuit. The function must be verified in the real application. Data Sheet 25 Rev. 2.1, 2007-05-30 TLE7189F Application Description 6.1 Layout Guide Lines Please refer also to the simplified application example. • • • • • • • • • Three separated bulk capacitors CB should be used - one per half bridge Three separated ceramic capacitors CC should be used - one per half bridge Each of the 3 bulk capacitors CB and each of the 3 ceramic capacitors CC should be assigned to one of the half bridges and should be placed very close to it The components within one half bridge should be placed close to each other: high side MOSFET, low side MOSFET, bulk capacitor CB and ceramic capacitor CC (CB and CC are in parallel) and the shunt resistor form a loop that should be as small and tight as possible. The traces should be short and wide The three half bridges can be separated; yet, when there is one common GND referenced shunt resistor for the three half bridges the sources of the three low side MOSFETs should be close to each other and close to the common shunt resistor VDH is the sense pin used for short circuit detection; VDH should be routed (via Rvdh) to the common point of the drains of the high side MOSFETs to sense the voltage present on drain high side CB2 is the buffer capacitor of charge pump 2; its negative terminal should be routed to the common point of the drains of the high side MOSFETs as well - this connection should be low inductive / resistive Additional R-C snubber circuits (R and C in series) can be placed to attenuate/suppress oscillations during switching of the MOSFETs, there may be one or two snubber circuits per half bridge, R (several Ohm) and C (several nF) must be low inductive in terms of routing and packaging (ceramic capacitors) the exposed pad on the backside of the VQFN is recommended to connect to GND Data Sheet 26 Rev. 2.1, 2007-05-30 TLE7189F Package Outlines 7 Package Outlines 11 x 0.65 = 7.15 0.9 MAX. 9 ±0.1 A 8.75 ±0.1 B (0.65) 48x 0.08 0.65 0.55 ±0.05 25 36 Index Marking C 37 6.8 ±0.15 0.65 11 x 0.65 = 7.15 12˚MAX. SEATING PLANE 9 ±0.1 8.75 ±0.1 24 13 48 1 12 0.35 ±0.05 (0.2) 0.05 MAX. STANDOFF Index Marking 48x 0.1 M A B C 6.8 ±0.15 GVQ01049 GPS09181 Figure 6 PG-VQFN-48 Green Product (RoHS compliant) To meet the world-wide customer requirements for environmentally friendly products and to be compliant with government regulations the device is available as a green product. Green products are RoHS-Compliant (i.e Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020). You can find all of our packages, sorts of packing and others in our Infineon Internet Page “Products”: http://www.infineon.com/products. Data Sheet 27 Dimensions in mm Rev. 2.1, 2007-05-30 TLE7189F Revision History 8 Revision History Version Date Changes V0.1 2005-11 Proposal for Target Data Sheet V1.0 2007-02-26 Preliminary Data Sheet V2.0 2007-03-29 Data Sheet V2.1 2007-05-30 5.1.25 + 26: turn on current - sign changed 5.3.10: Input bias current - sign changed 5.3.15: Output short circuit current - sign changed Description of OpAmp slightly changed Names of some parameters changed Data Sheet 28 Rev. 2.1, 2007-05-30 Edition 2007-05-30 Published by Infineon Technologies AG 81726 Munich, Germany © 2007 Infineon Technologies AG All Rights Reserved. Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices, please contact the nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements, components may contain dangerous substances. For information on the types in question, please contact the nearest Infineon Technologies Office. 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