IRF JANTX2N6788U

PD - 93983
REPETITIVE AVALANCHE AND dv/dt RATED

HEXFET TRANSISTORS
SURFACE MOUNT (LCC-18)
IRFE120
JANTX2N6788U
[REF:MIL-PRF-19500/555]
100V, N-CHANNEL
Product Summary
Part Number
IRFE120
BVDSS
100V
RDS(on)
0.30Ω
ID
4.5A
The leadless chip carrier (LCC) package represents the
logical next step in the continual evolution of surface
mount technology. Desinged to be a close replacement
for the TO-39 package, the LCC will give designers the
extra flexibility they need to increase circuit board density. International Rectifier has engineered the LCC package to meet the specific needs of the power market by
increasing the size of the bottom source pad, thereby
enhancing the thermal and electrical performance. The
lid of the package is grounded to the source to reduce
RF interference.
LCC-18
Features:
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Surface Mount
Small Footprint
Alternative to TO-39 Package
Hermetically Sealed
Dynamic dv/dt Rating
Avalanche Energy Rating
Simple Drive Requirements
Light Weight
Absolute Maximum Ratings
Parameter
ID @ VGS = 10V, TC = 25°C
ID @ VGS = 10V, TC = 100°C
I DM
PD @ TC = 25°C
VGS
EAS
IAR
EAR
dv/dt
TJ
T STG
Units
Continuous Drain Current
Continuous Drain Current
Pulsed Drain Current ➀
Max. Power Dissipation
Linear Derating Factor
Gate-to-Source Voltage
Single Pulse Avalanche Energy ➁
Avalanche Current ➀
Repetitive Avalanche Energy ➀
Peak Diode Recovery dv/dt ➂
Operating Junction
Storage Temperature Range
4.5
3.0
18
14
0.11
±20
76
5.5
-55 to 150
Pckg. Mounting Surface Temp.
Weight
300 (for 5 S)
0.42(typical)
A
W
W/°C
V
mJ
A
mJ
V/ns
o
C
g
For footnotes refer to the last page
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1
1/16/01
IRFE120
Electrical Characteristics
Parameter
Min
Drain-to-Source Breakdown Voltage
100
Typ Max Units
—
—
V
—
0.10
—
V/°C
—
—
2.0
1.5
—
—
—
—
—
—
—
—
0.30
0.345
4.0
—
25
250
V GS(th)
gfs
IDSS
Temperature Coefficient of Breakdown
Voltage
Static Drain-to-Source On-State
Resistance
Gate Threshold Voltage
Forward Transconductance
Zero Gate Voltage Drain Current
IGSS
IGSS
Qg
Qgs
Qgd
td(on)
tr
td(off)
tf
LS + LD
Gate-to-Source Leakage Forward
Gate-to-Source Leakage Reverse
Total Gate Charge
Gate-to-Source Charge
Gate-to-Drain (‘Miller’) Charge
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Total Inductance
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
6.1
100
-100
17
4.0
7.7
40
70
40
70
—
Ciss
Coss
Crss
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
—
—
—
350
150
24
—
—
RDS(on)
Test Conditions
VGS = 0V, ID = 1.0mA
Reference to 25°C, ID = 1.0mA
nC
VGS = 10V, ID =3.0A➃
VGS =10V, ID = 4.5A ➃
VDS = VGS, ID =250µA
VDS > 15V, IDS =3.0A➃
VDS=80V, VGS=0V
VDS =80V
VGS = 0V, TJ = 125°C
VGS = 20V
VGS = -20V
VGS =10V, ID= 4.5A
VDS =50V
ns
VDD =50V, ID =4.5A,
RG =7.5Ω
Ω
V
S( )
Ω
BVDSS
∆BV DSS/∆TJ
@ Tj = 25°C (Unless Otherwise Specified)
µA
nA
nH
Measured from the center of
drain pad to center of source
pad
pF
VGS = 0V, VDS = 25V
f = 1.0MHz
Source-Drain Diode Ratings and Characteristics
Parameter
Min Typ Max Units
IS
ISM
Continuous Source Current (Body Diode)
Pulse Source Current (Body Diode) ➀
—
—
—
—
4.5
18
A
VSD
t rr
QRR
Diode Forward Voltage
Reverse Recovery Time
Reverse Recovery Charge
—
—
—
—
—
—
1.8
240
2.0
V
nS
µc
ton
Forward Turn-On Time
Test Conditions
Tj = 25°C, IS =4.5A, VGS = 0V ➃
Tj = 25°C, IF = 4.5A, di/dt ≤ 100A/µs
VDD ≤ 50V ➃
Intrinsic turn-on time is negligible. Turn-on speed is substantially controlled by LS + LD.
Thermal Resistance
Parameter
R thJC
R thJ-PCB
Junction to Case
Junction to PC Board
Min Typ Max Units
—
—
—
—
9.1
°C/W
26" " "
Test Conditions
Soldered to a copper clad PC board
For footnotes refer to the last page
2
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IRFE120
Fig 1. Typical Output Characteristics
Fig 3.
Typical Transfer Characteristics
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Fig 2. Typical Output Characteristics
Fig 4.
Normalized On-Resistance
Vs. Temperature
3
IRFE120
13 a& b
4
Fig 5. Typical Capacitance Vs.
Drain-to-Source Voltage
Fig 6. Typical Gate Charge Vs.
Gate-to-Source Voltage
Fig 7. Typical Source-Drain Diode
Forward Voltage
Fig 8. Maximum Safe Operating Area
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IRFE120
V DS
VGS
RG
RD
D.U.T.
+
-V DD
10V
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
Fig 10a. Switching Time Test Circuit
VDS
90%
10%
VGS
Fig 9. Maximum Drain Current Vs.
Case Temperature
td(on)
tr
t d(off)
tf
Fig 10b. Switching Time Waveforms
Fig 11.
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Maximum Effective Transient Thermal Impedance, Junction-to-Case
5
IRFE120
15V
L
VDS
D.U.T
RG
10V
20V
IAS
DRIVER
+
V
- DD
A
0.01Ω
tp
Fig 12a. Unclamped Inductive Test Circuit
V(BR)DSS
tp
Fig 12c. Maximum Avalanche Energy
Vs. Drain Current
I AS
Fig 12b.
Current Regulator
Same Type as D.U.T.
Unclamped Inductive Waveforms
50KΩ
QG
12V
.2µF
.3µF
10 V
QGS
QGD
+
V
- DS
VGS
VG
3mA
Charge
Fig 13a. Basic Gate Charge Waveform
6
D.U.T.
IG
ID
Current Sampling Resistors
Fig 13b. Gate Charge Test Circuit
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IRFE120
Foot Notes:
➀ Repetitive Rating; Pulse width limited by
maximum junction temperature.
➁ VDD = 25V, starting TJ = 25°C,
Peak IL = 4.5A,
➂ ISD ≤ 4.5A, di/dt ≤ 110A/µs,
VDD≤ 100V, TJ ≤ 150°C
Suggested RG =7.5 Ω
➃ Pulse width ≤ 300 µs; Duty Cycle ≤ 2%
Case Outline and Dimensions — LCC-18
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Data and specifications subject to change without notice.1/01
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