IRF IRF7807ZUPBF

PD-96068A
IRF7807ZUPbF
HEXFET® Power MOSFET
Applications
l Control FET for Notebook Processor Power
l Synchronous Rectifier MOSFET for
Graphics Cards and POL Converters in
Networking and Telecommunication
Systems
Benefits
l Very Low RDS(on) at 4.5V VGS
l Ultra-Low Gate Impedance
l Fully Characterized Avalanche Voltage and
Current
V DSS
R DS(on) max
Qg(typ.)
30V
13.8m @VGS = 10V
7.2nC
:
A
A
D
S
1
8
S
2
7
D
S
3
6
D
G
4
5
D
SO-8
Top View
l 100% Tested for RG
l Lead-Free
Absolute Maximum Ratings
Parameter
Max.
Units
Drain-to-Source Voltage
30
V
Gate-to-Source Voltage
± 20
VDS
VGS
ID @ TA = 25°C
Continuous Drain Current, VGS @ 10V
11
ID @ TA = 70°C
Continuous Drain Current, VGS @ 10V
8.7
IDM
Pulsed Drain Current
c
PD @TA = 70°C
f
Power Dissipation f
TJ
Linear Derating Factor
Operating Junction and
TSTG
Storage Temperature Range
PD @TA = 25°C
A
88
Power Dissipation
W
2.5
1.6
W/°C
°C
0.02
-55 to + 150
Thermal Resistance
Parameter
RθJL
RθJA
Junction-to-Drain Lead
Junction-to-Ambient
f
Typ.
Max.
Units
–––
20
°C/W
–––
50
Notes  through „ are on page 10
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09/14/06
IRF7807ZUPbF
Static @ TJ = 25°C (unless otherwise specified)
Parameter
Min. Typ. Max. Units
–––
V
Conditions
BVDSS
Drain-to-Source Breakdown Voltage
30
–––
∆ΒVDSS/∆TJ
Breakdown Voltage Temp. Coefficient
–––
0.023
–––
V/°C Reference to 25°C, ID = 1mA
RDS(on)
Static Drain-to-Source On-Resistance
–––
11
13.8
mΩ
–––
14.5
18.2
VGS = 10V, ID = 11A
e
e
VGS = 4.5V, ID = 8.8A
VGS(th)
Gate Threshold Voltage
1.35
1.8
2.25
V
∆VGS(th)
Gate Threshold Voltage Coefficient
–––
- 4.7
–––
mV/°C
IDSS
Drain-to-Source Leakage Current
–––
–––
1.0
µA
–––
–––
150
Gate-to-Source Forward Leakage
–––
–––
100
Gate-to-Source Reverse Leakage
–––
–––
-100
gfs
Forward Transconductance
22
–––
–––
Qg
IGSS
VGS = 0V, ID = 250µA
VDS = VGS, ID = 250µA
VDS = 24V, VGS = 0V
VDS = 24V, VGS = 0V, TJ = 125°C
nA
VGS = 20V
S
VDS = 15V, ID = 8.8A
nC
VGS = 4.5V
VGS = -20V
Total Gate Charge
–––
7.2
11
Qgs1
Pre-Vth Gate-to-Source Charge
–––
2.1
–––
Qgs2
Post-Vth Gate-to-Source Charge
–––
0.7
–––
Qgd
Gate-to-Drain Charge
–––
2.7
–––
ID = 8.8A
Qgodr
Gate Charge Overdrive
–––
1.7
–––
See Fig. 16
Qsw
Switch Charge (Qgs2 + Qgd)
–––
3.4
–––
Qoss
Output Charge
–––
2.8
–––
nC
RG
Gate Resistance
–––
2.5
4.8
Ω
td(on)
Turn-On Delay Time
–––
6.9
–––
tr
Rise Time
–––
6.2
–––
td(off)
Turn-Off Delay Time
–––
10
–––
tf
Fall Time
–––
3.1
–––
Ciss
Input Capacitance
–––
770
–––
Coss
Output Capacitance
–––
190
–––
Crss
Reverse Transfer Capacitance
–––
100
–––
VDS = 15V
VDS = 15V, VGS = 0V
VDD = 15V, VGS = 4.5V
e
ID = 8.8A
ns
Clamped Inductive Load
pF
VDS = 15V
VGS = 0V
ƒ = 1.0MHz
Avalanche Characteristics
EAS
IAR
Parameter
Single Pulse Avalanche Energy
Avalanche Current c
d
Typ.
Max.
Units
–––
63
mJ
–––
8.8
A
Diode Characteristics
Parameter
IS
Continuous Source Current
Min. Typ. Max. Units
–––
–––
3.1
(Body Diode)
Conditions
MOSFET symbol
A
showing the
ISM
Pulsed Source Current
–––
–––
88
VSD
(Body Diode)
Diode Forward Voltage
–––
–––
1.0
V
p-n junction diode.
TJ = 25°C, IS = 8.8A, VGS = 0V
trr
Reverse Recovery Time
–––
31
46
ns
TJ = 25°C, IF = 8.8A, VDD = 15V
Qrr
Reverse Recovery Charge
–––
17
26
nC
di/dt = 100A/µs
2
c
integral reverse
e
e
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IRF7807ZUPbF
ID, Drain-to-Source Current (A)
TOP
10
BOTTOM
1
100
VGS
10V
8.0V
4.5V
3.8V
3.3V
3.0V
2.8V
2.5V
2.5V
20µs PULSE WIDTH
Tj = 25°C
BOTTOM
10V
8.0V
4.5V
3.8V
3.3V
3.0V
2.8V
2.5V
10
2.5V
20µs PULSE WIDTH
Tj = 150°C
0.1
1
0.1
0
1
10
100
100
0.1
0
VDS, Drain-to-Source Voltage (V)
1
10
100
100
VDS, Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
2.0
T J = 150°C
10.0
TJ = 25°C
VDS = 15V
20µs PULSE WIDTH
1.0
2.0
3.0
4.0
5.0
VGS , Gate-to-Source Voltage (V)
Fig 3. Typical Transfer Characteristics
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6.0
ID = 11A
VGS = 10V
1.5
(Normalized)
RDS(on) , Drain-to-Source On Resistance
100.0
ID, Drain-to-Source Current (Α)
VGS
TOP
ID, Drain-to-Source Current (A)
100
1.0
0.5
-60 -40 -20
0
20
40
60
80 100 120 140 160
TJ , Junction Temperature (°C)
Fig 4. Normalized On-Resistance
Vs. Temperature
3
IRF7807ZUPbF
10000
12
VGS = 0V,
f = 1 MHZ
Ciss = Cgs + Cgd, C ds SHORTED
Crss = Cgd
VGS, Gate-to-Source Voltage (V)
ID= 8.8A
C, Capacitance (pF)
Coss = Cds + Cgd
1000
Ciss
Coss
Crss
100
8
6
4
2
0
10
1
10
0
100
1000
ID, Drain-to-Source Current (A)
100.0
T J = 150°C
T J = 25°C
OPERATION IN THIS AREA
LIMITED BY R DS(on)
100µsec
0.8
1.0
1.2
VSD, Source-toDrain Voltage (V)
Fig 7. Typical Source-Drain Diode
Forward Voltage
1.4
1msec
1
0.1
0.1
0.6
16
10
VGS = 0V
0.4
12
100
10.0
1.0
8
Fig 6. Typical Gate Charge Vs.
Gate-to-Source Voltage
Fig 5. Typical Capacitance Vs.
Drain-to-Source Voltage
ISD, Reverse Drain Current (A)
4
Q G Total Gate Charge (nC)
VDS, Drain-to-Source Voltage (V)
4
VDS= 24V
VDS= 15V
10
Tc = 25°C
Tj = 150°C
Single Pulse
0.1
1.0
10msec
10.0
100.0
1000.0
VDS , Drain-toSource Voltage (V)
Fig 8. Maximum Safe Operating Area
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IRF7807ZUPbF
12
VGS(th) Gate threshold Voltage (V)
2.2
ID , Drain Current (A)
10
8
6
4
2
2.0
ID = 250µA
1.8
1.6
1.4
1.2
0
1.0
25
50
75
100
125
150
-75
-50
-25
T J , Junction Temperature (°C)
Fig 9. Maximum Drain Current Vs.
Case Temperature
0
25
50
75
100
125
150
T J , Temperature ( °C )
Fig 10. Threshold Voltage Vs. Temperature
Thermal Response ( Z thJA )
100
10
D = 0.50
0.20
0.10
0.05
1
0.02
0.01
τJ
0.1
0.01
R1
R1
τJ
τ1
τ1
R2
R2
τ2
τ2
Ci= τi/Ri
Ci i/Ri
SINGLE PULSE
( THERMAL RESPONSE )
R3
R3
τ3
τC
τ
Ri (°C/W) τi (sec)
5.770
0.002691
24.37
19.86
τ3
0.54585
7.25
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthja + Tc
0.001
1E-006
1E-005
0.0001
0.001
0.01
0.1
1
10
100
t1 , Rectangular Pulse Duration (sec)
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Ambient
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5
IRF7807ZUPbF
VDS
D.U.T
RG
VGS
20V
DRIVER
L
+
V
- DD
IAS
A
0.01Ω
tp
Fig 12a. Unclamped Inductive Test Circuit
V(BR)DSS
EAS, Single Pulse Avalanche Energy (mJ)
300
15V
TOP
250
BOTTOM
ID
1.2A
1.5A
8.8A
200
150
100
50
0
tp
25
50
75
100
125
150
Starting T J , Junction Temperature (°C)
Fig 12c. Maximum Avalanche Energy
Vs. Drain Current
LD
I AS
VDS
Fig 12b. Unclamped Inductive Waveforms
+
VDD D.U.T
Current Regulator
Same Type as D.U.T.
VGS
Pulse Width < 1µs
Duty Factor < 0.1%
50KΩ
12V
.2µF
Fig 14a. Switching Time Test Circuit
.3µF
D.U.T.
+
V
- DS
VDS
90%
VGS
3mA
10%
IG
ID
Current Sampling Resistors
Fig 13. Gate Charge Test Circuit
6
VGS
td(on)
tr
td(off)
tf
Fig 14b. Switching Time Waveforms
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IRF7807ZUPbF
D.U.T
Driver Gate Drive
ƒ
+
‚
-
„
*
D.U.T. ISD Waveform
Reverse
Recovery
Current
+

RG
•
•
•
•
dv/dt controlled by RG
Driver same type as D.U.T.
I SD controlled by Duty Factor "D"
D.U.T. - Device Under Test
P.W.
Period
VGS=10V
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
-
D=
Period
P.W.
+
V DD
+
-
Body Diode Forward
Current
di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt
Re-Applied
Voltage
Body Diode
VDD
Forward Drop
Inductor Curent
ISD
Ripple ≤ 5%
* VGS = 5V for Logic Level Devices
Fig 15. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs
Id
Vds
Vgs
Vgs(th)
Qgs1 Qgs2
Qgd
Qgodr
Fig 16. Gate Charge Waveform
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IRF7807ZUPbF
Power MOSFET Selection for Non-Isolated DC/DC Converters
Control FET
Synchronous FET
Special attention has been given to the power losses
in the switching elements of the circuit - Q1 and Q2.
Power losses in the high side switch Q1, also called
the Control FET, are impacted by the Rds(on) of the
MOSFET, but these conduction losses are only about
one half of the total losses.
The power loss equation for Q2 is approximated
by;
*
Ploss = Pconduction + Pdrive + Poutput
(
2
Ploss = Irms × Rds(on)
)
Power losses in the control switch Q1 are given
by;
+ (Qg × Vg × f )
Ploss = Pconduction+ Pswitching+ Pdrive+ Poutput
⎛Q
⎞
+ ⎜ oss × Vin × f + (Qrr × Vin × f )
⎝ 2
⎠
This can be expanded and approximated by;
Ploss = (Irms 2 × Rds(on ) )
⎛
Qgs 2
Qgd
⎞ ⎛
⎞
+⎜I ×
× Vin × f ⎟ + ⎜ I ×
× Vin × f ⎟
ig
ig
⎝
⎠ ⎝
⎠
+ (Qg × Vg × f )
+
⎛ Qoss
× Vin × f ⎞
⎝ 2
⎠
This simplified loss equation includes the terms Qgs2
and Qoss which are new to Power MOSFET data sheets.
Qgs2 is a sub element of traditional gate-source
charge that is included in all MOSFET data sheets.
The importance of splitting this gate-source charge
into two sub elements, Qgs1 and Qgs2, can be seen from
Fig 16.
Qgs2 indicates the charge that must be supplied by
the gate driver between the time that the threshold
voltage has been reached and the time the drain current rises to Idmax at which time the drain voltage begins to change. Minimizing Qgs2 is a critical factor in
reducing switching losses in Q1.
Qoss is the charge that must be supplied to the output capacitance of the MOSFET during every switching cycle. Figure A shows how Qoss is formed by the
parallel combination of the voltage dependant (nonlinear) capacitance’s Cds and Cdg when multiplied by
the power supply input buss voltage.
8
*dissipated primarily in Q1.
For the synchronous MOSFET Q2, Rds(on) is an important characteristic; however, once again the importance of gate charge must not be overlooked since
it impacts three critical areas. Under light load the
MOSFET must still be turned on and off by the control IC so the gate drive losses become much more
significant. Secondly, the output charge Qoss and reverse recovery charge Qrr both generate losses that
are transfered to Q1 and increase the dissipation in
that device. Thirdly, gate charge will impact the
MOSFETs’ susceptibility to Cdv/dt turn on.
The drain of Q2 is connected to the switching node
of the converter and therefore sees transitions between ground and Vin. As Q1 turns on and off there is
a rate of change of drain voltage dV/dt which is capacitively coupled to the gate of Q2 and can induce
a voltage spike on the gate that is sufficient to turn
the MOSFET on, resulting in shoot-through current .
The ratio of Qgd/Qgs1 must be minimized to reduce the
potential for Cdv/dt turn on.
Figure A: Qoss Characteristic
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IRF7807ZUPbF
SO-8 Package Outline
Dimensions are shown in millimeters (inches)
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SO-8 Part Marking
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9
IRF7807ZUPbF
SO-8 Tape and Reel
Dimensions are shown in milimeters (inches)
TERMINAL NUMBER 1
12.3 ( .484 )
11.7 ( .461 )
8.1 ( .318 )
7.9 ( .312 )
FEED DIRECTION
NOTES:
1. CONTROLLING DIMENSION : MILLIMETER.
2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS(INCHES).
3. OUTLINE CONFORMS TO EIA-481 & EIA-541.
330.00
(12.992)
MAX.
14.40 ( .566 )
12.40 ( .488 )
NOTES :
1. CONTROLLING DIMENSION : MILLIMETER.
2. OUTLINE CONFORMS TO EIA-481 & EIA-541.
Notes:
 Repetitive rating; pulse width limited by
max. junction temperature.
‚ Starting TJ = 25°C, L = 1.6mH
RG = 25Ω, IAS = 8.8A.
ƒ Pulse width ≤ 400µs; duty cycle ≤ 2%.
„ When mounted on 1 inch square copper board
Data and specifications subject to change without notice.
This product has been designed and qualified for the Consumer market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information. 09/2006
10
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