IRF IRF8010LPBF

PD - 95433
IRF8010SPbF
IRF8010LPbF
SMPS MOSFET
Applications
l High frequency DC-DC converters
l UPS and Motor Control
l Lead-Free
HEXFET® Power MOSFET
VDSS
RDS(on) max
ID
15mΩ
80A‡
100V
Benefits
l Low Gate-to-Drain Charge to Reduce
Switching Losses
l Fully Characterized Capacitance Including
Effective COSS to Simplify Design, (See
App. Note AN1001)
l Fully Characterized Avalanche Voltage
and Current
l Typical RDS(on) = 12mΩ
D2Pak
IRF8010S
TO-262
IRF8010L
Absolute Maximum Ratings
Parameter
Max.
Units
i
ID @ TC = 25°C Continuous Drain Current, VGS @ 10V
80
ID @ TC = 100°C Continuous Drain Current, VGS @ 10V
Pulsed Drain Current
IDM
320
PD @TC = 25°C Power Dissipation
260
W
1.8
± 20
W/°C
V
16
-55 to + 175
V/ns
57
c
VGS
Linear Derating Factor
Gate-to-Source Voltage
dv/dt
TJ
Peak Diode Recovery dv/dt
Operating Junction and
TSTG
Storage Temperature Range
e
A
°C
Soldering Temperature, for 10 seconds
300 (1.6mm from case )
Thermal Resistance
Parameter
RθJC
Junction-to-Case
Junction-to-Case (end of life)
RθJC
RθCS
Case-to-Sink, Flat, Greased Surface
Junction-to-Ambient (PCB Mount, steady state)
j
RθJA
Notes 
g
through ˆ
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Typ.
Max.
–––
0.57
–––
0.80
0.50
–––
–––
40
Units
°C/W
are on page 8
1
06/21/04
IRF8010S/LPbF
Static @ TJ = 25°C (unless otherwise specified)
Parameter
Min. Typ. Max. Units
V(BR)DSS
Drain-to-Source Breakdown Voltage
∆V(BR)DSS/∆TJ
RDS(on)
100
–––
–––
Breakdown Voltage Temp. Coefficient
–––
0.11
–––
Static Drain-to-Source On-Resistance
–––
12
15
VGS(th)
Gate Threshold Voltage
2.0
–––
4.0
V
IDSS
Drain-to-Source Leakage Current
µA
IGSS
–––
–––
20
–––
–––
250
Gate-to-Source Forward Leakage
–––
–––
200
Gate-to-Source Reverse Leakage
–––
–––
-200
V
Conditions
VGS = 0V, ID = 250µA
V/°C Reference to 25°C, ID = 1mA
mΩ VGS = 10V, ID = 45A
f
VDS = VGS, ID = 250µA
VDS = 100V, VGS = 0V
VDS = 100V, VGS = 0V, TJ = 125°C
nA
VGS = 20V
VGS = -20V
Dynamic @ TJ = 25°C (unless otherwise specified)
Parameter
gfs
Qg
Forward Transconductance
Qgs
Min. Typ. Max. Units
V
Conditions
82
–––
–––
VDS = 25V, ID = 45A
Total Gate Charge
–––
81
120
Gate-to-Source Charge
–––
22
–––
Qgd
Gate-to-Drain ("Miller") Charge
–––
26
–––
VGS = 10V
td(on)
Turn-On Delay Time
–––
15
–––
VDD = 50V
tr
Rise Time
–––
130
–––
td(off)
Turn-Off Delay Time
–––
61
–––
tf
Fall Time
–––
120
–––
VGS = 10V
Ciss
Input Capacitance
–––
3830
–––
VGS = 0V
Coss
Output Capacitance
–––
480
–––
Crss
Reverse Transfer Capacitance
–––
59
–––
Coss
Output Capacitance
–––
3830
–––
VGS = 0V, VDS = 1.0V, ƒ = 1.0MHz
Coss
Output Capacitance
–––
280
–––
VGS = 0V, VDS = 80V, ƒ = 1.0MHz
Coss eff.
Effective Output Capacitance
–––
530
–––
VGS = 0V, VDS = 0V to 80V
ID = 80A
nC
VDS = 80V
f
ID = 80A
ns
RG = 39Ω
f
VDS = 25V
pF
ƒ = 1.0MHz
e
Avalanche Characteristics
EAS
Parameter
Single Pulse Avalanche Energy
IAR
Avalanche Current
EAR
Repetitive Avalanche Energy
c
di
c
Typ.
Max.
Units
–––
310
mJ
–––
45
A
–––
26
mJ
Diode Characteristics
Parameter
Min. Typ. Max. Units
Conditions
IS
Continuous Source Current
–––
–––
80
ISM
(Body Diode)
Pulsed Source Current
–––
–––
320
showing the
integral reverse
VSD
(Body Diode)
Diode Forward Voltage
–––
–––
1.3
V
p-n junction diode.
TJ = 25°C, IS = 80A, VGS = 0V
trr
Reverse Recovery Time
–––
99
150
ns
Qrr
Reverse RecoveryCharge
–––
460
700
nC
ton
Forward Turn-On Time
2
ci
MOSFET symbol
A
D
G
S
f
TJ = 150°C, IF = 80A, VDD = 50V
di/dt = 100A/µs
f
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
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IRF8010S/LPbF
10000
1000
1000
100
BOTTOM
TOP
ID, Drain-to-Source Current (A)
ID, Drain-to-Source Current (A)
TOP
VGS
15V
12V
10V
6.0V
5.5V
5.0V
4.5V
4.0V
10
4.0V
1
10
4.0V
10
1
0.1
1
BOTTOM
20µs PULSE WIDTH
Tj = 175°C
20µs PULSE WIDTH
Tj = 25°C
0.1
100
0.1
100
1
Fig 1. Typical Output Characteristics
3.5
T J = 25°C
VDS = 50V
20µs PULSE WIDTH
1
6.0
8.0
10.0
12.0
14.0
Fig 3. Typical Transfer Characteristics
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16.0
2.5
(Normalized)
100
VGS , Gate-to-Source Voltage (V)
I D = 80A
3.0
RDS(on) , Drain-to-Source On Resistance
ID, Drain-to-Source Current (Α)
T J = 175°C
4.0
100
Fig 2. Typical Output Characteristics
1000
2.0
10
VDS, Drain-to-Source Voltage (V)
VDS, Drain-to-Source Voltage (V)
10
VGS
15V
12V
10V
6.0V
5.5V
5.0V
4.5V
4.0V
2.0
1.5
1.0
0.5
V GS = 10V
0.0
-60
-40
-20
0
20
40
60
80
TJ , Junction Temperature
100 120 140 160 180
( ° C)
Fig 4. Normalized On-Resistance
Vs. Temperature
3
IRF8010S/LPbF
100000
VGS , Gate-to-Source Voltage (V)
Coss = Cds + Cgd
10000
C, Capacitance(pF)
12
VGS = 0V,
f = 1 MHZ
Ciss = C gs + Cgd, C ds SHORTED
Crss = Cgd
Ciss
1000
Coss
100
Crss
ID= 80A
VDS= 80V
VDS= 50V
10
VDS= 20V
8
6
4
2
0
10
1
10
0
100
60
80
100
Fig 6. Typical Gate Charge Vs.
Gate-to-Source Voltage
Fig 5. Typical Capacitance Vs.
Drain-to-Source Voltage
10000
ID, Drain-to-Source Current (A)
1000
OPERATION IN THIS AREA
LIMITED BY R DS(on)
1000
100
I SD , Reverse Drain Current (A)
40
Q G Total Gate Charge (nC)
VDS, Drain-to-Source Voltage (V)
100
TJ = 175 ° C
10
T J= 25 ° C
1
V GS = 0 V
0.0
0.5
1.0
1.5
V SD,Source-to-Drain Voltage (V)
Fig 7. Typical Source-Drain Diode
Forward Voltage
100µsec
10
1msec
1
Tc = 25°C
Tj = 175°C
Single Pulse
10msec
0.1
0.1
4
20
2.0
1
10
100
1000
VDS, Drain-to-Source Voltage (V)
Fig 8. Maximum Safe Operating Area
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IRF8010S/LPbF
LIMITED BY PACKAGE
VGS
D.U.T.
RG
60
I D , Drain Current (A)
RD
V DS
80
+
-VDD
10V
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
40
Fig 10a. Switching Time Test Circuit
20
VDS
90%
0
25
50
75
100
125
150
175
TC , Case Temperature ( °C)
10%
VGS
Fig 9. Maximum Drain Current Vs.
Case Temperature
td(on)
tr
t d(off)
tf
Fig 10b. Switching Time Waveforms
Thermal Response
(Z thJC )
10
1
D = 0.50
P DM
0.20
0.1
t1
0.10
t2
0.05
0.02
0.01
SINGLE PULSE
(THERMAL RESPONSE)
Notes:
1. Duty factor D =
2. Peak T
0.01
0.00001
0.0001
0.001
0.01
t1/ t 2
J = P DM x Z thJC
+T C
0.1
1
t 1, Rectangular Pulse Duration (sec)
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
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5
IRF8010S/LPbF
600
15V
+
V
- DD
IAS
20V
tp
A
0.01Ω
Fig 12a. Unclamped Inductive Test Circuit
V(BR)DSS
tp
EAS , Single Pulse Avalanche Energy (mJ)
D.U.T
RG
ID
18A
BOTTOM
32A
45A
500
DRIVER
L
VDS
TOP
400
300
200
100
0
25
50
75
100
125
150
175
Starting Tj, Junction Temperature (°C)
Fig 12c. Maximum Avalanche Energy
Vs. Drain Current
I AS
Fig 12b. Unclamped Inductive Waveforms
Current Regulator
Same Type as D.U.T.
QG
10 V
50KΩ
12V
.2µF
.3µF
QGS
QGD
D.U.T.
VG
+
V
- DS
VGS
3mA
Charge
Fig 13a. Basic Gate Charge Waveform
6
IG
ID
Current Sampling Resistors
Fig 13b. Gate Charge Test Circuit
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IRF8010S/LPbF
Peak Diode Recovery dv/dt Test Circuit
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
+
D.U.T
ƒ
+
‚
-
-
„
+

RG
•
•
•
•
dv/dt controlled by RG
Driver same type as D.U.T.
ISD controlled by Duty Factor "D"
D.U.T. - Device Under Test
Driver Gate Drive
P.W.
Period
D=
+
-
VDD
P.W.
Period
VGS=10V
*
D.U.T. ISD Waveform
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt
Re-Applied
Voltage
Body Diode
VDD
Forward Drop
Inductor Curent
Ripple ≤ 5%
ISD
* VGS = 5V for Logic Level Devices
Fig 14. For N-Channel HEXFET® Power MOSFETs
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7
IRF8010S/LPbF
D2Pak Package Outline
Dimensions are shown in millimeters (inches)
D2Pak Part Marking Information
T HIS IS AN IRF530S WIT H
LOT CODE 8024
AS S EMB LED ON WW 02, 2000
IN T HE AS SEMBLY LINE "L"
INT ERNAT IONAL
RECT IFIER
L OGO
Note: "P" in ass embly line
position indicates "Lead-Free"
PART NUMBER
F530S
AS S EMB LY
LOT CODE
DAT E CODE
YEAR 0 = 2000
WEEK 02
L INE L
OR
INT E RNAT IONAL
RECT IF IER
LOGO
AS S E MB LY
LOT CODE
8
PART NUMBE R
F530S
DAT E CODE
P = DE S IGNAT ES LEAD-FRE E
PRODUCT (OPT IONAL)
YE AR 0 = 2000
WE EK 02
A = AS S E MB LY S IT E CODE
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IRF8010S/LPbF
TO-262 Package Outline
Dimensions are shown in millimeters (inches)
TO-262 Part Marking Information
EXAMPLE: T HIS IS AN IRL3103L
LOT CODE 1789
AS S EMBL ED ON WW 19, 1997
IN T HE AS S EMBLY LINE "C"
Note: "P" in as s embly line
pos ition indicates "Lead-Free"
INT ERNAT IONAL
RECT IFIER
LOGO
AS S EMBLY
L OT CODE
PART NUMBER
DAT E CODE
YEAR 7 = 1997
WEEK 19
LINE C
OR
INT ERNAT IONAL
RECT IFIER
LOGO
AS S EMBLY
LOT CODE
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PART NUMBER
DAT E CODE
P = DES IGNAT ES LEAD-FREE
PRODUCT (OPT IONAL)
YEAR 7 = 1997
WEEK 19
A = AS S EMBLY S IT E CODE
9
IRF8010S/LPbF
D2Pak Tape & Reel Information
Dimensions are shown in millimeters (inches)
TRR
1.60 (.063)
1.50 (.059)
4.10 (.161)
3.90 (.153)
FEED DIRECTION 1.85 (.073)
1.65 (.065)
1.60 (.063)
1.50 (.059)
11.60 (.457)
11.40 (.449)
0.368 (.0145)
0.342 (.0135)
15.42 (.609)
15.22 (.601)
24.30 (.957)
23.90 (.941)
TRL
10.90 (.429)
10.70 (.421)
1.75 (.069)
1.25 (.049)
4.72 (.136)
4.52 (.178)
16.10 (.634)
15.90 (.626)
FEED DIRECTION
13.50 (.532)
12.80 (.504)
27.40 (1.079)
23.90 (.941)
4
330.00
(14.173)
MAX.
60.00 (2.362)
MIN.
NOTES :
1. COMFORMS TO EIA-418.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION MEASURED @ HUB.
4. INCLUDES FLANGE DISTORTION @ OUTER EDGE.
26.40 (1.039)
24.40 (.961)
3
30.40 (1.197)
MAX.
4
Notes:
 Repetitive rating; pulse width limited by max. junction
† Coss eff. is a fixed capacitance that gives the same
charging time as Coss while VDS is rising from 0 to 80%
temperature.
‚ Starting TJ = 25°C, L = 0.31mH, RG = 25Ω, IAS = 45A.
VDSS.
ƒ ISD ≤ 45A, di/dt ≤ 110A/µs, VDD ≤ V(BR)DSS, TJ ≤ 175°C.
‡ Calculated continuous current based on maximum
„ Pulse width ≤ 300µs; duty cycle ≤ 2%.
allowable junction temperature. Package limitation
… Rth(jc) (end of life) is the maximum measured value
current is 75A.
after 1000 temperature cycles from -55 to 150°C and
ˆ When mounted on 1" square PCB ( FR-4 or G-10
is accounted for by the physical wearout of the die attach
Material ). For recommended footprint and soldering
medium in worse case PCB mounting condition of
techniques refer to application note #AN-994.
material (solder/substrate), process and re-flow
temperature.
Data and specifications subject to change without notice.
This product has been designed and qualified for the Industrial market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information.06/04
10
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