INFINEON SAF-C517A-LN

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C517A Data Sheet
Revision History :
01.99
Previous Releases :
08.97 (Original Version)
Page
(previous
version)
Page
(new
version)
Subjects (changes since last revision)
All sections
2
2
2 to 3
All sections
2
2
2
VCC is changed to VDD and ICC is changed to IDD.
5
5
47
48
49
49
5
6
50
50
52
52
49
50
51
53
55
62
-
52
53
54
56
58
65
69
"with wake-up capability through INT0 pin" is removed.
P-LCC-84 package is added under the feature list.
Table 1; deleted and replaced by “Ordering Information” paragraph
“Additional Literature”;deleted.
Figure 4; added.
Table 1; modified, column “P-LCC-84” is added.
"or by a short low pulse at pin P3.2/INT0" is removed.
"Short low pulse at pin P3.2/INT0" is removed.
“Absolute Maximum Ratings” is changed to tabular form.
Fifth line; “During overload conditions ...” changed to “During absolute
maximum rating conditons ...”.
“Operating Conditions” is added.
“VCC = 5 V + 10% ... “ is replaced by “(Operating Conditions apply)”.
Notes (7); modified.
“VCC = 5 V + 10% ... “ is replaced by “(Operating Conditions apply)”.
“VCC = 5 V + 10% ... “ is replaced by “(Operating Conditions apply)”.
First line; “C517A-1RM” is replaced by “C517A-4RM/4RN”
Figure 38; added.
Edition 01.99
This edition was realized using the software system FrameMaker.
Published by : Siemens AG, Semiconductor Group, Product Definition 8-Bit Microcontroller Components,
Balanstraße 73, D-81541 München .
©
Siemens AG 01.99,. All Rights Reserved.
“Enhanced Hooks Technology“ is a trademark and patent of Metalink Corporation, licensed to Siemens.
As far as patents or other rights of third parties are concerned, liability is only assumed for components, not for
applications, processes and circuits implemented within components or assemblies.
The information describes the type of component and shall not be considered as assured characteristics.
Terms of delivery and rights to change design reserved.
For questions on technology, delivery and prices please contact the Semiconductor Group Offices in Germany or
the Siemens Companies and Representatives worldwide.
Due to technical requirements components may contain dangerous substances. For information on the type in
question please contact your nearest Siemens Office, Components Group.
Siemens AG is an approved CECC manufacturer.
Packing
Please use the recycling operators known to you. We can also help you - get in touch with your nearest sales
office. By agreement we will take packing material back, if it is sorted. You must bear the costs of transport.
For packing material that is returned to us unsorted or which we are not obliged to accept, we shall have ti invoice
you for any costs incurred.
C517A
8-Bit CMOS Microcontroller
C517A
Advance Information
• Full upward compatibility with SAB 80C517A/83C517A-5
• Up to 24 MHz external operating frequency
•
•
•
•
•
•
•
•
– 500 ns instruction cycle at 24 MHz operation
Superset of the 8051 architecture with 8 datapointers
On-chip emulation support logic (Enhanced Hooks Technology TM)
32K byte on-chip ROM (with optional ROM protection)
– alternatively up to 64K byte external program memory
Up to 64K byte external data memory
256 byte on-chip RAM
Additional 2K byte on-chip RAM (XRAM)
Seven 8-bit parallel I/O ports
Two input ports for analog/digital input
On-Chip Emulation Support Module
(further features are on next page)
Oscillator
Watchdog
Power
Saving
Modes
CCU
XRAM
2K x 8
Watchdog
Timer
Compare
Timer
T0
CPU
(8 Datapointer)
T2
8 Bit
UART
ROM
32k x 8
Port 8
Port 7
Analog/ Analog/
Digital Digital
Input
Input
Figure 1
C517A Functional Units
Semiconductor Group
1
Port 0
I/O
Port 1
I/O
Port 2
I/O
Port 3
I/O
Port 4
I/O
MDU
T1
10-Bit
A/D Converter
8 Bit
USART
RAM
256 x 8
Port 6
Port 5
I/O
I/O
MCA03317
C517A
Features (continued) :
• Two full duplex serial interfaces (USART)
•
•
•
•
•
•
•
•
– 4 operating modes, fixed or variabie baud rates
– programmable baud rate generators
Four 16-bit timer/counters
– Timer 0 / 1 (C501 compatible)
– Timer 2 for 16-bit reload, compare, or capture functions
– Compare timer for compare/capture functions
Powerful 16-bit compare/capture unt (CCU) with up to 21 high-speed or PWM output channels
and 5 capture inputs
10-bit A/D converter
– 12 multiplexed analog inputs
– Built-in self calibration
Extended watchdog facilities
– 15-bit programmable watchdog timer
– Oscillator watchdog
Power saving modes
– Slow down mode
– Idle mode (can be combined with slow down mode)
– Software power-down mode
– Hardware power-down mode
17 interrupt sources (7 external, 10 internal) selectable at 4 priority levels
P-MQFP-100 and P-LCC-84 packages
Temperature Ranges : SAB-C517A
TA = 0 to 70 °C
SAF-C517A
TA = -40 to 85 °C
TA = -40 to 110 °C
SAH-C517A
Ordering Information
The ordering code for Siemens microcontrollers provides an exact reference to the required
product. This ordering code identifies:
• the derivative itself, i.e. its function set
• the specified temperature range
• the package and the type of delivery.
For the available ordering codes for the C517A please refer to the
„Product Information Microcontrollers“, which summarizes all available microcontroller variants.
Note: The ordering codes for the Mask-ROM versions are defined for each product after
verification of the respective ROM code.
Semiconductor Group
2
C517A
VCC
DD
VSS
Port 7
8-bit Analog/
Digital Input
Port 0
8-Bit Digital I/O
Port 8
4-bit Analog/
Digital Input
XTAL1
XTAL2
ALE
PSEN
EA
RESET
PE/SWD
OWE
RO
HWPD
Port 1
8-Bit Digital I/O
Port 2
8-Bit Digital I/O
C517A
Port 4
8-Bit Digital I/O
Port 5
8-Bit Digital I/O
Port 6
8-Bit Digital I/O
VAREF
VAGND
MCL03318
Figure 2
Logic Symbol
Semiconductor Group
Port 3
8-Bit Digital I/O
3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
C517A
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
P7.7/AIN7
VAGND
VAREF
N.C.
N.C.
N.C.
N.C.
RESET
P4.7/CM7
P4.6/CM6
P4.5/CM5
P4.4/CM4
P4.3/CM3
PE/SWD
P4.2/CM2
P4.1/CM1
P4.0/CM0
VVCC
DD
VSS
RO
P8.3/AIN11
P8.2/AIN10
P8.1/AIN9
P8.0/AIN8
P6.7
P6.6
P6.5
N.C.
N.C.
N.C.
P0.3/AD3
P0.4/AD4
P0.5/AD5
P0.6/AD6
P0.7/AD7
HWPD
CCM7/P5.7
CCM6/P5.6
CCM5/P5.5
CCM4/P5.4
CCM3/P5.3
CCM2/P5.2
CCM1/P5.1
CCM0/P5.0
OWE
ADST/P6.0
RxD1/P6.1
TxD1/P6.2
P6.3
P6.4
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
CC4/INT2/P1.4
N.C.
N.C.
N.C.
N.C.
CC3/INT6/P1.3
CC2/INT5/P1.2
CC1/INT4/P1.1
CC0/INT3/P1.0
V SS
DD
VVCC
XTAL2
XTAL1
P2.0/A8
P2.1/A9
P2.2/A10
P2.3/A11
P2.4/A12
P2.5/A13
P2.6/A14
P2.7/A15
PSEN
ALE
EA
N.C.
P0.0/AD0
P0.1/AD1
N.C.
N.C.
P0.2/AD2
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
P1.5/T2EX
P1.6/CLKOUT
P1.7/T2
P3.7/RD
P3.6/WR
P3.5/T1
P3.4/T0
P3.3/INT1
P3.2/INT0
P3.1/TxD0
P3.0/RxD0
N.C.
N.C.
P7.0/AIN0
P7.1/AIN1
P7.2/AIN2
P7.3/AIN3
P7.4/AIN4
P7.5/AIN5
P7.6/AIN6
C517A
Figure 3
Pin Configuration P-MQFP-100 Package (Top View)
Semiconductor Group
4
MCP03319
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
&$
P1.3/INT6/CC3
P1.2/INT5/CC2
P1.1/INT4/CC1
P1.0/INT3/CC0
VSS
VDD
XTAL2
XTAL1
P2.0/A8
P2.1/A9
P2.2/A10
P2.3/A11
P2.4/A12
P2.5/A13
P2.6/A14
P2.7/A15
PSEN
ALE
EA
P0.0/AD0
P0.1/AD1
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
VAGND
P7.7/AIN7
P7.6/AIN6
P7.5/AIN5
P7.4/AIN4
P7.3/AIN3
P7.2/AIN2
P7.1/AIN1
P7.0/AIN0
P3.0/RxD0
P3.1/TxD0
P3.2/INT0
P3.3/INT1
P3.4/T0
P3.5/T1
P3.6/WR
P3.7/RD
P1.7/T2
P1.6/CLKOUT
P1.5/T2EX
P1.4/INT2/CC4
11
10
9
8
7
6
5
4
3
2
1
84
83
82
81
80
79
78
77
76
75
VAREF
RESET
P4.7/CM7
P4.6/CM6
P4.5/CM5
P4.4/CM4
P4.3/CM3
PE/SWD
P4.2/CM2
P4.1/CM1
P4.0/CM0
VDD
VSS
RO
P8.3/AIN11
P8.2/AIN10
P8.1/AIN9
P8.0/AIN8
P6.7
P6.6
P6.5
C517A
Figure 4
Pin Configuration P-LCC-84 Package (Top View)
Semiconductor Group
5
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
P6.4
P6.3
P6.2/TxD1
P6.1/RxD1
P6.0/ADST
OWE
P5.0/CCM0
P5.1/CCM1
P5.2/CCM2
P5.3/CCM3
P5.4/CCM4
P5.5/CCM5
P5.6/CCM6
P5.7/CCM7
HWPD
P0.7/AD7
P0.6/AD6
P0.5/AD5
P0.4/AD4
P0.3/AD3
P0.2/AD2
C517A
Table 1
Pin Definitions and Functions
6\PERO
3LQ1XPEHU
304)3
P1.0 - P1.7
,2
)XQFWLRQ
I/O
Port 1
is an 8-bit quasi-bidirectional I/O port with
internal pullup resistors. Port 1 pins that
have 1’s written to them are pulled high by
the internal pullup resistors, and in that state
can be used as inputs. As inputs, port 1 pins
being externally pulled low will source
current (I IL, in the DC characteristics)
because of the internal pullup resistors. The
port is used for the low-order address byte
during program verification. Port 1 also
contains the interrupt, timer, clock, capture
and compare pins that are used by various
options. The output latch corresponding to a
secondary function must be programmed to
a one (1) for that function to operate (except
when used for the compare functions). The
secondary functions are assigned to the port
1 pins as follows :
P1.0 / INT3 / CC0 Interrupt 3 input /
compare 0 output /
capture 0 input
P1.1 / INT4 / CC1 Interrupt 4 input /
compare 1 output /
capture 1 input
P1.2 / INT5 / CC2 Interrupt 5 input /
compare 2 output /
capture 2 input
P1.3 / INT6 / CC3 Interrupt 6 input /
compare 3 output /
capture 3 input
P1.4 / INT2 / CC4 Interrupt 2 input /
compare 4 output /
capture 4 input
P1.5 / T2EX
Timer 2 external
reload / trigger input
P1.6 / CLKOUT
System clock output
P1.7 / T2
Counter 2 input
3/&&
9 - 6, 1,
100 - 98
36 - 29
9
36
8
35
7
34
6
33
1
32
100
31
99
98
30
29
*) I = Input,
O = Output
Semiconductor Group
6
C517A
Table 1
Pin Definitions and Functions
6\PERO
(cont’d)
3LQ1XPEHU
304)3
,2
)XQFWLRQ
3/&&
VSS
10, 62
37, 83
–
Ground (0V)
during normal, idle, and power down
operation.
VDD
11, 63
38, 84
–
Supply voltage
during normal, idle, and power down mode.
XTAL2
12
39
–
XTAL2
is the input to the inverting oscillator
amplifier and input to the internal clock
generator circuits.
To drive the device from an external clock
source, XTAL2 should be driven, while
XTAL1 is left unconnected. Minimum and
maximum high and low times as well as rise/
fall times specified in the AC characteristics
must be observed.
XTAL1
13
40
–
XTAL1
is the output of the inverting oscillator
amplifier. This pin is used for the oscillator
operation with crystal or ceramic resonator.
P2.0 - P2.7
14 - 21
41 - 48
I/O
Port 2
is an 8-bit quasi-bidirectional I/O port with
internal pullup resistors. Port 2 pins that
have 1's written to them are pulled high by
the internal pullup resistors, and in that state
can be used as inputs. As inputs, port 2 pins
being externally pulled low will source
current (I IL, in the DC characteristics)
because of the internal pullup resistors.
Port 2 emits the high-order address byte
during fetches from external program
memory and during accesses to external
data memory that use 16-bit addresses
(MOVX @DPTR). In this application it uses
strong internal pullup resistors when issuing
1's. During accesses to external data
memory that use 8-bit addresses
(MOVX @Ri), port 2 issues the contents of
the P2 special function register.
*) I = Input
O = Output
Semiconductor Group
7
C517A
Table 1
Pin Definitions and Functions
6\PERO
(cont’d)
3LQ1XPEHU
304)3
,2
)XQFWLRQ
3/&&
PSEN
22
49
O
The Program Store Enable
output is a control signal that enables the
external program memory to the bus during
external fetch operations. It is activated
every six oscillator periods except during
external data memory accesses. The signal
remains high during internal program
execution.
ALE
23
50
O
The Address Latch enable
output is used for latching the address into
external memory during normal operation. It
is activated every six oscillator periods
except during an external data memory
access.
EA
24
51
I
External Access Enable
When held high, the C517A executes
instructions from the internal ROM as long
as the PC is less than 8000H. When held
low, the C517A fetches all instructions from
external program memory. For the C517A-L
this pin must be tied low. For the C517A-4R,
if the device is protected (see section 4.6 in
the User Manual) then this pin is only
latched during reset.
P0.0 - P0.7
26, 27,
30 - 35
52 - 59
I/O
Port 0
is an 8-bit open-drain bidirectional I/O port.
Port 0 pins that have 1’s written to them
float, and in that state can be used as highimpedance inputs. Port 0 is also the
multiplexed low-order address and data bus
during accesses to external program and
data memory. In this application it uses
strong internal pullup resistors when issuing
1’s. Port 0 also outputs the code bytes
during program verification in the C517A4R. External pullup resistors are required
during program verification.
*) I = Input
O = Output
Semiconductor Group
8
C517A
Table 1
Pin Definitions and Functions
6\PERO
(cont’d)
3LQ1XPEHU
304)3
,2
)XQFWLRQ
3/&&
HWPD
36
60
I
Hardware Power Down
A low level on this pin for the duration of one
machine cycle while the oscillator is running
resets the C517A. A low level for a longer
period will force the part into hardware
power down mode with the pins floating.
There is no internal pullup resistor
connected to this pin.
P5.0 - P5.7
44 - 37
68 - 61
I/O
Port 5
is a quasi-bidirectional I/O port with internal
pull-up resistors. Port 5 pins that have 1 s
written to them are pulled high by the
internal pull-up resistors, and in that state
can be used as inputs. As inputs, port 5 pins
being externally pulled low will source
current (IIL, in the DC characteristics)
because of the internal pull-up resistors.
This port also serves the alternate function
"Concurrent Compare" and "Set/Reset
Compare". The secondary functions are
assigned to the port 5 pins as follows:
CCM0 to CCM7 P5.0 to P5.7 :
concurrent compare or
Set/Reset lines
OWE
45
69
I
Oscillator Watchdog Enable
A high level on this pin enables the oscillator
watchdog. When left unconnected this pin is
pulled high by a weak internal pull-up
resisitor. The logic level at OWE should not
be changed during normal operation. When
held at low level the oscillator watchdog
function is turned off. During hardware
power down the pullup resistor is switched
off.
*) I = Input
O = Output
Semiconductor Group
9
C517A
Table 1
Pin Definitions and Functions
6\PERO
3LQ1XPEHU
304)3
P6.0 - P6.7
(cont’d)
,2
)XQFWLRQ
I/O
Port 6
is a quasi-bidirectional I/O port with internal
pull-up resistors. Port 6 pins that have 1 s
written to them are pulled high by the
internal pull-up resistors, and in that state
can be used as inputs. As inputs, port 6 pins
being externally pulled low will source
current (I IL, in the DC characteristics)
because of the internal pull-up resistors.
Port 6 also contains the external A/D
converter start control pin and the transmit
and receive pins for the serial interface 1.
The output latch corresponding to a
secondary function must be programmed to
a one (1) for that function to operate.
The secondary functions are assigned to the
pins of port 6, as follows :
external A/D converter
P6.0 ADST
start pin
P6.1 RxD1
receiver data input of serial
interface 1
P6.2 TxD1
transmitter data input of
serial interface 1
3/&&
46 - 50,
54 - 56
70 - 77
46
70
47
71
48
72
P8.0 - P8.3
57 - 60
78 - 81
I
Port 8
is a 4-bit unidirectional input port. Port pins
can be used for digital input, if voltage levels
meet the specified input high/low voltages,
and for the higher 4-bit of the multiplexed
analog inputs of the A/D converter,
simultaneously.
P8.0 - P8.3
AIN8 - AIN11 analog
input 8 - 11
RO
61
82
O
Reset Output
This pin outputs the internally synchronized
reset request signal. This signal may be
generated by an external hardware reset, a
watchdog timer reset or an oscillator
watchdog reset. The RO output signal is
active low.
*) I = Input
O = Output
Semiconductor Group
10
C517A
Table 1
Pin Definitions and Functions
6\PERO
(cont’d)
3LQ1XPEHU
304)3
,2
)XQFWLRQ
3/&&
P4.0 - P4.7
64 - 66,
68 - 72
1 - 3,
5-9
I/O
Port 4
is an 8-bit quasi-bidirectional I/O port with
internal pull-up resistors. Port 4 pins that
have 1’s written to them are pulled high by
the internal pull-up resistors, and in that
state can be used as inputs. As inputs, port
4 pins being externally pulled low will source
current (I IL, in the DC characteristics)
because of the internal pull-up resistors.
Port 4 also serves as alternate compare
functions. The output latch corresponding to
a secondary function must be programmed
to a one (1) for that function to operate. The
secondary functions are assigned to the
pins of port 4 as follows :
P4.0 - P4.7 CM0 - CM7 Compare
channel 0 - 7
PE/SWD
67
4
I
Power saving mode enable / Start
watchdog timer
A low level at this pin allows the software to
enter the power saving modes (idle mode,
slow down mode, and power down mode).
In case the low level is also seen during
reset, the watchdog timer function is off on
default.
Usage of the software controlled power
saving modes is blocked, when this pin is
held at high level. A high level during reset
performs an automatic start of the watchdog
timer immediately after reset.
When left unconnected this pin is pulled
high by a weak internal pull-up resistor.
During hardware power down the pullup
resisitor is switched off.
*) I = Input
O = Output
Semiconductor Group
11
C517A
Table 1
Pin Definitions and Functions
6\PERO
3LQ1XPEHU
304)3
P3.0 - P3.7
(cont’d)
,2
)XQFWLRQ
I/O
Port 3
is an 8-bit quasi-bidirectional I/O port with
internal pullup resistors. Port 3 pins that
have 1’s written to them are pulled high by
the internal pullup resistors, and in that state
can be used as inputs. As inputs, port 3 pins
being externally pulled low will source
current (I IL, in the DC characteristics)
because of the internal pullup resistors. Port
3 also contains the interrupt, timer, serial
port and external memory strobe pins that
are used by various options. The output
latch corresponding to a secondary function
must be programmed to a one (1) for that
function to operate. The secondary
functions are assigned to the pins of port 3,
as follows:
P3.0 / RxD0
Receiver data input
(asynch.) or data
input/output (synch.)of
serial interface 0
P3.1 / TxD0
Transmitter data output
(asynch.) or clock output
(synch.) of serial interface
0
External interrupt 0 input /
P3.2 / INT0
timer 0 gate control input
External interrupt 1 input /
P3.3 / INT1
timer 1 gate control input
P3.4 / T0
Timer 0 counter input
P3.5 / T1
Timer 1 counter input
WR control output; latches
P3.6 / WR
the data byte from port 0
into the external data
memory
RD control output; enables
P3.7 / RD
the external data memory
3/&&
90 - 97
21 - 28
90
21
91
22
92
23
93
24
94
95
96
25
26
27
97
28
*) I = Input
O = Output
Semiconductor Group
12
C517A
Table 1
Pin Definitions and Functions
6\PERO
(cont’d)
3LQ1XPEHU
304)3
,2
)XQFWLRQ
3/&&
RESET
73
10
I
RESET
A low level on this pin for the duration of two
machine cycles while the oscillator is
running resets the C517A. A small internal
pullup resistor permits power-on reset using
only a capacitor connected to VSS .
VAREF
78
11
–
Reference voltage for the A/D converter
VAGND
79
12
–
Reference ground for the A/D converter
P7.0 - P7.7
87 - 80
20-13
I
Port 7
is an 8-bit unidirectional input port. Port pins
can be used for digital input, if voltage levels
meet the specified input high/low voltages,
and for the lower 8-bit of the multiplexed
analog inputs of the A/D converter,
simultaneously.
P7.0 - P7.7
AIN0 - AIN7
analog
input0 - 7
N.C.
2 - 5, 25,
28, 29,
51 - 53,
74 - 77
88, 89
–
–
Not connected
These pins of the P-MQFP-100 package
must not be connected.
*) I = Input
O = Output
Semiconductor Group
13
C517A
Oscillator Watchdog
RAM
256 x 8
XTAL1
XRAM
2k x 8
ROM
32k x 8
OSC & Timing
XTAL2
ALE
CPU
PSEN
8 Datapointer
EA
PE/SWD
RESET
Programmable
Watchdog Timer
HWPD
Timer 0
Emulation
Support
Logic
Port 0
Port 0
8-Bit Digital I/O
Port 1
Port 1
8-Bit Digital I/O
Port 2
Port 2
8-Bit Digital I/O
Port 3
Port 3
8-Bit Digital I/O
Port 4
Port 4
8-Bit Digital I/O
Port 5
Port 5
8-Bit Digital I/O
Interrupt Unit
Port 6
Port 6
8-Bit Digital I/O
A/D Converter
10 Bit
Port 7
Port 7
8-Bit Analog/
Digital Input
Port 8
Port 8
4-Bit Analog/
Digital Input
RO
OWE
Timer 1
Timer 2
Capture
Compare Unit
Compare Timer
Serial Channel 0
Programmable
Baud Rate Generator
Serial Channel 1
Programmable
Baud Rate Generator
VAREF
VAGND
S&H
Analog
MUX
C517A
MCB03320
Figure 5
Block Diagram of the C517A
Semiconductor Group
14
C517A
CPU
The C517A is efficient both as a controller and as an arithmetic processor. It has extensive facilities
for binary and BCD arithmetic and excels in its bit-handling capabilities. Efficient use of program
memory results from an instruction set consisting of 44 % one-byte, 41 % two-byte, and 15% threebyte instructions. With a 12 MHz crystal, 58% of the instructions are executed in 1µs (24 MHz : 500
ns).
Special Function Register PSW (Address D0H)
Reset Value : 00H
Bit No. MSB
D0H
LSB
D7H
D6H
D5H
D4H
D3H
D2H
D1H
D0H
CY
AC
F0
RS1
RS0
OV
F1
P
Bit
Function
CY
Carry Flag
Used by arithmetic instruction.
AC
Auxiliary Carry Flag
Used by instructions which execute BCD operations.
F0
General Purpose Flag
RS1
RS0
Register Bank select control bits
These bits are used to select one of the four register banks.
PSW
RS1
RS0
Function
0
0
Bank 0 selected, data address 00H-07H
0
1
Bank 1 selected, data address 08H-0FH
1
0
Bank 2 selected, data address 10H-17H
1
1
Bank 3 selected, data address 18H-1FH
OV
Overflow Flag
Used by arithmetic instruction.
F1
General Purpose Flag
P
Parity Flag
Set/cleared by hardware after each instruction to indicate an odd/even
number of "one" bits in the accumulator, i.e. even parity.
Semiconductor Group
15
C517A
Memory Organization
The C517A CPU manipulates operands in the following five address spaces:
–
–
–
–
–
up to 64 Kbyte of program memory (32K on-chip program memory for C517A-4R)
up to 64 Kbyte of external data memory
256 bytes of internal data memory
2K bytes of internal XRAM data memory
a 128 byte special function register area
Figure 6 illustrates the memory address spaces of the C517A.
FFFF H
FFFF H
int.
(XMAP0 = 0)
ext.
(XMAP0 = 1)
ext.
F800 H
8000 H
F7FF H
FF H
80 H
ext.
ext.
(EA = 0)
Direct
Address
Internal
RAM
7FFF H
int.
(EA = 1)
Indirect
Address
Special
Function
Regs.
FF H
80 H
7F H
Internal
RAM
0000 H
"Code Space"
0000 H
"Data Space"
00 H
"Internal Data Space"
MCB03321
Figure 6
C517A Memory Map
Semiconductor Group
16
C517A
Reset and System Clock
The reset input is an active low input at pin RESET. Since the reset is synchronized internally, the
RESET pin must be held low for at least two machine cycles (24 oscillator periods) while the
oscillator is running. A pullup resistor is internally connected to VDD to allow a power-up reset with
an external capacitor only. An automatic reset can be obtained when VDD is applied by connecting
the RESET pin to VSS via a capacitor. Figure 7 shows the possible reset circuitries.
a)
b)
&
+
RESET
RESET
C517A
C517A
c)
+
RESET
C517A
MCS03323
Figure 7
Reset Circuitries
Semiconductor Group
17
C517A
Figure 8 shows the recommended oscillator circiutries for crystal and external clock operation.
Crystal Oscillator Mode
Driving from External Source
C
N.C.
XTAL1
3.5 - 24
MHz
External Oscillator
Signal
XTAL2
XTAL1
XTAL2
C
Crystal Mode:
C = 20 pF 10 pF
(Incl. Stray Capacitance)
Figure 8
Recommended Oscillator Circuitries
Semiconductor Group
18
MCS03245
C517A
Enhanced Hooks Emulation Concept
The Enhanced Hooks Emulation Concept of the C500 microcontroller family is a new, innovative
way to control the execution of C500 MCUs and to gain extensive information on the internal
operation of the controllers. Emulation of on-chip ROM based programs is possible, too.
Each production chip has built-in logic for the supprt of the Enhanced Hooks Emulation Concept.
Therefore, no costly bond-out chips are necessary for emulation. This also ensure that emulation
and production chips are identical.
The Enhanced Hooks TechnologyTM 1), which requires embedded logic in the C500 allows the C500
together with an EH-IC to function similar to a bond-out chip. This simplifies the design and reduces
costs of an ICE-system. ICE-systems using an EH-IC and a compatible C500 are able to emulate
all operating modes of the different versions of the C500 microcontrollers. This includes emulation
of ROM, ROM with code rollover and ROMless modes of operation. It is also able to operate in
single step mode and to read the SFRs after a break.
ICE-System interface
to emulation hardware
RESET
EA
ALE
PSEN
SYSCON
PCON
TCON
C500
MCU
opt.
I/O Ports
RSYSCON
RPCON
RTCON
Enhanced Hooks
Interface Circuit
Port 0
Port 2
Port 3
EH-IC
RPORT RPORT
2
0
TEA TALE TPSEN
Port 1
Target System Interface
MCS03254
Figure 9
Basic C500 MCU Enhanced Hooks Concept Configuration
Port 0, port 2 and some of the control lines of the C500 based MCU are used by Enhanced Hooks
Emulation Concept to control the operation of the device during emulation and to transfer
informations about the programm execution and data transfer between the external emulation
hardware (ICE-system) and the C500 MCU.
1 “Enhanced Hooks Technology“ is a trademark and patent of Metalink Corporation licensed to Siemens.
Semiconductor Group
19
C517A
Special Function Registers
The registers, except the program counter and the four general purpose register banks, reside in
the special function register area.
The 94 special function registers (SFRs) in the standard and mapped SFR area include pointers
and registers that provide an interface between the CPU and the other on-chip peripherals. All SFRs
with addresses where address bits 0-2 are 0 (e
.g. 80H, 88H, 90H, 98H, ..., F8H, FFH) are bitaddressable. The SFRs of the C517A are listed in
table 2 and table 3. In table 2 they are organized in groups which refer to the functional blocks of
the C517A. Table 3 illustrates the contents of the SFRs in numeric order of their addresses.
Semiconductor Group
20
C517A
Table 2
Special Function Registers - Functional Blocks
Block
Symbol
Name
Address
Contents after
Reset
CPU
ACC
B
DPH
DPL
DPSEL
PSW
SP
Accumulator
B-Register
Data Pointer, High Byte
Data Pointer, Low Byte
Data Pointer Select Register
Program Status Word Register
Stack Pointer
E0H 1)
F0H 1)
83H
82H
92H
D0H 1)
81H
00H
00H
00H
00H
XXXX X000B 3)
00H
07H
A/D Converter Control Register 0
A/D Converter Control Register 1
A/D Converter Data Register, High Byte
A/D Converter Data Register, Low Byte
D8H 1)
DCH
D9H
DAH
00H
0XXX 0000B 3)
00H
00XX XXXXB 3
A/DADCON0 2)
Converter ADCON1
ADDATH
ADDATL
Interrupt
System
IEN0 2)
IEN1 2)
IEN2
IP0 2)
IP1
IRCON0 2)
IRCON1
TCON 2)
T2CON 2)
S0CON 2)
CTCON 2)
Interrupt Enable Register 0
Interrupt Enable Register 1
Interrupt Enable Register 2
Interrupt Priority Register 0
Interrupt Priority Register 1
Interrupt Request Control Register 0
Interrupt Request Control Register 1
Timer 0/1 Control Register
Timer 2 Control Register
Serial Channel 0 Control Register
Compare Timer Control Register
A8H 1)
B8H 1)
9AH
A9H
B9H
C0H 1)
D1H
88H 1)
C8H 1)
98H 1)
E1H
00H
00H
XX00 00X0B 3)
00H
XX00 0000B 3)
00H
00H
00H
00H
00H
0X00 0000B 3)
MUL/DIV
Unit
ARCON
MD0
MD1
MD2
MD3
MD4
MD5
Arithmetic Control Register
Multiplication/Division Register 0
Multiplication/Division Register 1
Multiplication/Division Register 2
Multiplication/Division Register 3
Multiplication/Division Register 4
Multiplication/Division Register 5
EFH
E9H
EAH
EBH
ECH
EDH
EEH
0XXXXXXXB 3)
XXH 3)
XXH 3)
XXH 3)
XXH 3)
XXH 3)
XXH 3)
Timer 0 /
Timer 1
TCON
TH0
TH1
TL0
TL1
TMOD
Timer 0/1 Control Register
Timer 0, High Byte
Timer 1, High Byte
Timer 0, Low Byte
Timer 1, Low Byte
Timer Mode Register
88H 1)
8CH
8DH
8AH
8BH
89H
00H
00H
00H
00H
00H
00H
2)
1) Bit-addressable special function registers
2) This special function register is listed repeatedly since some bits of it also belong to other functional blocks.
3) “X“ means that the value is undefined and the location is reserved
Semiconductor Group
21
C517A
Table 2
Special Function Registers - Functional Blocks (cont’d)
Block
Symbol
Compare/
Capture
Unit
(CCU)
Timer 2
CCEN
CC4EN
CCH1
CCH2
CCH3
CCH4
CCL1
CCL2
CCL3
CCL4
CMEN
CMH0
CMH1
CMH2
CMH3
CMH4
CMH5
CMH6
CMH7
CML0
CML1
CML2
CML3
CML4
CML5
CML6
CML7
CMSEL
CRCH
CRCL
Name
Compare/Capture Enable Register
Compare/Capture 4 Enable Register
Compare/Capture Register 1, High Byte
Compare/Capture Register 2, High Byte
Compare/Capture Register 3, High Byte
Compare/Capture Register 4, High Byte
Compare/Capture Register 1, Low Byte
Compare/Capture Register 2, Low Byte
Compare/Capture Register 3, Low Byte
Compare/Capture Register 4, Low Byte
Compare Enable Register
Compare Register 0, High Byte
Compare Register 1, High Byte
Compare Register 2, High Byte
Compare Register 3, High Byte
Compare Register 4, High Byte
Compare Register 5, High Byte
Compare Register 6, High Byte
Compare Register 7, High Byte
Compare Register 0, Low Byte
Compare Register 1, Low Byte
Compare Register 2, Low Byte
Compare Register 3, Low Byte
Compare Register 4, Low Byte
Compare Register 5, Low Byte
Compare Register 6, Low Byte
Compare Register 7, Low Byte
Compare Input Select
Comp./Rel./Capt. Register High Byte
Comp./Rel./Capt. Register Low Byte
COMSETL Compare Set Register Low Byte
COMSETH Compare Set Register, High Byte
COMCLRL Compare Clear Register, Low Byte
COMCLRH Compare Clear Register, High Byte
Compare Set Mask Register
SETMSK
CLRMSK Compare Clear Mask Register
CTCON 2) Compare Timer Control Register
Compare Timer Rel. Register, High Byte
CTRELH
Compare Timer Rel. Register, Low Byte
CTRELL
Timer 2, High Byte
TH2
Timer 2, Low Byte
TL2
T2CON 2) Timer 2 Control Register
IRCON0 2) Interrupt Request Control Register 0
Address
Contents after
Reset
C1H
C9H
C3H
C5H
C7H
CFH
C2H
C4H
C6H
CEH
F6H
D3H
D5H
D7H
E3H
E5H
E7H
F3H
F5H
D2H
D4H
D6H
E2H
E4H
E6H
F2H
F4H
F7H
CBH
CAH
A1H
A2H
A3H
A4H
A5H
A6H
E1H
DFH
DEH
CDH
CCH
C8H 1)
C0H 1)
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
0X00 0000B 3)
00H
00H
00H
00H
00H
00H
1) Bit-addressable special function registers
2) This special function register is listed repeatedly since some bits of it also belong to other functional blocks.
3) “X“ means that the value is undefined and the location is reserved
Semiconductor Group
22
C517A
Table 2
Special Function Registers - Functional Blocks (cont’d)
Block
Symbol
Name
Address
Contents after
Reset
Ports
P0
P1
P2
P3
P4
P5
P6
P7
P8
Port 0
Port 1
Port 2
Port 3
Port 4
Port 5
Port 6
Port 7, Analog/Digital Input
Port 8, Analog/Digital Input, 4-bit
80H 1)
90H 1)
A0H 1)
B0H 1)
E8H 1)
F8H 1)
FAH
DBH
DDH
FFH
FFH
FFH
FFH
FFH
FFH
FFH
–
–
XRAM
XPAGE
91H
00H
SYSCON 2)
Page Address Register for Extended
On-Chip RAM
System/XRAM Control Register
B1H
XXXX XX01B 3)
ADCON0 2)
PCON 2)
S0BUF
S0CON
S0RELL
S0RELH
S1BUF
S1CON
S1RELL
S1RELH
A/D Converter Control Register
Power Control Register
Serial Channel 0 Buffer Register
Serial Channel 0 Control Register
Serial Channel 0 Reload Reg., Low Byte
Serial Channel 0 Reload Reg., High Byte
Serial Channel 1 Buffer Register
Serial Channel 1 Control Register
Serial Channel 1 Reload Reg., Low Byte
Serial Channel 1 Reload Reg., High Byte
D8H 1)
87H
99H
98H 1)
AAH
BAH
9CH
9BH
9DH
BBH
00H
00H
XXH 3)
00H
D9H
XXXX XX11B 3)
XXH 3)
0X00 0000B 3)
00H
XXXX XX11B 3)
Watchdog IEN0 2)
IEN1 2)
IP0 2)
WDTREL
Interrupt Enable Register 0
Interrupt Enable Register 1
Interrupt Priority Register 0
Watchdog Timer Reload Register
A8H1)
B8H 1)
A9H
86H
00H
00H
00H
00H
Pow. Sav. PCON 2)
Modes
Power Control Register
87H
00H
Serial
Channels
1) Bit-addressable special function registers
2) This special function register is listed repeatedly since some bits of it also belong to other functional blocks.
3) “X“ means that the value is undefined and the location is reserved.
Semiconductor Group
23
C517A
Table 3
Contents of the SFRs, SFRs in numeric order of their addresses
Addr Register Content Bit 7
after
Reset1)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
80H 2) P0
81H SP
FFH
.7
.6
.5
.4
.3
.2
.1
.0
07H
.7
.6
.5
.4
.3
.2
.1
.0
82H
83H
DPL
00H
.7
.6
.5
.4
.3
.2
.1
.0
DPH
00H
.7
.6
.5
.4
.3
.2
.1
.0
83H
WDTREL 00H
WDTPSEL
.6
.5
.4
.3
.2
.1
.0
87H PCON
88H 2) TCON
00H
SMOD PDS
IDLS
SD
GF1
GF0
PDE
IDLE
00H
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
89H
8AH
TMOD
00H
GATE
C/T
M1
M0
GATE
C/T
M1
M0
TL0
00H
.7
.6
.5
.4
.3
.2
.1
.0
8BH
TL1
00H
.7
.6
.5
.4
.3
.2
.1
.0
8CH
8DH
TH0
00H
.7
.6
.5
.4
.3
.2
.1
.0
TH1
00H
.7
.6
.5
.4
.3
.2
.1
.0
90H 2) P1
FFH
T2
CLKOUT
T2EX
INT2
INT6
INT5
INT4
INT3
91H
92H
XPAGE
00H
.7
.6
.5
.4
.3
.2
.1
.0
DPSEL
XXXXX000B
00H
–
–
–
–
–
.2
.1
.0
SM0
SM1
SM20
REN0
TB80
RB80
TI0
RI0
XXH
.7
.6
.5
.4
.3
.2
.1
.0
98H 2) S0CON
99H S0BUF
9AH
IEN2
XX0000X0B
–
–
ECR
ECS
ECT
ECMP
–
ES1
9BH
S1CON
SM
–
SM21
REN1
TB81
RB81
TI1
RI1
9CH
9DH
S1BUF
0X000000B
XXH
.7
.6
.5
.4
.3
.2
.1
.0
00H
FFH
.7
.6
.5
.4
.3
.2
.1
.0
.7
.6
.5
.4
.3
.2
.1
.0
.7
.6
.5
.4
.3
.2
.1
.0
.7
.6
.5
.4
.3
.2
.1
.0
.3
.2
.1
.0
S1RELL
A0H2) P2
A1H COMSETL 00H
A2H COMSETH 00H
A3H
COMCLRL 00H
.7
.6
.5
.4
1) X means that the value is undefined and the location is reserved
2) Shaded registers are bit-addressable special function registers
Semiconductor Group
24
C517A
Table 3
Contents of the SFRs, SFRs in numeric order of their addresses (cont’d)
Addr Register Content Bit 7
after
Reset1)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
A4H
A5H
COMCLRH 00H
.7
.6
.5
.4
.3
.2
.1
.0
SETMSK 00H
.7
.6
.5
.4
.3
.2
.1
.0
A6H CLRMSK 00H
A8H2) IEN0
00H
A9H IP0
00H
.7
.6
.5
.4
.3
.2
.1
.0
EAL
WDT
ET2
ES0
ET1
EX1
ET0
EX0
OWDS WDTS .5
.4
.3
.2
.1
.0
AAH S0RELL
B0H2) P3
D9H
.7
.6
.5
.4
.3
.2
.1
.0
FFH
RD
WR
T1
T0
INT1
INT0
TxD0
RxD0
–
–
–
–
–
–
XMAP1 XMAP0
B1H
SYSCON XXXXXX01B
B8H2) IEN1
B9H IP1
BAH S0RELH
00H
EXEN2 SWDT EX6
EX5
EX4
EX3
EX2
EADC
XX000000B
XXXXXX11B
–
–
.5
.4
.3
.2
.1
.0
–
–
–
–
–
–
.1
.0
BBH S1RELH
XXXXXX11B
–
–
–
–
–
–
.1
.0
C0H
IRCON0
00H
EXF2
TF2
IEX6
IEX5
IEX4
IEX3
IEX2
IADC
C1H
CCEN
00H
COCA
H3
COCA
L3
COCA
H2
COCA
L2
COCA
H1
COCA
L1
COCA
H0
COCA
L0
C2H
C3H
CCL1
00H
.7
.6
.5
.4
.3
.2
.1
.0
CCH1
00H
.7
.6
.5
.4
.3
.2
.1
.0
C4H
C5H
CCL2
00H
.7
.6
.5
.4
.3
.2
.1
.0
CCH2
00H
.7
.6
.5
.4
.3
.2
.1
.0
C6H
C7H
CCL3
00H
.7
.6
.5
.4
.3
.2
.1
.0
CCH3
00H
.7
.6
.5
.4
.3
.2
.1
.0
C8H
T2CON
00H
T2PS
I3FR
I2FR
T2R1
T2R0
T2CM
T2I1
T2I0
CC4EN
00H
2)
2)
C9H
COCO COCO COCO COCO COCO COCA
EN1
N2
N1
N0
EN0
H4
1) X means that the value is undefined and the location is reserved
2) Shaded registers are bit-addressable special function registers
Semiconductor Group
25
COCA COMO
L4
C517A
Table 3
Contents of the SFRs, SFRs in numeric order of their addresses (cont’d)
Addr Register Content Bit 7
after
Reset1)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CAH CRCL
CBH CRCH
CCH TL2
CDH TH2
00H
.7
.6
.5
.4
.3
.2
.1
.0
00H
.7
.6
.5
.4
.3
.2
.1
.0
00H
.7
.6
.5
.4
.3
.2
.1
.0
00H
.7
.6
.5
.4
.3
.2
.1
.0
CEH CCL4
CFH CCH4
00H
.7
.6
.5
.4
.3
.2
.1
.0
00H
.7
.6
.5
.4
.3
.2
.1
.0
D0H
PSW
00H
CY
AC
F0
RS1
RS0
OV
F1
P
D1H
D2H
IRCON1
00H
ICMP7 ICMP6 ICMP5 ICMP4 ICMP3 ICMP2 ICMP1 ICMP0
CML0
00H
.7
.6
.5
.4
.3
.2
.1
.0
D3H
D4H
CMH0
00H
.7
.6
.5
.4
.3
.2
.1
.0
CML1
00H
.7
.6
.5
.4
.3
.2
.1
.0
D5H
D6H
CMH1
00H
.7
.6
.5
.4
.3
.2
.1
.0
CML2
00H
.7
.6
.5
.4
.3
.2
.1
.0
D7H
D8H
CMH2
00H
.7
.6
.5
.4
.3
.2
.1
.0
BD
CLK
ADEX
BSY
ADM
MX2
MX1
MX0
.9
.8
.7
.6
.5
.4
.3
.2
.1
.0
–
–
–
–
–
–
DBH P7
–
DCH ADCON1 0XXX0000B
.7
.6
.5
.4
.3
.2
.1
.0
ADCL
–
–
–
MX3
MX2
MX1
MX0
DDH P8
DEH CTRELL
–
–
–
–
.3
.2
.1
.0
.7
.6
.5
.4
.3
.2
.1
.0
2)
2)
ADCON0 00H
D9H ADDATH 00H
DAH ADDATL 00XXXXXXB
–
00H
DFH CTRELH 00H
E0H2) ACC
00H
.7
.6
.5
.4
.3
.2
.1
.0
.7
.6
.5
.4
.3
.2
.1
.0
E1H
CTCON
0X00.
0000B
T2PS1 –
ICR
ICS
CTF
CLK2
CLK1
CLK0
E2H
CML3
00H
.7
.5
.4
.3
.2
.1
.0
.6
1) X means that the value is undefined and the location is reserved
2) Shaded registers are bit-addressable special function registers
Semiconductor Group
26
C517A
Table 3
Contents of the SFRs, SFRs in numeric order of their addresses (cont’d)
Addr Register Content Bit 7
after
Reset1)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
E3H
E4H
CMH3
00H
.7
.6
.5
.4
.3
.2
.1
.0
CML4
00H
.7
.6
.5
.4
.3
.2
.1
.0
CMH4
00H
.7
.6
.5
.4
.3
.2
.1
.0
CML5
00H
.7
.6
.5
.4
.3
.2
.1
.0
E7H CMH5
E8H2) P4
00H
.7
.6
.5
.4
.3
.2
.1
.0
FFH
CM7
CM6
CM5
CM4
CM3
CM2
CM1
CM0
XXH
.7
.6
.5
.4
.3
.2
.1
.0
XXH
.7
.6
.5
.4
.3
.2
.1
.0
XXH
.7
.6
.5
.4
.3
.2
.1
.0
XXH
.7
.6
.5
.4
.3
.2
.1
.0
XXH
.7
.6
.5
.4
.3
.2
.1
.0
XXH
.7
.6
.5
.4
.3
.2
.1
.0
0XXX.
XXXXB
00H
MDEF
MDOV SLR
SC.4
SC.3
SC.2
SC.1
SC.0
.7
.6
.5
.4
.3
.2
.1
.0
00H
.7
.6
.5
.4
.3
.2
.1
.0
E5H
E6H
E9H MD0
EAH MD1
EBH MD2
ECH MD3
EDH MD4
EEH MD5
EFH
ARCON
F0H2) B
F2H CML6
F3H
F4H
CMH6
00H
.7
.6
.5
.4
.3
.2
.1
.0
CML7
00H
.7
.6
.5
.4
.3
.2
.1
.0
F5H
F6H
CMH7
00H
.7
.6
.5
.4
.3
.2
.1
.0
CMEN
00H
.7
.6
.5
.4
.3
.2
.1
.0
F7H CMSEL
F8H2) P5
00H
.7
.6
.5
.4
.3
.2
.1
.0
FFH
CCM7
CCM6
CCM5
CCM4
CCM3
CCM2
CCM1
CCM0
FAH
FFH
.7
.6
.5
.4
.3
TxD1
RxD1
ADST
P6
1) X means that the value is undefined and the location is reserved
2) Shaded registers are bit-addressable special function registers
Semiconductor Group
27
C517A
Digital I/O Ports
The C517A allows for digital I/O on 56 lines grouped into 7 bidirectional 8-bit ports. Each port bit
consists of a latch, an output driver and an input buffer. Read and write accesses to the I/O ports P0
through P6 are performed via their corresponding special function registers P0 to P6.
The output drivers of port 0 and 2 and the input buffers of port 0 are also used for accessing external
memory. In this application, port 0 outputs the low byte of the external memory address, timemultiplexed with the byte being written or read. Port 2 outputs the high byte of the external memory
address when the address is 16 bits wide. Otherwise, the port 2 pins continue emitting the P2 SFR
contents.
Analog Input Ports
Ports 7 (8-bit) and 8 (4-bit) are input ports only and provide two functions. When used as digital
inputs, the corresponding SFR P7 and P8 contains the digital value applied to the port 7/8 lines.
When used for analog inputs the desired analog channel is selected by a four-bit field in SFR
ADCON1. Of course, it makes no sense to output a value to these input-only ports by writing to the
SFR P7 or P8. This will have no effect.
lf a digital value is to be read, the voltage levels are to be held within the input voltage specifications
(VIL/VIH). Since P7 and P8 are not bit-addressable, all input lines of P7 and P8 are read at the same
time by byte instructions.
Nevertheless, it is possible to use port 7 and 8 simultaneously for analog and digital input. However,
care must be taken that all bits of P7 and P8 that have an undetermined value caused by their
analog function are masked.
Semiconductor Group
28
C517A
Timer / Counter 0 and 1
Timer/Counter 0 and 1 can be used in four operating modes as listed in table 4 :
Table 4
Timer/Counter 0 and 1 Operating Modes
Mode
Description
TMOD
Input Clock
M1
M0
internal
external (max)
fOSC/12x32
fOSC/24x32
fOSC/12
fOSC/24
0
8-bit timer/counter with a
divide-by-32 prescaler
0
0
1
16-bit timer/counter
1
1
2
8-bit timer/counter with
8-bit autoreload
1
0
3
Timer/counter 0 used as one
8-bit timer/counter and one
8-bit timer
Timer 1 stops
1
1
In the “timer” function (C/T = ‘0’) the register is incremented every machine cycle. Therefore the
count rate is fOSC/12.
In the “counter” function the register is incremented in response to a 1-to-0 transition at its
corresponding external input pin (P3.4/T0, P3.5/T1). Since it takes two machine cycles to detect a
falling edge the max. count rate is fOSC/24. External inputs INT0 and INT1 (P3.2, P3.3) can be
programmed to function as a gate to facilitate pulse width measurements. Figure 10 illustrates the
input clock logic.
f OSC
f OSC/12
÷ 12
C/T
TMOD
0
P3.4/T0
P3.5/T1
max f OSC/24
Timer 0/1
Input Clock
1
TR 0/1
Control
TCON
Gate
&
=1
TMOD
<_ 1
P3.2/INT0
P3.3/INT1
MCS01768
Figure 10
Timer/Counter 0 and 1 Input Clock Logic
Semiconductor Group
29
C517A
Cpmpare / Capture Unit (CCU)
The compare/capture unit is one of the C517A’s most powerful peripheral units for use in all kinds
of digital signal generation and event capturing like pulse generation, pulse width modulation, pulse
width measuring etc. The CCU consists of two 16-bit timer/counters with automatic reload feature
and an array of 13 compare or compare/capture registers. A set of six control registers is used for
flexible adapting of the CCU to a wide variety of user’s applications.
The block diagram in figure 11 shows the general configuration of the CCU. All CC1 to CC4
registers and the CRC register are exclusively assigned to timer 2. Each of the eight compare
registers CM0 through CM7 can either be assigned to timer 2 or to the faster compare timer, e.g. to
provide up to 8 PWM output channels. The assignment of the CMx registers - which can be done
individually for every single register - is combined with an automatic selection of one of the two
possible compare modes.
(CTREL)
"Internal Bus"
16-bit Reload
Prescaler
(CM0)
Compare Timer
Prescaler
Max.Clock = f OSC/2
8x
16-bit
Compare
(CM7)
Shadow
Latch
Port
Control
Logik
P4I/OLatch
CC4EN
P5I/OLatch
Port
Control
Logik
P1I/OLatch
Timer 2
Capt./Comp. 4 (CC4)
Max.Clock = f OSC /12
Capt./Comp. 3 (CC3)
Capt./Comp. 2 (CC2)
Capt./Comp.1 (CC1)
16-bit Rel.Capt. (CRC)
Comp.
MCB01577
Figure 11
Timer 2 Block Diagram
Semiconductor Group
30
C517A
The main functional blocks of the CCU are :
– Timer 2 with fOSC/12 input clock, 2-bit prescaler, 16-bit reload, counter/gated timer mode and
overflow interrupt request.
– Compare timer with fOSC/2 input clock, 3-bit prescaler, 16-bit reload and overflow interrupt
request.
– Compare/(reload/)capture register array consisting of four different kinds of registers:
one 16-bit compare/reload/capture register,
three 16-bit compare/capture registers,
one 16-bit compare/capture register with additional "concurrent compare" feature,
eight 16-bit compare registers with timer-overflow controlled loading.
Table 5 shows the possible configurations of the CCU and the corresponding compare modes
which can be selected. The following sections describe the function of these configurations.
Table 5
CCU Configurations
Assigned
Timer
Compare
Register
Compare Output at
Possible Modes
Timer 2
CRCH/CRCL
CCH1/CCL1
CCH2/CCL2
CCH3/CCL3
CCH4/CCL4
P1.0/INT3/CC0
P1.1/INT4/CC1
P1.2/INT5/CC2
P1.3/INT6/CC3
P1.4/INT2/CC4
Compare mode 0, 1 + Reload
Compare mode 0, 1 / capture
Compare mode 0, 1 / capture
Compare mode 0, 1 / capture
Compare mode 0, 1 / capture
CCH4/CCL4
P1.4/INT2/CC4
P5.0/CCM0
to
P5.7/CCM7
Compare mode 1
“Concurrent compare“
CMH0/CML0
to
CMH7/CML7
P4.0/CM0
to
P4.7/CM7
Compare mode 0
COMSET
COMCLR
P5.0/CCM0
to
P5.7/CCM7
Compare mode 2
CMH0/CML0
to
CMH7/CML7
P4.0/CM0
to
P4.7/CM7
Compare mode 1
Compare
Timer
Semiconductor Group
31
C517A
Timer 2 Operation
Timer Mode : In timer function, the count rate is derived from the oscillator frequency. A prescaler
offers the possibility of selecting a count rate of 1/12 or 1/24 of the oscillator frequency.
Gated Timer Mode : In gated timer function, the external input pin P1.7/T2 operates as a gate to the
input of timer 2. lf T2 is high, the internal clock input is gated to the timer. T2 = 0 stops the counting
procedure. The external gate signal is sampled once every machine cycle.
Event Counter Mode : In the event counter function. the timer 2 is incremented in response to a 1to-0 transition at its corresponding external input pin P1.7/T2. In this function, the external input is
sampled every machine cycle. The maximum count rate is 1/24 of the oscillator frequency.Reload
of Timer 2 : Two reload modes are selectable:
In mode 0, when timer 2 rolls over from all 1’s to all 0’s, it not only sets TF2 but also causes the timer
2 registers to be loaded with the 16-bit value in the CRC register, which is preset by software.
In mode 1, a 16-bit reload from the CRC register is caused by a negative transition at the corresponding input pin P1.5/T2EX.
Programmable
Prescaler
T2PS T2PS1
OSC
P1.7/T2
TL2
(8 Bits)
SFR T2CON
T2I1
T2I0
0
0
No input selected
Timer stop
0
1
Timer function
1
0
Counter function
via ext. input P1.7/T2
1
1
Gated timer function
by ext. input P1.7/T2
TH2
(8 Bits)
Timer 2
Input Clock
TF2
<_1
P1.5/T2EX
Sync
Interrupt
EXF2
EXEN2
<_1
Reload
MCB03328
Figure 12
Block Diagram of Timer 2
Semiconductor Group
32
C517A
Compare Timer Operation
The compare timer receives its input clock from a programmable prescaler which provides input
frequencies, ranging from fOSC/2 up to fOSC/256. The compare timer is, once started, a free-running
16-bit timer, which on overflow is automatically reloaded by the contents of a 16-bit reload register.
The compare timer has - as any other timer in the C517A - their own interrupt request flags CTF.
These flags are set when the timer count rolls over from all ones to the reload value. Figure 13
shows the block diagram of compare timer and compare timer 1.
f OSC /2
3-Bit Prescaler
/2
/4
/8
/16
Compare Timer
/32
/64
/128
Control (CTCON)
16
To Compare
Circuitry
To Interrupt
Circuitry
CTF
16-Bit Compare Timer
Overflow
16-Bit Reload (CTREL)
MCB00783
Figure 13
Compare Timer Block Diagram
Semiconductor Group
33
C517A
Compare Modes
The compare function of a timer/register combination operates as follows : the 16-bit value stored
in a compare or compare/capture register is compared with the contents of the timer register; if the
count value in the timer register matches the stored value, an appropriate output signal is generated
at a corresponding port pin and an interrupt can be generated.
Compare Mode 0
In compare mode 0, upon matching the timer and compare register contents, the output signal
changes from low to high. lt goes back to a low level on timer overflow. As long as compare mode
0 is enabled, the appropriate output pin is controlled by the timer circuit only and writing to the port
will have no effect. Figure 14 shows a functional diagram of a port circuit when used in compare
mode 0. The port latch is directly controlled by the timer overflow and compare match signals. The
input line from the internal bus and the write-to-latch line of the port latch are disconnected when
compare mode 0 is enabled.
Port Circuit
Read Latch
Compare Register
Circuit
DD
VV
CC
Compare Reg.
16 Bit
Comparator
16 Bit
Compare
Match
S
D
Q
Port
Latch
CLK
Q
R
Internal
Bus
Write to
Latch
Port
Pin
Timer Register
Timer Circuit
Timer
Overflow
Read Pin
MCS02661
Figure 14
Port Latch in Compare Mode 0
Compare Mode 1
If compare mode 1 is enabled and the software writes to the appropriate output latch at the port, the
new value will not appear at the output pin until the next compare match occurs. Thus, it can be
choosen whether the output signal has to make a new transition (1-to-0 or 0-to-1, depending on the
actual pin-level) or should keep its old value at the time when the timer value matches the stored
compare value.
In compare mode 1 (see figure 15) the port circuit consists of two separate latches. One latch
(which acts as a "shadow latch") can be written under software control, but its value will only be
transferred to the port latch (and thus to the port pin) when a compare match occurs.
Semiconductor Group
34
C517A
Port Circuit
Read Latch
VVCC
DD
Compare Register
Circuit
Compare Reg.
Internal
Bus
16 Bit
Comparator
16 Bit
Compare
Match
D
Q
D
Q
Port
Latch
CLK
Q
Shadow
Latch
CLK
Write to
Latch
Port
Pin
Timer Register
Timer Circuit
Read Pin
MCS02662
Figure 15
Compare Function in Compare Mode 1
Compare Mode 2
In the compare mode 2 the port 5 pins are under control of compare/capture register CC4, but under
control of the compare registers COMSET and COMCLR. When a compare match occurs with
register COMSET, a high level appears at the pins of port 5 when the corresponding bits in the mask
register SETMSK are set. When a compare match occurs with register COMCLR, a low level
appears at the pins of port 5 when the corresponding bits in the mask register CLRMSK are set.
Port Circuit
Read Latch
COMSET
VVCCDD
16 Bit
Comparator
16 Bit
TH2
Compare
Signal
SETMSK
Bits
Internal
Bus
Write to
Latch
TL2
Timer 2
16 Bit
Comparator
16 Bit
Compare
Signal
S
D
Q
Port
Latch
CLK
Q
R
Port
Pin
CLRMSK
Bits
COMCLR
Read Pin
MCS02663
Figure 16
Compare Function of Compare Mode 2
Semiconductor Group
35
C517A
Multiplication / Division Unit (MDU)
This on-chip arithmetic unit of the C517A provides fast 32-bit division, 16-bit multiplication as well
as shift and normalize features. All operations are unsigned integer operations. Table 6 describes
the five general operations the MDU is able to perform.
Table 6
MDU Operation Characteristics
Operation
Result
Remainder
Execution Time
32bit/16bit
16bit/16bit
16bit x 16bit
32-bit normalize
32-bit shift L/R
32bit
16bit
32bit
–
–
16bit
16bit
–
–
–
6 tCY 1)
4 tCY 1)
4 tCY 1)
6 tCY 2)
6 tCY 2)
1) 1 tCY = 12 tCLCL= 1 machine cycle = 500 ns at 24 MHz oscillator frequency
2) The maximal shift speed is 6 shifts per machine cycle
The MDU consists of seven special function registers (MD0-MD5, ARCON) which are used as
operand, result, and control registers. The three operation phases are shown in figure 17.
Figure 17
Operating Phases of the MDU
Semiconductor Group
36
C517A
For starting an operation, registers MD0 to MD5 and ARCON must be written to in a certain
sequence according table 7 and 8. The order the registers are accessed determines the type of the
operation. A shift operation is started by a final write operation to SFR ARCON.
Table 7
Programming the MDU for Multiplication and Division
Operation
32Bit/16Bit
16Bit/16Bit
16Bit x 16Bit
First Write
MD0
MD1
MD2
MD3
MD4
MD5
D’endL
D’end
D’end
D’endH
D’orL
D’orH
MD0
MD1
D’endL
D’endH
MD0
MD4
M’andL
M’orL
MD4
D’orL
MD1
M’andH
MD5
D’orH
MD5
M’orH
MD0
MD1
MD2
MD3
MD4
MD5
QuoL
Quo
Quo
QuoH
RemL
RemH
MD0
MD1
QuoL
QuoH
MD0
MD1
PrL
MD4
RemL
MD2
MD5
RemH
MD3
Last Write
First Read
Last Read
Abbrevations :
D’end
: Dividend, 1st operand of division
D’or
: Divisor, 2nd operand of division
M’and
: Multiplicand, 1st operand of multiplication
M’or
: Multiplicator, 2nd operand of multiplication
Pr
: Product, result of multiplication
Rem
: Remainder
Quo
: Quotient, result of division
...L
: means, that this byte is the least significant of the 16-bit or 32-bit operand
...H
: means, that this byte is the most significant of the 16-bit or 32-bit operand
Table 8
Programming athe MDU for a Shift or Normalize Operation
Operation
Normalize, Shift Left, Shift Right
First write
MD0
MD1
MD2
MD3
ARCON
least significant byte
.
.
most significant byte
start of conversion
MD0
MD1
MD2
MD3
least significant byte
.
.
most significant byte
Last write
First read
Last read
Semiconductor Group
37
PrH
C517A
Serial Interfaces 0 and 1
The C517A has two serial interfaces which are functionally nearly identical concerning the
asynchronous modes of operation. The two channels are full-duplex, meaning they can transmit
and receive simultaneously. The serial channel 0 is completely compatible with the serial channel
of the C501 (one synchronous mode, three asynchronous modes). Serial channel 1 has the same
functionality in its asynchronous modes, but the synchronous mode and the fixed baud rate UART
mode is missing.
The operating modes of the serial interfaces is illustrated in table 9. The possible baudrates can be
calculated using the formulas given in table 10.
Table 9
Operating Modes of Serial Interface 0 and 1
Mode
Serial
Interface
0
1
S0CON
S1CON Description
SM0
SM1
SM
0
0
0
–
Shift register mode
Serial data enters and exits through R×D0;
T×D0 outputs the shift clock; 8-bit are
transmitted/received (LSB first); fixed baud rate
1
0
1
–
8-bit UART, variable baud rate
10 bits are transmitted (through T×D0) or
received (at R×D0)
2
1
0
–
9-bit UART, fixed baud rate
11 bits are transmitted (through T×D0) or
received (at R×D0)
3
1
1
–
9-bit UART, variable baud rate
Like mode 2
A
–
–
0
9-bit UART; variable baud rate
11 bits are transmitted (through T×D1) or
received (at R×D1)
B
–
–
1
8-bit UART; variable baud rate
10 bits are transmitted (through T×D1) or
received (at R×D1)
Semiconductor Group
38
C517A
For clarification some terms regarding the difference between "baud rate clock" and "baud rate"
should be mentioned. In the asynchronous modes the serial interfaces require a clock rate which is
16 times the baud rate for internal synchronization. Therefore, the baud rate generators/timers have
to provide a "baud rate clock" (output signal in figure 18 and figure 19) to the serial interface
which - there divided by 16 - results in the actual "baud rate". Further, the abrevation fOSC refers to
the oscillator frequency (crystal or external clock operation).
The variable baud rates for modes 1 and 3 of the serial interface 0 can be derived from either timer
1 or a decdicated baud rate generator (see figure 18). The variable baud rates for modes A and B
of the serial interface 1 are derived from a decdicated baud rate generator as shown in figure 19.
Timer 1 Overflow
ADCON0.7
(BD)
f OSC /2
Baud
Rate
Generator
Mode 1
Mode 3
Mode 2
0
1
(S0RELH
S0RELL)
S0CON.7
S0CON.6
(SM0/
SM1)
PCON.7
(SMOD)
÷2
0
Baud
Rate
Clock
1
Mode 0
Only one mode
can be selected
÷6
Note : The switch configuration shows the reset state.
MCS03329
Figure 18
Serial Interface 0 : Baud Rate Generation Configuration
Baud Rate Generator
S1RELH
f OSC /2
Input Clock
.1 .0
S1RELL
10-Bit Timer
Owerflow
Baud
Rate
Clock
MCS03331
Figure 19
Serial Interface 1 : Baud Rate Generator Configuration
The baud rate generator block in figure 18 has the same structure (10-bit auto-reload timer) as the
baud rate generator block which is shown in detail in figure 19.
Semiconductor Group
39
C517A
Table 10 below lists the values/formulas for the baud rate calculation of serial interface 0 and 1 with
its dependencies of the control bits BD and SMOD.
Table 10
Serial Interfaces - Baud Rate Dependencies
Serial Interface
Operating Modes
Active Control
Bits
Baud Rates
SMOD
BD
Mode 0 (Shift Register)
–
–
Fixed baud rate clock fosc/12
Mode 1 (8-bit UART)
Mode 3 (9-bit UART)
X
0
Timer 1 overflow is used for baud rate
generation; SMOD controls a divide-by-2 option.
Baud rate = 2SMOD x timer 1 overflow rate / 32
1
Baud rate generator is used for baud rate
generation; SMOD controls a divide-by-2 option
Baud rate = 2SMOD x oscillator frequency /
64 x (baud rate gen. overflow rate)
Mode 2 (9-bit UART)
X
–
Fixed baud rate clock fosc/32 (SMOD=1) or fosc/
64 (SMOD=0)
Mode A (9-bit UART)
Mode B (8-bit UART)
–
–
Baud rate generator is used for baud rate
generation; SMOD controls a divide-by-2 option
Baud rate = oscillator frequency /
32 x (baud rate gen. overflow rate)
Semiconductor Group
40
C517A
10-Bit A/D Converter
The C517A provides an A/D converter with the following features:
–
–
–
–
–
–
–
12 multiplexed input channels (port 7, 8), which can also be used as digital inputs
10-bit resolution
Single or continuous conversion mode
Internal or external start-of-conversion trigger capability
Interrupt request generation after each conversion
Using successive approximation conversion technique via a capacitor array
Built-in hidden calibration of offset and linearity errors
The A/D converter operates with a successive approximation technique and uses self calibration
mechanisms for reduction and compensation of offset and linearity errors. The externally applied
reference voltage range has to be held on a fixed value within the specifications. The main
functional blocks of the A/D converter are shown in figure 20.
Semiconductor Group
41
C517A
internal
Bus
IEN1 (B8 H )
EX6
EX5
EX4
EX3
EX2
EADC
TF2
IEX6
IEX5
IEX4
IEX3
IEX2
IADC
_
_
_
P8.3
P8.2
P8.1
P8.0
P7.6
P7.5
P7.4
P7.3
P7.2
P7.1
P7.0
_
_
MX3
MX2
MX1
MX0
ADEX
BSY
ADM
MX2
MX1
MX0
EXEN2 SWDT
IRCON0 (C0 H )
EXF2
P8 (DD H )
_
P7 (DB H )
P7.7
ADCON1 (DC H )
ADCL
_
ADCON0 (D8 H )
BD
CLK
Single/
Continuous Mode
Port 7
ADDATH ADDATL
(D9 H ) (DA H )
_
.2
MUX
Port 8
S&H
f OSC /2
Clock
Prescaler
÷8, ÷4
A/D
Converter
Conversion
Clock fADC
Input
Clock f IN
VAREF
.3
_
.4
_
.5
_
.6
_
.7
_
.8
LSB
MSB
.1
VAGND
Start of
Conversion
P6.0/ADST
Write to ADDATL
Shaded bit locations are not used in ADC-functions
Figure 20
A/D Converter Block Diagram
Semiconductor Group
42
internal
Bus
MCB03332
C517A
Interrupt System
The C517A provides 17 interrupt sources with four priority levels. Ten interrupts can be generated
by the on-chip peripherals (timer 0, timer 1, timer 2, compare timer, compare match/set/clear, A/D
converter, and serial interface 0 and 1) and seven interrupts may be triggered externally (P3.2/INT0,
P3.3/INT1, P1.4/INT2, P1.0/INT3, P1.1/INT4, P1.2/INT5, P1.3/INT6).
This chapter shows the interrupt structure, the interrupt vectors and the interrupt related special
function registers. Figure 21 to 23 give a general overview of the interrupt sources and illustrate the
request and the control flags which are described in the next sections.
Semiconductor Group
43
C517A
Highest
Priority Level
P3.2/
INT0
IE0
TCON.1
IT0
TCON.0
EX0
IEN0.0
0003 H
ES1
IEN2.0
0083 H
EADC
IEN1.0
0043 H
Lowest
Priority Level
RI1
S1CON.0
UART 1
<_ 1
TI1
A/D Converter
IADC
IRCON0.0
Timer 0
Overflow
TF0
TCON.5
P1.4/
INT2/
CC4
ET0
IEN0.1
000B H
EX2
IEN1.1
004B H
IEX2
I2FR
T2CON.5
IRCON0.1
Bit addressable
EAL
IEN0.7
Request Flag is
cleared by hardware
Figure 21
Interrupt Structure, Overview (Part 1)
Semiconductor Group
44
IP1.0
IP0.0
IP1.1
IP0.1
Polling Sequence
S1CON.1
MCS03333
C517A
Highest
Priority Level
IE1
IT1
TCON.2
TCON.3
Match in CM0-CM7
ICMP0-7
IRCON1.0-7
P1.0/
INT3/
CC0
EX1
IEN0.2
0013 H
ECMP
IEN2.2
0093 H
EX3
IEN1.2
0053 H
IEX3
I3FR
T2CON.5
Timer 1
Overflow
IRCON0.2
TF1
TCON.7
Compare Timer
Overflow
P1.1/
INT4/
CC1
ET1
IEN0.3
001B H
ECT
IEN2.3
009B H
EX4
IEN1.3
005B H
CTF
CTCON.3
IEX4
IRCON0.3
Bit addressable
Lowest
Priority Level
EAL
IEN0.7
Request Flag is
cleared by hardware
Figure 22
Interrupt Structure, Overview (Part 2)
Semiconductor Group
45
IP1.2
IP0.2
IP1.3
IP0.3
Polling Sequence
P3.3/
INT1
MCS03334
C517A
Highest
Priority Level
RI0
<_ 1
S0CON.0
TI0
ES0
IEN0.4
0023 H
ECS
IEN2.4
00A3 H
EX5
IEN1.4
0063 H
Lowest
Priority Level
S0CON.1
ICS
Match in COMSET
CTCON.4
P1.2/
INT5/
CC2
IEX5
IRCON0.4
Timer 2
Overflow
IP1.4
IP0.4
IP1.5
IP0.5
TF2
IRCON0.6
P1.5/
T2EX
<_ 1
EXF2
EXEN2 IRCON0.7
IEN1.7
Match in COMCLR
002B H
ECR
IEN2.5
00AB H
EX6
IEN1.5
006B H
ICR
CTCON.5
P1.3/
INT6/
CC3
ET2
IEN0.5
IEX6
IRCON0.5
Bit addressable
EAL
IEN0.7
Request Flag is
cleared by hardware
Figure 23
Interrupt Structure, Overview (Part 3)
Semiconductor Group
46
Polling Sequence
USART 0
MCS03335
C517A
Table 11
Interrupt Source and Vectors
Interrupt Source
Interrupt Vector Address
Interrupt Request Flags
External Interrupt 0
0003H
IE0
Timer 0 Overflow
000BH
0013H
TF0
TF1
Serial Channel 0
001BH
0023H
Timer 2 Overflow / Ext. Reload
002BH
TF2 / EXF2
A/D Converter
0043H
IADC
External Interrupt 2
004BH
IEX2
External Interrupt 3
0053H
IEX3
External Interrupt 4
005BH
IEX4
External Interrupt 5
0063H
IEX5
External Interrupt 6
006BH
IEX6
Serial Channel 1
0083H
RI1 / TI1
Compare Match Interupt of
Compare Registers CM0-CM7
assigned to Timer 2
0093H
ICMP0 - ICMP7
Compare Timer Overflow
009BH
CTF
Compare Match Interupt of
Compare Register COMSET
00A3H
ICS
Compare Match Interupt of
Compare Register COMCLR
00ABH
ICR
External Interrupt 1
Timer 1 Overflow
Semiconductor Group
IE1
RI0 / TI0
47
C517A
Fail Save Mechanisms
The C517A offers enhanced fail safe mechanisms, which allow an automatic recovery from
software upset or hardware failure :
– a programmable watchdog timer (WDT), with variable time-out period from 512 µs up to
approx. 1.1 s at 12 MHz. (256 µs up to approx. 0.65 s at 24 MHz)
– an oscillator watchdog (OWD) which monitors the on-chip oscillator and forces the
microcontroller into reset state in case the on-chip oscillator fails; it also provides the clock for
a fast internal reset after power-on.
The watchdog timer in the C517A is a 15-bit timer, which is incremented by a count rate of fOSC/24
up to fOSC/384. The system clock of the C517A is divided by two prescalers, a divide-by-two and a
divide-by-16 prescaler. For programming of the watchdog timer overflow rate, the upper 7 bit of the
watchdog timer can be written. Figure 24 shows the block diagram of the watchdog timer unit.
0
f OSC /12
7
16
2
WDTL
14
WDT Reset-Request
8
WDTH
IP0 (A9 H )
-
WDTS
-
-
-
-
-
-
WDTPSEL
External HW Reset
External HW Power-Down
7 6
PE/SWD
0
WDTREL (86 H )
Control Logic
-
WDT
-
-
-
-
-
-
IEN0 (A8 )H
-
SWDT
-
-
-
-
-
-
IEN1 (B8 )H
MCB03250
Figure 24
Block Diagram of the Watchdog Timer
The watchdog timer can be started by software (bit SWDT) or by hardware through pin PE/SWD,
but it cannot be stopped during active mode of the C517A. If the software fails to refresh the running
watchdog timer an internal reset will be initiated on watchdog timer overflow. For refreshing of the
watchdog timer the content of the SFR WDTREL is transfered to the upper 7-bit of the watchdog
timer. The refresh sequence consists of two consequtive instructions which set the bits WDT and
SWDT each. The reset cause (external reset or reset caused by the watchdog) can be examined
by software (flag WDTS). It must be noted, however, that the watchdog timer is halted during the
idle mode and power down mode of the processor.
Semiconductor Group
48
C517A
Oscillator Watchdog
The oscillator watchdog unit serves for four functions:
– Monitoring of the on-chip oscillator’s function
The watchdog supervises the on-chip oscillator's frequency; if it is lower than the frequency of
the auxiliary RC oscillator in the watchdog unit, the internal clock is supplied by the RC
oscillator and the device is brought into reset; if the failure condition disappears (i.e. the onchip oscillator has a higher frequency than the RC oscillator), the part executes a final reset
phase of typ. 1 ms in order to allow the oscillator to stabilize; then the oscillator watchdog reset
is released and the part starts program execution again.
– Fast internal reset after power-on
The oscillator watchdog unit provides a clock supply for the reset before the on-chip oscillator
has started. The oscillator watchdog unit also works identically to the monitoring function.
– Restart from the hardware power down mode.
If the hardware power down mode is terminated the oscillator watchdog has to control the
correct start-up of the on-chip oscillator and to restart the program. The oscillator watchdog
function is only part of the complete hardware power down sequence; however, the watchdog
works identically to the monitoring function.
RC
Oscillator
f RC
3MHz
÷5
f1
Frequency
Comparator
f2<f1
Delay
<_1
Internal Reset
f2
XTAL1
XTAL2
IP0 (A9 H)
On-Chip
Oscillator
OWDS
÷2
Internal Clock
MCB03337
Figure 25
Block Diagram of the Oscillator Watchdog
Semiconductor Group
49
C517A
Power Saving Modes
The C517A provides two basic power saving modes, the idle mode and the power down mode.
Additionally, a slow down mode is available. This power saving mode reduces the internal clock
rate in normal operating mode and it can be also used for further power reduction in idle mode.
– Idle mode
The CPU is gated off from the oscillator. All peripherals are still provided with the clock and
are able to work. Idle mode is entered by software and can be left by an interrupt or reset.
– Slow down mode
The controller keeps up the full operating functionality, but its normal clock frequency is
internally divided by 8. This slows down all parts of the controller, the CPU and all peripherals,
to 1/8th of their normal operating frequency and also reduces power consumption.
– Software power down mode
The operation of the C517A is completely stopped and the oscillator is turned off. This mode
is used to save the contents of the internal RAM with a very low standby current. This power
down mode is entered by software and can be left by reset.
– Hardware Power down mode
If pin HWPD gets active (low level) the part enters the hardware power down mode and starts
a complete internal reset sequence. Thereafter, both oscillators of the chip are stopped and
the port pins and several control lines enter a floating state.
In the power down mode of operation, VDD can be reduced to minimize power consumption. It must
be ensured, however, that VDD is not reduced before the power down mode is invoked, and that VDD
is restored to its normal operating level, before the power down mode is terminated. Table 12 gives
a general overview of the entry and exit procedures of the power saving modes.
Semiconductor Group
50
C517A
Table 12
Power Saving Modes Overview
Mode
Entering
2-Instruction
Example
Leaving by
Remarks
Idle mode
ORL PCON, #01H
ORL PCON, #20H
Ocurrence of an
interrupt from a
peripheral unit
CPU clock is stopped;
CPU maintains their data;
peripheral units are active (if
enabled) and provided with
clock
Hardware Reset
Slow Down Mode
In normal mode :
ORL PCON,#10H
ANL PCON,#0EFH
or
Hardware Reset
Internal clock rate is reduced
to 1/8 of its nominal frequency
With idle mode :
ORL PCON,#01H
ORL PCON, #30H
Ocurrence of an
interrupt from a
peripheral unit
CPU clock is stopped;
CPU maintains their data;
peripheral units are active (if
enabled) and provided with 1/8
of its nominal frequency
Hardware reset
Software
Power Down Mode
ORL PCON, #02H
ORL PCON, #40H
Hardware Reset
Hardware
Power Down Mode
HWPD = 0
HWPD = 1
Semiconductor Group
Rising edge at
PE/SWD
51
Oscillator is stopped;
contents of on-chip RAM and
SFR’s are maintained;
Oscillator is stopped; internal
reset is executed;
C517A
Absolute Maximum Ratings
Parameter
Symbol
Limit Values
Unit Notes
min.
max.
TST
– 65
150
°C
–
Voltage on VDD pins with respect VDD
to ground (VSS)
–0.5
6.5
V
–
VIN
–0.5
VDD + 0.5
V
–
Input current on any pin during
overload condition
–10
10
mA
–
Absolute sum of all input
currents during overload
condition
–
| 100 |
mA
–
–
TBD
W
–
Storage temperature
Voltage on any pin with respect
to ground (VSS)
Power dissipation
PDISS
Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent
damage of the device. This is a stress rating only and functional operation of the device at
these or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for longer
periods may affect device reliability. During absolute maximum rating overload conditions
(VIN > VDD or VIN < VSS) the voltage on VDD pins with respect to ground (VSS) must not exceed
the values defined by the absolute maximum ratings.
Operating Conditions
Parameter
Symbol
Supply voltage
VDD
Ground voltage
VSS
Ambient temperature
SAB-C517A
SAF-C517A
SAH-C517A
Limit Values
min.
max.
4.25
5.5
0
Unit Notes
V
–
V
–
TA
TA
TA
0
–40
–40
70
85
110
°C
°C
°C
18 and 24 MHz
18 and 24 MHz
18 MHz
Analog reference voltage
VAREF
4
VDD + 0.1
V
–
Analog ground voltage
VAGND
VSS - 0.1
VSS + 0.2
V
–
Analog input voltage
VAIN
VAGND
VAREF
V
–
CPU clock
fCPU
3.5
24
MHz –
Semiconductor Group
52
C517A
DC Characteristics
(Operating Conditions apply)
Parameter
Input low voltage
Pins except EA,RESET,HWPD
EA pin
HWPD and RESET pins
Symbol
VIL
VIL1
VIL2
Limit Values
Unit Test Condition
min.
max.
– 0.5
– 0.5
– 0.5
0.2 VDD – 0.1 V
0.2 VDD – 0.3 V
0.2 VDD + 0.1 V
–
–
–
Input high voltage
pins except RESET, XTAL2 and
VIH
HWPD
XTAL2 pin
VIH1
VIH2
RESET and HWPD pin
0.2 VDD + 0.9 VDD + 0.5
0.7 VDD
VDD + 0.5
VDD + 0.5
0.6 VDD
V
V
V
–
–
–
Output low voltage
Ports 1, 2, 3, 4, 5, 6
Port 0, ALE, PSEN, RO
VOL
VOL1
–
–
0.45
0.45
V
V
I OL = 1.6 mA 1)
I OL = 3.2 mA 1)
Output high voltage
Ports 1, 2, 3, 4, 5, 6
VOH
2.4
0.9 VDD
2.4
0.9 VDD
–
–
–
–
V
V
V
V
I OH = – 80 µA
I OH = – 10 µA
I OH = – 800 µA2)
I OH = – 80 µA 2)
Port 0 in external bus mode,
ALE, PSEN, RO
VOH1
Logic 0 input current
Ports 1, 2, 3, 4, 5, 6
I LI
– 10
– 70
µA
VIN = 2 V
Logical 0-to-1 transition current,
Ports 1, 2, 3, 4, 5, 6
I TL
– 65
– 650
µA
VIN = 2 V
Input leakage current
Port 0, 7 and 8, EA, HWPD
I LI
–
±1
µA
0.45 < V I N < VDD
Input low current
to RESET for reset
XTAL2
PE/SWD, OWE
I IL2
I IL3
I IL4
– 10
–
–
– 100
– 15
– 20
µA
µA
µA
VI N = 0.45 V
V I N = 0.45 V
V I N = 0.45 V
Pin capacitance
C IO
–
10
pF
f C = 1 MHz,
T A = 25°C
Overload current
IOV
–
±5
mA
Notes see next page
Semiconductor Group
53
7) 8)
C517A
Power Supply Current
Parameter
Symbol
Limit Values
typ. 9)
max. 10)
Unit Test Condition
Active mode
18 MHz
24 MHz
IDD
IDD
21.3
27.3
29.2
37.6
mA
mA
4)
Idle mode
18 MHz
24 MHz
IDD
IDD
11.6
14.6
16.2
20.4
mA
mA
5)
Active mode with
slow-down enabled
18 MHz
24 MHz
IDD
IDD
9.5
10.7
13.1
14.9
mA
mA
6)
IPD
15
50
µA
VDD = 2…5.5 V 3)
Power-down mode
Notes:
1) Capacitive loading on ports 0 and 2 may cause spurious noise pulses to be superimposed on the VOL of ALE
and port 3. The noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these
pins make 1-to-0 transitions during bus operation. In the worst case (capacitive loading > 100 pF), the noise
pulse on ALE line may exceed 0.8 V. In such cases it may be desirable to qualify ALE with a schmitt-trigger,
or use an address latch with a schmitt-trigger strobe input.
2) Capacitive loading on ports 0 and 2 may cause the VOH on ALE and PSEN to momentarily fall below the 0.9 VDD
specification when the address lines are stabilizing.
3) IPD (power-down mode) is measured under following conditions:
EA = RESET = Port 0 = Port 7 = Port 8 = V DD ; XTAL1 = N.C.; XTAL2 = V SS ; PE/SWD = OWE = V SS ;
HWPD = VDD for software power-down mode; VAGND = VSS ; VAREF = VDD ; all other pins are disconnected.
IPD (hardware power-down mode) is independent of any particular pin connection.
4) IDD (active mode) is measured with:
XTAL2 driven with tCLCH , tCHCL = 5 ns , VIL = VSS + 0.5 V, VIH = VDD – 0.5 V; XTAL1 = N.C.;
EA = PE/SWD == V SS ; Port 0 = Port 7 = Port 8 = V DD ; HWPD = V DD ; RESET = V DD ; all other pins are
disconnected.
5) IDD (idle mode) is measured with all output pins disconnected and with all peripherals disabled;
XTAL2 driven with tCLCH , tCHCL = 5 ns, VIL = VSS + 0.5 V, VIH = VDD – 0.5 V; XTAL1 = N.C.;
RESET = VDD ; HWPD = Port 0 = Port 7 = Port 8 = VDD ; EA = PE/SWD = VSS ;
all other pins are disconnected;
6) IDD (active mode with slow-down mode) is measured with all output pins disconnected and with all peripherals
disabled; XTAL2 driven with tCLCH , tCHCL = 5 ns , VIL = VSS + 0.5 V, VIH = VDD – 0.5 V; XTAL1 = N.C.;
HWPD = VDD ; RESET = VDD ; Port 7 = Port 8 = VDD ;; EA = PE/SWD == VSS ; all other pins are disconnected.
7) Overload conditions under operating conditions occur if the voltage on the respective pin exceeds the specified
operating range (i.e. VOV > VDD + 0.5 V or VOV < VSS - 0.5 V). The absolute sum of input currents on all port
pins may not exceed 50 mA. The supply voltage VDD and VSS must remain within the specified limits.
8) Not 100% tested, guaranteed by design characterization
9) The typical IDD values are periodically measured at TA = +25 °C and VDD = 5 V but not 100% tested.
10)The maximum IDD values are measured under worst case conditions (TA = 0 °C or -40 °C and VDD = 5.5 V)
Semiconductor Group
54
C517A
MCD03338
40
IΙ DD
CC max
IΙ DD
CC typ
mA
ΙICC
DD
ode
M
tive
Ac
30
e
Activ
20
e
Mod
ode
Idle M
e
Idle Mod
10
Active + Slow Down Mode
0
0
3.5
8
12
16
Figure 26
IDD Diagram
Table 13
Power Supply Current Calculation Formulas
Parameter
Symbol
Formula
Active mode
IDD typ
IDD max
1 * fOSC + 3.3
1.4 * fOSC + 4.0
Idle mode
IDD typ
IDD max
0.5 * fOSC + 2.6
0.7 * fOSC + 3.6
Active mode with
slow-down enabled
IDD typ
IDD max
0.25 * fOSC + 4.95
0.3 * fOSC + 7.7
Note : fosc is the oscillator frequency in MHz. IDD values are given in mA.
Semiconductor Group
55
20 MHz
f OSC
24
C517A
A/D Converter Characteristics
(Operating Conditions apply)
Parameter
Symbol
Limit Values
min.
max.
Unit
Test Condition
1)
Analog input voltage
VAIN
VAGND
VAREF
V
Sample time
tS
–
16 x tIN
8 x tIN
ns
96 x tIN
48 x tIN
ns
LSB
Conversion cycle time
tADCC
–
Total unadjusted error
TUE
–
±2
Internal resistance of
reference voltage source
RAREF
–
tADC / 250 kΩ
Internal resistance of
analog source
RASRC
ADC input capacitance
CAIN
Prescaler ÷ 8
Prescaler ÷ 4
tS / 500
–
tADC in [ns]
kΩ
tS in [ns]
pF
6)
- 0.25
–
50
Clock calculation table :
Clock Prescaler ADCL
Ratio
tADC
tS
tADCC
÷8
1
8 x tIN
16 x tIN
96 x tIN
÷4
0
4 x tIN
8 x tIN
48 x tIN
Further timing conditions : tADC min = 500 ns
tIN = 2 / fOSC = 2 tCLCL
56
2)
3)
VSS+0.5V ≤ VIN ≤ VDD-0.5V 4)
5) 6)
- 0.25
Notes see next page.
Semiconductor Group
Prescaler ÷ 8
Prescaler ÷ 4
2) 6)
C517A
Notes:
1) VAIN may exeed VAGND or VAREF up to the absolute maximum ratings. However, the conversion result in
these cases will be X000H or X3FFH, respectively.
2) During the sample time the input capacitance CAIN can be charged/discharged by the external source. The
internal resistance of the analog source must allow the capacitance to reach their final voltage level within tS.
After the end of the sample time tS, changes of the analog input voltage have no effect on the conversion result.
3) This parameter includes the sample time tS, the time for determining the digital result and the time for the
calibration. Values for the conversion clock tADC depend on programming and can be taken from the table on
the previous page.
4) TUE is tested at VAREF = 5.0 V, VAGND = 0 V, VDD = 4.9 V. It is guaranteed by design characterization for all
other voltages within the defined voltage range.
If an overload condition occurs on maximum 2 not selected analog input pins and the absolute sum of input
overload currents on all analog input pins does not exceed 10 mA, an additional conversion error of 1/2 LSB
is permissible.
5) During the conversion the ADC’s capacitance must be repeatedly charged or discharged. The internal
resistance of the reference source must allow the capacitance to reach their final voltage level within the
indicated time. The maximum internal resistance results from the programmed conversion timing.
6) Not 100% tested, but guaranteed by design characterization.
Semiconductor Group
57
C517A
AC Characteristics (18 MHz)
(Operating Conditions apply)
(CL for port 0, ALE and PSEN outputs = 100 pF; CL for all other outputs = 80 pF)
Program Memory Characteristics
Parameter
Symbol
Limit Values
18 MHz
Clock
Unit
Variable Clock
1/tCLCL = 3.5 MHz to 18 MHz
min.
max.
min.
max.
ALE pulse width
tLHLL
71
–
2 tCLCL – 40
–
ns
Address setup to ALE
tAVLL
26
–
tCLCL – 30
–
ns
Address hold after ALE
tLLAX
26
–
tCLCL – 30
–
ns
ALE low to valid instruction in
tLLIV
–
122
–
4 tCLCL – 100
ns
ALE to PSEN
tLLPL
31
–
tCLCL – 25
–
ns
PSEN pulse width
tPLPH
132
–
3 tCLCL – 35
–
ns
PSEN to valid instruction in
tPLIV
–
92
–
3 tCLCL – 75
ns
Input instruction hold after PSEN
tPXIX
0
–
0
–
ns
Input instruction float after PSEN
tPXIZ*)
–
46
–
tCLCL – 10
ns
Address valid after PSEN
tPXAV*)
48
–
tCLCL – 8
–
ns
Address to valid instr in
tAVIV
–
180
–
5 tCLCL – 98
ns
Address float to PSEN
tAZPL
0
–
0
–
ns
*)
Interfacing the C517A to devices with float times up to 45 ns is permissible. This limited bus contention will not
cause any damage to port 0 drivers.
CLKOUT Characteristics
Parameter
Symbol
Limit Values
18 MHz
Clock
Unit
Variable Clock
1/tCLCL = 3.5 MHz to 18 MHz
min.
max.
min.
max.
ALE to CLKOUT
tLLSH
349
–
7 tCLCL – 40
–
ns
CLKOUT high time
tSHSL
71
–
2 tCLCL – 40
–
ns
CLKOUT low time
tSLSH
516
–
10 tCLCL – 40
–
ns
CLKOUT low to ALE high
tSLLH
16
96
tCLCL – 40
tCLCL + 40
ns
Semiconductor Group
58
C517A
AC Characteristics (18 MHz, cont’d)
External Data Memory Characteristics
Parameter
Symbol
Limit Values
18 MHz
Clock
Unit
Variable Clock
1/tCLCL = 3.5 MHz to 18 MHz
min.
max.
min.
max.
RD pulse width
tRLRH
233
–
6 tCLCL – 100
–
ns
WR pulse width
tWLWH
233
–
6 tCLCL – 100
–
ns
Address hold after ALE
tLLAX2
81
–
2 tCLCL – 30
–
ns
RD to valid data in
tRLDV
–
128
–
5 tCLCL – 150
ns
Data hold after RD
tRHDX
0
–
0
–
ns
Data float after RD
tRHDZ
–
51
–
2 tCLCL – 60
ns
ALE to valid data in
tLLDV
–
294
–
8 tCLCL – 150
ns
Address to valid data in
tAVDV
–
335
–
9 tCLCL – 165
ns
ALE to WR or RD
tLLWL
117
217
3 tCLCL – 50
3 tCLCL + 50
ns
Address valid to WR or RD
tAVWL
92
–
4 tCLCL – 130
–
ns
WR or RD high to ALE high
tWHLH
16
96
tCLCL – 40
tCLCL + 40
ns
Data valid to WR transition
tQVWX
11
–
tCLCL – 45
–
ns
Data setup before WR
tQVWH
239
–
7 tCLCL – 150
–
ns
Data hold after WR
tWHQX
16
–
tCLCL – 40
–
ns
Address float after RD
tRLAZ
–
0
–
0
ns
External Clock Drive Characteristics
Parameter
Symbol
Limit Values
Unit
Variable Clock
Freq. = 3.5 MHz to 18 MHz
min.
max.
Oscillator period
tCLCL
55.6
285.7
ns
High time
tCHCX
15
tCLCL – tCLCX
ns
Low time
tCLCX
15
tCLCL – tCHCX
ns
Rise time
tCLCH
–
15
ns
Fall time
tCHCL
–
15
ns
Semiconductor Group
59
C517A
AC Characteristics (24 MHz)
(Operating Conditions apply)
(CL for port 0, ALE and PSEN outputs = 100 pF; CL for all other outputs = 80 pF)
Program Memory Characteristics
Parameter
Symbol
Limit Values
24 MHz
Clock
Unit
Variable Clock
1/tCLCL = 3.5 MHz to 24 MHz
min.
max.
min.
max.
ALE pulse width
tLHLL
43
–
2 tCLCL – 40
–
ns
Address setup to ALE
tAVLL
17
–
tCLCL – 25
–
ns
Address hold after ALE
tLLAX
17
–
tCLCL – 25
–
ns
ALE low to valid instruction in
tLLIV
–
80
–
4 tCLCL – 87
ns
ALE to PSEN
tLLPL
22
–
tCLCL – 20
–
ns
PSEN pulse width
tPLPH
95
–
3tCLCL – 30
–
ns
PSEN to valid instruction in
tPLIV
–
60
–
3 tCLCL – 65
ns
Input instruction hold after PSEN
tPXIX
0
–
0
–
ns
Input instruction float after PSEN
tPXIZ*)
–
32
–
tCLCL – 10
ns
Address valid after PSEN
tPXAV*)
37
–
tCLCL – 5
–
ns
Address to valid instr in
tAVIV
–
148
–
5 tCLCL – 60
ns
Address float to PSEN
tAZPL
0
–
0
–
ns
*)
Interfacing the C517A to devices with float times up to 37 ns is permissible. This limited bus contention will not
cause any damage to port 0 drivers.
CLKOUT Characteristics
Parameter
Symbol
Limit Values
24 MHz
Clock
Unit
Variable Clock
1/tCLCL = 3.5 MHz to 24 MHz
min.
max.
min.
max.
ALE to CLKOUT
tLLSH
252
–
7 tCLCL – 40
–
ns
CLKOUT high time
tSHSL
43
–
2 tCLCL – 40
–
ns
CLKOUT low time
tSLSH
377
–
10 tCLCL – 40
–
ns
CLKOUT low to ALE high
tSLLH
2
82
tCLCL – 40
tCLCL + 40
ns
Semiconductor Group
60
C517A
AC Characteristics (24 MHz, cont’d)
External Data Memory Characteristics
Parameter
Symbol
Limit Values
24 MHz
Clock
Unit
Variable Clock
1/tCLCL = 3.5 MHz to 24 MHz
min.
max.
min.
max.
RD pulse width
tRLRH
180
–
6 tCLCL – 70
–
ns
WR pulse width
tWLWH
180
–
6 tCLCL – 70
–
ns
Address hold after ALE
tLLAX2
53
–
2 tCLCL – 30
–
ns
RD to valid data in
tRLDV
–
118
–
5 tCLCL – 90
ns
Data hold after RD
tRHDX
0
–
0
–
ns
Data float after RD
tRHDZ
–
63
–
2 tCLCL – 20
ns
ALE to valid data in
tLLDV
–
200
–
8 tCLCL – 133
ns
Address to valid data in
tAVDV
–
220
–
9 tCLCL – 155
ns
ALE to WR or RD
tLLWL
75
175
3 tCLCL – 50
3 tCLCL + 50
ns
Address valid to WR or RD
tAVWL
67
–
4 tCLCL – 97
–
ns
WR or RD high to ALE high
tWHLH
17
67
tCLCL – 25
tCLCL + 25
ns
Data valid to WR transition
tQVWX
5
–
tCLCL – 37
–
ns
Data setup before WR
tQVWH
170
–
7 tCLCL – 122
–
ns
Data hold after WR
tWHQX
15
–
tCLCL – 27
–
ns
Address float after RD
tRLAZ
–
0
–
0
ns
External Clock Drive Characteristics
Parameter
Symbol
Limit Values
Unit
Variable Clock
Freq. = 3.5 MHz to 24 MHz
min.
max.
Oscillator period
tCLCL
41.7
285.7
ns
High time
tCHCX
12
tCLCL – tCLCX
ns
Low time
tCLCX
12
tCLCL – tCHCX
ns
Rise time
tCLCH
–
12
ns
Fall time
tCHCL
–
12
ns
Semiconductor Group
61
C517A
t LHLL
ALE
t AVLL
t PLPH
t LLPL
t
LLIV
t PLIV
PSEN
t AZPL
t PXAV
t LLAX
t PXIZ
t PXIX
Port 0
A0 - A7
Instr.IN
A0 - A7
t AVIV
Port 2
A8 - A15
A8 - A15
MCT00096
Figure 27
Program Memory Read Cycle
Semiconductor Group
62
C517A
t WHLH
ALE
PSEN
t LLDV
t LLWL
t RLRH
RD
t RLDV
t AVLL
t RHDZ
t LLAX2
t RLAZ
Port 0
t RHDX
A0 - A7 from
Ri or DPL
Data IN
A0 - A7
from PCL
Instr.
IN
t AVWL
t AVDV
Port 2
P2.0 - P2.7 or A8 - A15 from DPH
A8 - A15 from PCH
MCT00097
Figure 28
Data Memory Read Cycle
Figure 29
CLKOUT Timing
Semiconductor Group
63
C517A
t WHLH
ALE
PSEN
t LLWL
t WLWH
WR
t QVWX
t AVLL
t WHQX
t LLAX2
t QVWH
A0 - A7 from
Ri or DPL
Port 0
A0 - A7
from PCL
Data OUT
Instr.IN
t AVWL
Port 2
P2.0 - P2.7 or A8 - A15 from DPH
A8 - A15 from PCH
MCT00098
Figure 30
Data Memory Write Cycle
t CLCL
VVCC
DD- 0.5V
0.45V
0.7 VCC
0.2 VCC- 0.1
t CHCL
t CLCX
Figure 31
External Clock Drive on XTAL2
Semiconductor Group
t CHCX
t CLCH
64
MCT00033
C517A
ROM Verification Characteristics for the C517A-4RM/4RN
ROM Verification Mode 1
Parameter
Symbol
Address to valid data
P1.0-P1.7
P2.0-P2.6
tAVQV
Limit Values
min.
max.
–
10 tCLCL
Address
New Address
t AVQV
Port 0
Data:
Addresses:
Data Out
New Data Out
P0.0-P0.7 = D0-D7
P1.0-P1.7 = A0-A7
P2.0-P2.6 = A8-A14
Inputs:
PSEN
= V SS
ALE, EA = V IH
RESET = V IL2
MCS03253
Figure 32
ROM Verification Mode 1
Semiconductor Group
65
Unit
ns
C517A
ROM Verification Mode 2
Parameter
Symbol
Limit Values
Unit
min.
typ
max.
ALE pulse width
tAWD
–
2 tCLCL
–
ns
ALE period
tACY
–
12 tCLCL
–
ns
Data valid after ALE
tDVA
–
–
4 tCLCL
ns
Data stable after ALE
tDSA
8 tCLCL
–
–
ns
P3.5 setup to ALE low
tAS
–
tCLCL
–
ns
Oscillator frequency
1/ tCLCL
3.5
–
24
MHz
t ACY
t AWD
ALE
t DSA
t DVA
Port 0
Data Valid
t AS
P3.5
MCT02613
Figure 33
ROM Verification Mode 2
Semiconductor Group
66
C517A
0.2 VCC+0.9
VDD
Test Points
VDD
0.2 VCC -0.1
0.45 V
MCT00039
VDD
AC Inputs during testing are driven at VDD - 0.5 V for a logic ’1’ and 0.45 V for a logic ’0’.
Timing measurements are made at VIHmin for a logic ’1’ and VILmax for a logic ’0’.
Figure 34
AC Testing: Input, Output Waveforms
Timing Reference
Points
VLoad
VLoad -0.1 V
VOL +0.1 V
MCT00038
For timing purposes a port pin is no longer floating when a 100 mV change from load voltage
occurs and begins to float when a 100 mV change from the loaded VOH/VOL level occurs.
IOL/IOH ≥ ± 20 mA
Figure 35
AC Testing : Float Waveforms
Crystal Oscillator Mode
Driving from External Source
C
N.C.
XTAL1
XTAL1
3.5-24 MHz
External Oscillator
Signal
C
XTAL2
Crystal Mode : C = 20 pF ± 10 pF
(incl. stray capacitance)
Figure 36
Recommended Oscillator Circuits for Crystal Oscillator
Semiconductor Group
67
XTAL2
MCS03339
C517A
GPR05365
Plastic Package, P-MQFP-100-2 (SMD)
(Plastic Metric Quad Flat Package)
Figure 37
P-LCC-100-2 Package Outlines
Semiconductor Group
68
C517A
0.5 min.
3.81±0.5
4.58 max.
Plastic Package, P-LCC-84-2 (SMD)
(Plastic Leaded Chip-Carrier)
0.2
1.27 x 45˚
28.2 ±0.5 2)
0.18
0.1
84x
25.4
M
29.31±0.076
30.23 ±0.13
1)
1.27
0.43 ±0.1
84
1
29.31±0.076
30.23 ±0.13
Index Marking
1.14 x 45˚
1)
1) Does not include plastic or metal protrusions of 0.25 max. per side
2) Dimension from center to center
Figure 38
P-LCC-84-2 Package Outline
Sorts of Packing
Package outlines for tubes, trays etc. are contained in our
Data Book “Package Information”
SMD = Surface Mounted Device
Semiconductor Group
69
Dimensions in mm
C517A
Semiconductor Group
70