Data Sheet No. PD94143 IRU3011 5-BIT PROGRAMMABLE SYNCHRONOUS BUCK CONTROLLER IC DESCRIPTION FEATURES Dual Layout compatible with HIP6004A Designed to meet Intel specification of VRM8.4 for Pentium III On-Board DAC programs the output voltage from 1.3V to 3.5V. The IRU3011 remains on for VID code of (11111). Loss-less Short Circuit Protection Synchronous operation allows maximum efficiency Patented architecture allows fixed frequency operation as well as 100% duty cycle during dynamic load Over-Voltage Protection Output Soft-Start High current totem pole driver for direct driving of the external power MOSFET Power Good Function The IRU3011 controller IC is specifically designed to meet Intel specification for latest Pentium III microprocessor applications as well as the next generation P6 family processors. These products feature a patented topology that in combination with a few external components as shown in the typical application circuit,will provide in excess of 20A of output current for an on-board DC/DC converter while automatically providing the right output voltage via the 5-bit internal DAC. These devices also features, loss less current sensing by using the RDS(ON) of the high side Power MOSFET as the sensing resistor, a Power Good window comparator that switches its open collector output low when the output is outside of a ±10% window and an Over-Voltage Protection output. Other features of the device are: Under-voltage lockout for both 5V and 12V supplies, an external programmable soft-start function as well as programming the oscillator frequency by using an external capacitor. APPLICATIONS Pentium III & Pentium II processor DC to DC converter application Low Cost Pentium with AGP TYPICAL APPLICATION 5V L1 Q1 C5 C1 Note: Pentium II and Pentium III are trade marks of Intel Corp. C8 C3 R2 VOUT (1.3V - 3.5V) L2 Q2 R1 C10 R4 R3 C6 C11 C4 D1 12V R7 V12 CS+ HDrv NC/Gnd NC/ Boot CS- LDrv Gnd NC/Sen R9 C12 V FB C13 IRU3011 R5 SS C2 D4 R8 V5/Comp D3 D2 D1 D0 Ct/Rt OVP PGd C9 VID4 C7 VID3 R6 VID2 Power Good C14 VID1 VID0 OVP Figure 1 - Typical application of the IRU3011. PACKAGE ORDER INFORMATION TA (8C) 0 To 70 Rev. 1.6 08/20/02 DEVICE IRU3011CW PACKAGE 20-Pin Plastic SOIC WB (W) www.irf.com VID VOLTAGE RANGE 1.3V to 3.5V 1 IRU3011 ABSOLUTE MAXIMUM RATINGS V5 Supply Voltage .................................................... V12 Supply Voltage .................................................. Storage Temperature Range ...................................... Operating Junction Temperature Range ...................... 7V 20V -65°C To 150°C 0°C To 125°C PACKAGE INFORMATION 20-PIN WIDE BODY PLASTIC SOIC (W) TOP VIEW NC 1 20 Ct CS+ 2 19 OVP SS 3 18 V12 D0 4 17 LDrv D1 5 16 Gnd D2 6 15 NC D3 7 14 HDrv D4 8 13 CS- V5 9 12 PGd V FB 10 11 NC uJA =858C/W ELECTRICAL SPECIFICATIONS Unless otherwise specified, these specifications apply over V12=12V, V5=5V and TA=0 to 70°C. Typical values refer to TA=25°C. Low duty cycle pulse testing is used which keeps junction and case temperatures equal to the ambient temperature. PARAMETER VID Section DAC Output Voltage (Note 1) DAC Output Line Regulation DAC Output Temp Variation VID Input LO VID Input HI VID Input Internal Pull-Up Resistor to V5 Power Good Section Under-Voltage lower trip point Under-Voltage upper trip point UV Hysterises Over-Voltage upper trip point Over-Voltage lower trip point OV Hysteresis Power Good Output LO Power Good Output HI Soft-Start Section Soft-Start Current 2 SYM TEST CONDITION MIN TYP MAX UNITS 0.99Vs Vs 1.01Vs 0.1 0.5 0.4 V % % V V KV 0.91Vs V V V V V V V V 2 27 VOUT Ramping Down VOUT Ramping Up VOUT Ramping Up VOUT Ramping Down 0.89Vs 0.015Vs 1.09Vs 0.015Vs RL=3mA RL=5K Pull-Up to 5V CS+=0V, CS-=5V www.irf.com 0.90Vs 0.92Vs 0.02Vs 1.10Vs 1.08Vs 0.02Vs 4.8 10 0.025Vs 1.11Vs 0.025Vs 0.4 mA Rev. 1.6 08/20/02 IRU3011 PARAMETER UVLO Section UVLO Threshold-12V UVLO Hysteresis-12V UVLO Threshold-5V UVLO Hysteresis-5V Error Comparator Section Input Bias Current Input Offset Voltage Delay to Output Current Limit Section CS Threshold Set Current CS Comp Offset Voltage Hiccup Duty Cycle Supply Current Operating Supply Current SYM TEST CONDITION Supply Ramping Up Supply Ramping Up MIN TYP MAX UNITS 9.2 0.3 4.1 0.2 10 0.4 4.3 0.3 10.8 0.5 4.5 0.4 V V V V 2 +2 100 mA mV ns 240 +5 2 mA mV % -2 VDIFF=10mV 160 -5 200 Css=0.1mF Output Drivers Section Rise Time Fall Time Dead Band Time Oscillator Section Osc Frequency Osc Valley Osc Peak Over-Voltage Section OVP Drive Current CL=3000pF: V5 V12 20 14 CL=3000pF CL=3000pF CL=3000pF 100 70 70 200 100 130 300 ns ns ns Ct=150pF 190 220 250 0.2 KHz V V mA V5 mA Note 1: Vs refers to the set point voltage given in Table 1. D4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 D2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 D1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 D0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Vs 1.30 1.35 1.40 1.45 1.50 1.55 1.60 1.65 1.70 1.75 1.80 1.85 1.90 1.95 2.00 2.05 D4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 D3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 D2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 D1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 D0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Vs 2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 Table 1 - Set point voltage vs. VID codes. Rev. 1.6 08/20/02 www.irf.com 3 IRU3011 PIN DESCRIPTIONS PIN# 1 2 PIN SYMBOL NC CS+ 3 SS 4 D0 5 D1 6 D2 7 D3 8 9 10 D4 V5 VFB 11 12 NC PGd 13 CS- 14 15 16 HDrv NC Gnd 17 18 LDrv V12 19 20 OVP Ct 4 PIN DESCRIPTION No connection. This pin is connected to the Drain of the power MOSFET of the Core supply and it provides the positive sensing for the internal current sensing circuitry. An external resistor programs the CS threshold depending on the RDS of the power MOSFET. An external capacitor is placed in parallel with the programming resistor to provide high frequency noise filtering. This pin provides the soft-start for the switching regulator. An internal current source charges an external capacitor that is connected from this pin to the ground which ramps up the outputs of the switching regulator, preventing the outputs from overshooting as well as limiting the input current. The second function of the Soft-Start cap is to provide long off time for the synchronous MOSFET or the Catch diode (HICCUP) during current limiting. LSB input to the DAC that programs the output voltage. This pin can be pulled up externally by a 10K resistor to either 3.3V or 5V supply. Input to the DAC that programs the output voltage. This pin can be pulled-up externally by a 10KV resistor to either 3.3V or 5V supply. Input to the DAC that programs the output voltage. This pin can be pulled-up externally by a 10K resistor to either 3.3V or 5V supply. MSB input to the DAC that programs the output voltage. This pin can be pulled-up externally by a 10K resistor to either 3.3V or 5V supply. This pin selects a range of output voltages for the DAC. 5V supply voltage. This pin is connected directly to the output of the Core supply to provide feedback to the Error comparator. No connection. This pin is an open collector output that switches LO when the output of the converter is not within ±10% (typ) of the nominal output voltage. When PGd pin switches LO the saturation voltage is less than 0.4V at 3mA. This pin is connected to the Source of the power MOSFET for the Core supply and it provides the negative sensing for the internal current sensing circuitry. Output driver for the high side power MOSFET. No connection. This pin serves as the ground pin and must be connected directly to the ground plane. A high frequency capacitor (0.1 to 1mF) must be connected from V5 and V12 pins to this pin for noise free operation. Output driver for the synchronous power MOSFET. This pin is connected to the 12 V supply and serves as the power Vcc pin for the output drivers. A high frequency capacitor (0.1 to 1mF) must be connected directly from this pin to ground pin in order to supply the peak current to the power MOSFET during the transitions. Over-voltage comparator output. This pin programs the oscillator frequency in the range of 50KHz to 500KHz with an external capacitor connected from this pin to the ground. www.irf.com Rev. 1.6 08/20/02 IRU3011 BLOCK DIAGRAM Enable V12 18 V5 9 Vset Enable UVLO Vset 4 D1 5 D2 6 D3 7 D4 8 Slope Comp 19 Gnd 16 HDrv 17 LDrv 13 CS- Soft Start & Fault Logic 2 CS+ 20 Ct 3 SS 12 PGd Osc Over Current 200uA Enable 1.18Vset OVP 14 V12 Enable 5Bit DAC, Ctrl Logic VFB PWM Control + D0 10 V12 1.1Vset 0.9Vset Figure 2 - Simplified block diagram of the IRU3011. Rev. 1.6 08/20/02 www.irf.com 5 IRU3011 TYPICAL APPLICATION Synchronous Operation (Dual Layout with HIP6004B) L1 L2 Q1 5V R10 Vcore R11 R1 C5 C1 C8 Q2 C3 C10 R4 R2 C15 R3 C6 C11 D1 R13 R9 C4 R7 12V V12 CS+ HDrv NC/ Boot NC/Gnd CS- LDrv Gnd C12 NC/Sen V FB C13 IRU3011 R5 SS D4 C2 R12 R8 V5/Comp D3 D2 D1 D0 Ct/Rt OVP PGd C9 Vcc3 C7 VID4 R6 VID3 Power Good VID2 C14 VID1 VID0 Figure 3 - Typical application of IRU3011 in an on board DC-DC converter providing the Core supply for microprocessor. Part # R5 R7 R8 R9 C4 C7 C9 C11 C12 C13 D1 HIP6004B O V V V V O O V V V V IRU3011 S O O V O V V O O O O S - Short O - Open V - See IR or Harris parts list for the value Table 2 - Components that need to be modified to make the dual layout work for IRU3011and HIP6004B. 6 www.irf.com Rev. 1.6 08/20/02 IRU3011 IRU3011 and HIP6004B Dual Layout Parts List Ref Desig Description Q1 MOSFET Q2 MOSFET L1 Inductor Qty 1 1 1 L2 Inductor 1 C1 C2, 9 C3 C5 C6 C7 C8 C10 C14 C15 R1 R2, 3, 4 R5 R6 R9 R10 R11 R12 R13 Capacitor, Electrolytic Capacitor, Ceramic Capacitor, Electrolytic Capacitor, Ceramic Capacitor, Ceramic Capacitor, Ceramic Capacitor, Ceramic Capacitor, Electrolytic Capacitor, Ceramic Capacitor, Ceramic Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor 1 2 2 1 1 1 1 6 1 1 1 3 1 1 1 1 1 1 1 Part # IRL3103s, TO-263 package IRL3103D1S, TO-263 package L=1mH, 5052 core with 4 turns of 1.0mm wire L=2.7mH, 5052B core with 7 turns of 1.2mm wire 10MV470GX, 470mF, 10V 1mF, 0603 10MV1200GX, 1200mF, 10V 220pF, 0603 1mF, 0805 150pF, 0603 1000pF, 0603 6MV1500GX, 1500mF, 6.3V 0.1mF, 0603 4.7mF, 1206 3.3KV, 5%, 0603 4.7V, 5%, 1206 0V, 0603 10KV, 5%, 0603 100V, 1%, 0603 220V, 1%, 0603 330V, 1%, 0603 22KV, 1%, 0603 10V, 5%, 0603 Manuf IR IR Micro Metal Micro Metal Sanyo Sanyo Sanyo Note 1: R10, R11, C15, R9, and R12 set the Vcore 2% higher for level shift to reduce CPU transient voltage. Rev. 1.6 08/20/02 www.irf.com 7 IRU3011 APPLICATION INFORMATION An example of how to calculate the components for the application circuit is given below. Assuming, two sets of output conditions that this regulator must meet, a) Vo=2.8V, Io=14.2A, DVo=185mV, DIo=14.2A b) Vo=2V, Io=14.2A, DVo=140mV, DIo=14.2A the regulator design will be done such that it meets the worst case requirement of each condition. Output Capacitor Selection The first step is to select the output capacitor. This is done primarily by selecting the maximum ESR value that meets the transient voltage budget of the total DVo specification. Assuming that the regulators DC initial accuracy plus the output ripple is 2% of the output voltage, then the maximum ESR of the output capacitor is calculated as: ESR [ 100 = 7mV 14.2 This intentional voltage level shifting during the load transient eases the requirement for the output capacitor ESR at the cost of load regulation. One can show that the new ESR requirement eases up by half the total trace resistance. For example, if the ESR requirement of the output capacitors without voltage level shifting must be 7mV then after level shifting the new ESR will only need to be 8.5mV if the trace resistance is 5mV (7 + 5/2=9.5). However, one must be careful that the combined “voltage level shifting” and the transient response is still within the maximum tolerance of the Intel specification. To insure this, the maximum trace resistance must be less than: Rs [ 23(Vspec - 0.023Vo - DVo) / DI Where : Rs = Total maximum trace resistance allowed Vspec = Intel total voltage spec Vo = Output voltage DVo = Output ripple voltage DI = load current step The Sanyo MVGX series is a good choice to achieve both the price and performance goals. The 6MV1500GX, 1500mF, 6.3V has an ESR of less than 36mV typical. Selecting 6 of these capacitors in parallel has an ESR of ≈ 6mV which achieves our low ESR goal. For example, assuming: Vspec = ±140mV = ±0.1V for 2V output Vo = 2V DVo = assume 10mV = 0.01V DI = 14.2A Other type of electrolytic capacitors from other manufacturers to consider are the Panasonic FA series or the Nichicon PL series. Then the Rs is calculated to be: Reducing the Output Capacitors Using Voltage Level Shifting Technique The trace resistance or an external resistor from the output of the switching regulator to the Slot 1 can be used to the circuit advantage and possibly reduce the number of output capacitors, by level shifting the DC regulation point when transitioning from light load to full load and vice versa. To accomplish this, the output of the regulator is typically set about half the DC drop that results from light load to full load. For example, if the total resistance from the output capacitors to the Slot 1 and back to the Gnd pin of the device is 5mV and if the total DI, the change from light load to full load is 14A, then the output voltage measured at the top of the resistor divider which is also connected to the output capacitors in this case, must be set at half of the 70mV or 35mV higher than the DAC voltage setting. 8 Rs [ 23(0.140 - 0.0232 - 0.01) / 14.2 = 12.6mV However, if a resistor of this value is used, the maximum power dissipated in the trace (or if an external resistor is being used) must also be considered. For example if Rs=12.6mV, the power dissipated is: Io23Rs = 14.22312.6 = 2.54W This is a lot of power to be dissipated in a system. So, if the Rs=5mV, then the power dissipated is about 1W which is much more acceptable. If level shifting is not implemented, then the maximum output capacitor ESR was shown previously to be 7mV which translated to ≈ 6 of the 1500mF, 6MV1500GX type Sanyo capacitors. With Rs=5mV, the maximum ESR becomes 9.5mV which is equivalent to ≈ 4 caps. Another important consideration is that if a trace is being used to implement the resistor, the power dissipated by the trace increases the case temperature of the output capacitors which could seriously effect the life time of the output capacitors. www.irf.com Rev. 1.6 08/20/02 IRU3011 Output Inductor Selection The output inductance must be selected such that under low line and the maximum output voltage condition, the inductor current slope times the output capacitor ESR is ramping up faster than the capacitor voltage is drooping during a load current step. However, if the inductor is too small, the output ripple current and ripple voltage become too large. One solution to bring the ripple current down is to increase the switching frequency, however, that will be at the cost of reduced efficiency and higher system cost. The following set of formulas are derived to achieve the optimum performance without many design iterations. The maximum output inductance is calculated using the following equation: L = ESR3C3(V IN(MIN) - Vo(MAX) ) / (23DI) L = 0.006390003(4.75 - 2.8) / (2314.2) = 3.7mH Assuming that the programmed switching frequency is set at 200KHz, an inductor is designed using the Micrometals’ powder iron core material. The summary of the design is outlined below: The selected core material is Powder Iron, the selected core is T50-52D from Micro Metal wounded with 8 turns of #16 AWG wire, resulting in 3mH inductance with ≈ 3mV of DC resistance. Assuming L=3mH and Fsw=200KHz(switching frequency), the inductor ripple current and the output ripple voltage is calculated using the following set of equations: Vsw = Vsync = Io3RDS D ≈ (Vo + Vsync) / (V IN - Vsw + Vsync) TON = D3T TOFF = T - TON DIr = (Vo + Vsync)3TOFF / L DVo = DIr3ESR Rev. 1.6 08/20/02 T = 1 / 200000 = 5ms Vsw = Vsync = 14.230.019 = 0.27V D ≅ (2.8 + 0.27) / (5 - 0.27 + 0.27) = 0.61 TON = 0.6135 = 3.1ms TOFF = 5 - 3.1 = 1.9ms DIr = (2.8 + 0.27)31.9 / 3 = 1.94A DVo = 1.9430.006 = 0.011V = 11mV Power Component Selection Assuming IRL3103 MOSFETs as power components, we will calculate the maximum power dissipation as follows: For high-side switch the maximum power dissipation happens at maximum Vo and maximum duty cycle. Where: VIN(MIN) = Minimum input voltage For Vo=2.8V and DI=14.2A T ≡ Switching Period D ≡ Duty Cycle Vsw ≡ High-side MOSFET ON Voltage RDS ≡ MOSFET On-Resistance Vsync ≡ Synchronous MOSFET ON Voltage DIr ≡ Inductor Ripple Current DVo ≡ Output Ripple Voltage T = 1/Fsw In our example for Vo=2.8V and 14.2A load, assuming IRL3103 MOSFET for both switches with maximum on resistance 0f 19mV, we have: DMAX ≅ (2.8 + 0.27) / (4.75 - 0.27 + 0.27) = 0.65 PDH = DMAX3Io23RDS(MAX) PDH = 0.65314.2230.029 = 3.8W RDS(MAX) = Maximum RDS(ON) of the MOSFET at 1258C For synch MOSFET, maximum power dissipation happens at minimum Vo and minimum duty cycle. DMIN ≅ (2 + 0.27) / (5.25 - 0.27 + 0.27) = 0.43 PDS = (1 - DMIN)3Io23RDS(MAX) PDS = (1 - 0.43)314.2230.029 = 3.33W Heat Sink Selection Selection of the heat sink is based on the maximum allowable junction temperature of the MOSFETS. Since we previously selected the maximum RDS(ON) at 1258C, then we must keep the junction below this temperature. Selecting TO-220 package gives uJC=1.88C/W (From the venders’ data sheet) and assuming that the selected heat sink is black anodized, the heat-sink-to-case thermal resistance is ucs=0.058C/W, the maximum heat sink temperature is then calculated as: Ts = TJ - PD3(uJC + ucs) Ts = 125 - 3.823(1.8 + 0.05) = 1188C With the maximum heat sink temperature calculated in the previous step, the heat-sink-to-air thermal resistance (uSA) is calculated as follows: Assuming TA = 358C: DT = Ts - TA = 118 - 35 = 838C Temperature Rise Above Ambient uSA = DT / PD = 83 / 3.82 = 228C/W www.irf.com 9 IRU3011 Next, a heat sink with lower uSA than the one calculated in the previous step must be selected. One way to do this is to simply look at the graphs of the “Heat Sink Temp Rise Above the Ambient” vs. the “Power Dissipation” given in the heat sink manufacturers’ catalog and select a heat sink that results in lower temperature rise than the one calculated in previous step. The following AAVID and Thermalloy heat sinks, meet this criteria. Co. Part # Thermalloy............................6078B AAVID...................................577002 Following the same procedure for the Schottky diode results in a heatsink with uSA=258C/W. Although it is possible to select a slightly smaller heatsink, for simplicity the same heatsink as the one for the high side MOSFET is also selected for the synchronous MOSFET. Switcher Current Limit Protection The PWM controller uses the MOSFET RDS(ON) as the sensing resistor to sense the MOSFET current and compares to a programmed voltage which is set externally via a resistor (Rcs) placed between the drain of the MOSFET and the “CS+” terminal of the IC as shown in the application circuit. For example, if the desired current limit point is set to be 22A and from our previous selection, the maximum MOSFET RDS(ON)=19mV, then the current sense resistor, Rcs is calculated as: Vcs = ICL3RDS = 2230.019 = 0.418V Rcs = Vcs / IB = (0.418V) / (200mA) = 2.1KV Where: IB = 200mA is the internal current setting of the IRU3011 Switcher Timing Capacitor Selection The switching frequency can be programmed using an external timing capacitor. The value of Ct can be approximated using the equation below: Fsw ≅ 3.5 3 10-5 Ct Where: Ct = Timing Capacitor FSW = Switching Frequency If, FSW = 200KHz: Ct ≅ 10 3.5 3 10-5 = 175pF 200 3 103 Switcher Output Voltage Adjust As it was discussed earlier, the trace resistance from the output of the switching regulator to the Slot 1 can be used to the circuit advantage and possibly reduce the number of output capacitors, by level shifting the DC regulation point when transitioning from light load to full load and vice versa. To account for the DC drop, the output of the regulator is typically set about half the DC drop that results from light load to full load. For example, if the total resistance from the output capacitors to the Slot 1 and back to the Gnd pin of the device is 5mV and if the total DI, the change from light load to full load is 14A, then the output voltage measured at the top of the resistor divider which is also connected to the output capacitors in this case, must be set at half of the 70mV or 35mV higher than the DAC voltage setting. To do this, the top resistor of the resistor divider, RTOP is set at 100V, and the bottom resistor, RB is calculated. For example, if DAC voltage setting is for 2.8V and the desired output under light load is 2.835V, then RB is calculated using the following formula: RB = 1003[VDAC /(Vo - 1.0043VDAC )] [V] RB = 1003[2.8 /(2.835 - 1.00432.800)] = 11.76KV Select 11.8KV, 1% Note: The value of the top resistor must not exceed 100V. The bottom resistor can then be adjusted to raise the output voltage. Soft-Start Capacitor Selection The soft-start capacitor must be selected such that during the start up when the output capacitors are charging up, the peak inductor current does not reach the current limit threshhold. A minimum of 1mF capacitor insures this for most applications. An internal 10mA current source charges the soft-start capacitor which slowly ramps up the inverting input of the PWM comparator VFB3. This insures the output voltage to ramp at the same rate as the soft-start cap thereby limiting the input current. For example, with 1mF and the 10mA internal current source the ramp up rate is (DV/Dt)=I/C=1V/100ms. Assuming that the output capacitance is 9000µF, the maximum start up current will be: I = 9000mF3(1V / 100ms) = 0.09A Input Filter It is recommended to place an inductor between the system 5V supply and the input capacitors of the switching regulator to isolate the 5V supply from the switching noise that occurs during the turn on and off of the switching components. Typically an inductor in the range of 1 to 3mH will be sufficient in this type of application. www.irf.com Rev. 1.6 08/20/02 IRU3011 Switcher External Shutdown The best way to shutdown the part is to pull down on the soft-start pin using an external small signal transistor such as 2N3904 or 2N7002 small signal MOSFET. This allows slow ramp up of the output, the same as the power up. Layout Considerations Switching regulators require careful attention to the layout of the components, specifically power components since they switch large currents. These switching components can create large amount of voltage spikes and high frequency harmonics if some of the critical components are far away from each other and are connected with inductive traces. The following is a guideline of how to place the critical components and the connections between them in order to minimize the above issues. 7) If the output voltage is to be adjusted, place resistor dividers close to the feedback pin. Note: Although, the device does not require resistor dividers and the feedback pin can be directly connected to the output, they can be used to set the outputs slightly higher to account for any output drop at the load due to the trace resistance. See the application note. 8) Place timing capacitor C7 close to pin 20 and softstart capacitor C2 close to pin 3. Component connections: Start the layout by first placing the power components: Note: It is extremely important that no data bus should be passing through the switching regulator section specifically close to the fast transition nodes such as PWM drives or the inductor voltage. 1) Place the input capacitors C3 and the high side MOSFET, Q1 as close to each other as possible Using 4 layer board, dedicate on layer to Gnd, another layer as the power layer for the 5V, 3.3V and Vcore. 2) Place the synchronous MOSFETs, Q2 and the Q1 as close to each other as possible with the intention that the connection from the source of Q1 and the drain of the Q2 has the shortest length. Connect all grounds to the ground plane using direct vias to the ground plane. 3) Place the snubber R4 & C7 between Q1 & Q2. 4) Place the output inductor, L2 and the output capacitors, C10 between the MOSFET and the load with output capacitors distributed along the slot 1 and close to it. 5) Place the bypass capacitors, C6 and C9 right next to 12V and 5V pins. C6 next to the 12V, pin 18 and C9 next to the 5V, pin 9. Use large low inductance/low impedance plane to connect the following connections either using component side or the solder side. a) b) c) d) e) f) C3 to Q1 Drain Q1 Source to Q2 Drain Q2 drain to L2 L2 to the output capacitors, C10 C10 to the slot 1 Input filter L1 to the C3 Connect the rest of the components using the shortest connection possible. 6) Place the IC such that the PWM output drives, pins 14 and 17 are relatively short distance from gates of Q1 and Q2. IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information Data and specifications subject to change without notice. 02/01 Rev. 1.6 08/20/02 www.irf.com 11 IRU3011 (W) SOIC Package 20-Pin Surface Mount, Wide Body H A B C R E DETAIL-A PIN NO. 1 L D 0.516 0.020 x 458 DETAIL-A K F G SYMBOL A B C D E F G I J K L R T I T J 20-PIN MIN MAX 12.598 12.979 1.018 1.524 0.66 REF 0.33 0.508 7.40 7.60 2.032 2.64 0.10 0.30 0.229 0.32 10.008 10.654 08 88 0.406 1.270 0.63 0.89 2.337 2.642 NOTE: ALL MEASUREMENTS ARE IN MILLIMETERS. 12 www.irf.com Rev. 1.6 08/20/02 IRU3011 PACKAGE SHIPMENT METHOD PKG DESIG W PACKAGE DESCRIPTION PIN COUNT PARTS PER TUBE PARTS PER REEL T&R Orientation 20 38 1000 Fig A SOIC, Wide Body 1 1 1 Feed Direction Figure A IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information Data and specifications subject to change without notice. 02/01 Rev. 1.6 08/20/02 www.irf.com 13