PD - 96189
IRFB4310ZGPbF
HEXFET® Power MOSFET
Applications
l High Efficiency Synchronous Rectification in SMPS
l Uninterruptible Power Supply
l High Speed Power Switching
l Hard Switched and High Frequency Circuits
D
G
S
Benefits
l Improved Gate, Avalanche and Dynamic dV/dt
Ruggedness
l Fully Characterized Capacitance and Avalanche
SOA
l Enhanced body diode dV/dt and dI/dt Capability
l Lead-Free
l Halogen-Free
VDSS
RDS(on) typ.
max.
ID (Silicon Limited)
100V
4.8m:
6.0m:
127A
ID (Package Limited)
120A
c
D
G
D
S
TO-220AB
IRFB4310ZGPbF
G
D
S
Gate
Drain
Source
Absolute Maximum Ratings
Symbol
ID @ TC = 25°C
ID @ TC = 100°C
ID @ TC = 25°C
IDM
PD @TC = 25°C
VGS
Parameter
Max.
127
90
120
560
250
1.7
± 20
18
-55 to + 175
d
Pulsed Drain Current
Maximum Power Dissipation
Linear Derating Factor
Gate-to-Source Voltage
Peak Diode Recovery
Operating Junction and
Storage Temperature Range
Soldering Temperature, for 10 seconds
(1.6mm from case)
Mounting torque, 6-32 or M3 screw
f
dv/dt
TJ
TSTG
Avalanche Characteristics
EAS (Thermally limited)
IAR
EAR
Single Pulse Avalanche Energy
Avalanche Current
Repetitive Avalanche Energy
c
e
g
Units
c
c
Continuous Drain Current, VGS @ 10V (Silicon Limited)
Continuous Drain Current, VGS @ 10V (Silicon Limited)
Continuous Drain Current, VGS @ 10V(Wire Bond Limited)
A
W
W/°C
V
V/ns
°C
300
x
x
10lb in (1.1N m)
130
See Fig. 14, 15, 22a, 22b,
mJ
A
mJ
Thermal Resistance
Symbol
RθJC
RθCS
RθJA
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Parameter
j
Junction-to-Case
Case-to-Sink, Flat Greased Surface
Junction-to-Ambient
jk
Typ.
Max.
Units
–––
0.50
–––
0.6
–––
62
°C/W
1
10/15/08
IRFB4310ZGPbF
Static @ TJ = 25°C (unless otherwise specified)
Symbol
V(BR)DSS
Parameter
Min. Typ. Max. Units
–––
–––
∆V(BR)DSS/∆TJ Breakdown Voltage Temp. Coefficient
RDS(on)
Static Drain-to-Source On-Resistance
–––
0.11
–––
V/°C Reference to 25°C, ID = 5mA
–––
4.8
6.0
mΩ VGS = 10V, ID = 75A
VGS(th)
Gate Threshold Voltage
2.0
–––
4.0
V
VDS = VGS, ID = 150µA
IDSS
Drain-to-Source Leakage Current
–––
–––
20
µA
VDS = 100V, VGS = 0V
–––
–––
250
Gate-to-Source Forward Leakage
–––
–––
100
Gate-to-Source Reverse Leakage
–––
–––
-100
Internal Gate Resistance
–––
0.7
–––
RG
V
Conditions
100
IGSS
Drain-to-Source Breakdown Voltage
VGS = 0V, ID = 250µA
g
d
VDS = 80V, VGS = 0V, TJ = 125°C
nA
VGS = 20V
VGS = -20V
Ω
Dynamic @ TJ = 25°C (unless otherwise specified)
Symbol
Parameter
Min. Typ. Max. Units
Conditions
gfs
Qg
Forward Transconductance
150
–––
–––
S
VDS = 50V, ID = 75A
Total Gate Charge
–––
120
170
nC
ID = 75A
Qgs
Gate-to-Source Charge
–––
29
–––
Qgd
Gate-to-Drain ("Miller") Charge
Total Gate Charge Sync. (Qg - Qgd)
–––
35
Qsync
–––
85
VDS =50V
VGS = 10V
–––
g
ID = 75A, VDS =0V, VGS = 10V
td(on)
Turn-On Delay Time
–––
20
–––
tr
Rise Time
–––
60
–––
td(off)
Turn-Off Delay Time
–––
55
–––
RG = 2.7Ω
tf
Fall Time
–––
57
–––
VGS = 10V
Ciss
Input Capacitance
–––
6860
–––
Coss
Output Capacitance
–––
490
–––
VDS = 50V
Reverse Transfer Capacitance
–––
Coss eff. (ER) Effective Output Capacitance (Energy Related) –––
Coss eff. (TR) Effective Output Capacitance (Time Related)
–––
220
–––
ƒ = 1.0MHz, See Fig. 5
570
–––
VGS = 0V, VDS = 0V to 80V
920
–––
VGS = 0V, VDS
Crss
h
ns
VDD = 65V
ID = 75A
pF
VGS = 0V
g
i, See Fig. 11
= 0V to 80V h
Diode Characteristics
Symbol
Parameter
Min. Typ. Max. Units
IS
Continuous Source Current
ISM
(Body Diode)
Pulsed Source Current
VSD
(Body Diode)
Diode Forward Voltage
–––
–––
trr
Reverse Recovery Time
–––
40
–––
49
–––
58
–––
89
–––
2.5
Qrr
–––
–––
d
Reverse Recovery Charge
IRRM
Reverse Recovery Current
ton
Forward Turn-On Time
–––
c
560
1.3
A
MOSFET symbol
A
showing the
integral reverse
V
ns
G
p-n junction diode.
TJ = 25°C, IS = 75A, VGS = 0V
VR = 85V,
TJ = 25°C
TJ = 125°C
nC
D
TJ = 25°C
S
g
IF = 75A
di/dt = 100A/µs
g
TJ = 125°C
–––
A
TJ = 25°C
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Notes:
Calculated continuous current based on maximum allowable junction
temperature. Bond wire current limit is 120A. Note that current
limitations arising from heating of the device leads may occur with
some lead mounting arrangements.
Repetitive rating; pulse width limited by max. junction
temperature.
Limited by TJmax, starting TJ = 25°C, L = 0.047mH
RG = 25Ω, IAS = 75A, VGS =10V. Part not recommended for use
above the Eas value and test conditions.
ISD ≤ 75A, di/dt ≤ 600A/µs, VDD ≤ V(BR)DSS, TJ ≤ 175°C.
2
––– 127
Conditions
Pulse width ≤ 400µs; duty cycle ≤ 2%.
Coss eff. (TR) is a fixed capacitance that gives the same charging time
as Coss while VDS is rising from 0 to 80% VDSS .
Coss eff. (ER) is a fixed capacitance that gives the same energy as
Coss while VDS is rising from 0 to 80% VDSS.
When mounted on 1" square PCB (FR-4 or G-10 Material). For
recommended footprint and soldering techniques refer to
application note #AN-994.
Rθ is measured at TJ approximately 90°C.
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IRFB4310ZGPbF
1000
1000
VGS
15V
10V
8.0V
6.0V
5.5V
5.0V
4.8V
4.5V
100
BOTTOM
VGS
15V
10V
8.0V
6.0V
5.5V
5.0V
4.8V
4.5V
TOP
ID, Drain-to-Source Current (A)
ID, Drain-to-Source Current (A)
TOP
10
4.5V
BOTTOM
100
4.5V
≤ 60µs PULSE WIDTH
Tj = 175°C
≤ 60µs PULSE WIDTH
Tj = 25°C
1
10
0.1
1
10
100
0.1
VDS , Drain-to-Source Voltage (V)
100
Fig 2. Typical Output Characteristics
2.5
RDS(on) , Drain-to-Source On Resistance
(Normalized)
1000
ID, Drain-to-Source Current(Α)
10
VDS, Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
100
TJ = 175°C
10
TJ = 25°C
1
VDS = 50V
≤ 60µs PULSE WIDTH
0.1
2.0
3.0
4.0
5.0
6.0
7.0
ID = 75A
VGS = 10V
2.0
1.5
1.0
0.5
8.0
-60 -40 -20 0
VGS, Gate-to-Source Voltage (V)
12000
VGS, Gate-to-Source Voltage (V)
Coss = Cds + Cgd
8000
Ciss
6000
4000
Coss
2000
Crss
10
100
VDS, Drain-to-Source Voltage (V)
Fig 5. Typical Capacitance vs. Drain-to-Source Voltage
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ID= 75A
VDS = 80V
VDS= 50V
VDS= 20V
16
12
8
4
0
0
1
Fig 4. Normalized On-Resistance vs. Temperature
20
VGS = 0V,
f = 1 MHZ
Ciss = Cgs + Cgd, Cds SHORTED
Crss = Cgd
10000
20 40 60 80 100 120 140 160 180
TJ , Junction Temperature (°C)
Fig 3. Typical Transfer Characteristics
C, Capacitance (pF)
1
0
40
80
120
160
200
QG Total Gate Charge (nC)
Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage
3
IRFB4310ZGPbF
10000
ID, Drain-to-Source Current (A)
ISD , Reverse Drain Current (A)
1000
TJ = 175°C
100
TJ = 25°C
10
1
OPERATION IN THIS AREA
LIMITED BY R DS (on)
1000
1msec
100
10msec
10
1
Tc = 25°C
Tj = 175°C
Single Pulse
VGS = 0V
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
0.1
2.0
LIMITED BY PACKAGE
ID, Drain Current (A)
120
100
80
60
40
20
0
75
100
125
150
175
V(BR)DSS , Drain-to-Source Breakdown Voltage
140
50
10
100
Fig 8. Maximum Safe Operating Area
Fig 7. Typical Source-Drain Diode
Forward Voltage
25
1
VDS, Drain-toSource Voltage (V)
VSD , Source-to-Drain Voltage (V)
130
ID = 5mA
120
110
100
90
-60 -40 -20
TC, Case Temperature (°C)
0
20 40 60 80 100 120 140 160 180
TJ , Junction Temperature (°C)
Fig 9. Maximum Drain Current vs.
Case Temperature
Fig 10. Drain-to-Source Breakdown Voltage
EAS, Single Pulse Avalanche Energy (mJ)
3.0
2.5
2.0
Energy (µJ)
DC
0.1
0.1
1.5
1.0
0.5
0.0
600
I D
11A
19A
BOTTOM 75A
TOP
500
400
300
200
100
0
0
20
40
60
80
VDS, Drain-to-Source Voltage (V)
Fig 11. Typical COSS Stored Energy
4
100µsec
100
25
50
75
100
125
150
175
Starting TJ, Junction Temperature (°C)
Fig 12. Maximum Avalanche Energy Vs. DrainCurrent
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IRFB4310ZGPbF
1
Thermal Response ( ZthJC )
D = 0.50
0.20
0.10
0.1
0.05
τJ
0.02
0.01
0.01
R1
R1
τJ
τ1
R2
R2
τ2
τ1
R3
R3
R4
R4
τC
τ
τ2
τ3
τ4
τ3
Ci= τi/Ri
Ci i/Ri
SINGLE PULSE
( THERMAL RESPONSE )
τ4
Ri (°C/W)
0.018756
0.159425
0.320725
0.101282
τι (sec)
0.000373
0.000734
0.005665
0.115865
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
0.001
1E-006
1E-005
0.0001
0.001
0.01
0.1
t1 , Rectangular Pulse Duration (sec)
Fig 13. Maximum Effective Transient Thermal Impedance, Junction-to-Case
100
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming ∆Tj = 150°C and
Tstart =25°C (Single Pulse)
Avalanche Current (A)
Duty Cycle = Single Pulse
0.01
10
0.05
0.10
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming ∆Τ j = 25°C and
Tstart = 150°C.
1
0.1
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
tav (sec)
Fig 14. Typical Avalanche Current vs.Pulsewidth
EAR , Avalanche Energy (mJ)
140
Notes on Repetitive Avalanche Curves , Figures 14, 15:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a temperature far in
excess of Tjmax. This is validated for every part type.
2. Safe operation in Avalanche is allowed as long asTjmax is not exceeded.
3. Equation below based on circuit and waveforms shown in Figures 16a, 16b.
4. PD (ave) = Average power dissipation per single avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase
during avalanche).
6. Iav = Allowable avalanche current.
7. ∆T = Allowable rise in junction temperature, not to exceed Tjmax (assumed as
25°C in Figure 14).
tav = Average time in avalanche.
D = Duty cycle in avalanche = tav ·f
ZthJC(D, tav) = Transient thermal resistance, see Figures 13)
TOP
Single Pulse
BOTTOM 1% Duty Cycle
ID = 75A
120
100
80
60
40
20
0
25
50
75
100
125
150
175
Starting TJ , Junction Temperature (°C)
PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC
Iav = 2DT/ [1.3·BV·Zth]
EAS (AR) = PD (ave)·tav
Fig 15. Maximum Avalanche Energy vs. Temperature
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5
IRFB4310ZGPbF
24
ID = 1.0A
ID = 1.0mA
ID = 250µA
ID = 150µA
4.0
3.5
20
16
IRRM - (A)
VGS(th) Gate threshold Voltage (V)
4.5
3.0
2.5
12
8
2.0
1.5
4
1.0
0
-75 -50 -25
0
25
50
75
100 125 150 175
IF = 30A
VR = 85V
TJ = 125°C
TJ = 25°C
100 200 300 400 500 600 700 800 900 1000
dif / dt - (A / µs)
Fig 16. Threshold Voltage Vs. Temperature
Fig. 17 - Typical Recovery Current vs. dif/dt
24
600
20
500
16
400
QRR - (nC)
IRRM - (A)
TJ , Temperature ( °C )
12
8
4
0
300
200
IF = 45A
VR = 85V
IF = 30A
VR = 85V
100
TJ = 125°C
TJ = 25°C
TJ = 125°C
TJ = 25°C
0
100 200 300 400 500 600 700 800 900 1000
100 200 300 400 500 600 700 800 900 1000
dif / dt - (A / µs)
dif / dt - (A / µs)
Fig. 19 - Typical Stored Charge vs. dif/dt
Fig. 18 - Typical Recovery Current vs. dif/dt
600
500
QRR - (nC)
400
300
200
100
0
IF = 45A
VR = 85V
TJ = 125°C
TJ = 25°C
100 200 300 400 500 600 700 800 900 1000
dif / dt - (A / µs)
6
Fig. 20 - Typical Stored Charge vs. dif/dt
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IRFB4310ZGPbF
Driver Gate Drive
D.U.T
+
-
-
*
RG
•
•
•
•
***
D.U.T. ISD Waveform
Reverse
Recovery
Current
+
dv/dt controlled by RG
Driver same type as D.U.T.
I SD controlled by Duty Factor "D"
D.U.T. - Device Under Test
VDD
**
P.W.
Period
VGS=10V
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
-
D=
Period
P.W.
+
+
-
Body Diode Forward
Current
di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt
Re-Applied
Voltage
Body Diode
VDD
Forward Drop
Inductor Curent
ISD
Ripple ≤ 5%
* Use P-Channel Driver for P-Channel Measurements
** Reverse Polarity for P-Channel
*** VGS = 5V for Logic Level Devices
Fig 21. Diode Reverse Recovery Test Circuit for HEXFET® Power MOSFETs
V(BR)DSS
15V
D.U.T
RG
VGS
20V
DRIVER
L
VDS
tp
+
V
- DD
IAS
tp
A
0.01Ω
I AS
Fig 22a. Unclamped Inductive Test Circuit
RD
V DS
Fig 22b. Unclamped Inductive Waveforms
VDS
90%
VGS
D.U.T.
RG
+
-VDD
10%
VGS
10V
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
td(on)
Fig 23a. Switching Time Test Circuit
td(off)
tr
tf
Fig 23b. Switching Time Waveforms
Id
Vds
Vgs
L
DUT
0
20K
1K
VCC
S
Vgs(th)
Qgodr
Fig 24a. Gate Charge Test Circuit
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Qgd
Qgs2 Qgs1
Fig 24b. Gate Charge Waveform
7
IRFB4310ZGPbF
TO-220AB Package Outline
Dimensions are shown in millimeters (inches)
TO-220AB Part Marking Information
(;$03/( 7+,6,6$1,5)%*3%)
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TO-220AB packages are not recommended for Surface Mount Application.
Note: For the most current drawing please refer to IR website at http://www.irf.com/package/
Data and specifications subject to change without notice.
This product has been designed and qualified for the Industrial market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information. 10/2008
8
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