D at a S h e e t , V 1. 2 , M ay 2 00 2 TC1775 32-Bit Single-Chip Microcontroller Microcontrollers N e v e r s t o p t h i n k i n g . Edition 2002-05 Published by Infineon Technologies AG, St.-Martin-Strasse 53, D-81541 München, Germany © Infineon Technologies AG 2002. All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as warranted characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Infineon Technologies is an approved CECC manufacturer. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide. Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. D at a S h e e t , V 1. 2 , M ay 2 00 2 TC1775 32-Bit Single-Chip Microcontroller Microcontrollers N e v e r s t o p t h i n k i n g . TC1775 Data Sheet Preliminary Revision History: 2002-05 Previous Versions: V1.1, 2001-08; V1.0, 2001-08; Page V1.2 Subjects (major changes since last revision) Changes from V1.1, 2001-08 to V1.2, 2002-05 – Status of data sheet changed from “Advance Information” into “Preliminary” 36 ADC features: example of 10-bit ADC conversion time added 54 Note below Figure 16 added 59 Column “Jitter” in Table 8 removed; the jitter is now defined in “PLL Parameters” on Page 82 and Figure 31; 2nd footnote for Table 8 added 60 Note on bottom extended “… specified by the crystal suppliers:” 66 Section “Package Parameters” added 68, 69, 70 Definition and values for pull-up/pull-down currents changed 71 Curves for pull-up/pull-down characteristics added 73 Formulas for conversion time tC corrected; fANA min./max. specification added 73 Definition of IAOV and kA improved 76 Note 1) for IOZ added 77 78 IDD max corrected; IDD active for VDDSB added; note for IID and ISL added tRFAnom (typ.) added 80 Figure 29 corrected 81 Figure 30 corrected 82, 83 PLL specification and parameters completed 84, 87, 89, Several AC timing parameter values added or corrected: t10, t11, t15, t20, 92, 94, 95 t21, t25, t45, t46, t47, t55, t61, t62 95 Definition of t61 and t62 changed several Formal changes Changes from V1.0, 2001-08 to V1.1, 2001-08 84 Reference for t31 and t32 to Page 90 added 89 t50 and t51 changed into TBD; note changed into “Will be guaranteed …” t31 and t32 (Data setup/hold to CLKIN in burst mode timing) changed; 90 note 1) added 95 t61 and t62 changed into TBD; note changed into “Will be guaranteed …” We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to: [email protected] Preliminary 32-Bit Single-Chip Microcontroller TriCore Family TC1775 • High Performance 32-bit TriCore CPU with 4-Stage Pipeline – 25 ns Instruction Cycle Time at 40 MHz CPU Clock • Dual Issue super-scalar implementation – Instruction triple issue • Circular Buffer and bit-reverse addressing modes for DSP algorithms • Flexible multi-master interrupt system • Very fast interrupt response time • Hardware controlled context switch for task switch and interrupts • 72 Kbytes of on-chip SRAM for data and time critical code • Independent Peripheral Control Processor (PCP) for low level driver support with 20 Kbytes code/parameter memory • Built-in calibration support • On-chip Flexible Peripheral Interface Bus (FPI Bus) for interconnections of functional units • Flexible External Bus Interface Unit (EBU) used for – Communication with external data memories and peripheral units – Instruction fetches from external Burst Flash program memories • On-Chip Peripheral Units – General Purpose Timer Array (GPTA) with a powerful set of digital signal filtering and timer functionality to realize autonomous and complex I/O management – Multifunctional General Purpose Timer Unit (GPTU) with three 32-bit timer/counters – Two Asynchronous/Synchronous Serial Channels (ASC0, ASC1) with baud rate generator, parity, framing and overrun error detection – Two High Speed Synchronous Serial Channels (SSC0, SSC1) with programmable data length and shift direction – TwinCAN module with two interconnected CAN nodes for high efficiency data handling via FIFO buffering and gateway data transfer – Serial Data Link module (SDLM) compliant to SAE Class B J1850 specification – Two Analog-to-Digital Converter Units (ADC0, ADC1) with 8-bit, 10-bit, or 12-bit resolution and 16 analog inputs each – Watchdog Timer and System Timer – Real Time Clock • Eleven 16-bit digital I/O ports and two 16-bit analog ports • On-chip Debug Support • Power Management System • Clock Generation Unit with PLL • Ambient temperature under bias: -40 °C to +125 °C • P-BGA-329 package Data Sheet 1 V1.2, 2002-05 TC1775 Preliminary Ordering Information The ordering code for Infineon microcontrollers provides an exact reference to the required product. This ordering code identifies: the derivative itself, i.e. its function set, the temperature range, and the package and the type of delivery. The TC1775 is available with the following ordering code: Type Ordering Code Package SAK-TC1775-L40E Q67121-C2285-A701 P-BGA-329 Data Sheet 2 Description 32-Bit Single-Chip Microcontroller 40 MHz -40 °C to +125 °C V1.2, 2002-05 16 16 16 16 JT A G IO BRKO UT B R K IN C on trol 16 16 5 2 16 16 16 16 16 16 SC U 16 P o rt 7 16 16 G PTU 16 P o rt 6 A DC 0 C e rb eru s & JT A G (P W R ) P ow e rW a tc hd o gR es et AD C1 P o rt 8 G PTA 2 P o rt 9 5 2 5 9 T ra ce & OCDS 8 2 ASC1 2 ASC0 1 6 K C od e-S R A M In te rru pt PCP C o re 4 K D a ta-S R A M (O v erlay F u nc tio na lity ) 16 P o rt 1 3 3 SSC1 F P I B us 3 SSC 0 64 4 Tw in C AN STM BCU In te rrup t FP I B u s TriC ore CPU FPI Interface 32 KB SRAM + 8 K B S tan d -b y S R A M OCDS O CDSE Port 5 Port 12 Port 11 3 Port 10 128 32 EBU C on trol 16 12 4 40 M H z f C P U m ax = 10 A d d re ss [2 5:16 ] 6 P ort 3 16 16 16 16 f R T C = 32 kH z EB U (E x te rn al B us U n it) P ort 4 RTC PLL J1850 32 8 K B B oo t R O M 32 K B S cratch P a d R A M 1 K B In stru ction C a ch e PM U (Program M em ory U nit) M C B 0 4671 A dd r. [1 5 :0] 16 1 6 A dd r./ D a ta [1 5 :0] C L K IN CLKO UT XTAL3 XTAL4 XTAL1 XTAL2 C o ntro l V DD V SS 1 6 A dd r./ D a ta (31 :1 6] Port 0 Data Sheet Port 1 Figure 1 Port 2 DM U (Data M em ory Unit) TC1775 Preliminary Block Diagram TC1775 Block Diagram V1.2, 2002-05 TC1775 Preliminary Logic Symbol TESTMODE Alternate Functions CLKIN CLKOUT HDRST PORST General Control NMI CFG 4 BYPASS CLKSEL N.C.1 N.C.2 Oscillators / PLL JTAG / OCDS 3 7 XTAL1 XTAL2 XTAL3 XTAL4 VDDOSC VSSOSC VDDPLL VSSPLL TC 1775 TRST TCK TDI TDO TMS OCDSE BRKIN BRKOUT VDD VDDP05 Digital Circuitry Power Supply 3 VDDP813 VDDSRAM VDDSB VSS 10 5 2 Data Sheet Port 5 16-Bit TRACE Port 6 16-Bit ADC0 Port 7 16-Bit ADC1 Port 8 16-Bit Port 9 16-Bit Port 10 16-Bit Port 11 16-Bit GPTA Port 12 16-Bit ADC0/1 J1850 / ASC0/1 Port 13 16-Bit GPTU / SSC0/1 / CAN VDDA0 ADC0 Analog Power Supply VSSA0 29 VAREF1 VAGND1 VSSSC VDDA1 VDDM ADC1 Analog Power Supply VSSA1 VSSM Figure 2 External Bus Interface VAREF0 VAGND0 6 VDDSC ADC0 / ADC1 Analog Power Supply Port 0 16-Bit Port 1 16-Bit Port 2 16-Bit Port 3 16-Bit Port 4 16-Bit MCA04679 TC1775 Logic Symbol 4 V1.2, 2002-05 TC1775 Preliminary Pin Configuration 1 2 3 A V DDSC V SSSC V SSM 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 AN 3 AN 6 AN 9 AN 11 AN 15 V SSA0 P12. 13 P 12 . 9 P 1 2. 5 P 1 2. 1 P13 15 P 13 . 11 P 13 . 8 P 1 3. 4 P 1 3. 2 P11. 15 P 11 . 12 P 1 1. 8 P 1 1. 5 P11. 4 A V D D S B P 13 . 13 P 13 . 9 P 1 3. 6 P 1 3. 3 P13. 0 P 11 . 13 P 1 1. 9 P 1 1. 6 P11. 3 B B AN 16 AN 17 AN 0 AN 4 AN 7 AN 10 AN 13 V A GN D0 P 1 2 . P12. 12 P 12 . 7 P 1 2. 6 P 1 2. 2 C AN 19 AN 20 V DDM AN 1 AN 5 AN 8 AN 14 V A RE F0 P 1 2 . 14 P12. 11 P 12 . 8 P 1 2. 4 P 1 2. 3 N .C . 2 P 13 . 14 P 13 . 10 P 1 3. 7 P 1 3. 1 P11. 14 P 11 . 10 P 1 1. 2 P 1 1. 0 P11. 1 C D AN 23 AN 24 AN 21 AN 18 AN 2 V DD AN 12 V DDA0 N .C . 1 P 12 . 10 V DD P 1 2. 0 V DD P 13 . 12 V DD P 1 3. 5 V SS P11. 11 P 11 . 7 N .C . 2 P 1 0. 13 P10. 14 D E AN 26 AN 27 AN 25 AN 22 P 10 . 15 P 1 0. 12 P 1 0. 10 P10. 11 E F AN 29 AN 30 AN 28 V SS V DD P 1 0. 9 P 1 0. 7 P10. 8 F G AN 31 P 10 . 5 P 1 0. 3 P 1 0. 4 P10. 6 G V DD V DD P813 P 1 0. 0 P 1 0. 1 P10. 2 H P 05 15 V DD P 81 3 P 81 3 P 81 3 V A REF1 V S S A 1 V A G ND1 H V DDA1 P 1 .0 J P 1.2 P 1 .4 P 1.5 P 1 .3 K P 1.6 P 1 .7 N .C . 2 V DD V SS V SS V SS V SS V SS V DD P 9 .9 P 9 .10 P 9.1 1 K L P 1.8 P 1 .9 P 1 .1 0 N .C . 2 V SS V SS V SS V SS V SS P 9.8 P 9 .6 P 9 .5 P 9 .7 L M P 1.12 P 1.1 3 P 1 .1 1 V DD V SS V SS V SS V SS V SS V DD P 9 .2 P 9 .4 P 9 .3 M P 9 .1 P 9 .0 P 8.1 5 N P 1.1 P 9.1 4 P 9 .1 2 P 9 .13 P 9.1 5 J P 05 P813 N P 0.0 P 1.1 4 P 1 .1 5 P 0 .1 V SS V SS V SS V SS V SS P 8.1 4 P P 0.4 P 0 .3 P 0.2 V DD V SS V SS V SS V SS V SS V DD P 8 .1 3 P 8 .12 P 8.1 1 P R C LK OUT P 0 .6 P 0.5 P 0 .7 P 8.8 P 8 .1 0 P 8 .9 P 8 .7 R T C LK IN P 0 .9 P 0.8 V DD V DD P 8 .6 P 8 .5 P 8 .4 T P 05 P813 P 8.1 P 8 .3 P 8 .2 P 8 .0 U U P 0.13 P 0.1 1 P 0 .1 0 P 0 .1 2 V P 0.15 P 0.1 4 P 4.0 V DD V SS CLK C LK S E L0 S E L 2 CLK S E L1 V W P 4.2 P 4 .1 P 4.3 P 4 .6 HD RST C FG 2 BY PASS C FG 3 W Y P 4.5 P 4 .4 P 4.7 P 4 .1 5 P 2 .2 V SS P 2 .1 2 V DD P 3 .3 V DD P 3.9 P05 AA P 4.9 P 4 .8 A B P 4.11 P 4.1 4 A C P 4.12 P 4.1 3 1 2 P 4 .1 0 P 2.0 P 2 .1 P 2 .4 N .C . 2 P 2 .3 3 4 P 2 .5 P 2 .7 P 2 .6 5 P 2 .8 P 2 .1 4 P 2.1 0 P 2 .1 3 P 2 .9 6 P 3 .1 P 3 .0 P 2 .1 1 P 2 .1 5 7 8 V DD P 5 .3 N .C . 1 P 5.8 P 5 .1 P 5 .4 P 5.7 P05 P 3 .5 P 3 .4 P 3 .2 9 P 3 .8 P 3 .7 P 3 .6 10 P 3 .1 2 P 3 .1 3 P 3 .1 1 P 3 .1 5 P 3 .1 0 P 3 .1 4 11 12 P 5 .0 P 5 .2 13 P 5 .5 P 5 .6 14 P 5 .1 5 V DD OCD SE NMI PO RST CFG 1 C FG 0 Y P 5.1 0 P 5 .1 3 TD O TR ST X TAL 4 V SS VDD V SS AA OSC P LL PLL N .C . 2 N .C . 1 P 5.1 1 P 5 .1 4 P 5.9 P 5.1 2 15 V DD TC K TMS XTA L 3 BRK IN V DD 20 21 SR AM 16 V DD BRK OUT TDI SRAM 17 18 19 OSC N .C . T E S T AB 2 MODE XTAL XTAL 2 1 22 AC 23 M C P 04680 Figure 3 Data Sheet TC1775 Pinning: P-BGA-329 Package (top view) 5 V1.2, 2002-05 TC1775 Preliminary Table 1 Symbol Pin Definitions and Functions Pin I/O P0 P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 P0.8 P0.9 P0.10 P0.11 P0.12 P0.13 P0.14 P0.15 Data Sheet In Functions Out N1 N4 P3 P2 P1 R3 R2 R4 T3 T2 U3 U2 U4 U1 V2 V1 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Port 0 Port 0 serves as 16-bit general purpose I/O port or as lower external address/data bus AD[15:0] (multiplexed bus mode) or data bus D[15:0] (demultiplexed bus mode) for the EBU. Port 0 is used as data input by an external bus master when accessing modules on the internal FPI Bus. AD0 / D0 Address/data bus line 0 / Data bus line 0 AD1 / D1 Address/data bus line 1 / Data bus line 1 AD2 / D2 Address/data bus line 2 / Data bus line 2 AD3 / D3 Address/data bus line 3 / Data bus line 3 AD4 / D4 Address/data bus line 4 / Data bus line 4 AD5 / D5 Address/data bus line 5 / Data bus line 5 AD6 / D6 Address/data bus line 6 / Data bus line 6 AD7 / D7 Address/data bus line 7 / Data bus line 7 AD8 / D8 Address/data bus line 8 / Data bus line 8 AD9 / D9 Address/data bus line 9 / Data bus line 9 AD10 / D10 Address/data bus line 10 / Data bus line 10 AD11 / D11 Address/data bus line 11 / Data bus line 11 AD12 / D12 Address/data bus line 12 / Data bus line 12 AD13 / D13 Address/data bus line 13 / Data bus line 13 AD14 / D14 Address/data bus line 14 / Data bus line 14 AD15 / D15 Address/data bus line 15 / Data bus line 15 6 V1.2, 2002-05 TC1775 Preliminary Table 1 Symbol Pin Definitions and Functions (cont’d) Pin I/O P1 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 P1.8 P1.9 P1.10 P1.11 P1.12 P1.13 P1.14 P1.15 Data Sheet In Functions Out H2 H3 J1 J4 J2 J3 K1 K2 L1 L2 L3 M3 M1 M2 N2 N3 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Port 1 Port 1 serves as 16-bit general purpose I/O port or as upper external address/data bus AD[31:16] (multiplexed bus mode) or data bus D[31:16] (demultiplexed bus mode) for the EBU. Port 1 is used as data input by an external bus master when accessing modules on the internal FPI Bus. AD16 / D16 Address/data bus line 16 / Data bus line 16 AD17 / D17 Address/data bus line 17/ Data bus line 17 AD18 / D18 Address/data bus line 18 / Data bus line 18 AD19 / D19 Address/data bus line 19 / Data bus line 19 AD20 / D20 Address/data bus line 20 / Data bus line 20 AD21 / D21 Address/data bus line 21 / Data bus line 21 AD22 / D22 Address/data bus line 22 / Data bus line 22 AD23 / D23 Address/data bus line 23 / Data bus line 23 AD24 / D24 Address/data bus line 24 / Data bus line 24 AD25 / D25 Address/data bus line 25 / Data bus line 25 AD26 / D26 Address/data bus line 26 / Data bus line 26 AD27 / D27 Address/data bus line 27 / Data bus line 27 AD28 / D28 Address/data bus line 28 / Data bus line 28 AD29 / D29 Address/data bus line 29 / Data bus line 29 AD30 / D30 Address/data bus line 30 / Data bus line 30 AD31 / D31 Address/data bus line 31 / Data bus line 31 7 V1.2, 2002-05 TC1775 Preliminary Table 1 Symbol Pin Definitions and Functions (cont’d) Pin I/O P2 P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 P2.8 P2.9 P2.10 P2.11 P2.12 P2.13 P2.14 P2.15 Data Sheet In Functions Out AB3 AA4 Y5 AC4 AB4 AA5 AC5 AB5 AA6 AC6 AB6 AC7 Y7 AB7 AA7 AC8 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Port 2 Port 2 serves as 16-bit general purpose I/O port or as lower external address bus for the EBU. When used as address bus, it outputs the addresses A[15:0] of an external access in demultiplexed bus mode. Port 2 is used as address input by an external bus master when accessing modules on the internal FPI Bus. A0 Address bus line 0 A1 Address bus line 1 A2 Address bus line 2 A3 Address bus line 3 A4 Address bus line 4 A5 Address bus line 5 A6 Address bus line 6 A7 Address bus line 7 A8 Address bus line 8 A9 Address bus line 9 A10 Address bus line 10 A11 Address bus line 11 A12 Address bus line 12 A13 Address bus line 13 A14 Address bus line 14 A15 Address bus line 15 8 V1.2, 2002-05 TC1775 Preliminary Table 1 Symbol Pin Definitions and Functions (cont’d) Pin I/O P3 P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 P3.8 P3.9 P3.101) P3.111) P3.121) P3.131) P3.141) P3.151) Data Sheet In Functions Out AB8 AA8 AC9 Y9 AB9 AA9 AC10 AB10 AA10 Y11 AC11 AB11 AA11 AA12 AC12 AB12 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O O O O O O O Port 3 Port 3 serves as 16-bit general purpose I/O port or as upper external address bus for the EBU. When used as address bus, it outputs the addresses A[25:16] of an external access in demultiplexed bus mode. P3[9:0] is used as address input by an external bus master when accessing modules on the internal FPI Bus. Port 3 also provides chip select output lines CS0 - CS3, CSEMU, and CSOVL. A16 Address bus line 16 A17 Address bus line 17 A18 Address bus line 18 A19 Address bus line 19 A20 Address bus line 20 A21 Address bus line 21 A22 Address bus line 22 A23 Address bus line 23 A24 Address bus line 24 A25 Address bus line 25 CS3 Chip select output line 3 Chip select output line 2 CS2 CS1 Chip select output line 1 Chip select output line 0 CS0 CSEMU Chip select output for emulator region CSOVL Chip select output for emulator overlay memory 9 V1.2, 2002-05 TC1775 Preliminary Table 1 Symbol Pin Definitions and Functions (cont’d) Pin I/O P4 P4.01) P4.11) P4.22) P4.31) P4.41) P4.51) P4.61) P4.71) P4.81) P4.91) P4.101) P4.111) P4.121) P4.131) P4.141) P4.151) Data Sheet In Functions Out V3 W2 W1 W3 Y2 Y1 W4 Y3 AA2 AA1 AA3 AB1 AC1 AC2 AB2 Y4 I/O I/O O O I/O I/O I/O I/O I O I I I/O O O I/O Port 4 Port 4 is used as general purpose I/O port but also serves as control bus for the EBU control lines. RD Read control line RD/WR Write control line ALE Address latch enable output ADV Address valid output Byte control line 0 BC0 Byte control line 1 BC1 BC2 Byte control line 2 Byte control line 3 BC3 Wait input / End of burst input WAIT/IND BAA Burst address advance output Chip select FPI input CSFPI Hold request input HOLD HLDA Hold acknowledge input/output Bus request output BREQ Code fetch status output CODE SVM Supervisor mode input/output The CODE signal has the same timing as the CSx signals which are located at Port 3. 10 V1.2, 2002-05 TC1775 Preliminary Table 1 Symbol Pin Definitions and Functions (cont’d) Pin I/O P5 P5.0 P5.1 P5.2 P5.3 P5.4 P5.5 P5.6 P5.7 P5.8 P5.9 P5.10 P5.11 P5.12 P5.13 P5.14 P5.15 Data Sheet In Functions Out AB13 AA13 AC13 Y13 AA14 AB14 AC14 AA15 Y15 AC15 AA16 AB16 AC16 AA17 AB17 Y17 O O O O O O O O O O O O O O O O Port 5 Port 5 serves as 16-bit general purpose I/O port or as CPU or PCP trace output port for the OCDS logic. TRACE0 CPU or PCP trace output 0 TRACE1 CPU or PCP trace output 1 TRACE2 CPU or PCP trace output 2 TRACE3 CPU or PCP trace output 3 TRACE4 CPU or PCP trace output 4 TRACE5 CPU or PCP trace output 5 TRACE6 CPU or PCP trace output 6 TRACE7 CPU or PCP trace output 7 TRACE8 CPU or PCP trace output 8 TRACE9 CPU or PCP trace output 9 TRACE10 CPU or PCP trace output 10 TRACE11 CPU or PCP trace output 11 TRACE12 CPU or PCP trace output 12 TRACE13 CPU or PCP trace output 13 TRACE14 CPU or PCP trace output 14 TRACE15 CPU or PCP trace output 15 11 V1.2, 2002-05 TC1775 Preliminary Table 1 Symbol Pin Definitions and Functions (cont’d) Pin I P6 P6.0 P6.1 P6.2 P6.3 P6.4 P6.5 P6.6 P6.7 P6.8 P6.9 P6.10 P6.11 P6.12 P6.13 P6.14 P6.15 B3 C4 D5 A4 B4 C5 A5 B5 C6 A6 B6 A7 D7 B7 C7 A8 Data Sheet I I I I I I I I I I I I I I I I I P7 P7.0 P7.1 P7.2 P7.3 P7.4 P7.5 P7.6 P7.7 P7.8 P7.9 P7.10 P7.11 P7.12 P7.13 P7.14 P7.15 In Functions Out B1 B2 D4 C1 C2 D3 E4 D1 D2 E3 E1 E2 F3 F1 F2 G1 I I I I I I I I I I I I I I I I Port 6 Port 6 provides the analog input lines for the AD Converter 0 (ADC0). AN0 Analog input 0 / VAREF[1] input for ADC0 AN1 Analog input 1 / VAREF[2] input for ADC0 AN2 Analog input 2 / VAREF[3] input for ADC0 AN3 Analog input 3 AN4 Analog input 4 AN5 Analog input 5 AN6 Analog input 6 AN7 Analog input 7 AN8 Analog input 8 AN9 Analog input 9 AN10 Analog input 10 AN11 Analog input 11 AN12 Analog input 12 AN13 Analog input 13 AN14 Analog input 14 AN15 Analog input 15 Port 7 Port 7 provides the analog input lines for the AD Converter 1 (ADC1). AN16 Analog input 16 / VAREF[1] input for ADC1 AN17 Analog input 17 / VAREF[2] input for ADC1 AN18 Analog input 18 / VAREF[3] input for ADC1 AN19 Analog input 19 AN20 Analog input 20 AN21 Analog input 21 AN22 Analog input 22 AN23 Analog input 23 AN24 Analog input 24 AN25 Analog input 25 AN26 Analog input 26 AN27 Analog input 27 AN28 Analog input 28 AN29 Analog input 29 AN30 Analog input 30 AN31 Analog input 31 12 V1.2, 2002-05 TC1775 Preliminary Table 1 Symbol Pin Definitions and Functions (cont’d) Pin I/O P8 P8.0 P8.1 P8.2 P8.3 P8.4 P8.5 P8.6 P8.7 P8.8 P8.9 P8.10 P8.11 P8.12 P8.13 P8.14 P8.15 U23 U20 U22 U21 T23 T22 T21 R23 R20 R22 R21 P23 P22 P21 N20 N23 Data Sheet I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O P9 P9.0 P9.1 P9.2 P9.3 P9.4 P9.5 P9.6 P9.7 P9.8 P9.9 P9.10 P9.11 P9.12 P9.13 P9.14 P9.15 In Functions Out N22 N21 M21 M23 M22 L22 L21 L23 L20 K21 K22 K23 J21 J22 J20 J23 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Port 8 Port 8 is a 16-bit bidirectional general purpose I/O port which also serves as input or output for the GPTA. IN0 / OUT0 line of GPTA IN1 / OUT1 line of GPTA IN2 / OUT2 line of GPTA IN3 / OUT3 line of GPTA IN4 / OUT4 line of GPTA IN5 / OUT5 line of GPTA IN6 / OUT6 line of GPTA IN7 / OUT7 line of GPTA IN8 / OUT8 line of GPTA IN9 / OUT9 line of GPTA IN10 / OUT10 line of GPTA IN11 / OUT11 line of GPTA IN12 / OUT12 line of GPTA IN13 / OUT13 line of GPTA IN14 / OUT14 line of GPTA IN15 / OUT15 line of GPTA Port 9 Port 9 is a 16-bit bidirectional general purpose I/O port which also serves as input or output for the GPTA. IN16 / OUT16 line of GPTA IN17 / OUT17 line of GPTA IN18 / OUT18 line of GPTA IN19 / OUT19 line of GPTA IN20 / OUT20 line of GPTA IN21 / OUT21 line of GPTA IN22 / OUT22 line of GPTA IN23 / OUT23 line of GPTA IN24 / OUT24 line of GPTA IN25 / OUT25 line of GPTA IN26 / OUT26 line of GPTA IN27 / OUT27 line of GPTA IN28 / OUT28 line of GPTA IN29 / OUT29 line of GPTA IN30 / OUT30 line of GPTA IN31 / OUT31 line of GPTA 13 V1.2, 2002-05 TC1775 Preliminary Table 1 Symbol Pin Definitions and Functions (cont’d) Pin I/O P10 P10.0 P10.1 P10.2 P10.3 P10.4 P10.5 P10.6 P10.7 P10.8 P10.9 P10.10 P10.11 P10.12 P10.13 P10.14 P10.15 H21 H22 H23 G21 G22 G20 G23 F22 F23 F21 E22 E23 E21 D22 D23 E20 Data Sheet I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O P11 P11.0 P11.1 P11.2 P11.3 P11.4 P11.5 P11.6 P11.7 P11.8 P11.9 P11.10 P11.11 P11.12 P11.13 P11.14 P11.15 In Functions Out C22 C23 C21 B23 A23 A22 B22 D20 A21 B21 C20 D19 A20 B20 C19 A19 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Port 10 Port 10 is a 16-bit bidirectional general purpose I/O port which also serves as input or output for the GPTA. IN32 / OUT32 line of GPTA IN33 / OUT33 line of GPTA IN34 / OUT34 line of GPTA IN35 / OUT35 line of GPTA IN36 / OUT36 line of GPTA IN37 / OUT37 line of GPTA IN38 / OUT38 line of GPTA IN39 / OUT39 line of GPTA IN40 / OUT40 line of GPTA IN41 / OUT41 line of GPTA IN42 / OUT42 line of GPTA IN43 / OUT43 line of GPTA IN44 / OUT44 line of GPTA IN45 / OUT45 line of GPTA IN46 / OUT46 line of GPTA IN47 / OUT47 line of GPTA Port 11 Port 11 is a 16-bit bidirectional general purpose I/O port which also serves as input or output for the GPTA. IN48 / OUT48 line of GPTA IN49 / OUT49 line of GPTA IN50 / OUT50 line of GPTA IN51 / OUT51 line of GPTA IN52 / OUT52 line of GPTA IN53 / OUT53 line of GPTA IN54 / OUT54 line of GPTA IN55 / OUT55 line of GPTA IN56 / OUT56 line of GPTA IN57 / OUT57 line of GPTA IN58 / OUT58 line of GPTA IN59 / OUT59 line of GPTA IN60 / OUT60 line of GPTA IN61 / OUT61 line of GPTA IN62 / OUT62 line of GPTA IN63 / OUT63 line of GPTA 14 V1.2, 2002-05 TC1775 Preliminary Table 1 Symbol Pin Definitions and Functions (cont’d) Pin I/O P12 P12.0 P12.1 P12.2 P12.3 P12.4 P12.5 P12.6 P12.7 P12.8 P12.9 P12.10 P12.11 P12.12 P12.13 P12.14 P12.15 Data Sheet In Functions Out D13 A13 B13 C13 C12 A12 B12 B11 C11 A11 D11 C10 B10 A10 C9 B9 O O O O O O I I I I I O I/O O I/O O Port 12 Port 12 is a 16-bit bidirectional general purpose I/O port or serves as ADC control port and SDLM/ASC I/O port. AD0EMUX0 ADC0 external multiplexer control 0 AD0EMUX1 ADC0 external multiplexer control 1 AD0EMUX2 ADC0 external multiplexer control 2 AD1EMUX0 ADC1 external multiplexer control 0 AD1EMUX1 ADC1 external multiplexer control 1 AD1EMUX2 ADC1 external multiplexer control 2 AD1EXTIN0 ADC1 external trigger input 0 AD1EXTIN1 ADC1 external trigger input 1 AD0EXTIN0 ADC0 external trigger input 0 AD0EXTIN1 ADC0 external trigger input 1 RXJ1850 SDLM receiver input TXJ1850 SDLM transmitter output RXD0A ASC0 receiver input/output A TXD0A ASC0 transmitter output A RXD1A ASC1 receiver input/output A TXD1A ASC1 transmitter output A 15 V1.2, 2002-05 TC1775 Preliminary Table 1 Symbol Pin Definitions and Functions (cont’d) Pin In Functions Out I/O P13 I/O I/O I/O I/O I/O O I/O I/O I/O O I/O I/O I/O I/O P13.0 P13.1 P13.2 B19 C18 A18 P13.3 B18 P13.4 A17 P13.5 D17 P13.6 B17 P13.7 C17 P13.8 A16 I/O P13.9 P13.10 B16 C16 I/O I/O P13.11 A15 I/O P13.12 P13.13 P13.14 P13.15 D15 B15 C15 A14 I O I O CLKSEL0 V21 CLKSEL1 V23 CLKSEL2 V22 Data Sheet I I I Port 13 Port 13 is a 16-bit bidirectional general purpose I/O port that is also used as input/output for the serial interfaces (ASC, SSC, CAN) and timers (GPTU). GPT0 GPTU I/O line 0 GPT1 GPTU I/O line 1 GPT2 GPTU I/O line 2 RXD0B ASC0 receiver input/output B GPT3 GPTU I/O line 3 TXD0B ASC0 transmitter output B GPT4 GPTU I/O line 4 RXD1B ASC1 receiver input/output B GPT5 GPTU I/O line 5 TXD1B ASC1 transmitter output B GPT6 GPTU I/O line 6 SCLK0 SSC0 clock input/output GPT7 GPTU I/O line 7 MRST0 SSC0 master receive / slave transmit input/output MTSR0 SSC0 master transmit / slave receive output/input SCLK1 SSC1 clock input/output MRST1 SSC1 master receive / slave transmit input/output MTSR1 SSC1 master transmit / slave receive output/input RXDCAN0 CAN receiver input 0 TXDCAN0 CAN transmitter output 0 RXDCAN1 CAN receiver input 1 TXDCAN1 CAN transmitter output 1 PLL Clock Selection Inputs These pins are sampled during power-on reset (PORST = low); they determine the division rate in the feedback path of the PLL (N-Factor). The latched values of these input pins are available in the PLL Clock Control Register PLL_CLC. The combination BYPASS = 1 and CLKSEL[2:0] = 000B during power-on reset is reserved. 16 V1.2, 2002-05 TC1775 Preliminary Table 1 Pin Definitions and Functions (cont’d) Symbol Pin In Functions Out BYPASS W22 I PLL Bypass Control Input BYPASS is used for direct drive mode operation of the clock circuitry. This pin is sampled during power-on reset (PORST = low). Its level is latched into the PLL Clock Control Register PLL_CLC. The combination BYPASS = 1 and CLKSEL[2:0] = 000B during power-on reset is reserved. CFG0 CFG1 CFG2 CFG3 Y23 Y22 W21 W23 I I I I Operation Configuration Inputs The configuration inputs define the boot options of the TC1775 after a hardware reset operation. TRST3) AA19 I JTAG Module Reset/Enable Input A low level at this pin resets and disables the JTAG module. A high level enables the JTAG module. TCK3) AB19 I JTAG Module Clock Input TDI4) AC19 I JTAG Module Serial Data Input TDO AA18 O JTAG Module Serial Data Output AB20 I JTAG Module State Machine Control Input OCDSE Y19 I OCDS Enable Input A low level on this pin during power-on reset (PORST = low) enables the on-chip debug support (OCDS). In addition, the level of this pin during power-on reset determines the boot configuration. BRKIN4) AC20 I OCDS Break Input A low level on this pin causes a break in the chip’s execution when the OCDS is enabled. In addition, the level of this pin during power-on reset determines the boot configuration. BRKOUT AC18 O OCDS Break Output A low level on this pin indicates that a programmable OCDS event has occurred. NMI4) I Non-Maskable Interrupt Input A high-to-low transition on this pin causes a NMI-Trap request to the CPU. 4) TMS 4) Data Sheet Y20 17 V1.2, 2002-05 TC1775 Preliminary Table 1 Pin Definitions and Functions (cont’d) Symbol Pin In Functions Out HDRST4) W20 I/O Hardware Reset Input/Reset Indication Output Assertion of this bidirectional open-drain pin causes a synchronous reset of the chip through external circuitry. This pin must be driven for a minimum duration. The internal reset circuitry drives this pin in response to a power-on, hardware, watchdog and power-down wake-up reset for a specific period of time. For a software reset, activation of this pin is programmable. PORST5) Y21 I Power-on Reset Input A low level on PORST causes an asynchronous reset of the entire chip. PORST is a fully asynchronous level sensitive signal. CLKIN T1 I EBU Clock Input CLKIN must be connected externally with CLKOUT. For finetuning of the external bus interface timing, this external connection can be an external delay circuit. CLKOUT R1 O Clock Output TEST MODE4) AB23 I Test Mode Select Input For normal operation of the TC1775, this pin should be connected to VDDP05. XTAL1 XTAL2 AC23 AC22 I O Oscillator/PLL/Clock Generator Input/Output Pins XTAL1 is the input to the main oscillator amplifier and input to the internal clock generator. XTAL2 is the output of the main oscillator amplifier circuit. For clocking the device from an external source, XTAL1 is driven with the clock signal while XTAL2 is left unconnected. For crystal oscillator operation XTAL1 and XTAL2 are connected to the crystal with the appropriate recommended oscillator circuitry. XTAL3 XTAL4 AB21 AA20 I O Real Time Clock Oscillator Input/Output XTAL3 and XTAL4 are the input and the output of the 32 kHz oscillator that is used for the Real Time Clock. Data Sheet 18 V1.2, 2002-05 TC1775 Preliminary Table 1 Pin Definitions and Functions (cont’d) Symbol Pin In Functions Out VDDOSC VSSOSC VDDPLL VSSPLL VSS AC21 – Main Oscillator Power Supply (2.5 V)6)7) AA21 – Main Oscillator Ground AA22 – PLL Power Supply (2.5 V)6)7) AA23 – PLL Ground F4, Y6, – V20, D18, K10 to K14, L10 to L14, M10 to M14, N10 to N14, P10 to P14 Ground VDD K4, P4 – V4, D6 Y10 D14 Y18 F20 K20 P20 Core Power Supply (2.5 V)6)7) Data Sheet 19 V1.2, 2002-05 TC1775 Preliminary Table 1 Pin Definitions and Functions (cont’d) Symbol Pin In Functions Out VDDP05 H4 M4 T4 Y8 Y12 – Ports 0 to 5 Power Supply (2.5 V)6)7) VDDP813 D8 D12 D16 H20 M20 T20 – Port 8-13 and Dedicated Pins Power Supply (3.3 to 5 V)8) VDDSRAM AC17, – AB18 SRAM (RAMs of DMU, PMU, and PCP) Power Supply (2.5 V)7) VDDSB VDDSC B14 – Stand-by Power Supply of 8 Kbyte SBSRAM (2.5 V)7) A1 – ADC Short Circuit/Broken Wire Logic Power Supply (5 V)8) VSSSC VDDM VSSM VDDA0 VSSA0 VDDA1 VSSA1 VAREF0 VAGND0 VAREF1 VAGND1 A2 – ADC Short Circuit/Broken Wire Logic Ground C3 – ADC Analog Part Power Supply (5 V)8) A3 – ADC Analog Part Ground D9 – ADC0 Analog Part Power Supply (2.5 V)6)7) A9 – ADC0 Analog Part Ground for VDDA0 H1 – ADC1 Analog Part Power Supply (2.5 V)6)7) G3 – ADC1 Analog Part Ground for VDDA1 C8 – ADC0 Reference Voltage8) B8 – ADC0 Reference Ground G2 – ADC1 Reference Voltage8) G4 – ADC1 Reference Ground Data Sheet 20 V1.2, 2002-05 TC1775 Preliminary Table 1 Pin Definitions and Functions (cont’d) Symbol Pin In Functions Out N.C.1 AB15, D10, Y14 – Not Connected 1 These pins must not be connected. N.C.2 AB22, C14, K3, AC3, L4, D21, Y16 – Not Connected 2 For compatibility reasons, these pins should not be connected. Any connection to 5 V does not harm the device. 1) After reset, an internal pull-up device is enabled for this pin. 2) After reset, an internal pull-down device is enabled for this pin. 3) These pins have an internal pull-down device connected. 4) These pins have an internal pull-up device connected. 5) The TC1775 BA11 step has an internal pull-up device connected to this pin. 6) The voltage on power supply pins marked with 8) has to be raised earlier or at least at the same time as on power supply pins marked with 6) (details see power supply section on Page 62). 7) In order to minimize the danger of latch-up conditions, these 2.5 V VDD power supply pins should be kept at the same voltage level during normal operating mode. This condition is best achieved by generating the 2.5 V power supplies from a single voltage source. The condition is also valid in normal operating mode if a separate stand-by power supply VDDSB is used. 8) The voltage on power supply pins marked with 8) has to be raised earlier or at least at the same time as on power supply pins marked with 6) (details see power supply section on Page 62). Data Sheet 21 V1.2, 2002-05 TC1775 Preliminary Parallel Ports The TC1775 has 196 digital input/output port lines, which are organized into twelve parallel 16-bit ports, Port 0 to Port 5 with 2.5 V nominal voltage (pin class B), and Port 8 to Port 13 with 3.0 to 5.25 V voltage (pin class A). Additionally, 32 analog input port lines are available, which are organized into two parallel 16-bit ports, Port 6 and Port 7. The digital parallel ports can be all used as general purpose I/O lines or they can perform input/output functions for the on-chip peripheral units. Port 0 to Port 5 are especially dedicated for the on-chip External Bus Interface Unit to communicate with external memories, external peripherals, or external debugging devices via an external bus interface. Port 8 to Port 13 can be assigned to the on-chip peripheral units for their specific I/O operations. An overview on the port-to-peripheral unit assignment is shown in Figure 4. Note: For further details on the three pin classes of the TC1775 I/O pins see also Table 10 on Page 64: A lte rna te F un ction s G P IO G P IO A ltern ate F u nc tio ns A d dre ss /D a ta B u s P o rt 0 P o rt 8 G PTA A d dre ss /D a ta B u s P o rt 1 P o rt 9 G PTA A dd res s B u s P o rt 2 TC 1775 P o rt 1 0 G P T A A dd res s B u s P o rt 3 B u s C on trol L ine s P a ralle l P o rts P o rt 1 1 G P T A P o rt 1 2 A D C 0 /1 / A S C 0 /1 / S D L M B u s C on trol L ine s P o rt 4 P o rt 1 3 O C D S T ra ce L ine s P o rt 5 P ort 6 ADC0 Figure 4 Data Sheet S S C 0 /1 / A S C 0/1 / G PTU / CAN P ort 7 ADC1 M C A 04734 Parallel Ports of the TC1775 22 V1.2, 2002-05 TC1775 Preliminary Serial Interfaces The TC1775 includes six serial peripheral interface units: – – – – Two Asynchronous/Synchronous Serial Interfaces (ASC0 and ASC1) Two High-Speed Synchronous Serial Interfaces (SSC0 and SSC1) One TwinCAN Interface One J1850 Serial Data Link Interface (SDLM) Asynchronous/Synchronous Serial Interfaces Figure 5 shows a global view of the functional blocks of the two Asynchronous/ Synchronous Serial interfaces ASC0 and ASC1. C lo ck C o ntro l fASC 0 P 12 .12 / RXD0A A d d res s D e co d er ASC0 M o d ule (K e rne l) RXD0 P 12 .13 / TXD0A TX D 0 P 13 .2 / RXD0B P 13 .3 / TXD0B In terru pt C o ntro l C lo ck C o ntro l A d d res s D e co d er P o rt 12 & P o rt 13 C on trol fASC 1 P 12 .14 / RXD1A ASC1 M o d ule (K e rne l) RXD1 P 12 .15 / TXD1A TX D 1 P 13 .4 / RXD1B P 13 .5 / TXD1B In terru pt C o ntro l M C B 04485 Figure 5 Data Sheet General Block Diagram of the ASC Interfaces 23 V1.2, 2002-05 TC1775 Preliminary Each ASC module, ASC0 and ASC1, communicates with the external world via two pairs of two I/O lines each. The RXD line is the receive data input signal (in Synchronous Mode also output). TXD is the transmit output signal. Clock control, address decoding, and interrupt service request control are managed outside the ASC module kernel. The Asynchronous/Synchronous Serial Interfaces provide serial communication between the TC1775 and other microcontrollers, microprocessors or external peripherals. The ASC supports full-duplex asynchronous communication and half-duplex synchronous communication. In Synchronous Mode, data is transmitted or received synchronous to a shift clock which is generated by the ASC internally. In Asynchronous Mode, 8-bit or 9-bit data transfer, parity generation, and the number of stop bits can be selected. Parity, framing, and overrun error detection are provided to increase the reliability of data transfers. Transmission and reception of data are double-buffered. For multiprocessor communication, a mechanism is included to distinguish address bytes from data bytes. Testing is supported by a loop-back option. A 13-bit baud rate generator provides the ASC with a separate serial clock signal that can be very accurately adjusted by a prescaler implemented as a fractional divider. Features: • Full duplex asynchronous operating modes – 8-bit or 9-bit data frames, LSB first – Parity bit generation/checking – One or two stop bits – Baud rate from 2.5 Mbit/s to 0.6 Bit/s (@ 40 MHz clock) – Multiprocessor mode for automatic address/data byte detection – Loop-back capability • Half-duplex 8-bit synchronous operating mode – Baud rate from 5 Mbit/s to 406.9 Bit/s (@ 40 MHz clock) • Double buffered transmitter/receiver • Interrupt generation – On a transmitter buffer empty condition – On a transmit last bit of a frame condition – On a receiver buffer full condition – On an error condition (frame, parity, overrun error) • Two pin pairs RXD/TXD for each ASC available at Port 12 or Port 13 Data Sheet 24 V1.2, 2002-05 TC1775 Preliminary High-Speed Synchronous Serial Interfaces Figure 6 shows a global view of the functional blocks of the two High-Speed Synchronous Serial interfaces SSC0 and SSC1. SSC0 M o du le (K e rne l) SCLK A d d res s D e co de r Slave Master fSSC 0 C lo ck C o ntro l In terru pt C o ntro l RXD P 13 .8 / M TS R 0 TX D RXD P 13 .7 / M R S T0 TX D S lav e P 13 .6 / SCLK0 M as te r P o rt C on trol In terru pt C o ntro l SSC1 M o du le (K e rne l) SCLK A d d res s D e co de r Slave Master fSSC 1 C lo ck C o ntro l RXD TX D RXD TX D S lav e M as te r P 13 .11 / M TS R 1 P 13 .10 / M R S T1 P 13 .9 / SCLK1 M C B 04486 Figure 6 General Block Diagram of the SSC Interfaces Each of the SSC modules has three I/O lines, located at Port 13. Each of the SSC modules is further supplied by separate clock control, interrupt control, address decoding, and port control logic. The SSC supports full-duplex and half-duplex serial synchronous communication up to 20 Mbit/s (@ 40 MHz module clock). The serial clock signal can be generated by the SSC itself (master mode) or can be received from an external master (slave mode). Data width, shift direction, clock polarity, and phase are programmable. This allows communication with SPI-compatible devices. Transmission and reception of data are double-buffered. A 16-bit baud rate generator provides the SSC with a separate serial clock signal. Data Sheet 25 V1.2, 2002-05 TC1775 Preliminary Features: • Master and slave mode operation – Full-duplex or half-duplex operation • Flexible data format – Programmable number of data bits: 2 to 16 bit – Programmable shift direction: LSB or MSB shift first – Programmable clock polarity: idle low or high state for the shift clock – Programmable clock/data phase: data shift with leading or trailing edge of the shift clock • Baud rate generation from 20 Mbit/s to 305.18 Bit/s (@ 40 MHz module clock) • Interrupt generation – On a transmitter empty condition – On a receiver full condition – On an error condition (receive, phase, baud rate, transmit error) • Three-pin interface – Flexible SSC pin configuration Data Sheet 26 V1.2, 2002-05 TC1775 Preliminary TwinCAN Interface Figure 7 shows a global view of the functional blocks of the TwinCAN module. C lo ck C o ntro l fCAN Tw inC A N M od u le K e rne l B its tre a m P roc es so r A d d res s D e co de r In terru pt C o ntro l TXDC0 RXDC0 M es sa ge B u ffe rs SR0 SR1 SR2 SR3 SR4 SR5 SR6 SR7 P 13 .13 / TXDCAN0 P 13 .12 / RXDCAN0 P o rt C o n tro l TXDC1 In terru pt C o ntro l Tim in g C o n tro l E rro r H a nd lin g C o ntrol RXDC1 P 13 .15 / TXDCAN1 P 13 .14 / RXDCAN1 M C B 04674 Figure 7 General Block Diagram of the TwinCAN Module The TwinCAN module has four I/O lines located at Port 13. The TwinCAN module is further supplied by a clock control, interrupt control, address decoding, and port control logic. The TwinCAN module contains two Full-CAN nodes operating independently or exchanging data and remote frames via a gateway function. Transmission and reception of CAN frames are handled in accordance to CAN specification V2.0 part B (active). Each of the two Full-CAN interfaces can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. Both CAN nodes share the TwinCAN module’s resources to optimize the CAN bus traffic handling and to minimize the CPU load. The flexible combination of Full-CAN functionality and the FIFO architecture reduces the efforts to fulfill the real-time requirements of complex embedded control applications. Improved CAN bus monitoring functionality as well as the increased number of message objects permit precise and convenient CAN bus traffic handling. Depending on the application, each of the thirty-two message objects can be individually assigned to one of the two CAN nodes. Gateway functionality allows automatic data exchange between two separate CAN bus systems to reduce CPU load and improve the real time behavior of the entire system. Data Sheet 27 V1.2, 2002-05 TC1775 Preliminary The bit timings for both CAN nodes are derived from the peripheral clock (fCAN) and are programmable up to a data rate of 1 Mbit/s. A pair of receive and transmit pins connect each CAN node to a bus transceiver. Features: • • • • Full CAN functionality conforms to CAN specification V2.0 B active Dedicated control registers are provided for each CAN node A data transfer rate up to 1 Mbit/s is supported Flexible and powerful message transfer control and error handling capabilities are implemented • Full-CAN functionality: 32 message objects can be individually – Assigned to one of the two CAN nodes – Configured as transmit or receive objects – Participate in a 2, 4, 8, 16 or 32 message buffer with FIFO algorithm – Setup to handle frames with 11-bit or 29-bit identifiers – Provided with programmable acceptance mask register for filtering – Monitored via a frame counter – Configured to Remote Monitoring Mode • Up to eight individually programmable interrupt nodes can be used • CAN Analyzer Mode for bus monitoring is implemented Data Sheet 28 V1.2, 2002-05 TC1775 Preliminary Serial Data Link Interface Figure 8 shows a global view of the functional blocks of the Serial Data Link Interface (SDLM). fSD LM C lo ck C o ntro l RXD A d d res s D e co de r S D LM M o du le (K e rne l) TXD P o rt C o n tro l P 12 .1 0 / R X J1 8 50 P 12 .1 1 / T X J 18 50 In terru pt C o ntro l M C B 04570 Figure 8 General Block Diagram of the SDLM Interface The SDLM module communicates with the external world via two I/O lines located at Port 12, the J1850 bus. The RXD line is the receive data input signal and TXD is the transmit data output signal. The Serial Data Link module (SDLM) provides serial communication to a J1850 based serial bus. J1850 bus transceivers must be implemented externally in a system. The SDLM module conforms to the SAE Class B J1850 Specification and is compatible to Class 2 protocol. General SDLM Features: • • • • • • • • Compliant to SAE Class B J1850 Specification Full support of GM Class 2 protocol Variable Pulse Width (VPW) format with 10.4 kbit/s High speed receive/transmit 4x mode with 41.6 kbit/s Digital noise filter Support of single byte headers or consolidated headers CRC generation and check Support of Block Mode for receive and transmit Data Sheet 29 V1.2, 2002-05 TC1775 Preliminary Data Link Operation Features: • • • • • • 11-byte transmit buffer Double buffered 11-byte receive buffer Support of In-Frame Response (IFR) types 1, 2, 3 Advanced interrupt handling for RX, TX, and error conditions All interrupt sources can be enabled/disabled individually Support of automatic IFR Transmission for IFR types 1 and 2 for 3-byte consolidated headers Note: The SDLM module does not support the Pulse Width Modulation (PWM) data format. Data Sheet 30 V1.2, 2002-05 TC1775 Preliminary Timer Units The TC1775 includes two timer units: – General Purpose Timer Unit (GPTU) – General Purpose Timer Array (GPTA) General Purpose Timer Unit Figure 9 shows a global view of all functional blocks of the General Purpose Timer Unit (GPTU) module. C lo ck C o ntro l fG PTU A d dre ss D e co de r In terru pt C o ntro l SR0 SR1 SR2 SR3 SR4 SR5 SR6 SR7 G P TU M o du le (K ern el) IN 0 IN 1 IN 2 IN 3 IN 4 IN 5 IN 6 IN 7 O UT0 O UT1 O UT2 O UT3 O UT4 O UT5 O UT6 O UT7 IO 0 IO 1 IO 2 IO 3 P ort C o ntro l IO 4 IO 5 IO 6 IO 7 P 13 .0 / G P T 0 P 13 .1 / G P T 1 P 13 .2 / G P T 2 P 13 .3 / G P T 3 P 13 .4 / G P T 4 P 13 .5 / G P T 5 P 13 .6 / G P T 6 P 13 .7 / G P T 7 M C B 04489 Figure 9 General Block Diagram of the GPTU Interface The GPTU consists of three 32-bit timers designed to solve such application tasks as event timing, event counting, and event recording. The GPTU communicates with the external world via eight inputs and eight outputs located at Port 13. The three timers of the GPTU module (T0, T1, and T2) can operate independently from each other, or can be combined: General Features: • • • • All timers are 32-bit precision timers with a maximum input frequency of fGPTU Events generated in T0 or T1 can be used to trigger actions in T2 Timer overflow or underflow in T2 can be used to clock either T0 or T1 T0 and T1 can be concatenated to form one 64-bit timer Data Sheet 31 V1.2, 2002-05 TC1775 Preliminary Features of T0 and T1: • Each timer has a dedicated 32-bit reload register with automatic reload on overflow • Timers can be split into individual 8-, 16-, or 24-bit timers with individual reload registers • Overflow signals can be selected to generate service requests, pin output signals, and T2 trigger events • Two input pins can define a count option Features of T2: • Count up or down is selectable • Operating modes: – Timer – Counter – Quadrature counter (incremental/phase encoded counter interface) • Options: – External start/stop, one-shot operation, timer clear on external event – Count direction control through software or an external event – Two 32-bit reload/capture registers • Reload modes: – Reload on overflow or underflow – Reload on external event: positive transition, negative transition, or both transitions • Capture modes: – Capture on external event: positive transition, negative transition, or both transitions – Capture and clear timer on external event: positive transition, negative transition, or both transitions • Can be split into two 16-bit counter/timers • Timer count, reload, capture, and trigger functions can be assigned to input pins. T0 and T1 overflow events can also be assigned to these functions • Overflow and underflow signals can be used to trigger T0 and/or T1 and to toggle output pins • T2 events are freely assignable to the service request nodes Data Sheet 32 V1.2, 2002-05 TC1775 Preliminary General Purpose Timer Array Figure 10 shows a global block diagram of the General Purpose Timer Array (GPTA) implementation. fG PTA C lo ck G e ne ra tio n U n it A d dre ss D e co de r S R 00 S R 01 In te rrup t C on trol A /D C on ve rter IO 0 IO 1 IN 0 IN 1 S R 52 S R 53 P TIN 00 P TIN 01 P TIN 10 P TIN 11 F ilte r & P res ca le r C e lls P ha se D iscrim ina tor Lo gic D u ty C ycle M ea su rem en t D igital P h as e L oc ke d Lo o p S ig na l G en era tio n U nit G lob a l T im er C e lls L oc al Tim e r C e lls G lo ba l T im ers IO Sharing Unit with Emergency Shut-Off C lo ck C on trol G PTA M odule K ernel IN 62 IN 63 IO 1 6 IO 1 7 AS0 AS1 A S 62 A S 63 O U T0 O U T1 O U T6 2 O U T6 3 In te rrup t C o ntro l U nit IO 1 4 IO 1 5 IO 3 0 IO 3 1 P ort C on trol IO 3 2 IO 3 3 IO 4 6 IO 4 7 IO 4 8 IO 4 9 IO 6 2 IO 6 3 P 8 .0 P 8 .1 P 8 .14 P 8 .15 P 9 .0 P 9 .1 P 9 .14 P 9 .15 P 1 0 .0 P 1 0 .1 P 10 .14 P 10 .15 P 1 1 .0 P 1 1 .1 P 11 .14 P 11 .15 M C B 04490 Figure 10 GPTA Module Block Diagram The GPTA module has 64 input lines and 64 output lines, which are connected with Port 8, Port 9, Port 10, and Port 11. The General Purpose Timer Array (GPTA) provides important digital signal filtering and timer support whose combination enables autonomous and complex functionalities. This architecture allows easy implementation and easy validation of any kind of timer functions. Data Sheet 33 V1.2, 2002-05 TC1775 Preliminary The General Purpose Timer Array (GPTA) provides a set of hardware modules required for high speed digital signal processing: • Filter and Prescaler Cells (FPC) support input noise filtering and prescaler operation. • Phase Discrimination Logic units (PDL) decode the direction information output by a rotation tracking system. • Duty Cycle Measurement Cells (DCM) provide pulse width measurement capabilities. • A Digital Phase Locked Loop unit (PLL) generates a programmable number of GPTA module clock ticks during an input signal’s period. • Global Timer units (GT) driven by various clock sources are implemented to operate as a time base for the associated “Global Timer Cells”. • Global Timer Cells (GTC) can be programmed to capture the contents of a Global Timer on an event that occurred at an external port pin or at an internal FPC output. A GTC may be also used to control an external port pin with the result of an internal compare operation. GTCs can be logically concatenated to provide a common external port pin with a complex signal waveform. • Local Timer Cells (LTC) operating in Timer, Capture, or Compare Mode may be also logically tied together to drive a common external port pin with a complex signal waveform. LTCs — enabled in Timer Mode or Capture Mode — can be clocked or triggered by – A prescaled GPTA module clock, – An FPC, PDL, DCM, PLL, or GTC output signal line, – An external port pin. Some input lines driven by processor I/O pads may be shared by an LTC and a GTC to trigger their programmed operation simultaneously. The following list summarizes all blocks supported: Clock Generation Unit (GPTA) • Filter and Prescaler Cell (FPC): – Six independent units – Three operating modes (Prescaler, Delayed Debounce Filter, Immediate Debounce Filter) – fGPTA down-scaling capability – fGPTA/2 maximum input signal frequency in Filter Mode • Phase Discriminator Logic (PDL): – Two independent units – Two operating modes (2 and 3 sensor signals) – fGPTA/4 maximum input signal frequency in 2-sensor mode, fGPTA/6 maximum input signal frequency in 3-sensor mode • Duty Cycle Measurement (DCM): – Four independent units – 0 to 100% margin and time-out handling Data Sheet 34 V1.2, 2002-05 TC1775 Preliminary – fGPTA maximum resolution – fGPTA/2 maximum input signal frequency • Digital Phase Locked Loop (PLL): – One unit – Arbitrary multiplication factor between 1 and 65535 – fGPTA maximum resolution – fGPTA/2 maximum input signal frequency GPTA Signal Generation Unit • Global Timers (GT): – Two independent units – Two operating modes (Free Running Timer and Reload Timer) – 24-bit data width – fGPTA maximum resolution – fGPTA/2 maximum input signal frequency • Global Timer Cell (GTC): – 32 independent units – Two operating modes (Capture, Compare and Capture after Compare) – 24-bit data width – fGPTA maximum resolution – fGPTA/2 maximum input signal frequency • Local Timer Cell (LTC): – 64 independent units – Three operating modes (Timer, Capture and Compare) – 16-bit data width – fGPTA maximum resolution – fGPTA/2 maximum input signal frequency Interrupt Control Unit • 111 interrupt sources generating 54 service requests I/O Sharing Unit • Able to process lines from FPC, GTC, and LTC • Emergency function Data Sheet 35 V1.2, 2002-05 TC1775 Preliminary Analog Digital Converters The two on-chip Analog-to-Digital Converter (ADC) modules of the TC1775 offer 8-bit, 10-bit, or 12-bit resolution including sample-and-hold functionality. The A/D converters operate using the method of the successive approximation. A multiplexer selects among up to 16 analog input channels for each ADC. Conversion requests are generated either under software control or by hardware. An automatic self-calibration adjusts the ADC modules to changing temperatures or process variations. Features: • • • • • • • • • • • • • • • • • • • 8-bit, 10-bit, 12-bit A/D conversion Successive approximation conversion method Fast conversion times: e.g. 10-bit conversion (without sample time): 5.05 µs Total Unadjusted Error (TUE) of ±2 LSB @ 10-bit resolution Integrated sample-and-hold functionality Sixteen analog input channels Dedicated control and status registers for each analog channel Powerful conversion request sources Selectable reference voltages for each channel Programmable sample and conversion timing schemes Limit checking Broken wire – short circuit detection Flexible service request generation Synchronization of the two on-chip A/D Converters Automatic control of external analog multiplexer Equidistant samples initiated by timer External trigger inputs for conversion requests Two external trigger inputs, connected with the General Purpose Timer Array (GPTA) Power reduction and clock control Figure 11 shows a global view of the ADC module kernels with the module specific interface connections. Each of the ADC modules communicates with the external world via five digital I/O lines and sixteen analog inputs. Clock control, address decoding, and interrupt service request control are managed outside the ADC module kernel. Two trigger inputs and a synchronization bridge are used for internal control purposes. Data Sheet 36 V1.2, 2002-05 TC1775 Preliminary V A R E F 0 V S SA 0 V SSM V AG ND0 V DDA0 V DDM C lo ck C o ntro l fADC0 P ort C on trol A d d res s D e co d er In terru pt C o ntro l SR0 SR1 SR2 SR3 ADC0 M o du le K ern e l A IN 0 P 6.0 / A N 0 A IN 1 P 6.1 / A N 1 A IN 1 4 P T IN 0 0 P T IN 0 1 A IN 1 5 P T IN 1 0 P T IN 1 1 P ort C on trol fADC1 ADC1 M o du le K ern e l A d d res s D e co d er A IN 0 A IN 1 In terru pt C o ntro l SR0 SR1 SR2 SR3 A IN 1 4 A IN 1 5 V A G N D 1 V D D A1 V D D M V A R EF 1 V S SA 1 V S SM Figure 11 Data Sheet P 6.1 4 / A N 14 P 6.1 5 / A N 15 S yn chro n iz ation B rid g e G PTA C lo ck C o ntro l P 12 .8 / A D 0 E X T IN 0 P 12 .9 / A D 0 E X T IN 1 P 12 .0 / AD0EM UX0 P 12 .1 / AD0EM UX1 P 12 .2 / AD0EM UX2 P 12 .6 / A D 1 E X T IN 0 P 12 .7 / A D 1 E X T IN 1 P 12 .3 / AD1EM UX0 P 12 .4 / AD1EM UX1 P 12 .5 / AD1EM UX2 P 7.0 / A N 1 6 P 7.1 / A N 1 7 P 7.1 4 / A N 30 P 7.1 5 / A N 31 M C B 04491 ADC0/ADC1 Modules with Interconnections 37 V1.2, 2002-05 TC1775 Preliminary On-Chip Memories The memory system of the TC1775 provides the following memories: • Program Memory Unit (PMU) with – 8 Kbytes Boot ROM (BROM) – 32 Kbytes Code Scratch-Pad RAM (SPRAM) – 1 Kbyte Instruction Cache (ICACHE) • Data Memory Unit (DMU) with – 40 Kbytes Data Memory (SRAM) – Includes 8 Kbytes static RAM (SBSRAM) for standby operation using a battery • Peripheral Control Processor (PCP) with – 16 Kbytes Data Memory (PCODE) – 4 Kbytes Parameter RAM (PRAM) Data Sheet 38 V1.2, 2002-05 TC1775 Preliminary Address Map Table 2 defines the specific segment oriented address blocks of the TC1775 with its address range, size, and PMU/DMU access view. Table 3 shows the block address map of memory segment 15 which includes the on-chip peripheral units. Seg- Address ment Range Size Description DMU Acc. PMU Acc.1) 0 to 7 0000 0000H – 7FFF FFFFH 2 GB Reserved – – 8 8000 0000H – 8FFF FFFFH 256 MB Reserved via FPI PMU local 9 9000 0000H – 9FFF FFFFH 256 MB Reserved DMU local via FPI 10 A000 0000H – AFFF FFFFH 256 MB External Memory Space via FPI via EBU or FPI B000 0000H – BDFF FFFFH 224 MB External Memory Space mappable into segment 10 via EBU BE00 0000H – BEFF FFFFH 16 MB External Emulator Space via FPI BF00 0000H – BFFF DFFFH – Reserved 11 12 BFFF E000H – 8 KB BFFF FFFFH Boot ROM 4 Kbytes general purpose 4 Kbytes factory test support C000 0000H – C000 7FFFH 32 KB Local Code Scratch-Pad RAM (SPRAM) C000 8000H – C7FF FEFFH – Reserved C7FF FF00H – 256 B C7FF FFFFH C800 0000H – CFFF FFFFH Data Sheet PMU Control Registers via FPI PMU local via FPI cached TC1775 Block Address Map non-cached Table 2 PMU local 128 MB Reserved 39 V1.2, 2002-05 TC1775 Preliminary TC1775 Block Address Map (cont’d) Seg- Address ment Range 13 Size Description D000 0000H – D000 7FFFH 32 KB Local Data Memory (SRAM) D000 8000H – D000 9FFFH 8 KB Local Data Memory for standby operation (SBSRAM) D000 A000H – D000 BFFFH 8 KB SBSRAM mirrored D000 C000H – 8 KB D000 DFFFH SBSRAM mirrored D000 E000H – D000 FFFFH 8 KB SBSRAM mirrored D000 A000H – D7FF FEFFH – Reserved D7FF FF00H – 256 B D7FF FFFFH 14 PMU Acc.1) DMU local via FPI via FPI not possible DMU Registers D800 0000H – DFFF FFFFH 256 MB Reserved E000 0000H – EFFF FFFFH 256 MB External Peripheral and Data Memory Space Data Sheet DMU Acc. non-cached Table 2 40 V1.2, 2002-05 TC1775 Preliminary TC1775 Block Address Map (cont’d) Seg- Address ment Range 15 1) Size Description F000 0000H – F000 3EFFH 16 KB On-Chip Peripherals & Ports F000 3F00H – F000 3FFFH 256 B PCP Registers F000 4000H – F000 FFFFH – Reserved F001 0000H – F001 0FFFH 4 KB PCP Parameter Memory (PRAM) F001 1000H – F001 FFFFH – Reserved F002 0000H – F002 3FFFH 16 KB PCP Code Memory (PCODE) F002 4000H – F00F FFFFH – Reserved F010 0000H – F010 0BFFH 12 × 256 B CAN Module F010 0C00H – FFFE FEFFH – Reserved FFFE FF00H – 256 B FFFE FFFFH CPU Slave Interface Registers (CPS) FFFF 0000H – FFFF FFFFH Core SFRs + GPRs 64 KB DMU Acc. PMU Acc.1) via FPI not possible non-cached Table 2 The PMU can access external memory directly (“via EBU”, only instruction accesses) or via the FPI Bus (“via FPI”). Data Sheet 41 V1.2, 2002-05 TC1775 Preliminary Table 3 Block Address Map of Segment 15 Symbol Description Address Range Size SCU System Control Unit F000 0000H – F000 00FFH 256 Bytes RTC Real Time Clock F000 0100H – F000 01FFH 256 Bytes BCU Bus Control Unit F000 0200H – F000 02FFH 256 Bytes STM System Timer F000 0300H – F000 03FFH 256 Bytes OCDS On-Chip Debug Support F000 0400H – F000 04FFH 256 Bytes EBU External Bus Unit F000 0500H – F000 05FFH 256 Bytes – Reserved F000 0600H – F000 06FFH – GPTU General Purpose Timer Unit F000 0700H – F000 07FFH 256 Bytes ASC0 Async./Sync. Serial Interface 0 F000 0800H – F000 08FFH 256 Bytes ASC1 Async./Sync. Serial Interface 1 F000 0900H – F000 09FFH 256 Bytes SSC0 High-Speed Synchronous Serial Interface 0 F000 0A00H – F000 0AFFH 256 Bytes SSC1 High-Speed Synchronous Serial Interface 1 F000 0B00H – F000 0BFFH 256 Bytes – Reserved F000 0C00H – F000 17FFH – GPTA General Purpose Timer Array F000 1800H – F000 1FFFH 8 × 256 Bytes – Reserved F000 2000H – F000 21FFH – ADC0 Analog-to-Digital Converter 0 F000 2200H – F000 23FFH 512 Bytes ADC1 Analog-to-Digital Converter 1 F000 2400H – F000 25FFH 512 Bytes SDLM Serial Data Link Module F000 2600H – F000 26FFH 256 Bytes – Reserved F000 2700H – F000 27FFH – P0 Port 0 F000 2800H – F000 28FFH 256 Bytes P1 Port 1 F000 2900H – F000 29FFH 256 Bytes P2 Port 2 F000 2A00H – F000 2AFFH 256 Bytes P3 Port 3 F000 2B00H – F000 2BFFH 256 Bytes P4 Port 4 F000 2C00H – F000 2CFFH 256 Bytes P5 Port 5 F000 2D00H – F000 2DFFH 256 Bytes P6 Port 6 (no registers available) F000 2E00H – F000 2EFFH 256 Bytes P7 Port 7 (no registers available) F000 2F00H – F000 2FFFH 256 Bytes P8 Port 8 F000 3000H – F000 30FFH 256 Bytes P9 Port 9 F000 3100H – F000 31FFH 256 Bytes Data Sheet 42 V1.2, 2002-05 TC1775 Preliminary Table 3 Block Address Map of Segment 15 (cont’d) Symbol Description Address Range Size P10 Port 10 F000 3200H – F000 32FFH 256 Bytes P11 Port 11 F000 3300H – F000 33FFH 256 Bytes P12 Port 12 F000 3400H – F000 34FFH 256 Bytes P13 Port 13 F000 3500H – F000 35FFH 256 Bytes – Reserved F000 3600H – F000 3EFFH – PCP PCP Registers F000 3F00H – F000 3FFFH 256 Bytes Reserved F000 4000H – F000 FFFFH – PCP Data Memory (PRAM) F001 0000H – F001 0FFFH 4 Kbytes Reserved F001 1000H – F001 FFFFH – PCP Code Memory (PCODE) F002 0000H – F002 3FFFH 16 Kbytes Reserved F002 4000H – F00F FFFFH – Controller Area Network Module F010 0000H – F010 0BFFH 12 × 256 Bytes – Reserved F010 0C00H – FFFE FEFFH – CPU Slave Interface Registers (CPS) FFFE FF00H – FFFE FFFFH 256 Bytes Reserved FFFF 0000H – FFFF BFFFH – Memory Protection Registers FFFF C000H – FFFF EFFFH 12 Kbytes Reserved FFFF F000H – FFFF FCFFH – – CAN 1) Core Debug Register (OCDS) FFFF FD00H – FFFF FDFFH 256 Bytes 1) Core Special Function Registers (CSFRs) FFFF FE00H – FFFF FEFFH 256 Bytes General Purpose Register (GPRs) FFFF FF00H – FFFF FFFFH 256 Bytes Access to unused address regions within this peripheral unit don’t generate a bus error. Data Sheet 43 V1.2, 2002-05 TC1775 Preliminary Memory Protection System The TC1775 memory protection system specifies the addressable range and read/write permissions of memory segments available to the currently executing task. The memory protection system controls the position and range of addressable segments in memory. It also controls the kinds of read and write operations allowed within addressable memory segments. Any illegal memory access is detected by the memory protection hardware, which then invokes the appropriate Trap Service Routine (TSR) to handle the error. Thus, the memory protection system protects critical system functions against both software and hardware errors. The memory protection hardware can also generate signals to the Debug Unit to facilitate tracing illegal memory accesses. There are two Memory Protection Register Sets in the TC1775, numbered 0 and 1, which specify memory protection ranges and permissions for code and data. The PSW.PRS bit field determines which of these is the set currently in use by the CPU. Because the TC1775 uses a Harvard-style memory architecture, each Memory Protection Register Set is broken down into a Data Protection Register Set and a Code Protection Register Set. Each Data Protection Register Set can specify up to four address ranges to receive particular protection modes. Each Code Protection Register Set can specify up to two address ranges to receive particular protection modes. Each of the Data Protection Register Sets and Code Protection Register Sets determines the range and protection modes for a separate memory area. Each contains register pairs which determine the address range (the Data Segment Protection Registers and Code Segment Protection Registers) and one register (Data Protection Mode Register) which determines the memory access modes which apply to the specified range. Data Sheet 44 V1.2, 2002-05 TC1775 Preliminary On-Chip FPI Bus The FPI Bus interconnects the functional units of the TC1775, such as the CPU and on-chip peripheral components. The FPI Bus also interconnects the TC1775 to external components by way of the External Bus Controller Unit (EBU). The FPI Bus is designed to be quick to acquire by on-chip functional units, and quick to transfer data. The low setup overhead of the FPI Bus access protocol guarantees fast FPI Bus acquisition, which is required for time-critical applications. The FPI Bus is designed to sustain high transfer rates. For example, a peak transfer rate of up to 160 Mbyte/s can be achieved with a 40 MHz bus clock and 32-bit data bus. Multiple data transfers per bus arbitration cycle allow the FPI Bus to operate at close to its peak bandwidth. Features: • • • • • • Supports multiple bus masters Supports demultiplexed address/data operation Address and data buses are 32 bits wide Data transfer types include 8-, 16-, and 32-bit sizes Single- and multiple-data transfers per bus acquisition cycle Designed to minimize EMI and power consumption Data Sheet 45 V1.2, 2002-05 TC1775 Preliminary External Bus Unit The External Bus Unit (EBU) of the TC1775 is the interface between external memories and peripheral units and the internal memories and peripheral units. The basic structure of the EBU is shown in Figure 12. PMU w ith o n -ch ip P ro g ra m M e m o ry B u rst M o de P o rt 4 C o n tro l Lin es Instru ction F etch e s P o rt 3 A [2 5:16 ] an d C h ip S e le ct P o rt 2 A [1 5:0] P o rt 1 A D [31 :1 6 ] P o rt 0 A D [1 5:0 ] F P I B us T riC o re CPU EBU DMU w ith o n -ch ip D a ta M e m o ry T o P e riph era l U nits an d P C P Figure 12 M C A04753 EBU Structure and Interfaces The EBU is primarily used for the following two operations: • Communication with external memories or peripheral units via the FPI Bus • Instruction fetches from the PMU to external Burst Flash program memories The EBU controls all transactions required for these two operations and in particular handles the arbitration between these two tasks. The types of external devices/bus modes controlled by the EBU are: • • • • • INTEL style peripherals (separate RD and WR signals) ROMs, EPROMs Static RAMs Demultiplexed A/D bus Multiplexed A/D bus The PMU controls accesses to external code memories. It especially supports: – Burst Mode Flash Memories (ROM) Note: Instruction fetches of the PMU from external Burst Flash program memories are only possible with 32-bit data bus width. Data Sheet 46 V1.2, 2002-05 TC1775 Preliminary Peripheral Control Processor The Peripheral Control Processor (PCP) performs tasks that would normally be performed by the combination of a DMA controller and its supporting CPU interrupt service routines in a traditional computer system. It could easily be considered as the host processor’s first line of defense as an interrupt-handling engine. The PCP can offload the CPU from having to service time-critical interrupts. This provides many benefits, including: • Avoiding large interrupt-driven task context-switching latencies in the host processor • Lessening the cost of interrupts in terms of processor register and memory overhead • Improving the responsiveness of interrupt service routines to data-capture and datatransfer operations • Easing the implementation of multitasking operating systems. The PCP has an architecture that efficiently supports DMA type transactions to and from arbitrary devices and memory addresses within the TC1775 and also has reasonable stand alone computational capabilities. The PCP is made up of several modular blocks as follows: • • • • • • PCP Processor Core Code Memory (PCODE) Parameter Memory (PRAM) PCP Interrupt Control Unit (PICU) PCP Service Request Nodes (PSRN) System bus interface to the FPI Bus The PCP is fully interrupt-driven, meaning it is only activated through service requests; there is no main program running in the background as with a conventional processor. Data Sheet 47 V1.2, 2002-05 TC1775 Preliminary Code M e m o ry PCO DE P a ram e ter M em ory PRAM PCP P ro ce ss or C o re P C P S e rvice R eq . N o de s PSRNs F P I-Interfa ce FPI Bus P C P In terru pt C on trol U n it P IC U P C P Inte rrup t A rb itra tio n B u s C P U Inte rrup t A rb itra tio n B u s Figure 13 PCP Block Diagram Table 4 PCP Instruction Set Overview M C B 04784 Instruction Group Description DMA primitives Efficient DMA channel implementation Load/Store Transfer data between PRAM or FPI memory and the general purpose registers, as well as move or exchange values between registers Arithmetic Add, subtract, compare and complement Divide/Multiply Divide and multiply Logical And, Or, Exclusive Or, Negate Shift Shift right or left, rotate right or left, prioritize Bit Manipulation Set, clear, insert and test bits Flow Control Jump conditionally, jump long, exit Miscellaneous No operation, Debug Data Sheet 48 V1.2, 2002-05 TC1775 Preliminary System Timer The STM within the TC1775 is designed for global system timing applications requiring both high precision and long range. The STM provides the following features: • • • • • • Free-running 56-bit counter All 56 bits can be read synchronously Different 32-bit portions of the 56-bit counter can be read synchronously Driven by clock fSTM (identical with the system clock fSYS) Counting begins at power-on reset Continuous operation is not affected by any reset condition except power-on reset The STM is an upward counter, running with the system clock frequency fSYS. It is enabled per default after reset, and immediately starts counting up. Other than via reset, it is not possible to affect the contents of the timer during normal operation of the application, it can only be read, but not written to. Depending on the implementation of the clock control of the STM, the timer can optionally be disabled or suspended for power-saving and debugging purposes via a clock control register. The maximum clock period is 256 × 1/fSTM. At fSTM = 40 MHz, for example, the STM counts 57.1 years before overflowing. Thus, it is capable of continuously timing the entire expected product life-time of a system without overflowing. STM Module 55 fSTM 47 39 31 23 15 7 56-Bit System Timer PORST Enable/ Clock Disable Control 00H CAP 00H TIM6 TIM5 Address Decoder TIM4 TIM3 TIM2 TIM1 TIM0 MCA04795 Figure 14 Data Sheet Block Diagram of the STM Module 49 V1.2, 2002-05 TC1775 Preliminary Watchdog Timer The Watchdog Timer (WDT) provides a highly reliable and secure way to detect and recover from software or hardware failure. The WDT helps to abort an accidental malfunction of the TC1775 in a user-specified time period. When enabled, the WDT will cause the TC1775 system to be reset if the WDT is not serviced within a userprogrammable time period. The CPU must service the WDT within this time interval to prevent the WDT from causing a TC1775 system reset. Hence, routine service of the WDT confirms that the system is functioning properly. In addition to this standard “Watchdog” function, the WDT incorporates the EndInit feature and monitors its modifications. A system-wide line is connected to the ENDINIT bit implemented in a WDT control register, serving as an additional write-protection for critical registers (besides Supervisor Mode protection). A further enhancement in the TC1775’s Watchdog Timer is its reset prewarning operation. Instead of immediately resetting the device on the detection of an error, as known from standard Watchdogs, the WDT first issues an Non-maskable Interrupt (NMI) to the CPU before finally resetting the device at a specified time period later. This gives the CPU a chance to save system state to memory for later examination of the cause of the malfunction, an important aid in debugging. Features: • 16-bit Watchdog counter • Selectable input frequency: fSYS/256 or fSYS/16384 • 16-bit user-definable reload value for normal Watchdog operation, fixed reload value for Time-Out and Prewarning Modes • Incorporation of the ENDINIT bit and monitoring of its modifications • Sophisticated password access mechanism with fixed and user-definable password fields • Proper access always requires two write accesses. The time between the two accesses is monitored by the WDT and limited. • Access Error Detection: Invalid password (during first access) or invalid guard bits (during second access) trigger the Watchdog reset generation. • Overflow Error Detection: An overflow of the counter triggers the Watchdog reset generation. • Watchdog function can be disabled; access protection and ENDINIT monitor function remain enabled. • Double Reset Detection: If a Watchdog induced reset occurs twice without a proper access to its control register in between, a severe system malfunction is assumed and the TC1775 is held in reset until a power-on reset. This prevents the device from being periodically reset if, for instance, connection to the external memory has been lost such that even system initialization could not be performed. Data Sheet 50 V1.2, 2002-05 TC1775 Preliminary • Important debugging support is provided through the reset prewarning operation by first issuing an NMI to the CPU before finally resetting the device after a certain period of time. Real Time Clock Figure 15 shows a global view of all functional blocks oft he RTC interface. X TA L3 RTC O sc illato r 32 kH z fR TC_CO UN T f S YS X TA L4 SCU RTC M o du le (K ern el) M o de _ S ele ct R TC IN T In terru pt C o ntro l A dd res s D ec od er M C B 04808 Figure 15 Block Diagram of the RTC Interface The Real Time Clock (RTC) module is an independent timer chain that counts time ticks. The base frequency of the RTC can be programmed via a reload counter. The RTC can work asynchronously with the system frequency, and is optimized on low power consumption. Features: • • • • On-chip 32.768 kHz oscillator for counting current time and date Cyclic time-based interrupts Alarm interrupt for wake-up on a defined time 48-bit timer for long-term measurements Data Sheet 51 V1.2, 2002-05 TC1775 Preliminary System Control Unit The System Control Unit (SCU) of the TC1775 handles the system control tasks. All these system functions are tightly coupled, thus, they are conveniently handled by one unit, the SCU. The system tasks of the SCU are: • Reset Control – Generation of all internal reset signals – Generation of external HDRST reset signal • PLL Control – PLL_CLC Clock Control Register • Power Management Control – Enabling of several power-down modes – Control of the PLL in power-down modes • Watchdog Timer • Port 5 Trace Control • Device Identification Data Sheet 52 V1.2, 2002-05 TC1775 Preliminary Interrupt System An interrupt request can be serviced either by the CPU or by the Peripheral Control Processor (PCP). These units are called “Service Providers”. Interrupt requests are called “Service Requests” rather than “Interrupt Requests” in this document because they can be serviced by either of the Service Providers. Each peripheral in the TC1775 can generate service requests. Additionally, the Bus Control Unit, the Debug Unit, the PCP, and even the CPU itself can generate service requests to either of the two Service Providers. As shown in Figure 16, each TC1775 unit that can generate service requests is connected to one or multiple Service Request Nodes (SRN). Each SRN contains a Service Request Control Register mod_SRCx, where “mod” is the identifier of the service requesting unit and “x” an optional index. Two buses connect the SRNs with two Interrupt Control Units, which handle interrupt arbitration among competing interrupt service requests, as follows: • The Interrupt Control Unit (ICU) arbitrates service requests for the CPU and administers the CPU Interrupt Arbitration Bus. • The Peripheral Interrupt Control Unit (PICU) arbitrates service requests for the PCP and administers the PCP Interrupt Arbitration Bus. Units, which can generate service requests are: – – – – – – – – – – – – General Purpose Timer Unit (GPTU) with 8 SRNs General Purpose Timer Array (GPTA) with 54 SRNs Two High-Speed Synchronous Serial Interfaces (SSC0/SSC1) with 3 SRNs each Two Asynchronous/Synchronous Serial Interfaces (ASC0/ASC1) with 4 SRNs each TwinCAN controller with 8 SRNs Serial Data Link Module (SDLM) with 2 SRNs Two Analog/Digital Converters (ADC0/ADC1) with 4 SRNs each Real Time Clock (RTC) with 1 SRN Bus Control Unit (BCU) with 1 SRN Peripheral Control Processor (PCP) with 4 SRNs Central Processing Unit (CPU) with 4 SRNs Debug Unit (OCDS) with 1 SRN The PCP can make service requests directly to itself (via the PICU), or it can make service requests to the CPU. The Debug Unit can generate service requests to the PCP or the CPU. The CPU can make service requests directly to itself (via the ICU), or it can make service requests to the PCP. The CPU Service Request Nodes are activated through software. External interrupt inputs in TC1775 are available using the input pins connected to the General-Purpose Timer Unit (GPTU). Each of the eight GPTU I/O pins can be used as an external interrupt input, using the Service Request Nodes of the GPTU module. In addition, such an external interrupt input can also trigger a timer function. Data Sheet 53 V1.2, 2002-05 TC1775 Preliminary CPU In terru pt A rbitration B u s PCP In te rru pt A rbitration B u s S erv ic e R e q ue stors G P TU G P TA SSC0 SSC1 ASC0 ASC1 SDLM ADC0 ADC1 BCU 8 54 3 3 4 4 8 CAN RTC S e rvice R e q ue st N od e s 2 4 4 1 1 8 SRNs 54 S R N s In te rru pt C o ntro l U nits 8 8 In t. R eq . 54 P IP N 54 2 3 3 3 SRNs Int. A ck . CCPN PIC U 3 3 SRNs In terru pt S e rvice P ro vid ers 2 3 2 SRNs 2 SRNs PCP 2 2 4 4 SRNs 4 1 4 4 SRNs 1 4 1 SRNs 1 D e bu g U nit 4 S o ftw a re Inte rrup t 8 8 SRNs 8 4 2 2 SRNs 4 2 4 SRNs 4 4 SRNs 4 IC U In t. R eq . 4 4 SRNs 4 P IP N 1 1 SRN C PU Int. A ck . CCPN 1 1 1 SRN 1 M C B 04779 Figure 16 Block Diagram of the TC1775 Interrupt System Note: Depending on the selected system frequency fSYS, the number of clocks for interrupt arbitration cycles must be selected as follows: fSYS ≤ 30 MHz: ICR.CONECYC = 1 fSYS > 30 MHz: ICR.CONECYC = 0 Data Sheet 54 V1.2, 2002-05 TC1775 Preliminary Boot Options The TC1775 booting schemes provides a number of different boot options for the start of code execution. Table 5 shows the boot options available in the TC1775. Table 5 Boot Selections OCDSE BRKIN CFG CFG [3] [2:0] Type of Boot Boot Source Initial PC Value 1 Start from Boot ROM Boot ROM BFFF FFFCH External Memory (cached) A000 0000H 1 X 000B 001B 010B 0 1 0 100B External memory as slave directly via EBU 1 100B External memory as master directly via EBU 0 101B External memory as slave via FPI Bus 1 101B External memory as master via FPI Bus X 011B 110B 111B Reserved; don’t use these combinations; 0 100B or 101B Go to halt with EBU enabled as slave 1 – – Go to halt with EBU enabled as master all other combinations Go to halt with EBU disabled 0 0 don’t care Go to external emulator space – BE00 0000H 1 0 don’t care Tri-state chip (deep sleep) – – Data Sheet 55 V1.2, 2002-05 TC1775 Preliminary Power Management System The TC1775 power management system allows software to configure the various processing units so that they automatically adjust to draw the minimum necessary power for the application. There are four power management modes: • • • • Run Mode Idle Mode Sleep Mode Deep Sleep Mode Table 6 describes these features of the power management modes. Table 6 Power Management Mode Summary Mode Description Run The system is fully operational. All clocks and peripherals are enabled, as determined by software. Idle The CPU clock is disabled, waiting for a condition to return it to Run Mode. Idle Mode can be entered by software when the processor has no active tasks to perform. All peripherals remain powered and clocked. Processor memory is accessible to peripherals. A reset, Watchdog Timer event, a falling edge on the NMI pin, or any enabled interrupt event will return the system to Run Mode. Sleep The system clock continues to be distributed only to those peripherals programmed to operate in Sleep Mode. Interrupts from operating peripherals, the Watchdog Timer, a falling edge on the NMI pin, or a reset event will return the system to Run Mode. Entering this state requires an orderly shut-down controlled by the Power Management State Machine. Deep Sleep The system clock is shut off; only an external signal will restart the system. Entering this state requires an orderly shut-down controlled by the Power Management State Machine (PMSM). Data Sheet 56 V1.2, 2002-05 TC1775 Preliminary On-Chip Debug Support The On-Chip Debug Support of the TC1775 consists of four building blocks: • OCDS module in the TriCore CPU – On-chip breakpoint hardware – Support of an external break signal • OCDS module in the PCP – Special DEBUG instruction for program execution tracing • Trace module of the TriCore – Outputs 16 bits per cycle with pipeline status information, PC bus information, and breakpoint qualification information • Debugger Interface (Cerberus) – Provided for debug purposes of emulation tool vendors – Accessible through a JTAG standard interface with dedicated JTAG port pins Figure 17 shows a basic block diagram of the building blocks. FPI Bus B R K IN PCP BRKOUT T rac e C o ntro l 16 Port 5 SC U T R A C E [15 :0 ] TriCore CPU OCDSE O CDS TDI TDO C erberus & JTA G TM S JT A G I/O Line s TCK TRST M C B 04810 Figure 17 Data Sheet OCDS Support Basic Block Diagram 57 V1.2, 2002-05 TC1775 Preliminary Clock Generation Unit The Clock Generation Unit (CGU) in the TC1775, shown in Figure 18, consists of an oscillator circuit and a Phase-Locked Loop (PLL). The PLL can convert a low-frequency external clock signal to a high-speed internal clock for maximum performance. The PLL also has fail-safe logic that detects degenerate external clock behavior such as abnormal frequency deviations or a total loss of the external clock. It can execute emergency actions if it looses its lock on the external clock. In general, the CGU is controlled through the System Control Unit (SCU) module of the TC1775. Clock Generation Unit CGU XTAL1 System_ CLK 1 Oscillator fOSC Circuit & Phase Detect. VCO fVCO 1 MUX 0 K Divider MUX 0 fSYS XTAL2 N Divider PLL Lock Detector CLKSEL[2:0] BYPASS OSC_OK PLL Locked Deep NDIV[2:0] Sleep VCO_ KDIV[2:0] PLL_ BYPASS BYPASS System Control Unit SCU Register PLL_CLC MCA04713 Figure 18 Clock Generation Unit Block Diagram Besides the two XTAL pins for the oscillator, input pins CLKSEL[2:0] and BYPASS are used for configuration of the clock generation unit. These inputs are checked by the SCU which generates the appropriate control signals and latches the state of these signals into register PLL_CLC. Data Sheet 58 V1.2, 2002-05 TC1775 Preliminary PLL Operation The fVCO clock of the PLL has a frequency which is a multiple of the externally applied clock fOSC. The factor for this is controlled through the value N applied to the divider in the feedback path. N is defined through three PLL configuration inputs CLKSEL[2:0]. Input Frequencies and N Factor for fVCO Table 7 CLKSEL[2:0] N-Factor fVCO = 150 MHz fVCO = 160 MHz fVCO = 200 MHz 000B 8 18.75 20 25 001B 9 16.67 17.76 22.22 010B 10 15 16 20 011B 11 13.64 14.55 18.18 100B 12 12.5 13.33 16.67 101B 13 11.54 12.31 15.38 110B 14 10.71 11.43 14.29 111B 15 10 10.67 13.33 Shaded combinations should not be used because the maximum oscillator frequency of 16 MHz is exceeded. The K-Divider is a software controlled divider. Table 8 lists the possible values for K and the resulting division factor. Table 8 Output Frequencies fSYS Derived from Various Output Factors fSYS1) K-Factor fVCO = fVCO = fVCO = 150 MHz 160 MHz 200 MHz Duty Cycle [%] 000B 75 80 100 50 010B 37.5 40 50 50 5 011B 30 32 40 40 6 100B 24.5 26.67 33.33 50 8 101B 18.75 20 25 50 92) 110B 16.67 17.78 22.22 44 10 111B 15 16 20 50 16 001B 9.38 10 12.5 50 Selected Factor KDIV 2 4 2) Shaded combinations cannot not be used because the maximum system clock frequency of 40 MHz is exceeded. 1) Depending on the selected system frequency fSYS, the number of clocks for interrupt arbitration cycles must be selected as follows: fSYS ≤ 30 MHz: ICR.CONECYC = 1, fSYS > 30 MHz: ICR.CONECYC = 0. 2) These odd K-Factors should not be used (not tested because of the unsymmetrical duty cycle). Data Sheet 59 V1.2, 2002-05 TC1775 Preliminary Recommended Oscillator Circuits V DDO SC V DDOSC E xterna l C lock S ig n a l X TA L 1 TC 1775 M ain O scillator 1 -1 6 M Hz TC1775 M ain O scillator X TA L 2 C1 XTAL1 XTAL2 C2 V SSOSC V SSO SC V DD M C S0 47 14 X T A L3 TC1775 R TC O scillator 3 2 .7 6 8 kH z X T A L4 C1 C2 V SS M C S 04 71 6 Figure 19 Oscillator Circuitries For the main oscillator of the TC1775 the following external passive components are recommended: – Crystal: max. 16 MHz – C1, C2: 10 pF A block capacitor between VDDOSC and VSSOSC is recommended, too. For the RTC oscillator of the TC1775 the following external passive components are recommended: – Crystal: 32.768 kHz – C1, C2: 12 pF Note: For crystal operation, it is strongly recommended to measure the negative resistance in the final target system (layout) to determine the optimum parameters for the oscillator operation. Please refer to the minimum and maximum values of the negative resistance specified by the crystal supplier. Data Sheet 60 V1.2, 2002-05 TC1775 Preliminary Power Supply Figure 20 shows the TC1775’s power supply concept, where certain logic modules are individually supplied with power. This concept improves the EMI behavior by reduction of the noise cross coupling. Also the operation margin is improved in sensitive modules like the A/D converter by noise reduction. V D D A0 V DDM V DDSC V D D A1 (2 .5 V ) (5 V ) (5 V ) (2 .5 V ) V SSA0 V S SM V S SS C V SSA1 TC 1775 S ho rt C ircu it / B rok en W ire Lo g ic ADC0 ADC1 C o n tro l L o gic C o ntrol Lo g ic G P IO P o rts (P 8-P 13 ) EBU P o rts (P 0-P 5) V DDSB V DDP813 V DDP05 V DD V D D PL L V D D O S C (2 .5 V ) (3.3 - 5 V ) (2.5 V ) (2 .5 V ) (2 .5 V ) (2.5 V ) V SS V SS V SSPLL V DDO SC PCP M em o ry DM U V DDSRAM (2 .5 V ) V SS S h ort C irc uit / B ro ke n W ire L og ic V SS PMU V SS CPU & C o ntrol & P e rip he rals PLL OSC M C D 04878 Figure 20 Data Sheet TC1775 Power Supply Concept 61 V1.2, 2002-05 TC1775 Preliminary Ports Power Supply The TC1775’s port power supply concept is shown in Figure 21. The ports assigned with the External Bus Unit (EBU) are in a separate power supply group for 2.5 V nominal operating voltage. The general purpose input/outputs (GPIOs) except the EBU provide 3.3 to 5 V input/output acceptance and drive characteristics. V DDP05 V DDP813 (2.5 V ) (3 .3 - 5 V ) V SS P o rts 0 to 5 (P ad s) & S ch m itt T rigg er V DD P o rts 8 to 1 3 (P ad s) & S ch m itt T rig g er P o rt Lo gic (2 .5 V ) M C A 04752 Figure 21 Ports Power Supply Concept Power-up Sequence During Power-up the reset pin PORST has to be held active until both power supply voltages have reached at least their minimum values. During the Power-up time (rising of the supply voltages from 0 to their regular operating values) it has to be ensured, that the difference between VDDP813 and VDDI (i.e. VDDP813 - VDDI) never drops below -0.3 V (VDDI = VDD and VDDP05). Power Loss If VDDP813 is dropping below VDDI, external circuitry in the power supply has to ensure, that VDDI is also limited to the same level. If VDDI is dropping below the operating range, VDDP813 may stay active. Powering Down During powering down (falling of the supply voltages from their regular operating values to zero), it has to be ensured, that the difference between VDDP813 and VDDI (VDDP813 - VDDI) never drops below -0.3 V. Data Sheet 62 V1.2, 2002-05 TC1775 Preliminary Identification Register Values Table 9 TC1775 Identification Registers Short Name Address Value PMU_ID C7FF FF08H 0006 C002H DMU_ID D7FF FF08H 0007 C002H SCU_ID F000 0008H 0003 C002H MANID F000 0070H 0000 1820H CHIPID F000 0074H 0000 8002H RTID F000 0078H 0000 0000H RTC_ID F000 0108H 0000 5A01H BCU_ID F000 0208H 0000 6A05H STM_ID F000 0308H 0000 C002H JPD_ID F000 0408H 0000 6301H EBU_ID F000 0508H 0005 C002H (BA11-Step) 0005 C003H (BA21-Step) GPTU_ID F000 0708H 0001 C002H ASC0_ID F000 0808H 0000 4401H ASC1_ID F000 0908H 0000 4401H SSC0_ID F000 0A08H 0000 4503H SSC1_ID F000 0B08H 0000 4503H GPTA_ID F000 1808H 0002 C001H ADC0_ID F000 2208H 0000 3101H ADC1_ID F000 2408H 0000 3101H SDLM_ID F000 2608H 0000 4202H PCP_ID F000 3F08H 000D C001H CAN_ID F010 0008H 0000 4110H CPU_ID FFFE FF08H 0000 0202H Data Sheet 63 V1.2, 2002-05 TC1775 Preliminary Parameter Interpretation The parameters listed on the following pages partly represent the characteristics of the TC1775 and partly its demands on the system. To aid in interpreting the parameters right, when evaluating them for a design, they are marked in column “Symbol”: CC (Controller Characteristics): The logic of the TC1775 will provide signals with the respective timing characteristics. SR (System Requirement): The external system must provide signals with the respective timing characteristics to the TC1775. Pin Classes The TC1775 has three classes of digital I/O pins: – Class A pins, which are 3.3 V to 5 V nominal voltage pins – Class B pins, which are 2.5 V nominal voltage pins (input tolerant for 3.3 V) – Class C pins, which are 2.5 V nominal voltage pins only Table 10 shows the assignments of all digital I/O pins to pin classes and to VDD power supply pins. Table 10 Assignments of Digital Pins to Pin Classes and Power Supply Pins Pins Pin Classes Port 8 to Port 13 CLKSEL[2:0], BYPASS, CFG[3:0], HDRST Class A VDDP813 (nominal 3.0 to 5.25 V) Port 0 to 5 TRST, TCK, TDI, TDO, TMS, ODCSE, BRKIN, BRKOUT, NMI, PORST, CLKOUT, CLKIN TESTMODE Class B (nominal 2.5 V, 3.3 V tolerant) VDDP05 Core supply, no pins assigned (nominal 2.5 V) VDD, VDDSRAM, VDDSB VDDPLL VDDOSC XTAL1, XTAL2, XTAL3, XTAL4 Data Sheet Class C (nominal 2.5 V) 64 Power Supply VSS VSSPLL VSSOSC V1.2, 2002-05 TC1775 Preliminary Absolute Maximum Ratings Parameter Symbol Limit Values Unit Notes min. max. -40 125 °C under bias -65 150 °C – – 150 °C under bias -0.5 6.2 V see Table 10 -0.5 3.25 V – -0.5 3.25 V – Voltage on any Class A input pin VIN with respect to VSS -0.5 VDD + 0.5 V – Voltage on any Class B input pin VIN with respect to VSS -0.5 3.7 V – Voltage on any Class C input pin VIN with respect to VSS -0.5 VDDOSC V – TA TA Storage temperature Junction temperature TJ Voltage on Class A power supply VDD pins with respect to VSS Voltage on Class B and C power VDD supply pins with respect to VSS Voltage on power supply pins VDD Ambient temperature “no pins assigned” with respect to VSS Input current on any pin during overload condition IIN Absolute sum of all input currents ΣIIN during overload condition + 0.5 -10 10 mA – – |100| mA – Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. During absolute maximum rating overload conditions (VIN > VDD or VIN < VSS) the voltage on VDD pins with respect to ground (VSS) must not exceed the values defined by the absolute maximum ratings. Data Sheet 65 V1.2, 2002-05 TC1775 Preliminary Package Parameters (P-BGA-329) Parameter Power dissipation Thermal resistance Symbol Limit Values PDISS RTHA Unit Notes min. max. – 1 W – 23 K/W Chip to ambient – Operating Conditions The following operating conditions must not be exceeded in order to ensure correct operation of the TC1775. All parameters specified in the following table refer to these operating conditions, unless otherwise noticed. Parameter Symbol Limit Values min. Digital supply voltage1) Digital ground voltage Ambient temperature under bias Analog supply voltages Analog reference voltage Unit Notes max. VDDP813 3.0 VDD2) 2.3 5.25 V Class A pins 2.75 V CPU Core and Class B pins VDDOSC VDDSB3) VSS TA 2.3 2.75 V Class C pins 2.25 2.75 V – V – -40 +125 °C – VDDA VDDM VAREF 2.25 2.75 V – 4.5 5.25 V – 4 VDDM + V 4) V 5) – 0 0.05 Analog ground voltage Analog input voltage CPU clock Overload current Short circuit current Absolute sum of overload + short circuit currents External load capacitance Data Sheet VAGND VAIN fSYS IOV ISC Σ|IOV| + |ISC| CL VSSA - VSSA + 0.05 0.05 VAGND VAREF V – 40 MHz – -10 10 mA 6)7)8) -10 10 mA 3)4)9) – |50| mA 7) – 50 pF – 66 V1.2, 2002-05 TC1775 Preliminary 1) Digital supply voltages applied to the TC1775 must be static regulated voltages which allow a typical voltage swing of ±10%. 2) This VDD specification is applicable for the power supply pins: VDD, VDDOSC, VDDPLL, VDDSRAM, VDDP05, and VDDSB. In order to minimize the danger of latch-up conditions, these 2.5 V VDD power supply pins should be kept at the same voltage level during normal operating mode. This condition is typically achieved by generating the 2.5 V power supplies from a single voltage source. The condition is also valid in normal operating mode if a separate stand-by power supply VDDSB is used. 3) The minimum voltage at pin VDDSB during TC1775 power down mode is 1.8 V in order to keep the contents of SBRAM valid. The core power supply VDD must be below the standby power supply VDD < VDDSB + 0.3 V. 4) The value of VAREF is permitted to be within the range of VSSA - 0.05 V < VAREF < VDDM + 0.05 V. The value specified for the total unadjusted error (TUE) is not guaranteed while the VAREF is out of the specified range. 5) The value of VAGND is permitted to be within the range of VSSA - 0.05 V < VAGND < VDDM + 0.05 V. The value specified for the total unadjusted error (TUE) is not guaranteed while the VAGND is out of the specified range. 6) Overload conditions occur if the standard operating conditions are exceeded, i.e. the voltage on any pin exceeds the specified range (i.e. VOV > VDD + 0.5 V or VOV < VSS - 0.5 V). The absolute sum of input overload currents on all port pins may not exceed 50 mA. The supply voltage must remain within the specified limits. 7) Not 100% tested, guaranteed by design and characterization. 8) Applicable for analog inputs. 9) Applicable for digital inputs. Data Sheet 67 V1.2, 2002-05 TC1775 Preliminary DC Characteristics Input/Output DC-Characteristics VSS = 0 V; TA = -40 °C to +125 °C; Parameter1) Symbol Limit Values min. Unit Test Conditions max. Class A Pins (VDDP813 = 3.0 to 5.25 V) Output low voltage2) VOL CC – 0.45 V 0.2 × V – V VDDP813 Output high voltage2) VOH CC 0.7 × VDDP813 V Input low voltage5) VIL SR -0.5 0.8 V IOL = 2.4 mA3) IOL = 600 µA4) VDDP813 = 4.5 to 5.25 V IOL = 2.4 mA IOL = 600 µA4) VDDP813 = 3.0 to 4.49 V IOH = -2.4 mA IOH = -600 µA4) VDDP813 = 4.5 to 5.25 V IOH = -2.4 mA IOH = -600 µA4) VDDP813 = 3.0 to 4.49 V VDDP813 = 4.5 to 5.25 V (TTL) 0.43 × V VDDP813 0.2 × Input high voltage5) VIH SR 2.0 (CMOS) V (CMOS) + 0.5 (TTL) V VDDP813 Pull-down current7) Data Sheet IPUH IPUL IPDL IPDH VDDP813 = 4.5 to 5.25 V VDDP813 = 3.0 to 5.25 V (CMOS) CC – 10 µA CC -120 – µA CC 10 – µA CC – 120 µA 68 VDDP813 = 3.0 to 4.49 V VDDP813 VDDP813 V 0.73 × Pull-up current6) VDDP813 = 4.5 to 5.25 V VOUT = VDDP813 - 0.02 V VOUT = 0.5 × VDDP813 VOUT = 0.02 V VOUT = 0.5 × VDDP813 V1.2, 2002-05 TC1775 Preliminary Input/Output DC-Characteristics (cont’d) VSS = 0 V; TA = -40 °C to +125 °C; Parameter1) Symbol Limit Values min. Unit Test Conditions max. Class B Pins (VDDP05 = 2.30 to 2.75 V) Output low voltage VOL CC 0.2 × – V IOL = 2.4 mA VDDP05 0.7 × – V IOL = 600 µA IOH = -2.4 mA 0.9 × – V IOH = -600 µA 0.7 × 3.7 V – -0.5 0.2 × V – 0.45 Output high voltage VOH CC VDDP05 VDDP05 Input high voltage Input low voltage Pull-up current6) Pull-down current7) VIH SR VIL SR IPUH IPUL IPDL IPDH CC – 10 µA CC -60 – µA CC 10 – µA CC – 60 µA VOUT = VDDP05 - 0.02 V VOUT = 0.5 × VDDP05 VOUT = 0.02 V VOUT = 0.5 × VDDP05 0.065 × – V TTL and CMOS9) – ±500 nA 0 V < VIN < VDDPx8) ±20 mA 12)9) VDDP05 VDDP05 Class A and B Pins Input Hysteresis HYS CC VDDPx8) Input leakage current IOZ2 CC (Digital I/O) Peak short-circuit current Peak back-drive current (per digital pin) Peak time & period time10)11) Data Sheet ISCBDpeak – SR 69 V1.2, 2002-05 TC1775 Preliminary Input/Output DC-Characteristics (cont’d) VSS = 0 V; TA = -40 °C to +125 °C; Parameter1) Symbol Limit Values min. max. Constant short-circuit ISCBDcons – SR current Constant back-drive current (per digital pin) Pin capacitance9) (Digital I/O) CIO CC Unit Test Conditions – ±10 mA 12)9) 10 pF f = 1 MHz TA = 25 °C Class C Pins (VDDOSC = 2.30 to 2.75 V), see Page 76 1) All Class A pins of the TC1775 are equipped with Low-Noise output drivers, which significantly improve the device’s EMI performance. These Low-Noise drivers deliver their maximum current only until the respective target output level is reached. After that the output current is reduced. This results in an increased impedance of the driver, which attenuates electrical noise from the connected PCB tracks. The current, which is specified in column “Test Conditions”, is delivered in any case. 2) This specification is not valid for outputs of GPIO lines, which are switched to open drain mode. In open drain mode the output will float and the voltage results from the external circuitry. 3) Output drivers in high current mode. 4) Condition for output driver in dynamic current mode & low current mode – guaranteed by design characterization. 5) Input characteristics can be switched between TTL and CMOS via register Px_PICON except for dedicated pins which have CMOS input characteristics. 6) The maximum current can be drawn while the respective signal line remains inactive. 7) The minimum current must be drawn in order to drive the respective signal line active. 8) In case of Class B pins VDDx = VDDP05. In case of Class A pins VDDx = VDDP813. 9) Guaranteed by design characterization. 10) The max. peak-short-circuit current resp. max. peak-back-drive current is limited by max. 20 mA and the peak period equivalent of 10 mA constant-short-circuit current resp. 10 mA constant-back-drive current. The integral of ISCBDpeak over the peak period is thus limited to 10 mA (provided: ISCBDpeak ≤ 20 mA). 11) To be defined for Class B pads. 12) Short-circuit or back-drive conditions during operation occur if the voltage on the respective pin exceeds the specified operating range (i.e. VSCBD > VDDPx + 0.5 V or VSCBD < VSS - 0.5 V) or a short circuit condition occurs on the respective pin. The absolute sum of input ISCBD and IOV currents on all port pins must not exceed 100 mA at any time. The supply voltage (VDDPx and VSS) must remain within the specified limits. Under shortcircuit conditions the corresponding pin is not ready for use. In case of Class B pins VDDx = VDDP05. In case of Class A pins VDDx = VDDP813. Data Sheet 70 V1.2, 2002-05 TC1775 Preliminary Pull-Up/Pull-Down Characteristics Pull-up Pull-down 700 µA 700 µA I Best Case I 600 600 Best Case 500 500 400 400 Nominal Nominal 300 200 300 100 0 0 Worst Case 200 Worst Case 100 1 2 3 4 0 0 5 V 6 1 2 3 V 4 5 V 6 V MCD05235 Figure 22 Data Sheet Pull-Up/Pull-Down Characteristics of Class A Pins 71 V1.2, 2002-05 TC1775 Preliminary Pull-up Pull-down 250 µA I 250 µA I Best Case 200 200 150 150 Best Case Nominal Nominal 100 100 Worst Case 50 0 0 Worst Case 50 0.5 1 1.5 2 0 0 2.5 V 3 0.5 1 1.5 V 2 2.5 V 3 V MCD05236 Figure 23 Pull-Up/Pull-Down Characteristics of Class B Pins Note: The pull-up/pull-down characteristics as shown in Figure 22 and Figure 23 are guaranteed by design characterization. Data Sheet 72 V1.2, 2002-05 TC1775 Preliminary AD Converter Characteristics TA = -40 °C to +125 °C; VSS = 0 V; Parameter Analog supply voltages Symbol Limit Values Unit Test Conditions min. typ. max. VDDAx SR 2.25 2.5 2.75 V 1) VDDM SR 4.5 5 5.25 V – VDDSC SR VDDM - – VDDM + V – 0.05 0.05 -0.1 – 0.1 V 2) Analog reference voltage VAREFx SR 4 – VDDM + V 3) Analog reference ground VAGNDx SR VSSAx - – VSSAx + V 4) 0.05 0.05 – Analog ground voltage VSSAx SR 0.05 Analog input voltage range VAIN SR VAGNDx – VAREFx V Internal ADC clock fANA 0.5 – 2 MHz – – – 3328 × (3 + µs CON.CPS) × tBC Power-up calibration time tPUC Sample time Conversion time Total unadjusted error Overload current7) tS tC CC CC TUE6) CC IAOV1 CC 8) IAOV2 CC 9) Data Sheet (3 + CON.CPS) × (CHCONn.STC + 2) × tBC µs 6 × tBC µs – – – 5) tS + (30 + CON.CPS × 4) × tBC + 2 × tDIV µs for 8-bit conv.5) tS + (36 + CON.CPS × 4) × tBC + 2 × tDIV µs for 10-bit conv.5) ts + (42 + CON.CPS × 4) × tBC + 2 × tDIV µs for 12-bit conv.5) – – ±1 LSB for 8-bit conv. – – ±2 LSB for 10-bit conv. – – ±6 LSB for 12-bit conv. -2 – +5 mA – -2 0 mA kA = 1.0 × 10-3 0 +5 mA kA = 1.0 × 10-4 +10 mA – -4 0 mA kA = 1.0 × 10-3 0 +10 mA kA = 1.0 × 10-4 -4 – 73 V1.2, 2002-05 TC1775 Preliminary AD Converter Characteristics (cont’d) TA = -40 °C to +125 °C; VSS = 0 V; Parameter Symbol Limit Values Unit Test Conditions min. typ. max. – – 1.0 × 10-3 – 1.0 × – see IAOV1 and IAOV2 Overload coupling factor10) kA Input leakage current at analog inputs IOZ1 CC – – ±200 nA 0 V < VIN < VDDA1) Input leakage current at VAGND and VAREF IOZ2 CC – – ±500 nA 0 V < VIN < VDDA1) Switched cap. at the positive reference voltage input CAREFSW – 15 20 pF 11) Switched cap. at the negative reference voltage input CAGNDS – 15 20 pF 11) Total cap. at the analog voltage input CAINTOT – 12 15 pF – Switched cap. at the analog voltage input CAINSW – – 10 pF 12) – – 0.7 kΩ – CC 10-4 CC CC CC CC ON resistance of the RAIN CC transmission gates in the analog voltage path 1) VDDAx = VDDA0 for A/D Converter ADC0 and VDDAx = VDDA1 for A/D Converter ADC1. 2) VSSAx = VSSA0 for A/D Converter ADC0 and VSSAx = VSSA1 for A/D Converter ADC1. 3) The value of VAREF is permitted to be within the range of VSSA - 0.05 V < VAREF < VDDM + 0.05 V. The value specified for the total unadjusted error (TUE) is not guaranteed while the VAREF is out of the specified range. 4) The value of VAGND is permitted to be within the range of VSSA - 0.05 V < VAGND < VDDM + 0.05 V. The value specified for the total unadjusted error (TUE) is not guaranteed while the VAGND is out of the specified range. 5) Definitions for CPS, STC, tBC and tDIV see Figure 25. 6) TUE is tested at VAREF = 5 V, VAGND = 0 V and VDDM = 4.9 V. 7) Analog overload conditions during operation occur if the voltage on the respective ADC pin exceeds the specified operating range (i.e. VAOV > VDDM + 0.5 V or VAOV < VSSM - 0.5 V) or a short circuit condition occurs on the respective ADC pin. The absolute sum of input currents on all port pins must not exceed 10 mA at any time. The supply voltage (VDD, VDDA0, VDDA1 and VSS, VSSA0, VSSA1) must remain within the specified limits. Under short-circuit conditions the corresponding pin is not ready for use. 8) Applies for one analog input pin. 9) Applies for two adjacent analog input pins. Data Sheet 74 V1.2, 2002-05 TC1775 Preliminary 10) The overload coupling factor (kA) defines the worst case relation of an overload condition (IOV) at one pin to the resulting leakage current (Ileak) into an adjacent pin: |Ileak| = kA × |IOV|. Thus under overload conditions an additional error leakage voltage (UAEL) will be induced onto an adjacent analog input pin due to the resistance of the analog input source (RAIN). That means UAEL = RAIN × |Ileak|. See also section 7.1.6 “Error Through Overload Conditions” in the TC1775 Peripheral Units User’s Manual for further explanations. 11) This represents an equivalent switched capacitance. This capacitance is not switched to the reference voltage at once. Instead of this smaller capacitances are successively switched to the reference voltage. Alternatively, the redistributed charge could be specified. 12) The switched capacitance at the analog voltage input must be charged within the sampling time. Alternatively, the redistributed charge could be specified. R A IN , S o u rce V A IN = R A IN , O n C A IN , B lo ck C A IN T O T - C A IN S W A /D C o nv erte r C A IN S W M C S 04879 Figure 24 Equivalent Circuitry of Analog Input Note: This equivalent circuitry for an analog input is also valid for the reference inputs VAREF and VAGND. Data Sheet 75 V1.2, 2002-05 TC1775 Preliminary A/D Converter Module fADC Peripheral Clock Divider (1:1) to (1:8) fDIV Programmable Clock Divider (1:1) to (1:128) CON.PCD Arbiter (1:20) CON.CTC fTIMER fBC fANA 4:1 3:1 CON.CPS Control Unit (Timer) Programmable Counter Sample Time tS CHCONn.STC Control/Status Logic Interrupt Logic External Trigger Logic External Multiplexer Logic Request Generation Logic MCA04657 Figure 25 ADC Clock Circuit Note: The frequency of fADC is the system clock frequency (fSYS) divided by the value of bit field ADCx_CLC.RMC. Oscillator Pins (Class C Pins) TA = -40 °C to +125 °C; VDDOSC = 2.30 to 2.75 V; VSSOSC = 0 V; Parameter Symbol Limit Values min. Input low voltage at XTAL1, XTAL3 Unit Test Conditions V – V – ±20 µA 0 V < VIN < VDDOSC ±0.5 µA 0 V < VIN < VDDOSC ±200 nA 0 V< VIN < VDDOSC max. 0.3 × VILX SR -0.5 VIHX SR 0.7 × VDDOSC Input current at XTAL1 IIX1 CC – Input current at XTAL3 IIX3 CC – Input leakage current IOZ CC – Input high voltage at XTAL1, XTAL3 1) VDDOSC VDDOSC + 0.5 XTAL1, XTAL3 1) Only applicable in deep sleep mode. Data Sheet 76 V1.2, 2002-05 TC1775 Preliminary Power Supply Current TA = -40 °C to +125 °C; Parameter Symbol Limit Values Unit Test Conditions min. typ.1) max. Active mode supply current IDD CC – – 250 mA PORST = VIL2)3) – 266 320 mA Sum of IDDS4) – 36 – mA – 4 – mA – 219 – mA – 34) 805) mA – 4 – mA Idle mode supply current IID CC – 80 200 mA Sleep mode supply current ISL CC – 50 160 mA IDD at VDDP054) IDD at VDDP8134) IDD at VDD and VDDSRAM4) IDD at VDDSB IDD at VDDSC and VDDAx4) PORST = VIH1)2)6)7) PORST = VIH1)2)7) Deep sleep mode supply current IDS CC – 4 1000 µA PORST = VIH8) Stand-by pin power supply current ISB CC – 1 200 µA IDD at VDDSB9) – 1 120 µA 10) 1) Parameters in this column are tested at 25 °C, 40 MHz system clock (if applicable) and nominal VDD voltages. 2) These parameters are tested at VDDmax and 40 MHz system clock with all outputs disconnected and all inputs at VIL or VIH. 3) These power supply currents are defined as the sum of all currents at the VDD power supply lines: VDD + VDDP05 + VDDP813 + VDDSRAM + VDDSB + VDDPLL + VDDOSC + VDDSC + VDDM + VDDA0 + VDDA1 4) These power consumption characteristics are measured while running a typical application pattern. The power consumption of modules can increase or decrease using other application programs. The PLL is inactive during this measurement. 5) This parameter has been evaluated at design characterization using an untypical test pattern that makes extensive usage of the SBSRAM. 6) All peripherals are enabled and in idle state. 7) Guaranteed by design characterization. 8) IDS is the sum of all power supply currents except VDDSB. 9) TC1775 in deep sleep mode. 10) All other VDD pins are at 0V; TJ = 150 °C; VDDSB = 2.0 V. Data Sheet 77 V1.2, 2002-05 TC1775 Preliminary AC Characteristics Output Rise/Fall Times Class A drivers (GPIO/peripheral ports 8 to 13): VDDP813 = 4.5 to 5.25 V; VSS = 0 V Class B drivers (Bus interface ports 0 to 5): VDDP05 = 2.30 to 2.75 V; VSS = 0 V TA = -40 °C to +125 °C, unless otherwise noted; fSYS = 40 MHz Parameter Symbol Limit Values min. typ. max. – – Unit Test Conditions Class A Pins Nominal output rise/ fall time1) tRFAnom 5 ns CC TA = 25 °C, CL = 50 pF, VDDP813 = 5.0 V Px_POCON.PEC = 00B Px_POCON.PDC = 0XB Maximal output rise/ fall time1) tRFAmax Slow output rise/fall time1) tRFAslow – – 12 ns CL = 50 pF Px_POCON.PEC = 00B Px_POCON.PDC = 0XB CC – – 55 ns CL = 100 pF Px_POCON.PEC = 01B Px_POCON.PDC = 0XB CC Class B Pins Output rise/fall time1) tRFBmax CC 1) – – 4 ns for CLKOUT CL = 50 pF – – 7 ns for all Class B pins except CLKOUT CL = 50 pF Measured from 10% output level to 90% output level and vice versa. Data Sheet 78 V1.2, 2002-05 TC1775 Preliminary Testing Waveforms TA = -40 °C to +125 °C; Frequency: max. 40 MHz; Class A Pins: VDDP813 = 3.0 to 5.25 V; VSS = 0 V; VIHmin VOHmin VOHmin Test Points VOLmax VILmax VOLmax MCT04880 AC inputs during testing are driven with VIHmin for a logic 1 and VILmax for a logic 0. Timing measurements are made at VOHmin for a logic 1 and VOLmax for a logic 0. Input and Output Low/High max./min. voltages are defined at Page 68. Figure 26 Testing Waveforms for Class A Pins Class B and Class C Pins: VDD = 2.30 to 2.75 V; VSS = 0 V; VDDOSC = 2.30 to 2.75 V; VSSOSC = 0 V; VIHmin VDD / 2 Test Points VDD / 2 VILmax MCT04881 AC inputs during testing are driven with VIHmin for a logic 1 and VILmax for a logic 0. Timing measurements are made at VDD/2 for a logic 1 and for a logic 0. Input Low/High max./min. voltages are defined at Page 69 and Page 76. Figure 27 Testing Waveforms for Class B and Class C Pins VLoad + 0.1 V VLoad - 0.1 V Timing Reference Points VOH - 0.1 V VOL - 0.1 V MCT05074 For timing purposes a port pin is no longer floating when a 100 mV change from load voltage occurs, but begins to float when a 100 mV change from the loaded VOH/VOL level occurs (IOH/IOL = 15 mA). Figure 28 Data Sheet Tri-State Testing Waveforms for Class B Pins 79 V1.2, 2002-05 TC1775 Preliminary Input Clock Timing VDDOSC = 2.30 to 2.75 V; VSSOSC = 0 V; TA = -40 °C to +125 °C; Parameter Symbol Oscillator clock frequency max. 1 16 MHz 10 16 MHz – 40 MHz 10 30 MHz SR 7 – ns SR 7 – ns SR – 4 ns SR – 4 ns Input clock frequency driving direct drive 1/tOSCDD SR at XTAL1 with PLL t1 t2 t3 t4 Input clock low time Input clock rise time Input clock fall time Unit min. direct drive fOSC SR (= 1/tOSC) with PLL Input clock high time Limit Values tOSC Input Clock at XTAL1 0.5 VDDOSC t1 t2 t4 t3 VIHX VILX MCT04882 Figure 29 Data Sheet Input Clock Timing 80 V1.2, 2002-05 TC1775 Preliminary CLKOUT Timing VSS = 0 V; VDDP05 = 2.30 to 2.75 V; TA = -40 °C to +125 °C; CL = 50 pF; Parameter Symbol Unit min. typ. max. 25 – – ns CC 7.5 – – ns CC 7.5 – – ns CC – – 4 ns CC – – 4 ns CC 45 50 55 % tCLKOUT Clock period Limit Values CC t5 t6 t7 t8 DC Clock high time Clock low time Clock rise time Clock fall time Clock duty cycle t5/(t5 + t6) tCLKOUT CLKOUT 0.5 VDDP05 t5 t6 t8 t7 0.9 VDDP 0.1 VDDP MCT04883 Figure 30 Data Sheet CLKOUT Output Clock Timing 81 V1.2, 2002-05 TC1775 Preliminary PLL Parameters Note: All PLL characteristics defined on this and the next page are guaranteed by design characterization. VSS = 0 V; VDD = 2.30 to 2.75 V; TA = -40 °C to +125 °C; Parameter Symbol Limit Values min. Accumulated jitter VCO frequency range PLL base frequency PLL lock-in time DN fVCO fPLLBASE tL Unit max. see Figure 31 – 150 200 MHz 40 130 MHz – 200 µs Phase Locked Loop Operation When PLL operation is enabled and configured (see Figure 18 and Page 59), the PLL clock fVCO (and with it the system clock fSYS) is constantly adjusted to the selected frequency. The relation between fVCO and fSYS is defined by: fVCO = K × fSYS. The PLL causes a jitter of fSYS and also of CLKOUT, which is directly derived from fSYS and which has its frequency. The following two formulas define the (absolute) approximate maximum value of jitter DN in ns dependent on the K-factor, the system clock frequency fSYS in MHz, and the number P of consecutive fSYS periods. for P < 23.5 for P > 23.5 K K DN [ns] = ± DN [ns] = ± 3.9 × P + 1.2 fSYS [MHz] 91.7 fSYS [MHz] × K + 1.2 [1] [2] With rising number P of clock cycles the maximum jitter increases linearly up to a value of P that is defined by the K-factor of the PLL. Beyond this value of P the maximum accumulated jitter remains at a constant value. Further, a lower system clock frequency fSYS results in a higher maximum jitter. Figure 31 gives an example for the jitter curves with K = 8. Data Sheet 82 V1.2, 2002-05 TC1775 Preliminary MCD05237 ±2.0 ns K=8 DN ±1.6 20 MHz 25 MHz 33 MHz 40 MHz ±1.4 ±1.2 ±1.0 0 1 2 3 4 5 6 P DN = Max. jitter P = Number of consecutive fSYS periods K = K-divider of PLL Figure 31 Approximated Maximum Accumulated PLL Jitter (for K = 8) Note: For safe clock generation and PLL operation the definitions and restrictions as defined at pages 58, 59, and 80 must be regarded. Data Sheet 83 V1.2, 2002-05 TC1775 Preliminary EBU Demultiplexed Timing VSS = 0 V; VDDP05 = 2.30 to 2.75 V; TA = -40 °C to +125 °C; CL = 50 pF; Parameter Symbol Output delay from CLKOUT Output delay from CLKOUT Data setup to CLKOUT Data hold from CLKOUT 1) Data valid after CLKOUT 1) Data setup to CLKIN Data hold from CLKIN 2) 2) t10 t11 t12 t13 t15 t31 t32 Limit Values Unit min. max. CC 0 9 ns CC -2 4 ns SR 9 – ns SR 1 – ns CC 2 – ns SR see Page 90 – ns SR see Page 90 – ns 1) Valid for EBU_BUSCONx.26 = 0. 2) Valid for EBU_BUSCONx.26 = 1 (early sample feature). Not applicable for TC1775 BA11 step. Data Sheet 84 V1.2, 2002-05 TC1775 Preliminary CLKOUT CLKIN 1) t10 A[25:0] CODE SVM Address Valid t11 t11 ADV t10 t10 CSx t11 t11 RD RD/WR t13 t12 D[31:0] Normal Sampling D[31:0] Early Sampling Data Valid t31 t32 Data Valid t10 t11 t11 t10 BC[3:0] MCT05075 1) Early sampling for D[31:0] not available in TC1775 BA11 step. Figure 32 EBU Demultiplexed Read Timing Note: WAIT timing see Figure 36. Data Sheet 85 V1.2, 2002-05 TC1775 Preliminary C LK O U T t1 0 A [2 5 :0 ] C O D E 1) SVM A dd re ss V a lid t11 t11 ADV t10 t10 CSx RD t11 t11 R D /W R t1 0 t15 D [31 :0 ] D a ta V a lid t10 t11 t11 t10 B C [3:0 ] 1) Figure 33 Data Sheet C O D E rem ain s at hig h leve l d u rin g a d e m ultip lex ed w rite cyc le M C T 04885 EBU Demultiplexed Write Timing 86 V1.2, 2002-05 TC1775 Preliminary EBU Multiplexed Timing VSS = 0 V, VDDP05 = 2.30 to 2.75 V; TA = -40 °C to +125 °C; CL = 50 pF; Parameter Symbol Limit Values min. Output delay from CLKOUT 1) Output delay from CLKOUT Data setup to CLKOUT Data hold from CLKOUT Address and data valid after CLKOUT 1) 1) t20 t21 t22 t23 t25 Unit max. CC -2 10 ns CC -2 4 ns SR 9 – ns SR 1 – ns CC 2 – ns The following condition is always valid: t25 < t20 C LK O U T t23 t20 t25 t22 A dd re ss V alid A D [3 1:0] D a ta In t20 CODE SVM t2 0 t20 A LE t2 0 t20 CSx t21 t21 t21 t21 RD R D /W R t20 t20 B C [3 :0 ] M C T 04886 Figure 34 Data Sheet EBU Multiplexed Read Timing 87 V1.2, 2002-05 TC1775 Preliminary C LK O U T t20 t20 A D [3 1:0] t25 t25 A d dre ss V alid D ata O ut t20 CODE SVM 1) t2 0 t20 A LE t2 0 t20 CSx RD t21 t21 t21 t21 R D /W R t20 t20 B C [3 :0 ] 1) Figure 35 Data Sheet C O D E re m a in s a t h ig h lev el du rin g a m u ltiplex ed w rite cy cle M C T 04887 EBU Multiplexed Write Timing 88 V1.2, 2002-05 TC1775 Preliminary WAIT Timing (FPI Bus to external Memory) VSS = 0 V; VDDP05 = 2.30 to 2.75 V; TA = -40 °C to +125 °C; CL = 50 pF; Parameter Symbol Limit Values min. WAIT setup to CLKOUT WAIT hold from CLKOUT WAIT setup to CLKOUT WAIT hold from CLKOUT 1) t50 t51 t52 t53 Unit max. SR 141) – ns SR 141) – ns SR 7 – ns SR 2 – ns Guaranteed by design characterization. Synchronous Mode CLKOUT t51 t50 t51 t50 WAIT Asynchronous Mode CLKOUT t53 t52 t53 t52 WAIT MCT04888 Figure 36 Data Sheet WAIT Timing (from FPI Bus to external Memory) 89 V1.2, 2002-05 TC1775 Preliminary EBU Burst Mode Timing VSS = 0 V, VDDP05 = 2.30 to 2.75 V; TA = -40 °C to +125 °C; CL = 50 pF; Parameter Symbol Limit Values min. t30 t31 t32 Output delay from CLKIN Data setup to CLKIN Data hold from CLKIN 1) Unit max. CC 0 14 ns SR 21) – ns SR 31) – ns Guaranteed by design characterization. C LK IN t30 A [2 5:2 ] A ddress V alid t30 t30 ADV t30 t3 0 CS0 CODE t30 t3 0 RD t30 t30 BAA t31 t31 t32 D [1 5 :0 ] V alid N ote : W A IT m u st b e 1 d urin g a B urs t M od e R ea d C yc le . Figure 37 t32 V alid M C T 04889 Burst Mode Timing (Instruction Read) Note: Burst mode and external Flash related application hints are described in a separate application note. Data Sheet 90 V1.2, 2002-05 TC1775 Preliminary EBU Arbitration Signal Timing VSS = 0 V, VDDP05 = 2.30 to 2.75 V; TA = -40 °C to +125 °C; CL = 50 pF; Parameter Symbol Limit Values min. t40 t41 t42 Output delay from CLKOUT Data setup to CLKOUT Data hold from CLKOUT Unit max. CC – 3 ns SR 8 – ns SR 2 – ns CLKOUT t40 t40 HLDA Output t40 t40 BREQ Output CLKOUT t41 t41 t42 HOLD Input HLDA Input Figure 38 Data Sheet t42 MCT04890 EBU Arbitration Signal Timing 91 V1.2, 2002-05 TC1775 Preliminary EBU External Access Timing VSS = 0 V, VDDP05 = 2.30 to 2.75 V; TA = -40 °C to +125 °C; CL = 50 pF; Parameter Symbol Limit Values min. Unit max. CSFPI, BC[3:0], A[23:2] setup before RD or RD/WR t43 SR 3 – ns Data valid after RD CC 2 × tCLKOUT – ns CC – 11 ns CC – 20 ns SR 3 – ns Data hold from RD/WR t44 t45 t46 t47 t48 SR 3 – ns Data Sheet 92 WAIT active after RD RD/WAIT float after RD Data setup to RD/WR or RD/WR or RD/WR V1.2, 2002-05 TC1775 Preliminary R ead Tim ing A [2 3:2] V alid A d dre ss & B yte C on trol B C [3:0 ] CSFPI t43 RD R D /W R t44 A D [31 :0] t46 D ata V alid t45 t46 W A IT W rite Tim ing A [2 3:2] V alid A d dre ss & B yte C on trol B C [3:0 ] CSFPI RD t4 3 R D /W R t47 A D [31 :0] t48 D a ta V a lid t45 t46 W A IT M C T 04891 Figure 39 Data Sheet EBU External Access Timing (external Master to FPI Bus) 93 V1.2, 2002-05 TC1775 Preliminary Port 5 (Trace Port) Timing This timing is applicable for Port 5 when CPU or PCP trace mode is enabled (SCU_CON.ETEN = 1). VSS = 0 V; VDDP05 = 2.30 to 2.75 V; TA = -40 °C to +125 °C; CL = 50 pF; Parameter Symbol Limit Values min. Port 5 lines high/low from CLKOUT t55 Unit max. CC -4 5 ns C LK O U T t55 P 5 [15 :0] O ld S ta te N e w S tate M C T 04892 Figure 40 Data Sheet Port 5 Timing 94 V1.2, 2002-05 TC1775 Preliminary SSC Master Mode Timing VSS = 0 V; VDDP813 = 4.5 to 5.25 V; TA = -40 °C to +125 °C; CL = 50 pF; Parameter Symbol SCLK/MTSR low/high from CLKOUT t60 t61 t62 1) MRST setup to SLCK rising/falling edge MRST hold from SLCK rising/falling edge Limit Values Unit min. max. CC – 7 ns SR 142) – ns SR 142) – ns 1) This parameter is valid for high current mode output driver characteristic and normal timing edge characteristic (P13_POCON.PECx = 00B and P13_POCON.PDCx = 00B). 2) Guaranteed by design characterization. tCLKOUT CLKOUT t60 t60 t60 SCLK MTSR State n-1 State n State n+1 t61 t62 MRST Data Valid MCT04893 Note: The timing diagram assumes the highest possible baud rate operation. (fSSC = fCLKOUT, SSCx_CLC.RMC = 1, SSCx_BR.BR_VALUE = 0000H) Figure 41 Data Sheet SSC Master Mode Timing 95 V1.2, 2002-05 TC1775 Preliminary Package Outlines P-BGA-329 (Plastic Ball Grid Array Package) 22 x 1.27 = 27.94 4 x 1.27 = 5.08 A1 4 x 1.27 = 5.08 22 x 1.27 = 27.94 A23 AC1 2.52 MAX. 1.17 ±0.05 1.27 30˚ 0.6 ±0.1 (0.56) 0.35 C ø0.76 +0.14 -0.16 329x ø0.3 M A B C ø0.15 M C C 0.2 31 ±0.2 26 ±1 A Index Marking 1.95 x 45˚ 4x 26 ±1 31 ±0.2 B GPA09280 You can find all of our packages, sorts of packing and others in our Infineon Internet Page “Products”: http://www.infineon.com/products. Dimensions in mm SMD = Surface Mounted Device Data Sheet 96 V1.2, 2002-05 Infineon goes for Business Excellence “Business excellence means intelligent approaches and clearly defined processes, which are both constantly under review and ultimately lead to good operating results. Better operating results and business excellence mean less idleness and wastefulness for all of us, more professional success, more accurate information, a better overview and, thereby, less frustration and more satisfaction.” Dr. Ulrich Schumacher http://www.infineon.com Published by Infineon Technologies AG