INFINEON TLE7272

5-V Low Drop Voltage Regulator
TLE 7272
Features
•
•
•
•
•
•
•
•
Output voltage 5 V ±2%
Ultra low current consumption: typ. 25µA
300 mA current capability
Inhibit input
Reset
Very low-drop voltage
Short-circuit-proof
Suitable for use in automotive electronics
P-TO252-5-1
Functional Description
The TLE 7272 is a monolithic integrated low-drop
voltage regulator for load currents up to 300 mA. An input
voltage up to 42 V is regulated to VQ,nom = 5.0 V with a
precision of ±2%. Due to its integrated reset circuitry
featuring power on timing and output voltage monitoring
P-TO263-5-1
the IC is well suited as µ-controller supply. The
sophisticated design allows to achieve stable operation
even with ceramic output capacitors down to 470 nF. The
device is designed for the harsh environment of automotive applications. Therefore it is
protected against overload, short circuit and overtemperature conditions. Of course the
TLE 7272 can be used also in all other applications, where a stabilized 5 V voltage is
required. Due to its ultra low stand-by current consumption of typ. 20 µA the TLE 7272
is dedicated for use in applications permanently connected to VBAT. In addition the IC can
be switched off via the Inhibit input reducing the current consumption to typ. 5 µA. An
integrated output sink current circuitry keeps the voltage at the Output pin Q below 5.5
V even when reverse currents are applied. Thus connected devices are protected from
overvoltage damage. For applications requiring extremely low noise levels the Infineon
voltage regulator family TLE 42XY and TLE 44XY is more suited than the TLE 7272. A
mV-range output noise on the TLE 7272 caused by the charge pump operation is
unavoidable due to the ultra low quiescent current concept.
Type
Ordering Code
Package
TLE 7272 D
Q67006-A9734
P-TO252-5
TLE 7272 G
Q67006-A9735
P-TO263-5
Data Sheet
1
Rev. 1.0a, 2005-02-08
TLE 7272
Reset
The Reset pin informs e.g. the microcontroller in case the output voltage has fallen below
the lower threshold VRT of typ. 4.65 V. The hysteresis is typically 100mV. Connecting the
regulator to a battery voltage at first the reset signal remains LOW. When the output
voltage has reached the reset threshold VRT the reset output RO remains still LOW for
the reset delay time trd (typ. 16 ms). Afterwards the reset output turns HIGH.
TLE 7272
1
Overtemperature
Shutdown
Bandgap
Reference
4
5
Reset
Generator
2
Q
RO
1
Inhibit
Charge
Pump
3
GND
Figure 1
Data Sheet
AEB03523.VSD
Block Diagram
2
Rev. 1.0a, 2005-02-08
TLE 7272
GND
I RO
Ι
INH Q
AEP02825_7272
GND Q
RO INH
IEP02528
Figure 2
Pin Configuration P-TO252-5 (D-PAK), P-TO263-5 (D2-PAK)(top view)
Table 1
Pin Definitions and Functions
Pin No.
Symbol
Function
1
I
Input; block to ground directly at the IC with a ceramic capacitor.
2
RO
Reset Output; Open Collector Output with integrated pull-up
resistor of typically 30kΩ. Optional external pull-up resistor of
≥ 10 kΩ to pin Q.
3
GND
Ground; Pin 3 internally connected to heatsink.
4
INH
Inhibit Input; low level disables the IC. Integrated pull-down
resistor.
5
Q
Output; block to ground with a ceramic capacitor, C ≥ 470 nF.
Data Sheet
3
Rev. 1.0a, 2005-02-08
TLE 7272
Table 2
Absolute Maximum Ratings
Parameter
Symbol
Limit Values
Unit Test Condition
Min.
Max.
VI
II
-0.3
45
V
–
-1
–
mA
–
VQ
VQ
IQ
-0.3
5.5
V
–
-0.3
6.2
V
t < 10 s1)
-1
–
mA
–
VRO
VRO
IRO
-0.3
5.5
V
–
-0.3
6.2
V
t < 10 s1)
-1
1
mA
–
Voltage
VINH
-0.3
45
V
Observe current
limit IINHmax2)
Current
IINH
-1
1
mA
–
Tj
Tstg
-40
150
°C
–
-50
150
°C
–
Input I
Voltage
Current
Output Q
Voltage
Voltage
Current
Reset Output RO
Voltage
Voltage
Current
Inhibit Input INH
Temperature
Junction temperature
Storage temperature
1) Exposure to these absolute maximum ratings for extended periods (t > 10 s) may affect device reliability.
2) External resistor required to keep the current below the absolute maximum rating when voltages ≥ 5.5 V are
applied.
Note: Stresses above those listed here may cause permanent damage to the device.
Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Data Sheet
4
Rev. 1.0a, 2005-02-08
TLE 7272
Table 3
Operating Range
Parameter
Symbol
Input voltage
Junction temperature
VI
Tj
Limit Values
Unit Remarks
Min.
Max.
5.5
42
V
–
-40
150
°C
–
Note: In the operating range, the functions given in the circuit description are fulfilled.
Table 4
Thermal Resistance
Parameter
Junction case
Junction ambient
Rthj-c
Rthj-a
Rthj-a
Limit Values
Unit Remarks
Min.
Max.
–
8
K/W –
–
80
K/W TO2521)
K/W TO2632)
Worst case, regarding peak temperature; zero airflow; mounted on a PCB FR4, 80 × 80 × 1.5 mm3, heat sink
Junction ambient
1)
Symbol
–
55
area 300 mm2
2) Worst case, regarding peak temperature; zero airflow; mounted on a PCB FR4, 80
area 300 mm2
Data Sheet
5
× 80 × 1.5 mm3, heat sink
Rev. 1.0a, 2005-02-08
TLE 7272
Application Information
Table 5
Electrical Characteristics
Parameter
Symbol
Limit Values
Min.
Typ. Max.
Unit
Measuring Condition
Output Q
Output voltage
VQ
4.9
5.0
5.1
V
0.1 mA<IQ<300 mA;
6 V < VI < 16 V
Output voltage
VQ
4.9
5.0
5.1
V
0.1 mA<IQ<100 mA;
6 V < VI < 40 V
Output current limitation IQ
320
–
–
mA
1)
Output current limitation IQ
–
–
800
mA
Current consumption;
Iq = II – IQ
Iq
–
20
30
µA
Current consumption;
Iq = II – IQ
Iq
–
–
40
µA
VQ = 0V
IQ = 0.1 mA;
Tj = 25 °C
IQ = 0.1 mA;
Tj ≤ 80 °C
Quiescent current
inhibited
Iq
–
5
9
µA
VINH = 0 V; TJ < 80°C
Drop voltage
Vdr
–
250
500
mV
Load regulation
∆VQ, lo
– 40
15
40
mV
IQ = 200 mA
Vdr = VI – VQ1)
IQ = 5 mA to 250 mA
Line regulation
∆VQ, li
– 20
5
20
mV
Power supply ripple
rejection
PSRR
–
60
–
dB
Temperature output
voltage drift
dVQ
----------dT
CQ
–
0.5
–
mV/K –
470
–
–
nF
ESR < 3 Ω
Turn-on Voltage
VINH ON
3.1
–
–
V
VQ ≥ 4.9 V
Turn-off Voltage
VINH OFF –
–
0.8
V
VQ ≤ 0.3 V
H-input current
IINH ON
–
3
4
µA
VINH = 5 V
L- input current
IINH OFF
–
0.5
1
µA
VINH = 0 V, TJ < 80°C
Output Capacitor
Vl = 10 V to 32 V;
IQ = 5 mA
fr = 100 Hz;
Vr = 0.5 Vpp
Inhibit INH
1) Measured when the output voltage VQ has dropped 100 mV from the nominal value obtained at VI = 13.5 V.
Data Sheet
6
Rev. 1.0a, 2005-02-08
TLE 7272
Reset Output RO
Reset switching
threshold
VRT
4.50
4.65
4.80
V
Reset Read Room
VRH
–
160
–
mV
–
0.2
0.4
V
30
45
kΩ
∞1)
kΩ
Reset output low voltage VROL
Internal reset pull up
resistor
RR,int
15
External reset pull up
resistor
RR,ext
10
Reset delay time
trd
trr
10
16
22
ms
–
–
12
µs
Reset reaction time
VQ decreasing
VI = 6V
RRO = 10 kΩ;
VQ > 1 V
see Fig. 3
1) An external reset pull up resistor is not required.
Data Sheet
7
Rev. 1.0a, 2005-02-08
TLE 7272
VBat
TLE7272
1 I
VCC
Q 5
100
nF
470
nF
Overtemperature
Shutdown
Bandgap
Reference
e. g.
Ignition 4 INH
2
Reset
Generator RO
22
kΩ
4.7
µF
Reset
1
Inhibit
Charge
Pump
GND
3
Figure 3
AEA03522.VSD
Application Diagram
Input, Output
An input capacitor is necessary for damping line influences. A resistor of approx. 1 Ω in
series with CI, can damp the LC of the input inductivity and the input capacitor.
The TLE 7272 requires a ceramic output capacitor of at least 470 nF to assure stability
of the regulation loop. In order to damp influences resulting from load current surges it is
recommended to add an additional electrolytic capacitor of 4.7 µF to 47 µF at the output
as shown in Figure 3.
Data Sheet
8
Rev. 1.0a, 2005-02-08
TLE 7272
Typical Performance Characteristics
Current Consumption Iq versus
Junction Temperature Tj
Current Consumption Iq versus Input
Voltage VI
1 _ Iq - T j .v s d
3 _ IQ - V I. V S D
Iq [µ A ]
T j = 2 5 °C
I q [µ A ]
V I = 1 3 .5 V
100
40
IQ = 1 0 0 µ A
IQ = 5 0 m A
10
30
IQ = 1 0 m A
IQ = 0 .2 m A
20
1
10
0 .0 1
-4 0 -2 0
0
20
60
40
0
80 100 120 140
20
10
30
Current Consumption Iq versus Output
Current IQ
Output Voltage VQ versus Junction
Temperature Tj
5 A _ V Q -T J .V S D
2 _ IQ - IQ .V S D
30
I q [µ A ]
40
V I [V ]
T j [° C ]
V I = 1 3 .5 V
V Q [V ]
V I = 1 3 .5 V
T j = 2 5 °C
T j = -4 0 ° C
20
5 .0 5
15
5 .0 0
10
4 .9 5
5
4 .9 0
0
Data Sheet
20
40
60
100
-4 0 -2 0
I Q [m A ]
I Q = 1 0 0 µ A .. . 1 0 0 m A
0
20
40
60
80 100 120 140
T j [° C ]
9
Rev. 1.0a, 2005-02-08
TLE 7272
Dropout Voltage Vdr versus Output
Current IQ
Maximum Output Current IQ versus
Junction Temperature Tj
6 _ V D R -IQ .V S D
600
8 _ I Q M A X - T J .V S D
620
V d r [m V ]
V I = 1 3 .5 V
I Q [m A ]
T j = 1 5 0 °C
580
400
T j = 2 5 °C
300
200
560
540
T j = -4 0 °C
520
100
0
100
200
500
-4 0 -2 0
300
0
20
40
60
80 100 120 140
T j [° C ]
IQ [m A ]
Dropout Voltage Vdr versus Junction
Temperature Tj
Maximum Output Current IQ versus
Input Voltage VI
7 _ V D R -T J .V S D
600
9 _ S O A .V S D
600
T j = 1 2 5 °C
I Q [m A ]
V d r [m V ]
I Q lim
T j = 2 5 °C
IQ = 2 5 0 m A
400
400
300
300
IQ = 1 5 0 m A
200
200
P v m a x = 1 ,1 8 W f o r T O 2 5 2 @
3 0 0 m m 2 c o o lin g a r e a
100
100
IQ = 1 0 m A
-4 0 -2 0
0
20
40
60
0
80 100 120 140
Data Sheet
10
20
30
40
V I [V ]
T j [° C ]
10
Rev. 1.0a, 2005-02-08
TLE 7272
Region of Stability
Output Voltage VQ Start-up behaviour
1 2 _ E S R -IQ .V S D
100
1 4 _ V It im e _ s t a r t u p . v s d
C Q = 1 0 n F . . .1 0 µ F
T j = 2 5 °C
E SRCQ
[Ω]
V Q [V ]
IN H = O N
10
5 .0 5
1
IQ = 5 m A
5 .0 0
S t a b le
R e g io n
4 .9 0
0 .1
4 .8 0
0 .0 1
0
50
100
200
150
1
2
3
t [m s ]
Power Supply Ripple Rejection PSRR
versus Frequency f
Load Regulation dVQ versus Output
Current Change dIQ
1 3 _ P S R R .V S D
80
5
4
I Q [m A ]
1 8 a _ d V Q - d I Q _ V i6 V . v s d
0
VI = 6V
∆VQ
PSRR
[d B ]
[m V ]
60
IQ = 3 0 m A
IQ = 0 .1 m A
-1 0
IQ = 1 0 0 m A
50
T j = -4 0 °C
-1 5
T j = 2 5 °C
-2 0
40
V R IP P L E = 1 V
V IN = 1 3 . 5 V
C Q = 1 0 µ F T a n t a lu m
T j = 2 5 °C
30
10
100
1k
10k
-3 0
100k
0
50
100
150
250
IQ [m A ]
f [H z ]
Data Sheet
T j = 1 5 0 °C
-2 5
11
Rev. 1.0a, 2005-02-08
TLE 7272
Load Regulation dVQ versus Output
Current Change dIQ
Line Regulation dVQ versus Input
Voltage ChangedVI
1 8 b _ d V Q - d I Q _ V i1 3 5 V . v s d
0
V I = 1 3 .5 V
∆VQ
1 9 _ d V Q -d V I_ _ 1 5 0 C .v s d
0
∆VQ
[m V ]
IQ = 1 m A
[m V ]
-1 0
T j = 1 5 0 °C
IQ = 1 0 0 m A
IQ = 1 0 m A
-2
-1 5
-3
T j = -4 0 °C
T j = 2 5 °C
-2 0
-4
IQ = 2 0 0 m A
-2 5
-5
T j = 1 5 0 °C
-3 0
0
50
100
150
-6
250
0
5
10
15
20
25
30
35
40
IQ [m A ]
Load Regulation dVQ versus Output
Current Change dIQ
Line Regulation dVQ versus Input
Voltage ChangedVI
1 8 c _ d V Q - d I Q _ V i 2 8 V .v s d
0
1 9 _ d V Q -d V I_ 2 5 C .v s d
0
VI = 28
∆VQ
45
V I [V ]
T j = 2 5 °C
∆VQ
[m V ]
[m V ]
IQ = 1 m A
-2
-1 0
IQ = 1 0 m A
IQ = 2 0 0 m A
IQ = 1 0 0 m A
-3
-1 5
T j = -4 0 °C
-2 0
-4
T j = 2 5 °C
-2 5
-5
T j = 1 5 0 °C
-3 0
0
50
100
150
-6
250
IQ [m A ]
Data Sheet
0
5
10
15
20
25
30
35
40
45
V I [V ]
12
Rev. 1.0a, 2005-02-08
TLE 7272
Line Regulation dVQ versus Input
Voltage ChangedVI
Load Transient Response Peak Voltage
dVQ
1 9 _ d V Q -d V I_ -4 0 C .v s d
0
T j = 4 0 °C
∆VQ
2 0 _ L o a d T r a n c ie n t v s t im e 1 2 5 . v s d
[m V ]
IQ 1 :1 0 0 m A
IQ = 1 m A
-2
T j= 1 2 5 ° C
V i= 1 3 .5 V
IQ = 1 0 m A
IQ = 1 0 0 m A
-3
IQ = 2 0 0 m A
-4
VQ
-5
-6
0
5
10
15
20
25
30
35
40
T = 4 0 µ s /D I V
45
V Q = 1 0 0 m V /D I V
V I [V ]
Load Transient Response Peak Voltage
dVQ
Line Transient Response Peak Voltage
dVQ
2 1 _ L in e T r a n c ie n t v s tim e 2 5 . v s d
2 0 _ L o a d T r a n c ie n t v s t im e 2 5 . v s d
IQ 1 :1 0 0 m A
T j= 2 5 ° C
V i= 1 3 .5 V
dVI 2V
T j= 2 5 ° C
V i= 1 3 .5 V
VQ
VQ
T = 4 0 µ s /D I V
Data Sheet
T = 4 0 0 µ s/D IV
V Q = 1 0 0 m V /D I V
13
V Q = 5 0 m V /D IV
Rev. 1.0a, 2005-02-08
TLE 7272
Line Transient Response Peak Voltage
dVQ
Inhibit Input Current IINH versus Input
Voltage VI, INH=Off
2 5 _ I IN H v s V I N IN H _ o ff . v s d
I IN H
2 1 _ L in e T r a n c ie n t v s t im e 1 2 5 . v s d
[µ A ]
1 .0
T j= 1 2 5 ° C
V i= 1 3 .5 V
dVI 2V
IN H = O F F
T j = 1 5 0 °C
T j = 2 5 °C
0 .8
T j = -4 0 °C
0 .6
VQ
0 .4
0 .2
T = 4 0 0 µ s/D IV
V Q = 5 0 m V /D IV
10
30
20
40
V IN [ V ]
Inhibit Input Current IINH versus Inhibit
Input Voltage VINH
Reset Threshold VRT versus Junction
Temperature TJ
2 6 _ V R T V S T E M P .V S D
2 4 _ IIN H v s V IN H .v s d
I IN H
[µ A ]
50
V I = 1 3 .5 V
V Q [V ]
T j = 1 5 0 °C
T j = 2 5 °C
40
4 .9 0
T j = -4 0 °C
30
4 .8 0
20
4 .7 0
R e s e t R e le a s e
T h r e s h o ld
R e s e t T r ig g e r
T h r e s h o ld
10
4 .6 0
10
20
30
40
-4 0 -2 0
V IN H [ V ]
Data Sheet
0
20
40
60
80 100 120 140
T j [° C ]
14
Rev. 1.0a, 2005-02-08
TLE 7272
Reset Delay TRD Time versus Junction
Temperature TJ
Thermal Resistance Junction-Ambient
RTHJA versus Power Dissipation PV
27_R E SE TD E LAY V S
T E M P .V S D
22
V I = 1 3 .5 V
TRD
3 2 _ R T H V S P V T O 2 5 2 .V S D
75
A = 300m m
R T H -J A
18
65
16
60
14
55
12
50
2
C o o lin g A r e a s in g le s id e d P C B
[K /W ]
[m s ]
T O 2 5 2 -3
T O 2 5 2 -5
-4 0 -2 0
0
20
40
60
3
80 100 120 140
6
9
12
P V [W ]
T j [° C ]
Reset Headroom versus Junction
Temperature TJ
28_VRT HEADR O O M VS
T E M P .V S D
240
V I = 1 3 .5 V
V Q [V ]
160
120
80
40
-4 0 -2 0
0
20
40
60
80 100 120 140
T j [° C ]
Data Sheet
15
Rev. 1.0a, 2005-02-08
TLE 7272
Package Outlines
2.3 +0.05
-0.10
A
0.9 +0.08
-0.04
1 ±0.1
0...0.15
0.51 min
0.15 max
per side
B
5.4 ±0.1
0.8 ±0.15
(4.17)
9.9 ±0.5
6.22 -0.2
1 ±0.1
6.5 +0.15
-0.10
0.5 +0.08
-0.04
5x0.6 ±0.1
1.14
4.56
0.1
0.25
M
A B
GPT09161
All metal surfaces tin plated, except area of cut.
Figure 4
P-TO252-5-1 (Plastic Transistor Single Outline)
You can find all of our packages, sorts of packing and others in our
Infineon Internet Page “Products”: http://www.infineon.com/products.
Data Sheet
16
Dimensions in mm
Rev. 1.0a, 2005-02-08
TLE 7272
6.5 +0.15
-0.05
A
1)
2.3 +0.05
-0.10
0.5 +0.08
-0.04
0.9 +0.20
-0.01
0...0.15
0.51 MIN.
0.15 MAX.
per side
B
(5)
0.8 ±0.15
(4.24) 1 ±0.1
9.98 ±0.5
6.22 -0.2
5.7 MAX.
5 x 0.6 ±0.1
0.5 +0.08
-0.04
1.14
4.56
0.1 B
0.25 M A B
1) Includes mold flashes on each side.
All metal surfaces tin plated, except area of cut.
GPT09527
Figure 5
P-TO252-5-11 (Plastic Transistor Single Outline)
You can find all of our packages, sorts of packing and others in our
Infineon Internet Page “Products”: http://www.infineon.com/products.
Data Sheet
17
Dimensions in mm
Rev. 1.0a, 2005-02-08
TLE 7272
10 ±0.2
4.4
9.8 ±0.15
1.27 ±0.1
B
0.1
0.05
2.7 ±0.3
8 1)
2.4
4.7 ±0.5
(15)
9.25 ±0.2
1±0.3
A
8.5 1)
0...0.15
5x0.8 ±0.1
0.5 ±0.1
4x1.7
8˚ max.
0.25
1)
M
A B
0.1
Typical
All metal surfaces tin plated, except area of cut.
GPT09113
Figure 6
P-TO263-5-1 (Plastic Transistor Single Outline)
You can find all of our packages, sorts of packing and others in our
Infineon Internet Page “Products”: http://www.infineon.com/products.
Data Sheet
18
Dimensions in mm
Rev. 1.0a, 2005-02-08
Edition 2005-02-08
Published by Infineon Technologies AG,
St.-Martin-Strasse 53,
81669 München, Germany
© Infineon Technologies AG 2004.
All Rights Reserved.
Attention please!
The information herein is given to describe certain components and shall not be considered as a guarantee of
characteristics.
Terms of delivery and rights to technical change reserved.
We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding
circuits, descriptions and charts stated herein.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest
Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in
question please contact your nearest Infineon Technologies Office.
Infineon Technologies Components may only be used in life-support devices or systems with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
TLE 7272
5-V Low Drop Voltage Regulator
Revision History:
2005-02-08
Previous Version:
Rev. 1.0a
0.41
minor text modifications
release final Version
Previous Version:
1.0a
minor text modifications
Template: ap_tmplt_a5.fm / 1 / 2004-01-01