1M × 72-Bit Dynamic RAM Module (ECC - Module) HYM 721000GS-60/-70 HYM 721010GS-60/-70 Advanced Information • 1 048 576 words by 72-bit ECC - mode organization • Fast access and cycle time 60 ns access time 110 ns cycle time (-60 version) 70 ns access time 130 ns cycle time (-70 version) • Fast page mode capability with 40 ns cycle time (-60 version) 45 ns cycle time (-70 version) • Single + 5 V (± 10 %) supply • Low power dissipation max. 10890 mW active (-60 version) max. 9900 mW active (-70 version) CMOS – 451 mW standby TTL – 550 mW standby • CAS-before-RAS refresh, RAS-only-refresh • 18 decoupling capacitors mounted on substrate • All inputs, outputs and clock fully TTL compatible • 4 Byte interleave enabled, Dual Address inputs (A0/B0) • Buffered inputs excepts RAS and DQ • 168 pin, dual read-out, Single in-Line Memory Module • Utilizes eighteen 1M × 4 -DRAMs in TSOPII-packages and four BiCMOS 8-bit buffers/line drivers 74ABT244 • Two versions: HYM 721000GS with TSOPII-components (4.06 mm module thickness) HYM 721010GS with SOJ-components (8.89 mm module thickness) • 1024 refresh cycles / 16 ms • Gold contact pad • double sided module with 25.35 mm (1000 mil) height Semiconductor Group 1 12.95 HYM721000/10GS-60/-70 1M x 72 ECC- Module The HYM 721000GS-60/-70 is a 8 MByte DRAM module organized as 1 048 576 words by 72-bit in a 168-pin, dual read-out, single-in-line package comprising eighteen HYB 514400BT 1M × 4 DRAMs in 300 mil wide TSOPII - packages mounted together with eighteen 0.2 µF ceramic decoupling capacitors on a PC board. All inputs except RAS and DQ are buffered by using four BiCMOS 8-bit buffers/line drivers. Each HYB 514400BT is described in the data sheet and is fully electrically tested and processed according to Siemens standard quality procedure prior to module assembly. After assembly onto the board, a further set of electrical tests is performed. The density and speed of the module can be detected by the use of presence detect pins. Ordering Information Type Ordering Code Package Descriptions HYM 721000GS-60 Q67100-Q2004 L-DIM-168-2 60ns DRAM module HYM 721000GS-70 on request L-DIM-168-2 70ns DRAM module HYM 721010GS-60 on request L-DIM-168-2 60ns DRAM module HYM 721010GS-70 on request L-DIM-168-2 70ns DRAM module Pin Names A0-A9,B0 DQ0 - DQ71 RAS0, RAS2 CAS0 , CAS2 WE0, WE2 OE0, OE2 Vcc Vss PD1 - PD8 PDE ID0 , ID1 N.C. Address Input Data Input/Output Row Address Strobe Column Address Strobe Read / Write Input Output Enable Power (+5 Volt) Ground Presence Detect Pins Presence Detect Enable ID indentification bit No Connection Presence-Detect and ID-pin Truth Table: Module ID0 ID1 PD1 PD2 PD3 PD4 PD5 PD6 PD7 PD8 HYM 721000/10GS-60 Vss Vss 0 0 1 0 0 1 1 0 HYM 721000/10GS-70 Vss Vss 0 0 1 0 0 0 1 0 Note: 1 = High Level ( Driver Output) , 0 = Low Level (Driver Output) for PDE active ( ground) . For PDE at a high level all PD terminal are in tri-state. Semiconductor Group 2 HYM721000/10GS-60/-70 1M x 72 ECC- Module Pin Configuration PIN # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 Symbol VSS DQ0 DQ1 DQ2 DQ3 VCC DQ4 DQ5 DQ6 DQ7 DQ8 VSS DQ9 DQ10 DQ11 DQ12 DQ13 VCC DQ14 DQ15 DQ16 DQ17 VSS NC NC VCC WE0 CAS0 NC RAS0 OE0 VSS A0 A2 A4 A6 A8 NC NC VCC NC NC Semiconductor Group PIN # 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 Symbol PIN # VSS OE2 RAS2 CAS4 NC WE2 VCC NC NC DQ18 DQ19 VSS DQ20 DQ21 DQ22 DQ23 VCC DQ24 NC NC NC NC DQ25 DQ26 DQ27 VSS DQ28 DQ29 DQ30 DQ31 VCC DQ32 DQ33 DQ34 DQ35 VSS PD1 PD3 PD5 PD7 ID0 (VSS) VCC 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 3 Symbol VSS DQ36 DQ37 DQ38 DQ39 VCC DQ40 DQ41 DQ42 DQ43 DQ44 VSS DQ45 DQ46 DQ47 DQ48 DQ49 VCC DQ50 DQ51 DQ52 DQ53 VSS NC NC VCC NC NC NC NC NC VSS A1 A3 A5 A7 A9 NC NC VCC NC B0 PIN # 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 Symbol VSS NC NC NC NC PDE VCC NC NC DQ54 DQ55 VSS DQ56 DQ57 DQ58 DQ59 VCC DQ60 NC NC NC NC DQ61 DQ62 DQ63 VSS DQ64 DQ65 DQ66 DQ67 VCC DQ68 DQ69 DQ70 DQ71 VSS PD2 PD4 PD6 PD8 ID1 (VSS) VCC HYM721000/10GS-60/-70 1M x 72 ECC- Module RAS0 CAS0 RAS2 CAS4 WE0 OE0 WE2 OE2 DQ0-DQ3 DQ36-DQ39 I/O1-I/O4 I/O1-I/O4 D0 DQ4-DQ7 D9 DQ40-DQ43 I/O1-I/O4 I/O1-I/O4 D1 DQ8-DQ11 D10 I/O1-I/O4 DQ44-DQ47 I/O1-I/O4 D2 DQ12-DQ15 D11 I/O1-I/O4 I/O1-I/O4 DQ48-DQ51 D3 DQ16-DQ19 D12 I/O1-I/O4 I/O1-I/O4 DQ52-DQ55 D4 DQ20-DQ23 D13 DQ56-DQ59 I/O1-I/O4 I/O1-I/O4 D5 DQ24-DQ27 D14 I/O1-I/O4 I/O1-I/O4 DQ60-DQ63 D6 DQ28-DQ31 D15 DQ64-DQ67 I/O1-I/O4 I/O1-I/O4 D7 DQ32-DQ35 D16 I/O1-I/O4 I/O1-I/O4 DQ68-DQ71 D8 D17 A0 D0 - D8 Vcc B0 D9 - D17 Vss A1-A9 D0 - D17 PDE Vcc or Vss Block Diagram Semiconductor Group 4 D0-D17, buffers PD1-PD8 HYM721000/10GS-60/-70 1M x 72 ECC- Module Absolute Maximum Ratings Operating temperature range ......................................................................................... 0 to + 70 °C Storage temperature range...................................................................................... – 55 to + 125 °C Input/output voltage ........................................................................................................ – 1 to + 7 V Power supply voltage...................................................................................................... – 1 to + 7 V Power dissipation................................................................................................................ 13,86 W Data out current (short circuit) ................................................................................................ 50 mA Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC Characteristics 1) TA = 0 to 70 °C; VCC = 5 V ± 10 % Parameter Symbol Limit Values Unit Test Condition min. max. 2.4 5.5 V – Input low voltage VIH VIL – 1.0 0.8 V – Output high voltage (IOUT = – 5 mA) VOH 2.4 – V – Output low voltage (IOUT = 4.2 mA) VOL – 0.4 V – Input leakage current (0 V < VIN < 6.5 V, all other pins = 0 V) II(L) – 10 10 µA – Output leakage current (DO is disabled, 0 V < VOUT < 5.5 V) IO(L) – 10 10 µA – – – 1980 1800 mA mA 2), 3) – 50 mA – Input high voltage Average VCC supply current: ICC1 HYM 721000/10GS-60 HYM 721000/10GS-70 (RAS, CAS, address cycling, tRC = tRC min.) Standby VCC supply current (RAS = CAS = VIH) ICC2 Average VCC supply current during RAS ICC3 only refresh cycles: HYM 721000/10GS-60 HYM 721000/10GS-70 (RAS cycling, CAS = VIH , tRC = tRC min.) Semiconductor Group 5 2) – – 1980 1800 mA mA HYM721000/10GS-60/-70 1M x 72 ECC- Module DC Characteristics (cont’d) 1) Parameter Symbol Limit Values min. ICC4 Average VCC supply current during fast page mode: HYM 721000/10GS-60 HYM 721000/10GS-70 Unit max. Test Condition 2), 3) – – – 1260 1260 mA mA – 30 mA (RAS = VIL, CAS, address cycling tPC = tPC min.) Standby VCC supply current (RAS = CAS = VCC – 0.2 V) ICC5 Average VCC supply current during ICC6 CAS-before-RAS refresh mode: HYM 721000/10GS-60 HYM 721000/10GS-70 – 1) – – 1980 1800 mA mA (RAS, CAS cycling, tRC = tRC min.) Capacitance TA = 0 to 70 °C; VCC = 5 V ± 10 %; f = 1 MHz Parameter Symbol Limit Values min. max. Unit Input capacitance (A0 to A9,B0) CI1 – 10 pF Input capacitance (RAS0, RAS2) CI2 – 50 pF Input capacitance (CAS0-CAS7) – 15 pF Input capacitance (WE0,WE2,OE0,OE2) CI3 CI4 – 15 pF I/O capacitance (DQ0-DQ71) CIO1 – 15 pF Semiconductor Group 6 HYM721000/10GS-60/-70 1M x 72 ECC- Module AC Characteristics (note: 5,6,7,8) TA = 0 to 70 °C,VCC = 5.0 ± 10 % Parameter Symbol -60 -70 min. max. min. max. Unit Note common parameters Random read or write cycle time tRC 110 – 130 – ns RAS precharge time tRP 40 – 50 – ns RAS pulse width tRAS 60 100k 70 100k ns CAS pulse width tCAS 15 100k 20 100k ns CAS precharge time tCP 10 – 10 – ns Row address setup time tASR 5 – 5 – ns 9 Row address hold time tRAH 8 – 8 – ns 10 Column address setup time tASC 2 – 2 – ns 11 Column address hold time tCAH 15 – 20 – ns 9 RAS to CAS delay time tRCD 18 40 18 45 RAS to column address delay time tRAD 13 25 13 30 ns 12 RAS hold time tRSH 20 – 25 – ns 9 CAS hold time tCSH 58 – 68 – ns 10 CAS to RAS precharge time tCRP 10 – 10 – ns 9 Transition time (rise and fall) tT 3 30 3 30 ns 7 Refresh period tREF – 16 – 16 ms Access time from RAS tRAC – 60 – 70 ns 13,14 Access time from CAS tCAC – 20 – 25 ns 9,13,14 Access time from column address tAA – 35 – 40 ns 9,13, 15 OE access time tOEA – 20 – 25 ns 9,13 Column address to RAS lead time tRAL 35 – 40 – ns 9 Read command setup time tRCS 2 – 2 – ns 11 Read command hold time tRCH 2 – 2 – ns 11,16 Read command hold time referenced to RAS tRRH 0 – 0 – ns 16 tCLZ 2 – 2 – ns 11,13 Output buffer turn-off delay tOFF – 20 – 25 ns 9,17 Output buffer turn-off delay from OE tOEZ – 20 – 25 ns 9,17 12 Read Cycle CAS to output in low-Z Semiconductor Group 7 HYM721000/10GS-60/-70 1M x 72 ECC- Module AC Characteristics (cont’d)(note: 5,6,7,8) TA = 0 to 70 °C,VCC = 5.0 ± 10 % Parameter Symbol -60 -70 min. max. min. max. Unit Note CAS delay time from Din tDZC 0 – 0 – ns 18 Data to OE low delay tDZO 0 – 0 – ns 18 CAS high to data delay tCDD 20 – 25 – ns 9,19 OE high to data delay tODD 20 – 25 – ns 9,19 Write command hold time tWCH 15 – 15 – ns 9 Write command pulse width tWP 10 – 10 – ns Write command setup time tWCS 2 – 2 – ns 11,20 Write command to RAS lead time tRWL 20 – 25 – ns 9 Write command to CAS lead time tCWL 15 – 20 – ns Data setup time tDS -2 – -2 – ns 10,21 Data hold time tDH 15 – 20 – ns 9,21 Read-write cycle time tRWC 155 – 185 – ns 9 RAS to WE delay time tRWD 82 – 97 – ns 11,21 CAS to WE delay time tCWD 37 – 47 – ns 11,21 Column address to WE delay time tAWD 52 – 62 – ns 11,21 OE command hold time tOEH 13 – 18 – ns 10 Fast page mode cycle time tPC 40 – 45 – ns Access time from CAS precharge tCPA – 40 – 45 ns tRAS 60 200k 70 200k ns tRHCP 40 – 45 – ns Write Cycle Read-Modify-Write Cycle Fast Page Mode Cycle RAS pulse width CAS precharge to RAS Delay Semiconductor Group 8 9,13 9 HYM721000/10GS-60/-70 1M x 72 ECC- Module AC Characteristics (cont’d)(note: 5,6,7,8) TA = 0 to 70 °C,VCC = 5.0 ± 10 % Parameter Symbol -60 -70 min. max. min. max. Unit Note Fast Page Mode Read-Modify-Write Cycle Fast page mode read-write cycle time tPRWC 82 – 97 – ns 11 CAS precharge to WE tCPWD 57 – 67 – ns 11,21 CAS setup time tCSR 12 – 12 – ns 11 CAS hold time tCHR 8 – 8 – ns 10 RAS to CAS precharge time tRPC 5 – 5 – ns Write to RAS precharge time tWRP 12 – 12 – ns 11 Write hold time referenced to RAS tWRH 8 – 8 – ns 10 PDE to valid presence detect data tPD – 10 ns PDE inactive to presence detects inactive tPDOFF 0 10 ns CAS-before-RAS Refresh Cycle Presence Detect Read Cycle Semiconductor Group 9 HYM721000/10GS-60/-70 1M x 72 ECC- Module Notes: 1) 2) 3) 4) All voltages are referenced to VSS. ICC1, ICC3, ICC4 and ICC6 and ICC7 depend on cycle rate. ICC1 and ICC4 depend on output loading. Specified values are measured with the output open. Address can be changed once or less while RAS = Vil.In the case of ICC4 it can be changed once or less during a fast page mode cycle ( tpc). 5) An initial pause of 100 µs is required after power-up followed by 8 RAS-only-refresh cycles, before proper device operation is achieved. In case of using internal refresh counter, a minimum of 8 CAS-before-RAS initialization cycles instead of 8 RAS cycles are required. 6) AC measurements assume tT = 5 ns. 7) VIH (min.) and VIL (max.) are reference levels for measuring timing of input signals. Also, transition times are measured between VIH and VIL. 8) The specified timings include buffer, loading and skew delay adders: 2ns minimum, 5ns (CAS, WE, OE, addresses) maximum delay, no pulse shrinkage to the DRAM device timings. The data and RAS signals are not buffered, which preserves the DRAMs access specification of 50ns and 60ns. 9) A +5ns timing skew from the DRAM to the module resulted from the addition of line drivers. 10) A -2ns timing skew from the DRAM to the module resulted from the addition of line drivers. 11) A +2ns timing skew from the DRAM to the module resulted from the addition of line drivers. 12) A -2ns (min.) and a -5ns (max.) timing skew from the DRAM to the module resulted from the addition of line drivers. 13) Measured with the specified current load and 100 pF at Voh = 2.4 V and Vol = 0.4 V. 14) Operation within the tRCD (max.) limit ensures that tRAC (max.) can be met. tRCD (max.) is specified as a reference point only: If tRCD is greater than the specified tRCD (max.) limit, then access time is controlled by tCAC. 15) Operation within the tRAD (max.) limit ensures that tRAC (max.) can be met. tRAD (max.) is specified as a reference point only: If tRAD is greater than the specified tRAD (max.) limit, then access time is controlled by tAA. 16) Either tRCH or tRRH must be satisfied for a read cycle. 17) tOFF (max.) and tOEZ (max.) define the time at which the outputs achieve the open-circuit condition and are not referenced to output voltage levels. 18) Either tDZC or tDZO must be satisfied. 19) Either tCDD or tODD must be satisfied. 20) tWCS, tRWD, tCWD, tAWD and tCPWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCS > tWCS (min.), the cycle is an early write cycle and the I/O pin will remain open-circuit (high impedance) through the entire cycle; if tRWD > tRWD (min.), tCWD > tCWD (min.), tAWD > tAWD (min.) and tCPWD > tCPWD (min.) , the cycle is a read-write cycle and I/O pins will contain data read from the selected cells. If neither of the above sets of conditions is satisfied, the condition of the I/O pins (at access time) is indeterminate. 21) These parameters are referenced to CAS leading edge in early write cycles and to WE leading edge in ReadModify-Write cycles. Semiconductor Group 10 HYM721000/10GS-60/-70 1M x 72 ECC- Module L-DIM-168-2 Module package (dual read-out, single in-line memory module) GLD05861 Semiconductor Group 11