INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: • The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications • The IC06 74HC/HCT/HCU/HCMOS Logic Package Information • The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT139 Dual 2-to-4 line decoder/demultiplexer Product specification File under Integrated Circuits, IC06 September 1993 Philips Semiconductors Product specification Dual 2-to-4 line decoder/demultiplexer 74HC/HCT139 FEATURES GENERAL DESCRIPTION • Demultiplexing capability The 74HC/HCT139 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard no. 7A. • Two independent 2-to-4 decoders • Multifunction capability • Active LOW mutually exclusive outputs The 74HC/HCT139 are high-speed, dual 2-to-4 line decoder/multiplexers. This device has two independent decoders, each accepting two binary weighted inputs (nA0 and nA1) and providing four mutually exclusive active LOW outputs (nY0 to nY3). Each decoder has an active LOW enable input (nE). When nE is HIGH, every output is forced HIGH. The enable can be used as the data input for a 1-to-4 demultiplexer application. The “139” is identical to the HEF4556 of the HE4000B family. • Output capability: standard • ICC category: MSI QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns TYPICAL SYMBOL PARAMETER CONDITIONS UNIT HC tPHL/ tPLH propagation delay HCT CL = 15 pF; VCC = 5 V nAn to nYn 11 13 ns nE3 to nYn 10 13 ns 3.5 3.5 pF 42 44 pF CI input capacitance CPD power dissipation capacitance per multiplexer notes 1 and 2 Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW): PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where: fi = input frequency in MHz fo = output frequency in MHz ∑ (CL × VCC2 × fo) = sum of outputs CL = output load capacitance in pF VCC = supply voltage in V 2. For HC the condition is VI = GND to VCC For HCT the condition is VI = GND to VCC − 1.5 V APPLICATIONS • Memory decoding or data-routing • Code conversion ORDERING INFORMATION See “74HC/HCT/HCU/HCMOS Logic Package Information”. September 1993 2 Philips Semiconductors Product specification Dual 2-to-4 line decoder/demultiplexer 74HC/HCT139 PIN DESCRIPTION PIN NO. SYMBOL NAME AND FUNCTION 1, 15 1E, 2E enable inputs (active LOW) 2, 3 1A0, 1A1 address inputs 4, 5, 6, 7 1Y0 to 1Y3 outputs (active LOW) 8 GND ground (0 V) 12, 11, 10, 9 2Y0 to 2Y3 outputs (active LOW) 14, 13 2A0, 2A1 address inputs 16 VCC positive supply voltage Fig.1 Pin configuration. Fig.2 Logic symbol. (a) (b) Fig.3 IEC logic symbol. September 1993 3 Philips Semiconductors Product specification Dual 2-to-4 line decoder/demultiplexer Fig.4 Functional diagram. FUNCTION TABLE INPUTS nE nA0 OUTPUTS nA1 nY0 nY1 nY2 nY3 H X X H H H H L L L L L H L H L L H H L H H H H L H H H H L H H H H L Notes 1. H = HIGH voltage level L = LOW voltage level X = don’t care Fig.5 Logic diagram (one decoder/demultiplexer). September 1993 4 74HC/HCT139 Philips Semiconductors Product specification Dual 2-to-4 line decoder/demultiplexer 74HC/HCT139 DC CHARACTERISTICS FOR 74HC For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”. Output capability: standard ICC category: MSI AC CHARACTERISTICS FOR 74HC GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (°C) TEST CONDITIONS 74HC SYMBOL PARAMETER +25 min. typ. −40 to +85 max. min. max. −40 to +125 min. UNIT VCC WAVEFORMS (V) max. tPHL/ tPLH propagation delay nAn to Yn 39 14 11 145 29 25 180 36 31 220 44 38 ns 2.0 4.5 6.0 Fig.6 tPHL/ tPLH propagation delay nE to nYn 33 12 10 135 27 23 170 34 29 205 41 35 ns 2.0 4.5 6.0 Fig.7 tTHL/ tTLH output transition time 19 7 6 75 15 13 95 19 16 110 22 19 ns 2.0 4.5 6.0 Figs 6 and 7 September 1993 5 Philips Semiconductors Product specification Dual 2-to-4 line decoder/demultiplexer 74HC/HCT139 DC CHARACTERISTICS FOR HCT For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”. Output capability: standard ICC category: MSI Note to HCT types The value of additional quiescent supply current (∆ICC) for a unit load of 1 is given in the family specifications. To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below. INPUT UNIT LOAD 1An 2An nE 0.70 0.70 1.35 COEFFICIENT AC CHARACTERISTICS FOR 74HCT GND = 0 V; tf = tf = 6 ns; CL = 50 pF Tamb (°C) TEST CONDITIONS 74HCT SYMBOL PARAMETER +25 min. typ. −40 to +85 max. min. max. −40 to +125 min. UNIT VCC WAVEFORMS (V) max. tPHL/ tPLH propagation delay nAn to Yn 16 34 43 51 ns 4.5 Fig.6 tPHL/ tPLH propagation delay nE to nYn 16 34 43 51 ns 4.5 Fig.7 tTHL/ tTLH output transition time 7 15 19 22 ns 4.5 Figs 6 and 7 September 1993 6 Philips Semiconductors Product specification Dual 2-to-4 line decoder/demultiplexer 74HC/HCT139 AC WAVEFORMS (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.6 Waveforms showing the address input (nAn) to output (nYn) propagation delays and the output transition times. (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.7 Waveforms showing the enable input (nE) to output (nYn) propagation delays and the output transition times. PACKAGE OUTLINES See “74HC/HCT/HCU/HCMOS Logic Package Outlines”. September 1993 7