Evaluation Board for Power Management Unit for Imaging Modules EVAL-ADP5020 FEATURES The motherboard features a 3.3 V regulator (VBOARD) a 3.7 V regulator (VBATT) and a 2.0 V regulator (VDDIO). VDDIO is the digital I/O voltage supplying the I2C interface and the control pins. VBOARD is the motherboard logic supply while VBATT provides power to the daughterboard. Jumpers on the top left of the motherboard define whether the internal regulators are supplied from the USB port or from external supplies connected to J10. The VBUS line from the USB connector powers the motherboard regulators when Jumper LK8 to Jumper LK10 are in the USB position. Connector J10 provides supply voltages for the motherboard and daughterboard when Jumper LK8 to Jumper LK10 are in the EXT position. Input voltage: 2.4 V to 5.5 V Evaluates three regulators (Buck 1, Buck 2, and LDO) USB to I2C interface translation Jumpers for input current measurement of regulators Supports EN, SYNC, and XSHTDWN pin interface Evaluation software included GENERAL DESCRIPTION The evaluation system is composed of a motherboard and a daughterboard. The motherboard provides the I2C® signals from the computer USB port and generates the I/O voltages and digital high and low signals for the daughterboard. The daughterboard contains numerous jumpers, LEDs, and test points for easy evaluation and monitoring of the board. 07794-001 MOTHERBOARD AND DAUGHTERBOARD LAYOUT Figure 1. Rev. 0 Evaluation boards are only intended for device evaluation and not for production purposes. Evaluation boards are supplied “as is” and without warranties of any kind, express, implied, or statutory including, but not limited to, any implied warranty of merchantability or fitness for a particular purpose. No license is granted by implication or otherwise under any patents or other intellectual property by application or use of evaluation boards. Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Analog Devices reserves the right to change devices or specifications at any time without notice. Trademarks and registered trademarks are the property of their respective owners. Evaluation boards are not authorized to be used in life support devices or systems. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2009 Analog Devices, Inc. All rights reserved. EVAL-ADP5020 TABLE OF CONTENTS Features .............................................................................................. 1 Additional Commands .............................................................. 12 General Description ......................................................................... 1 Warning ....................................................................................... 12 Motherboard and Daughterboard Layout ..................................... 1 History ......................................................................................... 12 Revision History ............................................................................... 2 Evaluation Board Overview .......................................................... 13 Software Installation......................................................................... 3 Motherboard ............................................................................... 13 USB Driver Installation.................................................................... 5 Daughterboard............................................................................ 14 Evaluation Board Software .............................................................. 6 Evaluation Board Schematics........................................................ 16 Quick Start..................................................................................... 6 Motherboard Schematics .......................................................... 16 Using the Software........................................................................ 8 Daughterboard Schematic......................................................... 18 View/Modify Register Settings ................................................... 8 PCB Layout. ................................................................................ 19 Program/Run Turn-On Sequence ............................................ 10 Ordering Information .................................................................... 21 Program/Run Turn-Off Sequence ............................................ 10 Bill of Materials ........................................................................... 21 Registers Commands ................................................................. 10 Ordering Guide .......................................................................... 22 Register Command Options ..................................................... 11 ESD Caution................................................................................ 22 Load/Save Registers Configuration.......................................... 12 REVISION HISTORY 5/09—Revision 0: Initial Version Rev. 0 | Page 2 of 24 EVAL-ADP5020 SOFTWARE INSTALLATION 1. 2. 3. 6. Click Next > to install the files to the default destination folder or click Browse… to choose a different file. 07794-004 4. Before starting the software installation, make sure that the ADP5020 adapter board is not connected to the PC USB port. The application software is a compiled LabVIEW™ program requiring the LabVIEW 8.5 run-time engine to be installed on the PC. Download the LabVIEW run-time engine from National Instruments. After installation, reboot the PC to complete the operation if necessary. Note that if the PC already has LabVIEW installed, this step is not needed. Launch the file Setup.exe. When the dialog box shown in Figure 2 appears, click Next > to continue. Figure 4. Choose Destination Location Click Next > to continue with the installation. 07794-002 7. Figure 2. ADP5020 Evaluation Software Setup 07794-005 Click Yes to accept the license agreement. Figure 5. Setup Type 07794-003 5. Figure 3. License Agreement Rev. 0 | Page 3 of 24 EVAL-ADP5020 Figure 6. Select Program Folder Wait while the program installs. 07794-007 9. Figure 7. Setup Status Rev. 0 | Page 4 of 24 07794-008 10. Click Finish to complete the installation. Click Next > to install the program to the default program folder. 07794-006 8. Figure 8. InstallShield Wizard Complete EVAL-ADP5020 USB DRIVER INSTALLATION 1. 4. Open the Device Manager and check that the USB driver is installed properly. 07794-011 2. Plug the ADP5020 board into the computer using the USB cable provided with the evaluation kit. Once the system recognizes the board, the dialog box shown in Figure 9 appears. Click Next > to install the driver. 07794-009 Figure 11. Check Driver Installation Figure 9. Found New Hardware Wizard Click Continue Anyway and then Finish to complete the driver installation. 07794-010 3. When the USB cable is connected to a PC port different from the one used to install the driver, the PC device driver may ask to install the driver again for that specific port. If this happens, follows the same steps described in the USB driver installation. Figure 10. Hardware Installation Rev. 0 | Page 5 of 24 EVAL-ADP5020 EVALUATION BOARD SOFTWARE QUICK START The program default settings are as follows: Make sure that the software and the USB driver are installed as described in the Software Installation and USB Driver Installation sections. Connect the board as shown in Figure 12. Upon connecting the USB cable, the D19, D20, and D21 indicators light up, indicating that the supplies are connected. • • Click the Start button, located at the bottom left-hand corner of your desktop. Select All Programs, then Analog Devices, then ADP5020 Evaluation Software, and then ADP5020 Evaluation SW to load the software. If the program starts correctly and the board is detected, the ADP5020 graphical user interface (GUI) appears as shown in Figure 13. • • • • USB • All registers initialized to zero. Software turn-on sequence is: Buck 1 first, Buck 2 second, LDO third. Delay between activations is 1000 ms. Software turn-off sequence is: LDO first, Buck 2 second, Buck 1 third. Delay between activations is 1000 ms. Regs Refresh check box is cleared (status registers are not read periodically). Refresh delay is 1000 ms. Smart Update check box is selected (any change to the registers control triggers a write operation to the device). Verify after write check box is selected (a write operation is followed by a read for verification). CONNECT USB MINI B CABLE EN/GPIO D21 D20 D19 BUCK2 LDO ON ACTIVATION INDICATORS BUCK1 OPTIONAL SIGNAL GENERATOR (SYNC) 07794-012 XSHTDWN INSTALL DAUGHTERBOARD Figure 12. ADP5020 Board Connections Rev. 0 | Page 6 of 24 EVAL-ADP5020 ENABLE CONTEXT HELP CLOSE APPLICATION VIEW/MODIFY REGISTERS READ DEVICE REGISTERS STOP APPLICATION WRITE DEVICE REGISTERS Figure 13. ADP5020 GUI Rev. 0 | Page 7 of 24 07794-013 CREATE SOFTWARE SEQUENCING EVAL-ADP5020 USING THE SOFTWARE 1 2 3 5 4 1. 2. 3. 4. 5. 6. VIEW/MODIFY REGISTER SETTINGS. PROGRAM/RUN SOFTWARE TURN-ON SEQUENCE. PROGRAM/RUN SOFTWARE TURN-OFF SEQUENCE. REGISTERS COMMANDS. REGISTERS COMMANDS OPTIONS. LOAD/SAVE REGISTERS CONFIGURATION. 07794-014 6 Figure 14. Evaluation Board Software Before running the software, ensure that the board is plugged into the computer USB port (the VBATT OKAY, VDDIO OKAY, and VOBARD OKAY LEDs on the motherboard should light up). 07794-015 Install the ADP5020 evaluation software as described in the Quick Start section. Failure to detect the adapter board prompts an error message, as shown in Figure 15. If this occurs, check the connection and restart the program. Figure 15. Board Detection Failure VIEW/MODIFY REGISTER SETTINGS The USER REGISTERS section of the GUI window displays the ADP5020 register settings (following a Read Registers operation) and allows you to modify the current values. To facilitate operation, all the possible device configurations are listed in the drop-down boxes. You can select the desired value, then program the device by clicking the Write Registers button. If the Smart Update check box is selected (default condition), as soon as a register value is changed, the application sends a programming command for that specific register without the need to click the Write Registers button. When the Smart Update check box is cleared, data is written to the device only after clicking the Write Registers button. The Buck 1 Vout Sel. drop-down box allows you to change the Buck 1 regulator output voltage to one of the following settings: 2.5 V, 2.8 V, 2.9 V, 3.0 V, 3.2 V, 3.3 V, or 3.7 V. The default value is 3.3 V. This box corresponds to BK1_VSEL, Bits[2:0] in the BUCK1_VSEL register (Address 0x01). The Buck 2 Vout Selection drop-down box allows you to change the Buck 2 regulator output voltage to one of the following settings: 1.1 V, 1.2 V, 1.3 V, 1.4 V, 1.5 V, 1.6 V, 1.7 V, or 1.8 V. The default value is 1.2 V. This box corresponds to BK2_VSEL, Bits[7:4] in the BUCK2_LDO_VSEL register (Address 0x02). Rev. 0 | Page 8 of 24 EVAL-ADP5020 The LDO Vout Selection drop-down box allows you to change the LDO regulator output voltage to one of the following settings: 1.8 V, 1.9 V, 2.0 V, 2.1 V, 2.2 V, 2.3 V, 2.4 V, 2.5 V, 2.6 V, 2.7 V, 2.8 V, 2.9 V, 3.0 V, 3.1 V, 3.2 V, or 3.3 V. The default value is 1.8 V. This box corresponds to LDO_VSEL, Bits[3:0] in the BUCK2_ LDO_VSEL register (Address 0x02). The Buck 2 PGOOD check box shows the power-good status for the Buck 2 regulator. If the check box is selected, the Buck 2 regulator is operating correctly; if cleared, it indicates that the Buck 2 regulator is either not activated or in a failing condition. This check box corresponds to BK2_PGOOD, Bit[2] in the REG_CONTROL_STATUS register (Address 0x03). The Buck 1 Control check box activates, if selected, or deactivates, if cleared, the Buck 1 regulator. This check box corresponds to BK1_EN, Bit[7] in the REG_CONTROL_STATUS register (Address 0x03). The LDO PGOOD check box shows the power-good status for the LDO regulator. If the check box is selected, the LDO regulator is operating correctly; if cleared, it indicates that the LDO regulator is either not activated or in a failing condition. This indicator corresponds to LDO_PGOOD, Bit[1] in the REG_ CONTROL_STATUS register (Address 0x03). The Buck 2 Control check box activates, if selected, or deactivates, if cleared, the Buck 2 regulator. This check box corresponds to BK2_EN, Bit[6] in the REG_CONTROL_STATUS register (Address 0x03). The LDO Control check box activates, if selected, or deactivates, if cleared, the LDO regulator. This check box corresponds to LDO_EN, Bit[5] in the REG_CONTROL_STATUS register (Address 0x03). The Enable All Regulators check box activates, if selected, or deactivates, if cleared, all regulators available. This check box corresponds to EN_ALL, Bit[4] in the REG_CONTROL_STATUS register (Address 0x03). The XSHTDWN on Buck 1 check box allows you to mask the Buck 1 power-good (PGOOD) signal, if selected, or to control the power-good signal, if cleared, to generate the XSHTDWN signal. This check box corresponds to BK1_XSHTDN, Bit[3] in the OPERATIONAL_CONTROL register (Address 0x04). The XSHTDWN on Buck 2 check box allows you to mask the Buck 2 power-good (PGOOD) signal, if selected, or to control the power-good signal, if cleared, to generate the XSHTDWN signal. This check box corresponds to BK2_XSHTDN, Bit[2] in the OPERATIONAL_CONTROL register (Address 0x04). The Thermal Shutdown check box shows the status for the thermal shutdown (TSD) protection. If the check box is selected, the device is in a TSD condition; if cleared, it indicates that the device is operating normally. This check box corresponds to TSD, Bit[0] in the OPERATIONAL_CONTROL register (Address 0x04). When this check box is selected (set to 1), you must clear this check box, then write this bit back to the device to clear a TSD condition. Make sure to clear the Regs Refresh check box to override this indicator. If the Regs Refresh option is enabled (check box is selected), the periodic refresh writes back the TSD indicator and you will not be able to clear the TSD bit. You must not write this indicator (that is, you must not click the Write Registers button ) while the Thermal Shutdown check box is selected (set to 1) because this forces a TSD condition and the regulators, if enabled, stops working. The EN/GPIO Options drop-down box allows you to program the function associated with the EN/GPIO pin to one of the following settings: input high impedance, output low, or output high. This box corresponds to ENO_DRV, Bit[0], and ENO_HIZ_BAR, Bit[1], in the EN_CONTROL register (Address 0x05). The XSHTDWN on LDO check box allows you to mask the LDO power-good (PGOOD) signal, if selected, or to control the power-good signal, if cleared, to generate the XSHTDWN signal. This check box corresponds to LDO_XSHTDN, Bit[1] in the OPERATIONAL_CONTROL register (Address 0x04). The SYNC Options drop-down box allows you to program the function associated with the SYNC pin to one of the following settings: internal clock, external dc-coupled 9.6 MHz clock, external dc-coupled 19.2 MHz clock, external ac-coupled 9.6 MHz clock, or external ac-coupled 19.2 MHz clock. This box corresponds to SYNC_9P6, Bit[6], and SYNC_19P2, Bit[5], in the OPERATIONAL_CONTROL register (Address 0x04). The Force XSHTDWN check box, if cleared, forces the XSHTDN pin level to Logic 0; if selected, the XSHTDN logic level depends on the power-good (PGOOD) status of the regulators. This check box corresponds to FORCE_XS, Bit[0] in the REG_CONTROL_ STATUS register (Address 0x03). The DEVICE REVISION box shows the major and minor revision, and the specific device option. It is not possible to alter the values in this box because it is a hard-coded value in the device. This box corresponds to MAJ, Bits[7:5], MIN, Bits[4:2], and OPT, Bits[1:0], in the revision register (Address 0x00). The Buck 1 PGOOD check box shows the power-good status for the Buck 1 regulator. If the check box is selected, the Buck 1 regulator is operating correctly; if cleared, it indicates that the Buck 1 regulator is either not activated or in a failing condition. This check box corresponds to BK1_PGOOD, Bit[3] in the REG_CONTROL_STATUS register (Address 0x03). To read or write the device register in bit or byte format as shown in the device memory map (see the ADP5020 data sheet), you can open the registers map utility by clicking the Registers MAP button. See the Registers Commands section for additional information. Rev. 0 | Page 9 of 24 EVAL-ADP5020 PROGRAM/RUN TURN-ON SEQUENCE The TURN ON SEQUENCE section of the GUI window allows you to create and run simple activation patterns for the available regulators, mimicking the desired regulator sequence needed for a specific application. The First Regulator option button allows you to turn on the first regulator and R1 to R2 Delay allows you to program the delay between the first and second regulator from 1 ms to 10 sec. The Second Regulator option button allows you to turn on the second regulator, and R2 to R3 Delay allows you to program the delay between the first and second regulator from 1 ms to 10 sec. Finally, the Third Regulator option button allows you to turn on the third and last regulator. It is not possible to select more than one regulator under each regulator box (for example, you cannot select both Buck 2 and Buck 1 under First Regulator). However, if the application requires more than one regulator to be turned on at the same time, set the R1 to R2 Delay time to 0 ms, then select another regulator under Second Regulator. If all three regulators must be activated at the same time, set the R2 to R3 Delay time to 0 ms, then select the third regulator under Third Regulator. PROGRAM/RUN TURN-OFF SEQUENCE The turn-off sequence follows the same indications provided for the turn-on sequence except that the operation is executed in reverse order. REGISTERS COMMANDS The Read Registers button, when clicked, reads all the ADP5020 internal registers (Addresses 0x00 to Address 0x05) and updates the USER REGISTERS section with the new values. The Write Registers button, when clicked, writes the current registers values set in the USER REGISTERS section into the ADP5020 volatile memory. If the Verify after write check box is selected, the program reads back the programmed registers and compares the device values with the set values (buffer). If one or more errors are detected, a message appears, indicating the registers at fault. Figure 17 shows a verification error example. 07794-016 Click the Start TON Sequence button to run the programmed pattern. Once the pattern is sent to the ADP5020 in the daughterboard, the Regs are OFF indicator changes to Regs are ON and lights up. Note that the timing used for the sequencing uses the PC internal clock with 1 ms resolution. In addition, there are time lags due to the program execution and communication with the adapter board. Therefore, timing precision may be affected, especially for short durations, and may vary from PC to PC. Once a sequence is started, you can verify the PGOOD and TSD device status (under Buck 1 PGOOD, Buck 2 PGOOD, LDO PGOOD, and Thermal Shutdown) in the USER REGISTER section of the GUI. If the option Regs Refresh is enabled (that is, the check box is selected), the status of PGOOD and TSD is updated automatically at the rate programmed under the Refresh Rate box. Figure 17. Verification Error The Clear Regs button, when clicked, sets the registers to 0. A message appears requesting confirmation to continue (click YES) with the operation or abort it (click NO), leaving the registers unchanged. Rev. 0 | Page 10 of 24 07794-018 Figure 16 shows a sequencing example where the first regulator activated is Buck 1. After one second, Buck 2 is activated. After another second, the LDO turns on. The XSHTDWN signal becomes high 1 ms after the last regulator (LDO in this example). This delay is hardcoded in the ADP5020 and cannot be changed. The software automatically sets the XSHTDN masking bit if the regulators are set to None. Although unnecessary, it is possible to create a sequence where all the regulators are set to None (that is, all disabled). 07794-017 Figure 16. Turn-On Sequence Example Figure 18. Register Clearing Confirmation EVAL-ADP5020 The Registers MAP button, when clicked, activates another method to read and write the ADP5020 registers, as shown in Figure 19. REGISTER COMMAND OPTIONS The Regs Refresh check box, when selected, enables the program to read the device statuses periodically. The refresh time is programmable in the Refresh Rate box from 100 ms to 10 sec. The registers read during the refresh are Register 0x00, the revision register, Register 0x03 (BK1_PGOOD, BK2_PGOOD, and LDO_PGOOD), and Register 0x04 (TSD), providing a realtime indication of the device functionality. If a thermal shutdown event is detected, you must disable the register refresh option (clear the Regs Refresh check box) to clear the TSD flag. The Access blue indicator, when lit up, indicates that the refresh operation is taking place. The Smart Update check box, when selected, enables the program to automatically write an ADP5020 register when a USER REGISTER option has been changed. This avoids the need to click the Write Registers button every time a value is changed. The Smart Update check box must be cleared if you want to control the write operations. 07794-019 The register values, previously set, are transferred into the Register MAP window. You have the choice to modify the registers bitwise by clicking the desired bit position. The bit value then switches from 0 to 1, or vice versa. It is not possible to change the values for the grayed bits. The register values can also be changed by entering a hexadecimal value in the text box for the respective register (for example, 4C is entered for Register 0x00 in Figure 19). The Hex/Dec button allows you to change the data format of the register values from hexadecimal to decimal, or vice versa. Binary and Byte controls are intercommunicating; therefore, changes to one control are automatically reflected in the other. The R and W buttons next to each register allow reading or writing a specific device address, and the Read ALL and Write ALL buttons allows you to read or write the entire register map from or to the ADP5020 under evaluation. The OK/Fail indicator next to these two buttons shows the operation result. Click EXIT to return in the main window. The modified registers are then transferred automatically into the USER REGISTER section of the GUI window. The register map utility does not have the Smart Update option; therefore, a new value is written into the ADP5020 following a write operation (by clicking the W or Write ALL buttons). Figure 19. Register MAP Utility Rev. 0 | Page 11 of 24 EVAL-ADP5020 LOAD/SAVE REGISTERS CONFIGURATION WARNING The software program allows saving a specific register configuration and loading it back into the USER REGISTERS section. The Save Config button, when clicked, opens the file utility where you can specify the directory and file name to save. The default extension is *.dat. Maintaining this convention is recommended. If the file does not exist, it is created; if the file already exists, it is overwritten. Upon starting the ADP5020 application, a dedicated firmware is loaded into the adapter board processor (Cypress IC). This firmware is needed for the operation of the USB adapter and communication with the ADP5020 daughterboard. If the evaluation board is not connected through the USB cable, an error message, as indicated in Figure 15, appears on the screen. This indicates that the firmware was not loaded into the adapter board. If this happens, check the USB connection and ensure that Jumper LK10 is in the USB position. The firmware is loaded in volatile memory inside the Cypress processor; therefore, if power is removed or the USB cable is disconnected, the firmware is lost. If this happens, close the application, connect the adapter board, and then launch the ADP5020 application again to reload the firmware. It is recommended to always stop the program (click the EXIT button) before removing the USB cable. 07794-020 HISTORY Whenever a command is issued (both read and write), it is recorded in the History dialog box shown in Figure 22. To display the History dialog box, click the History button on the bottom right corner of the software GUI (see Figure 14). To clear the history, click Clear History. Figure 20. Save Configuration The Load Config button, when clicked, opens the file utility where you can specify the directory and file name to load. The default extension is *.dat. If you choose to cancel the operation, an error message appears (see Figure 21). Click Continue to abort the operation. 07794-021 You can copy and paste the history into a file for future evaluation purposes. Figure 21. Load/Save Error Message ADDITIONAL COMMANDS The INFO button, when clicked, provides information regarding the software revision number and other release notes. On-line help is available by selecting Show Context Help from the Help menu, or by pressing CTRL + H. Moving the pointer over a control option or indicator displays information related to it in the context help window. Rev. 0 | Page 12 of 24 07794-022 The EXIT button, when clicked, stops the program, leaving the window active and open. To terminate the program completely, click the close button (X) on the upper right corner of the application window. Figure 22. History EVAL-ADP5020 EVALUATION BOARD OVERVIEW MOTHERBOARD EXTERNAL SUPPLIES USB CONNECTOR INT/EXT SUPPLIES JUMPER SELECTION EN PIN EXTERNAL FORCING LEVEL VBATT LED INDICATOR EN/GPIO STATUS LED VDDIO LED INDICATOR VBOARD LED INDICATOR SYNC PIN SELECTION BUCK2 REGULATOR ACTIVATION LED LDO REGULATOR ACTIVATION LED EXTERNAL FREQUENCY ON SYNC PIN CONNECTOR BUCK1 REGULATOR ACTIVATION LED ADP5020 TEST-POINTS DAUGHTERBOARD CONNECTORS 07794-023 XSHTDWN STATUS LED Figure 23. Motherboard The ADP5020 motherboard provides the interface signals to the ADP5020 power management IC. These include the SDA and SCL lines for I2C, or the control line voltages for the hardware interface modes (EN/GPIO, SYNC, and XSHTDWN). The Cypress Semiconductor Corporation CY7C68013A provides the USB interface and I2C signals. The selected I2C frequency is 100 kHz. The M24C64R serial EEPROM provides the USB address of the board. The interface voltage is selected with the VBOARD header on the board and is set to 3.3 V by default. Typically, the daughterboard is inserted directly into the 2 × 20-pin header of the motherboard. For temperature measurements, however, it may be necessary to use an extension cable to connect the motherboard and the daughterboard because the Cypress CY7C68013A is not rated at −40°C. The 8-pin Header J10 on the top of the motherboard can be used to connect external supplies. The VBATT OKAY, VDDIO OKAY, and VBOARD OKAY LEDs located at the top left of the board lights up when the board is powered from the USB cable, or when external supplies are connected to J10 and Jumper LK8 to Jumper LK10 are set in the EXT position. It is possible to choose several supply combinations. For example, VBOARD, which supplies the motherboard ICs, can be provided from the USB while VDDIO and VBATT are provided externally. The motherboard contains three LDOs generating the default supply voltage, as indicated in Table 1. Table 1. Power Supply Options Supply Line VBATT VDDIO VBOARD LK8 to LK10 in USB Position Internal: 3.7 V Internal: 2.0 V Internal: 3.3 V LK8 to LK10 in EXT Position External: 2.3 V to 5.5 V External: 1.7 V to 3.6 V External: 2.7 V to 3.6 V Jumper LK11 defines the forcing level for the EN/GPIO pin. With the jumper in the low position, the EN/GPIO pin is forced to logic low. With the jumper in the high position, the EN/GPIO pin is forced to logic high. The VDDIO supply line determines the logic level. Jumper LK12 selects the clock mode for the SYNC pin. With the jumper in the GND position, the SYNC pin is tied to ground. With the jumper in the EXT position, an external frequency can be applied to the SYNC pin through Connector SM2. The logic level of the clock signal must be referred to the VDDIO supply level. Rev. 0 | Page 13 of 24 EVAL-ADP5020 DAUGHTERBOARD The ADP5020 evaluation daughterboard is designed to quickly evaluate key parameters of the ADP5020 IC. The board layout footprint is extended so that parts can be exchanged easily, and headers are available to measure currents using a current probe or ammeter. Connect a power supply or Li-Ion battery with 2 A capability to VBATT. Up to 1.8 A (nominal) can be drawn from the battery; therefore, short thick cables are recommended to minimize the IR drops. A high current can cause a big IR drop, and VBATT can be low enough to put the part into UVLO. IF JP1 IS IN INT POSITION JP4 SELECTS EN/GPIO TO VDDIO OR GND EN/GPIO SELECTION FORCED INTERNALLY OR EXT. REMOVE FILTER ON VDDA LOOP MEASUREMENT PORT INPUT SUPPLIES AND REGULATORS OUTPUTS I/OS SIGNALS AND KELVIN MEASUREMENTS VDD2 INPUT SELECTION AND CURRENT MEASUREMENT VDD3 INPUT SELECTION AND CURRENT MEASUREMENT Figure 24. Daughterboard Rev. 0 | Page 14 of 24 VDD3 INPUT SOURCE SELECTION (EXT VDD3 OR +VO1) 07794-026 VDD1 INPUT CURRENT MEASUREMENT EVAL-ADP5020 Table 2. Measurement Signals on J6 Quiescent Current Measurement The ADP5020 has separated supply lines for Buck 1 (VDD1), Buck 2 (VDD2) and LDO (VDD3), in addition to the analog circuit supply (VDDA). The IDD1 current can be measured using a current loop across LK12. IDD2 can be measured using a current loop across JP3 Position 1 to JP3 Position 2. IDD3 can be measured using a current loop across JP5 Position 1 to JP5 Position 2. IDDA can be measured using a current loop across JP10. R4 must be removed. Regulator Switching Nodes The Buck 1 switching frequency can be measured on TP25 (SW1). TP21 is a local power ground that can be used to con-nect the scope probe to minimize the switching noise pickup. Buck 2 switching frequency can be measured on TP22. TP24 is a local power ground that can be used to connect the scope probe to minimize the switching noise pickup. Kelvin Measurements The input and output voltages are routed to Connector J6 using Kelvin connections, meaning that the point of measurement is directly on the capacitor pads. This minimizes the measurement error due to IR drop from the trace resistance. Table 2 and Table 3 show the signals available on Connector J6 and Connector J5, respectively. Power Board from USB Port Only To power the board via the USB without using an external supply, short Jumper LK10 on the motherboard (USB position). Avoid exceeding the 500 mA current limit of the USB. Signal EN/GPIO VDDIO SYNC SDA SCL XSHTDWN +VO2S, VO2S +VD2S, −VD2S +VD1S,−VD1S +VO3S, −VO3S +VD3S, −VD3S +VO1S, −VO1S GND J6 Pins 20 19 18 17 16 15 14, 13 12, 11 10, 9 8, 7 6, 5 4, 3 2 Description EN/GPIO pin from IC ADP5020 logic supply External frequency I2C bidirectional line I2C clock line XSHTDN pin from IC Buck 2 output voltage (+/−) Buck 2 input voltage (+/−) Buck 1 input voltage (+/−) LDO output voltage (+/−) LDO input voltage (+/−) Buck 1 output voltage (+/−) Ground plane and digital grounds Table 3. Measurement Signals on J5 Signal VDDA +VDA, −VDA +VO2 −VO2 VDD2 VDD1A, VDD1B +VO3 −VO3 −VO1 +VO1 VDD3 GND Rev. 0 | Page 15 of 24 J5 Pins 20 19, 13 18, 17 16, 15 14 12, 11 10, 9 8 6, 5 4, 3 2 7, 1 Description Analog supply input VDDA input voltage (+/−) Buck 2 output positive voltage Buck 2 output negative voltage Buck 2 input voltage Buck 1 input voltage LDO output voltage (+) LDO output voltage (−) Buck 1 output voltage (−) Buck 1 output voltage (+) LDO input voltage Ground plane and digital grounds EXT_VBATT GND DD+ ID VDD USB-miniB X7 X8 MS1 MS2 MS3 MS4 JP1 5 2 3 4 1 3 1 3 2 07794-024 PGND DGND R16 680 R15 SYNC EN/GPIO SCL SDA VDDIO 1208 R26 31.6k R23 15.4K 46.4K R20 680 R18 VBATT VDDIO VBOARD 18B 20B 16B 17B 19B 20A 2A 14A 12A 11A DD+ SYNC EN/GPIO SCL SDA VDD_IO VDDA VDD3 VDD2 VDD1A VDD1B EN GND1 8 IN GND2 7 OUT GND3 6 ADJ/SS/TRKGND4 5 ADP1715/16 R27 10k 1 2 3 4 U7 EN GND1 8 IN GND2 7 OUT GND3 6 ADJ/SS/TRKGND4 5 ADP1715/16 R24 10k 1 2 3 4 U6 EN GND1 8 IN GND2 7 OUT GND3 6 ADJ/SS/TRKGND4 5 R21 ADP1715/16 10k U5 LED LED LED 1 2 3 4 D21 D20 D19 C16 6.2pF C10 6.2pF C11 100nF Output Voltage Sensing 5A 6A 17A 18A 15A 16A 10A 9A 8A 3A 4A FSW1_TP20 1 FSW2_TP25 2 FSW3_TP22 3 XSHTDWN 15B -VO1A -VO1B +VO2A +VO2B -VO2A -VO2B +VO3A +VO3B -VO3 +VO1A +VO1B 652-CG0603MLC-05E XSHTDWN -VLDO +VLDO -VBK +VBK -VBB +VBB AGND Mouser p/n C14 2.2uF R25 10k C28 0.1uF R29 2.2k R28 2.2k C13 100nF VBOARD VDDIO VDDIO C21 0.1uF C18 2.2uF VBOARD VBOARD D24 CG0603MLC-05E VBOARD 1 3 652-CG0603MLC-05E D23 CG0603MLC-05E CRYSTAL24 Y1 Mouser p/ n 4 2 M1 ADP5020_Daughter Input Voltage Sensing Connectors to Daughterboard VBATT C25 47 uF C24 2.2 uF C23 2.2 uF C20 2.2 uF C19 2.2 uF C17 2.2 uF C15 2.2 uF 2 LK10 2 Way Link 47 LK9 2 Way Link ower Ground & Digital round must be manually onnected in the Layout. his will make initial lacement and routing asier to figure out. URGENT* 10 11 6 7 8 9 Tanya may have a different one than this CON4 EXT_VDDIO 3 1 1 USB_VBOARD 3.3V USB_VDDIO 1.8V USB_VBATT 3.68V 2 GND1 1A 1 2 3 4 14 13 12 11 10 9 8 7 6 5 4 3 2 1 U8 RES IFCLK GND1 VCC1 AGND2 D- D+ AVCC2 AGND1 XTALIN XTALOUT AVCC1 RDY1/SLWR RDY0/SLRD U4 VCC A0 J10 WP A1 LK8 2 Way Link 19A 13A 10B 9B 12B 11B 6B 5B 1B +VDA -VDA +VD1S -VD1S +VD2S -VD2S +VD3S -VD3S AGND GND2 7A Regulators Input Host Interface 4B 3B 14B 13B 8B 7B +VO1S -VO1S +VO2S -VO2S +VO3S -VO3S Rev. 0 | Page 16 of 24 GND4 Figure 25. Motherboard Schematic—Main Section 2B Regulator Outputs VBOARD C7 0.1uF 56 CY7C68013A C8 10uF R17 100k VBOARD M24AA64-R SDA SCL C26 0.1uF VBOARD C9 0.1uF 41 C27 0.1uF PAD 29 30 31 32 VBOARD PAD CTL0 CTL1 CTL2 VCC4 PA0/INT1 33 PA1/INT1 34 PA2/*SLOE 35 PA3/*WU2 36 PA4/FIFOADR0 37 PA5/FIFOADR1 38 PA6/*PKTEND 39 PA7/*FLAG 40 GND4 RESET 42 VCC2 17 55 PB0/FD0 18 GND6 SCL 15 PD6/FD13 51 PB1/FD1 19 53 16 PD7/FD14 52 PB2/FD2 20 54 SCL PD5/FD12 50 PB3/FD3 VCC6 SDA A2 PD4/FD11 49 PB4/FD4 21 47 22 PD3/FD10 48 PB5/FD5 23 46 PD2/FD9 PB6/FD6 24 45 PD1/FD9 PB7/FD7 PD0/FD8 GND2 26 25 GND5 SDA 43 VCC5 VCC3 CLKOUT VSS *WAKEUP 44 GND3 28 27 EXT_VBOARD VBOARD VBOARD VBOARD ForceEN R19 100k C22 0.1uF R22 100k C12 0.1uF EVAL-ADP5020 EVALUATION BOARD SCHEMATICS MOTHERBOARD SCHEMATICS 07794-025 VBOARD C1 10uF C2 0.1uF C3 10uF VBOARD VBOARD VBOARD VBOARD LED LED D5 VBOARD LDO ON LED D4 Buck-Boost ON EN/GPIO = High LED D9 S D S D EN/GPIO Q6 FDN335N Q5 FDN335N 4 - U113 3 2.2K R33 G G G G ADCMP600 S + S D D Q3 FDN335N Q4 FDN335N 1 XSHTDWN = High LED D7 Buck ON C4 0.1uF 680 R13 680 R7 680 R5 680 R3 680 D1 5 2 R34 1M R32 1M +VLDO Q7 FDN335N R36 0 S D G 2 LK11 2 Way Link VDDIO XSHTDWN +VBK R31 1M R30 1M +VBB 1 D22 BAT54TW-7-F R35 1M EN = Low ForceEN EN = High R37 10K A1 K1 6 2 A2 K2 5 3 A3 K3 4 3 R1 SYNC CLR 1 2 LK12 2 Way Link 2 3 4 5 SM2 9.6MHz/19.2MHz Ext. Frequency 1 1 1 1 1 1 1 1 1 EXT FREQ. AGND XSHTDWN -VLO +VLDO -VBK +VBK -VBB +VBB 3 Rev. 0 | Page 17 of 24 1 Figure 26. Motherboard Schematic—Interface Section 1 VBOARD TP10 TP9 TP8 TP7 TP6 TP5 TP4 TP3 TP2 AGND PGND XSHTDWN - VOUT_LDO + VOUT_LDO - VOUT_BK + VOUT_BK - VOUT_BB + VOUT_BB EVAL-ADP5020 Figure 27. Daughterboard Schematic Rev. 0 | Page 18 of 24 07794-027 VDD3 +VO1 -VO1 -VO3 +VO3 VDD1A VDD2 -VO2 +VO2 VDDA VDDIO SDA 2 4 6 8 10 12 14 16 18 20 1 3 5 7 9 11 13 15 17 19 HEADER 10X2 J5 EN/GPIO SYNC SCL R2 10K INTF JP4 3 2 1 3 2 1 +VO1 -VO1 +VO3 VDD1B -VDA -VO2 +VO2 +VDA R1 10K VDD3 VDD2 VDD1B VDD1A VDDA 3 2 1 2 2 10 3 2 1 -VD3S INTF 3 2 1 1 3 2 1 C9 +VD3S 3 2 1 +VD1S JP1 LK10 INTF 3 2 1 INTF JP3 LK12 1 JP5 1 1 1UF -VD2S +VD2S -VD1S -VDA +VDA C7 C6 1UF 2.2UF 2.2UF C5 10UF C8 TP5 11 5 8 7 9 13 19 18 3 EN/GPIO SYNC SCL SDA VDD_IO VDD3 VDD2 VDD1 VDDA U1 ADP5020_LFCSP BUCK1 BUCK2 VANA PGND2 VOUT2 SW2 PGND1 VOUT1B VOUT1A SW1 XSHTDWN LDO R4 1 10 12 1 2 20 16 14 15 17 L1 1 1 2.2uH LK15 2 1UF C4 TP24 R5 L2 C2 49.9 2.2uH 2.2uH TP21 L3 TP22 TP25 1 10UF C3 C1 1 +VO3 -VO2S +VO2S XSHTDWN -VO3 -VO3S +VO3S 4.7UF 10UF TP20 1 C10 DGND 6 AGND 4 1UF 1 TP4 1 TP3 -VO1S -VD3S -VO3S -VD1S -VD2S -VO2S XSHTDWN SDA VDDIO -VO1S +VO1S +VO2 +VO2 -VO2 +VO1 J6 2 2 4 6 8 10 12 14 16 18 20 HEADER 10X2 -VO2 1 3 5 7 9 11 13 15 17 19 LK13 +VO1 1 -VO1 -VO1 +VO1S +VD3S +VO3S +VD1S +VD2S +VO2S SCL SYNC EN/GPIO EVAL-ADP5020 DAUGHTERBOARD SCHEMATIC EVAL-ADP5020 PCB LAYOUT 07794-028 07794-030 Evaluation Board Layout 07794-029 07794-031 Figure 30. Inner Layer 2 Figure 28. Top Layer Figure 31. Bottom Layer Figure 29. Inner Layer 1 Rev. 0 | Page 19 of 24 EVAL-ADP5020 Figure 32. Top Layer 07794-034 07794-032 Motherboard Layout Figure 33. Inner Layer 1 07794-035 07794-033 Figure 34. Inner Layer 2 Figure 35. Bottom Layer Rev. 0 | Page 20 of 24 EVAL-ADP5020 ORDERING INFORMATION BILL OF MATERIALS Table 4. Description Daughterboard Capacitor, MLCC, 10 μF, 6.3 V, 0603, X5R Capacitor, MLCC, 1 μF, 6.3 V, 0402, X5R Capacitor, MLCC, 4.7 μF, 6.3 V, 0603, X5R Capacitor, MLCC, 2.2 μF, 6.3 V, 0402, X5R Capacitor, MLCC, 1 μF, 6.3 V, 0402, X5R Inductor, 2.2 μH Inductor, 2.2 μH Inductor, 2.2 μH Resistor, 10 kΩ, 1%, 0402 Resistor, 10 Ω, 1%, 0403 Resistor, 49.9 Ω, 1%, 0404 ADP5020, 20-Lead LFCSP, 4 mm × 4 mm Header 0.100, Double-Row 10 Pins Header 0.100, Single, STR, 2 Pins Header 0.100, Single, STR, 3 Pins Motherboard Capacitor, MLCC, 100 nF, 10 V, 0402, X5R Capacitor, MLCC, 10 μF, 6.3 V, 0805, X5R Capacitor, MLCC, 6.2 pF, 0402, NP0 Capacitor, MLCC, 2.2 μF, 10 V, 0603, X5R Capacitor, MLCC, 47 μF, 6.3 V, 1206, X5R Red LED, 0402, SMD Green LED, 0402, SMD White LED, 0402, SMD Triple Schottky Diode, SC70 USB ESD Protector Resistor, 680 Ω, 1%, 0402, SMD Resistor, 47 Ω, 1%, 0402, SMD Resistor, 100 kΩ, 1%, 0402, SMD Resistor, 15.4 kΩ, 1%, 0402, SMD Resistor, 31.6 kΩ, 1%, 0402, SMD Resistor, 0 Ω, 1%, 0402, SMD Resistor, 1 MΩ, 1%, 0402, SMD Resistor, 10 kΩ, 1%, 0402, SMD Resistor, 2.2 kΩ, 1%, 0402, SMD Resistor, 46.4 kΩ, 1%, 0402, SMD IC MCU USB Periph High SPD-56QFN Microchip Serial EEPROM-64K, MSOP8 IC Comparator Reference Designator Qty Manufacturer/Vendor Part Number C2, C5, C11 C4 C3 C6, C7 C8, C9, C10 L1 L2 L3 (alternative to L1) R1, R2 R4 R5 U1 J5, J6 LK10, LK12, LK13, LK15 JP1, JP3 to JP5 3 1 1 2 3 1 1 1 2 1 1 1 2 4 Taiyo Yuden Taiyo Yuden Taiyo Yuden Taiyo Yuden Panasonic Taiyo Yuden Taiyo Yuden Coilcraft Vishay Dale Panasonic Panasonic Analog Devices, Inc. SAMTEC Sullins Electronics, Inc./3M JMK107BJ106MA LMK105BJ105MV JMK107BJ475MA JMK105BJ225MV ECJ-1VF1A105Z BRL2518T2R2M BRL2012T2R2M LPS4012 CRCW04021002F ERJ-3EKF10 ERJ-2RKF49.9 ADP5020 SSW-110-03-G-D S1012-36-ND 4 Sullins Electronics, Inc./3M S1012-36-ND C2, C4, C7, C9, C11, C13, C12, C21, C22, C26, C27, C28 C1, C3, C8 C10, C16 C14, C15, C17, C18, C19, C20, C23, C24 C25 D4, D19, D21, D1, D5, D20 D7, D9 D22 D23, D24 R1, R3, R5, R7, R13, R15, R18 R16 R17, R19, R22 R23 R26 R36 R30, R31, R32, R34, R35 R21, R24, R25, R27, R37 R28, R29, R33 R20 U4 U8 U113 11 Murata Manufacturing Co., Ltd. GRM155R61A104KA01B 3 2 8 Murata Manufacturing Co., Ltd. Vishay/Panasonic Murata Manufacturing Co., Ltd. GRM21BR60J106K ECJ-OEC1H0600 GRM188R61A225K 1 3 3 2 1 2 7 Murata Manufacturing Co., Ltd. Lumex Inc. Lumex Inc. Lumex Inc. Diodes, Inc. Bourns Vishay Dale or equivalent GRM32ER61C476K SML-LX0402SIC-TR SML-LX0402SUGC-TR LTW-170TK BAT54TW-7-F CG0603MLC-05E CRCW04026810F 1 3 1 1 1 5 Vishay Dale or equivalent Vishay Dale or equivalent Vishay Dale or equivalent Vishay Dale or equivalent Vishay Dale or equivalent Vishay Dale or equivalent CRCW04024700F CRCW04021003F CRCW04021542F CRCW04023162F CRCW04020000Z0ED CRCW04021004F 5 Vishay Dale or equivalent CRCW040210022F 3 1 1 1 1 Vishay Dale or equivalent Vishay Dale or equivalent Cypress Semiconductor Corp Microchip Analog Devices CRCW040222021F CRCW04024642FF CY7C68013A M24LC64 or 24AA64 ADCMP600 Rev. 0 | Page 21 of 24 EVAL-ADP5020 Description IC LDO Regulator, 500 mA, 8-Lead MSOP Crystal 24 MHz MOSFET N-Channel, SOT23 USB Connector USB Mini B, 5p Header, Male 0.100, Dual, STR, 2 × 10 Pins Header 0.100, Single, STR, 3 Pins Header 0.100, Single, STR, 4 Pins SMB Connector, Receptacle Reference Designator U5, U6, U7 Y1 Q3, Q4, Q5, Q6, Q7 JP1 M1 LK8, LK9, LK10, LK11, LK12 J10 SM2 ORDERING GUIDE Model ADP5020CP-EVALZ1 1 Qty 3 1 5 1 2 5 Manufacturer/Vendor Analog Devices CTS Corporation Fairchild Delphi Corporation/Molex Sullins Connector Solutions Sullins Connector Solutions Part Number ADP1715/16 CTX651CT FDN335N 15430262-110 PTC10SAAN PEC03SAAN 1 1 Sullins Electronics, Inc. Emerson Network Power Connectivity Solution PEC36SAAN 131-3701-266 ESD CAUTION Description Evaluation Board Z = RoHS Compliant Part. Rev. 0 | Page 22 of 24 EVAL-ADP5020 NOTES Rev. 0 | Page 23 of 24 EVAL-ADP5020 NOTES ©2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. EB07794-0-5/09(0) Rev. 0 | Page 24 of 24